®
RT8068A
3A, 1MHz, Synchronous Step-Down Converter
General Description
Features
The RT8068A is a high efficiency synchronous, step-down
DC-DC converter. It's input voltage range from 2.7V to 5.5V
that provides an adjustable regulated output voltage from
0.6V to VIN while delivering up to 3A of output current.
The internal synchronous low on resistance power
switches increase efficiency and eliminate the need for
an external Schottky diode. The switching frequency is
fixed internally at 1MHz. The 100% duty cycle provides
low dropout operation, hence extending battery life in
portable systems. Current mode operation with internal
compensation allows the transient response to be
optimized over a wide range of loads and output capacitors.
The RT8068A is available in WDFN-10L 3x3 and SOP-8
(Exposed Pad) packages.
Ordering Information
RT8068A
Note :
Richtek products are :
RoHS compliant and compatible with the current require-
Portable Instruments
Battery Powered Equipment
Notebook Computers
Distrib uted Power Systems
IP Phones
Digital Cameras
Pin Configuration
(TOP VIEW)
LX
LX
LX
PGOOD
EN
4
5
11
10
9
8
7
6
PVIN
PVIN
SVIN
NC
FB
WDFN-10L 3x3
ments of IPC/JEDEC J-STD-020.
1
2
3
GND
Lead Plating System
Z : ECO (Ecological Element with
Halogen Free and Pb free)
Ω/49mΩ
Ω at VIN
Low RDS(ON) Internal Switches : 69mΩ
= 5V
Fixed Frequency : 1MHz
No Schottky Diode Required
Internal Compensation
0.6V Reference Allows Low Output Voltage
Low Dropout Operation : 100% Duty Cycle
OCP, UVP, OVP, OTP
RoHS Compliant and Halogen Free
Applications
Package Type
QW : WDFN-10L 3x3 (W-Type)
SP : SOP-8 (Exposed Pad-Option 2)
High Efficiency : Up to 95%
Suitable for use in SnPb or Pb-free soldering processes.
LX
Marking Information
RT8068AZQW
13 : Product Code
13 YM
DNN
YMDNN : Date Code
8
LX
2
PGOOD
3
EN
7
GND
6
9
4
5
PVIN
PVIN
SVIN
FB
SOP-8 (Exposed Pad)
RT8068AZSP
RT8068AZSP : Product Code
RT8068A
ZSPYMDNN
YMDNN : Date Code
Copyright © 2019 Richtek Technology Corporation. All rights reserved.
DS8068A-08 June 2019
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
1
RT8068A
Typical Application Circuit
L
RT8068A
PGOOD
PGOOD
LX
VOUT
R1
100k
COUT
PVIN
VIN
CIN
10µF
SVIN
FB
C1
1µF
Chip Enable
CFF
RFB1
RFB2
EN
GND
Table 1. Recommended Component Selection
VOUT (V)
RFB1 (k)
RFB2 (k)
CFF (pF)
L (H)
COUT (F)
3.3
229.5
51
22
2
22 x 2
2.5
161.5
51
22
2
22 x 2
1.8
102
51
22
1.5
22 x 2
1.5
76.5
51
22
1.5
22 x 2
1.2
51
51
22
1.5
22 x 2
1.0
34
51
22
1.5
22 x 2
Functional Pin Description
Pin No.
WDFN-10L
1, 2, 3
Pin
SOP-8
Name
(Exposed Pad)
1, 2
LX
Pin Function
Switch node. Connect this pin to the inductor.
4
3
PGOOD
Power good indicator. This pin is an open drain logic output that is
pulled to ground when the output voltage is less than 90% of the
target output voltage. Hysteresis = 5%.
5
4
EN
Enable control. Pull high to turn on. Do not float.
6
5
FB
Feedback pin. This pin receives the feedback voltage from a resistive
voltage divider connected across the output.
7
--
NC
No internal connection.
8
6
SVIN
Signal input pin. Decouple this pin to GND with at least 1F ceramic
cap.
9,10
7,8
PVIN
Power input pin. Decouple this pin to GND with at least 4.7F
ceramic cap.
11
9
GND
(Exposed Pad) (Exposed Pad)
Ground. The exposed pad must be soldered to a large PCB and
connected to GND for maximum power dissipation.
Copyright © 2019 Richtek Technology Corporation. All rights reserved.
www.richtek.com
2
is a registered trademark of Richtek Technology Corporation.
DS8068A-08 June 2019
RT8068A
Functional Block Diagram
EN
EN
PVIN
ISEN
PGOOD
PGOOD
Slope
Com
OSC
VREF
0.6V
EA
FB
OC
Limit
Output
Clamp
Driver
Int-SS
0.72V
OV
LX
Control
Logic
0.54V
NISEN
PGOOD
0.4V
Zero Current
UV
POR
OTP
100
SVIN
Copyright © 2019 Richtek Technology Corporation. All rights reserved.
DS8068A-08 June 2019
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
3
RT8068A
Absolute Maximum Ratings
(Note 1)
Supply Input Voltage, PVIN, SVIN -----------------------------------------------------------------------------LX Pin
DC ---------------------------------------------------------------------------------------------------------------------< 100ns -------------------------------------------------------------------------------------------------------------- Other I/O Pin Voltage --------------------------------------------------------------------------------------------- Power Dissipation, PD @ TA = 25°C
WDFN-10L 3x3 -----------------------------------------------------------------------------------------------------SOP-8 (Exposed Pad) ------------------------------------------------------------------------------------------- Package Thermal Resistance (Note 2)
WDFN-10L 3x3, θJA -----------------------------------------------------------------------------------------------WDFN-10L 3x3, θJC -----------------------------------------------------------------------------------------------SOP-8 (Exposed Pad), θJA --------------------------------------------------------------------------------------SOP-8 (Exposed Pad), θJC ------------------------------------------------------------------------------------- Lead Temperature (Soldering, 10 sec.) ----------------------------------------------------------------------- Junction Temperature --------------------------------------------------------------------------------------------- Storage Temperature Range ------------------------------------------------------------------------------------ ESD Susceptibility (Note 3)
HBM (Human Body Model) --------------------------------------------------------------------------------------MM (Machine Model) ---------------------------------------------------------------------------------------------
−0.3V to 6.5V
Recommended Operating Conditions
−0.3V to (VIN + 0.3V)
−2.5V to 9V
−0.3V to 6.5V
1.429W
1.333W
70°C/W
8.2°C/W
75°C/W
15°C/W
260°C
150°C
−65°C to 150°C
2kV
200V
(Note 4)
Supply Input Voltage, PVIN, SVIN ------------------------------------------------------------------------------ 2.7V to 5.5V
Junction Temperature Range ------------------------------------------------------------------------------------- −10°C to 105°C
Electrical Characteristics
(VIN = 5.5V, TA = 25°C, unless otherwise specified)
Parameter
Symbol
Feedback Reference Voltage
VREF
Feedback Leakage Current
IFB
Test Conditions
Active , VFB = 0.7V, not
switching
DC Bias Current
Shutdown
VIN = 2.7V to 5.5V
IOUT = 0A
(Note 5)
Output Voltage Line Regulation
Output Voltage Load Regulation
Switch Leakage Current
Switching Frequency
Min
Typ
Max
Unit
0.594
0.6
0.606
V
--
0.1
0.4
A
--
110
140
--
--
1
--
0.3
--
%/V
1
--
1
%
--
--
1
A
0.8
1
1.2
MHz
A
Switch On Resistance, High
RDS(ON)_P
--
69
--
m
Switch On Resistance, Low
RDS(ON)_N
--
49
--
m
P-MOSFET Current Limit
ILIM
4
--
--
A
Copyright © 2019 Richtek Technology Corporation. All rights reserved.
www.richtek.com
4
is a registered trademark of Richtek Technology Corporation.
DS8068A-08 June 2019
RT8068A
Parameter
Min
Typ
Max
VIN rising
2.2
2.4
2.6
VIN falling
2
2.2
2.4
VIH
1.6
--
--
VIL
--
--
0.4
--
500
--
k
--
150
--
C
--
20
--
C
500
--
-100
---
s
VOUT Over-Voltage Protection
(Latch-Off, Delay Time = 10s)
115
120
130
%
VOUT Under-Voltage Lock Out
(Latch-Off)
57
66
75
%
85
90
--
%
--
5
--
%
Under-Voltage Lockout
Threshold
Logic-High
EN Input
Threshold Voltage Logic-Low
Symbol
VUVLO
Test Conditions
EN Pull Low Resistance
Over-Temperature Protection
TSD
Over-Temperature Protection
Hysteresis
Soft-Start Time
VOUT Discharge Resistance
tSS
Power Good
Measured FB, with respect to
VREF
Power Good Hysteresis
Unit
V
V
Note 1. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation of the device at these or any other conditions beyond those
indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating
conditions may affect device reliability.
Note 2. θJA is measured at TA = 25°C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. θJC is
measured at the exposed pad of the package.
Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
Note 5. Guaranteed by design.
Copyright © 2019 Richtek Technology Corporation. All rights reserved.
DS8068A-08 June 2019
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
5
RT8068A
Typical Operating Characteristics
Efficiency vs. Load Current
Efficiency vs. Load Current
100
100
90
80
VIN = 3.3V
VIN = 5V
80
70
Efficiency (%)
Efficiency (%)
90
VIN = 4.2V
VIN = 5V
60
50
40
30
20
70
60
50
40
30
20
10
10
VOUT = 3.3V
0
VOUT = 1.8V
0
0
0.5
1
1.5
2
2.5
3
0
0.5
1
Load Current (A)
2.5
3
1.820
90
1.815
70
Output Voltage (V)
VIN = 3.3V
VIN = 5V
80
Efficiency (%)
2
Output Voltage vs. Output Current
Efficiency vs. Load Current
100
60
50
40
30
20
1.810
1.805
1.800
VIN = 5V
1.795
VIN = 3.3V
1.790
1.785
10
VOUT = 1.05V
VOUT = 1.8V
0
1.780
0
0.5
1
1.5
2
2.5
3
0
0.5
1
1.5
2
2.5
3
Output Current (A)
Load Current (A)
Current Limit vs. Temperature
Current Limit vs. Input Voltage
7.0
7.0
6.5
6.5
6.0
6.0
Current Limit (A)
Current Limit (A)
1.5
Load Current (A)
5.5
5.0
4.5
4.0
3.5
VIN = 5V
5.5
VIN = 3.3V
5.0
4.5
4.0
3.5
VOUT = 1.05V
3.0
VOUT = 1.05V
3.0
2.5
3
3.5
4
4.5
5
Input Voltage (V)
Copyright © 2019 Richtek Technology Corporation. All rights reserved.
www.richtek.com
6
5.5
-50
-25
0
25
50
75
100
125
Temperature (°C)
is a registered trademark of Richtek Technology Corporation.
DS8068A-08 June 2019
RT8068A
RDS(ON) vs. Temperature
Load Transient Response
90
85
80
Ω)
RDS(ON) (mΩ
VOUT
(50mV/Div)
P-MOSFET
75
70
65
60
55
IOUT
(2A/Div)
50
45
N-MOSFET
40
VIN = 5V
VIN = 5V, VOUT = 1.8V, IOUT = 0.5A to 3A
35
-50
-25
0
25
50
75
100
Time (50μs/Div)
125
Temperature (°C)
Load Transient Response
VOUT
(50mV/Div)
Switching
VOUT
(5mV/Div)
VLX
(5V/Div)
IOUT
(2A/Div)
VIN = 5V, VOUT = 1.8V, IOUT = 1.5A to 3A
ILX
(1A/Div)
VIN = 5V, VOUT = 1.8V, IOUT = 1.5A
Time (50μs/Div)
Time (500ns/Div)
Switching
Over Voltage Protection
VOUT
(5mV/Div)
VLX
(5V/Div)
VOUT
(1V/Div)
ILX
(2A/Div)
VLX
(2V/Div)
VIN = 5V, VOUT = 1.8V, IOUT = 3A
Time (500ns/Div)
Copyright © 2019 Richtek Technology Corporation. All rights reserved.
DS8068A-08 June 2019
VIN = 5V, VOUT = 1.8V, IOUT = 1A
Time (10μs/Div)
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
7
RT8068A
Under Voltage Protection
Over Current Protection
VIN = 5V, VOUT = 1.8V
VIN = 5V, VOUT = 1.8V
VOUT
(1V/Div)
VOUT
(1V/Div)
ILX
(5A/Div)
VLX
(2V/Div)
VLX
(2V/Div)
Time (5μs/Div)
Time (2.5μs/Div)
Power On from VIN
Power Off from VIN
VIN
(2V/Div)
VIN
(2V/Div)
VOUT
(1V/Div)
VOUT
(1V/Div)
ILX
(2A/Div)
ILX
(2A/Div)
VOUT = 1.8V, IOUT = 3A
Time (2.5ms/Div)
Time (2.5ms/Div)
Power On from EN
Power Off from EN
VEN
(5V/Div)
VEN
(5V/Div)
VOUT
(1V/Div)
VOUT
(1V/Div)
ILX
(2A/Div)
ILX
(2A/Div)
VIN = 5V, VOUT = 1.8V, IOUT = 3A
Time (200μs/Div)
Copyright © 2019 Richtek Technology Corporation. All rights reserved.
www.richtek.com
8
VOUT = 1.8V, IOUT = 3A
VIN = 5V, VOUT = 1.8V, IOUT = 3A
Time (40μs/Div)
is a registered trademark of Richtek Technology Corporation.
DS8068A-08 June 2019
RT8068A
Application Information
The RT8068A is a single-phase buck converter. It provides
single feedback loop, current mode control with fast
transient response. An internal 0.6V reference allows the
output voltage to be precisely regulated for low output
voltage applications. A fixed switching frequency (1MHz)
oscillator and internal compensation are integrated to
minimize external component count. Protection features
include over-current protection, under-voltage protection,
over-voltage protection and over-temperature protection.
UVLO Protection
Output Voltage Setting
Inductor Selection
Connect a resistive voltage divider at the FB between VOUT
and GND to adjust the output voltage. The output voltage
is set according to the following equation :
R
VOUT = VREF 1 + FB1
R
FB2
where VREF is 0.6V (typ.).
The switching frequency (on-time) and operating point (%
ripple or LIR) determine the inductor value as shown below:
VOUT
RFB1
FB
RFB2
GND
Figure 1. Setting VOUT with a Voltage Divider
Chip Enable and Disable
The RT8068A has input under voltage lockout protection
(UVLO). If the input voltage exceeds the UVLO rising
threshold voltage (2.4V typ.), the converter resets and
prepares the PWM for operation. If the input voltage falls
below the UVLO falling threshold voltage during normal
operation, the device will stop switching. The UVLO rising
and falling threshold voltage has a hysteresis to prevent
noise-caused reset.
L=
VOUT VIN VOUT
fSW LIR ILOAD(MAX) VIN
where LIR is the ratio of the peak-to-peak ripple current to
the average inductor current.
Find a low loss inductor having the lowest possible DC
resistance that fits in the allotted dimensions. Ferrite cores
are often the best choice, although powdered iron is
inexpensive and can work well at 200kHz. The core must
be large enough not to saturate at the peak inductor current
(IPEAK) :
IPEAK = ILOAD(MAX) + LIR ILOAD(MAX)
2
The EN pin allows for power sequencing between the
controller bias voltage and another voltage rail. The
RT8068A remains in shutdown if the EN pin is lower than
400mV. When the EN pin rises above the VEN trip point,
the RT8068A begins a new initialization and soft-start cycle.
The calculation above serves as a general reference. To
further improve transient response, the output inductor
can be further reduced. This relation should be considered
along with the selection of the output capacitor.
Internal Soft-Start
Input Capacitor Selection
The RT8068A provides an internal soft-start function to
prevent large inrush current and output voltage overshoot
when the converter starts up. The soft-start (SS)
automatically begins once the chip is enabled. During softstart, the internal soft-start capacitor becomes charged
and generates a linear ramping up voltage across the
capacitor. This voltage clamps the voltage at the FB pin,
causing PWM pulse width to increase slowly and in turn
reduce the output surge current. The internal 0.6V
reference takes over the loop control once the internal
ramping-up voltage becomes higher than 0.6V.
High quality ceramic input decoupling capacitor, such as
X5R or X7R, with values greater than 20μF are
recommended for the input capacitor. The X5R and X7R
ceramic capacitors are usually selected for power regulator
capacitors because the dielectric material has less
capacitance variation and more temperature stability.
Copyright © 2019 Richtek Technology Corporation. All rights reserved.
DS8068A-08 June 2019
Voltage rating and current rating are the key parameters
when selecting an input capacitor. Generally, selecting an
input capacitor with voltage rating 1.5 times greater than
the maximum input voltage is a conservatively safe design.
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
9
RT8068A
The input capacitor is used to supply the input RMS
current, which can be approximately calculated using the
following equation :
VOUT VOUT
IIN_RMS = ILOAD
1
VIN
VIN
during load transient. However, the ceramic capacitor can
only provide low capacitance value. Therefore, use a mixed
combination of electrolytic capacitor and ceramic capacitor
to obtain better transient performance.
The next step is selecting a proper capacitor for RMS
current rating. One good design is using more than one
capacitor with low equivalent series resistance (ESR) in
parallel to form a capacitor bank.
Power Good Output (PGOOD)
The input capacitance value determines the input ripple
voltage of the regulator. The input voltage ripple can be
approximately calculated using the following equation :
IOUT(MAX) 0.25
VIN =
CIN fSW
For example, if IOUT_MAX = 3A, CIN = 20μF, fSW = 1MHz,
the input voltage ripple will be 37.5mV.
Output Capacitor Selection
The output capacitor and the inductor form a low pass
filter in the buck topology. In steady state condition, the
ripple current flowing into/out of the capacitor results in
ripple voltage. The output voltage ripple (VP-P) can be
calculated by the following equation :
VP_P
1
= LIR ILOAD(MAX) ESR +
8 COUT fSW
When load transient occurs, the output capacitor supplies
the load current before the controller can respond.
Therefore, the ESR will dominate the output voltage sag
during load transient. The output voltage undershoot (VSAG)
can be calculated by the following equation :
VSAG = ILOAD ESR
For a given output voltage sag specification, the ESR value
can be determined.
Another parameter that has influence on the output voltage
sag is the equivalent series inductance (ESL). The rapid
change in load current results in di/dt during transient.
Therefore, the ESL contributes to part of the voltage sag.
Using a capacitor with low ESL can obtain better transient
performance. Generally, using several capacitors
connected in parallel can have better transient performance
than using a single capacitor for the same total ESR.
PGOOD is an open-drain type output and requires a pullup resistor. PGOOD is actively held low in soft-start,
standby, and shutdown. It is released when the output
voltage rises above 90% of nominal regulation point. The
PGOOD signal goes low if the output is turned off or is
10% below its nominal regulation point.
Under-Voltage Protection (UVP)
The output voltage can be continuously monitored for under
voltage. When under-voltage protection is enabled, both
UGATE and LGATE gate drivers will be forced low if the
output is less than 66% of its set voltage threshold. The
UVP will be ignored for at least 3ms (typ.) after start up or
a rising edge on the EN threshold. Toggle EN threshold or
cycle VIN to reset the UVP fault latch and restart the
controller.
Over-Voltage Protection (OVP)
The RT8068A is latched once OVP is triggered and can
only be released by toggling EN threshold or cycling VIN.
There is a 10μs delay built into the over-voltage protection
circuit to prevent false transition.
Over-Current Protection (OCP)
The RT8068A provides over-current protection by detecting
high-side MOSFET peak inductor current. If the sensed
peak inductor current is over the current limit threshold
(4A typ.), the OCP will be triggered. When OCP is tripped,
the RT8068A will keep the over current threshold level
until the over current condition is removed.
Internal Output Voltage Discharge
An internal open-drain logic output is implemented on LX
pin. During the conditions of OVP, UVP, OTP and enable
low, the internal discharge path is activated and the left
energy from output terminal is able to be released with an
internal resistance about 100Ω to ground.
Unlike the electrolytic capacitor, the ceramic capacitor has
relatively low ESR and can reduce the voltage deviation
Copyright © 2019 Richtek Technology Corporation. All rights reserved.
www.richtek.com
10
is a registered trademark of Richtek Technology Corporation.
DS8068A-08 June 2019
RT8068A
The device implements an internal thermal shutdown
function when the junction temperature exceeds 150°C.
The thermal shutdown forces the device to stop switching
when the junction temperature exceeds the thermal
shutdown threshold. Once the die temperature decreases
below the hysteresis of 20°C, the device reinstates the
power up sequence.
Thermal Considerations
For continuous operation, do not exceed absolute
maximum junction temperature. The maximum power
dissipation depends on the thermal resistance of the IC
package, PCB layout, rate of surrounding airflow, and
difference between junction and ambient temperature. The
maximum power dissipation can be calculated by the
following formula :
PD(MAX) = (TJ(MAX) − TA) / θJA
where TJ(MAX) is the maximum junction temperature, TA is
the ambient temperature, and θJA is the junction to ambient
thermal resistance.
For recommended operating condition specifications, the
maximum junction temperature is 125°C and TA is the
ambient temperature. The junction to ambient thermal
resistance, θJA, is layout dependent. For SOP-8 (Exposed
Pad) packages, the thermal resistance, θJA, is 75°C/W
on a standard JEDEC 51-7 four-layer thermal test board.
For WDFN-10L 3x3 packages, the thermal resistance, θJA,
is 70°C/W on a standard JEDEC 51-7 four-layer thermal
test board. The maximum power dissipation at TA = 25°C
can be calculated by the following formulas :
PD(MAX) = (125°C − 25°C) / (75°C/W) = 1.333W for
SOP-8 (Exposed Pad) package
PD(MAX) = (125°C − 25°C) / (70°C/W) = 1.429W for
WDFN-10L 3x3 package
The maximum power dissipation depends on the operating
ambient temperature for fixed T J(MAX) and thermal
resistance, θJA. For the RT8068A package, the derating
curves in Figure 2 allow the designer to see the effect of
rising ambient temperature on the maximum power
dissipation.
Copyright © 2019 Richtek Technology Corporation. All rights reserved.
DS8068A-08 June 2019
Maximum Power Dissipation (W)1
Thermal Shutdown (OTP)
1.50
1.40
1.30
1.20
1.10
1.00
0.90
0.80
0.70
0.60
0.50
0.40
0.30
0.20
0.10
0.00
Four-Layer PCB
WDFN-10L 3x3
SOP-8 (Exposed Pad)
0
25
50
75
100
125
Ambient Temperature (°C)
Figure 2. Derating Curve of Maximum Power Dissipation
Layout Considerations
Layout is very important in high frequency switching
converter design. The PCB can radiate excessive noise
and contribute to converter instability with improper layout.
Certain points must be considered before starting a layout
using the RT8068A.
Make
the traces of the main current paths as short and
wide as possible.
Put the input capacitor as close as possible to the device
pins (VIN and GND).
LX node encounters high frequency voltage swings so it
should be kept in a small area. Keep sensitive
components away from the LX node to prevent stray
capacitive noise pick-up.
Ensure all feedback network connections are short and
direct. Place the feedback network as close to the chip
as possible.
The GND pin and Exposed Pad should be connected to
a strong ground plane for heat sinking and noise
protection.
An
example of PCB layout guide is shown in Figure 3.
for reference.
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
11
RT8068A
LX
LX
VOUT
LX
RPGOOD
PGOOD
VIN
EN
REN
1
2
3
4
5
11
LX should be connected to
inductor by wide and short trace.
Keep sensitive components
away from this trace.
10
9
8
7
6
PVIN
PVIN
SVIN
NC
FB
CIN1
CIN2
R2
R1
VOUT
COUT
Input capacitor must be placed
as close to the IC as possible.
GND
GND
The output capacitor must
be placed near the IC.
The voltage divider must
be connected as close to
the device as possible.
Figure 3. PCB Layout Guide
Copyright © 2019 Richtek Technology Corporation. All rights reserved.
www.richtek.com
12
is a registered trademark of Richtek Technology Corporation.
DS8068A-08 June 2019
RT8068A
Outline Dimension
D2
D
L
E
E2
1
e
SEE DETAIL A
b
2
1
2
1
A
A1
A3
DETAIL A
Pin #1 ID and Tie Bar Mark Options
Note : The configuration of the Pin #1 identifier is optional,
but must be located within the zone indicated.
Symbol
Dimensions In Millimeters
Dimensions In Inches
Min
Max
Min
Max
A
0.700
0.800
0.028
0.031
A1
0.000
0.050
0.000
0.002
A3
0.175
0.250
0.007
0.010
b
0.180
0.300
0.007
0.012
D
2.950
3.050
0.116
0.120
D2
2.300
2.650
0.091
0.104
E
2.950
3.050
0.116
0.120
E2
1.500
1.750
0.059
0.069
e
L
0.500
0.350
0.020
0.450
0.014
0.018
W-Type 10L DFN 3x3 Package
Copyright © 2019 Richtek Technology Corporation. All rights reserved.
DS8068A-08 June 2019
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
13
RT8068A
H
A
M
EXPOSED THERMAL PAD
(Bottom of Package)
Y
J
X
B
F
C
I
D
Dimensions In Millimeters
Symbol
Dimensions In Inches
Min
Max
Min
Max
A
4.801
5.004
0.189
0.197
B
3.810
4.000
0.150
0.157
C
1.346
1.753
0.053
0.069
D
0.330
0.510
0.013
0.020
F
1.194
1.346
0.047
0.053
H
0.170
0.254
0.007
0.010
I
0.000
0.152
0.000
0.006
J
5.791
6.200
0.228
0.244
M
0.406
1.270
0.016
0.050
X
2.000
2.300
0.079
0.091
Y
2.000
2.300
0.079
0.091
X
2.100
2.500
0.083
0.098
Y
3.000
3.500
0.118
0.138
Option 1
Option 2
8-Lead SOP (Exposed Pad) Plastic Package
Richtek Technology Corporation
14F, No. 8, Tai Yuen 1st Street, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: (8863)5526789
Richtek products are sold by description only. Customers should obtain the latest relevant information and data sheets before placing orders and should verify
that such information is current and complete. Richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek
product. Information furnished by Richtek is believed to be accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use;
nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent
or patent rights of Richtek or its subsidiaries.
www.richtek.com
14
DS8068A-08 June 2019
工商网监
湘ICP备2023018690号
