®
RT8073
6A, 2MHz, High Efficiency Synchronous Step-Down Converter
General Description
Features
The RT8073 is a high efficiency PWM step-down converter
and capable of delivering 6A output current over a wide
input voltage range from 2.9V to 5.5V.
The RT8073 provides accurate regulation for a variety of
loads with an ±1% reference voltage at room temperature.
For reducing inductor size, it provides up to 2MHz
switching frequency. The efficiency is maximized through
the integrated 50mΩ for high side, 35mΩ for low side
MOSFETs and 250μA typical supply current.
The RT8073 features over current protection, frequency
fold back function in shorted circuit, hiccup mode under
voltage protection and over temperature protection.
The RT8073 is available in SOP-8 (Exposed Pad) and
WDFN-12L 3x3 packages.
Ω MOSFETs
Integrated 50mΩ
Ω and 35mΩ
6A Output Current
High Efficiency Up to 95%
2.9V to 5.5V Input Range
Adjustable PWM Frequency : 300kHz to 2MHz
0.8V ±1% Reference Voltage
Adjustable External Soft-Start
Power Good Indicator (WDFN-12L 3x3 only)
Over Current Protection
Under Voltage Protection
Over Temperature Protection
SOP-8 (Exposed Pad) and 12-Lead WDFN Packages
RoHS Compliant and Halogen Free
Applications
Ordering Information
RT8073
Package Type
SP : SOP-8 (Exposed Pad-Option 2)
QW : WDFN-12L 3x3 (W-Type)
(Exposed Pad-Option 1)
Low Voltage, High Density Power Systems
Distributed Power Systems
Point-of-Load Conversions
Marking Information
RT8073GSP
RT8073GSP : Product Number
RT8073
GSPYMDNN
Lead Plating System
G : Green (Halogen Free and Pb Free)
YMDNN : Date Code
Note :
RT8073GQW
Richtek products are :
5C= : Product Code
RoHS compliant and compatible with the current require-
YMDNN : Date Code
5C=YM
DNN
ments of IPC/JEDEC J-STD-020.
Suitable for use in SnPb or Pb-free soldering processes.
Simplified Application Circuit
VIN
VIN
BOOT
RT8073
CIN
CBOOT
L
LX
EN
RC
CC
RT
RT
RFB1
FB
GND
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DS8073-02 August 2014
VOUT
COUT
COMP
RFB2
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RT8073
Pin Configurations
COMP
GND
2
EN
3
VIN
4
PGND
8
FB
7
RT
6
LX
5
BOOT
9
COMP
PGOOD
SS
EN
VIN
VIN
SOP-8 (Exposed Pad)
1
2
3
4
5
6
PGND
(TOP VIEW)
13
12
11
10
9
8
7
FB
RT
LX
LX
LX
BOOT
WDFN-12L 3x3
Functional Pin Description
Pin No.
Pin Function
Pin Name
SOP-8
(Exposed Pad)
WDFN-12L 3x3
1
1
COMP
Compensation Node.
2
--
GND
Analog Ground.
3
4
EN
Chip Enable. Externally pulled high to enable and pulled low to
disable this chip, and it is internally pulled up to high when the
pin is floating.
4
5, 6
VIN
Power Input.
5
7
BOOT
Bootstrap Supply for High Side Gate Driver.
6
8, 9, 10
LX
Switch Node.
7
11
RT
Frequency Setting.
8
12
FB
Feedback Voltage Input.
9
13
(Exposed Pad)
PGND
Power Ground. The exposed pad must be shouldered to a
large PCB and connected to PGND for maximum power
dissipation.
--
2
PGOOD
Power Good Indicator with Open Drain Output. It is high
impedance when the output voltage is regulated. It is internally
pulled low when the chip is shutdown, thermal shutdown or
VIN is under UVLO threshold.
--
3
SS
Soft-Start Control.
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is a registered trademark of Richtek Technology Corporation.
DS8073-02 August 2014
RT8073
Function Block Diagram
For SOP-8 (Exposed Pad) Package
VIN
VIN
Over Temperature
Protection
Internal
pull up
current
EN
EN Threshold
UVLO
Shutdown
Control
Current
Sense
GND
BOOT
RT
Oscillator
Control
Logic
Slope
Compensation
Soft-Start
Driver
LX
PWM
Comparator
Voltage
Reference
Error
Amplifier
FB
PGND
COMP
For WDFN-12L 3x3 Package
VIN
VIN
Internal
pull up
current
EN
EN Threshold
RT
UVLO
Shutdown
Control
Current
Sense
BOOT
Oscillator
VIN
SS
Over Temperature
Protection
SoftStart
Voltage
Reference
Control
Logic
Slope
Compensation
Driver
LX
PWM
Comparator
Error
Amplifier
PGND
FB
PGOOD
Power Good
Threshold
COMP
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RT8073
Operation
The RT8073 is a current mode synchronous step-down
DC/DC converter with two integrated power MOSFETs. It
can deliver up to 6A output current from a 2.9V to 5.5V
input supply. The RT8073's current mode architecture
allows the transient response to be optimized over a wide
input voltage and load range. Cycle-by-cycle current limit
provides protection against shorted outputs and soft-start
eliminates input current surge during start-up.
PGOOD Comparator
When the feedback voltage (VFB) rises above 94% or falls
below 106% of reference voltage, the PGOOD open drain
output will be high impedance. The PGOOD open drain
output will be internally pulled low when the feedback
voltage (VFB) falls below 90% or rises above 110% of
reference voltage.
Soft-Start (SS)
Error Amplifier
The error amplifier adjusts COMP voltage by comparing
the feedback signal (VFB) from the output voltage with the
internal 0.8V reference. When the load current increases,
it causes a drop in the feedback voltage relative to the
reference, the COMP voltage then rises to allow higher
inductor current to match the load current.
Oscillator (OSC)
The frequency of the oscillator is adjustable by an external
resistor connected between the RT pin and GND. The
available switching frequency range is from 300kHz to
2MHz.
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An internal current source charges an external capacitor
to build the soft-start ramp voltage (VSS). The VFB voltage
will track the VSS during soft-start interval. The chip will
use internal soft-start if the SS pin is floating. The nominal
internal soft-start time is 800μs.
Over Temperature Protection (OTP)
The RT8073 implements an internal over temperature
protection. When junction temperature is higher than
165°C, it will stop switching operation. Once the junction
temperature decreases below 145°C, the RT8073 will
automatically resume switching.
is a registered trademark of Richtek Technology Corporation.
DS8073-02 August 2014
RT8073
Absolute Maximum Ratings
(Note 1)
Supply Input Voltage, VIN ----------------------------------------------------------------------------------------BOOT to LX ----------------------------------------------------------------------------------------------------------Other Pins ------------------------------------------------------------------------------------------------------------Power Dissipation, PD @ TA = 25°C
SOP-8 (Exposed Pad) --------------------------------------------------------------------------------------------WDFN-12L 3x3 ------------------------------------------------------------------------------------------------------Package Thermal Resistance (Note 2)
SOP-8 (Exposed Pad), θJA ---------------------------------------------------------------------------------------SOP-8 (Exposed Pad), θJC --------------------------------------------------------------------------------------WDFN-12L 3x3, θJA ------------------------------------------------------------------------------------------------WDFN-12L 3x3, θJC ------------------------------------------------------------------------------------------------Lead Temperature (Soldering, 10 sec.) ------------------------------------------------------------------------Junction Temperature ----------------------------------------------------------------------------------------------Storage Temperature Range -------------------------------------------------------------------------------------ESD Susceptibility (Note 3)
HBM (Human Body Model) ----------------------------------------------------------------------------------------
Recommended Operating Conditions
−0.3V to 6.5V
−0.3V to 6V
−0.3V to (VIN + 0.3V)
2.041W
1.667W
49°C/W
15°C/W
60°C/W
7.5°C/W
260°C
150°C
−65°C to 150°C
2kV
(Note 4)
Supply Input Voltage, VIN ----------------------------------------------------------------------------------------- 2.9V to 5.5V
Junction Temperature Range -------------------------------------------------------------------------------------- −40°C to 125°C
Ambient Temperature Range -------------------------------------------------------------------------------------- −40°C to 85°C
Electrical Characteristics
(VIN = 5V, CIN = 10μF, TA = 25°C, unless otherwise specified)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
Input Power Supply
Under Voltage Lockout Threshold
VUVLO
VIN Rising
--
2.6
2.8
V
Quiescent Current
IQ
Active, VFB = 0.9V, Not switching
--
250
--
A
Shutdown Current
ISHDN
--
2
5
A
VREF
0.792
0.8
0.808
V
Voltage Reference
Voltage Reference
Enable
Logic-High
VIH
1.5
--
5.5
Logic-Low
VIL
--
--
0.4
300
--
2000
RT = 28.7k
--
1400
--
RT pin is floating
--
300
--
Minimum On-Time
--
80
--
ns
Minimum Off-Time
--
60
--
ns
EN Input Voltage
V
Switching Frequency Setting
Switching Frequency
fOSC
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kHz
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RT8073
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
MOSFET
High Side MOSFET On-resistance
VIN = 5V, BOOT LX = 5V
--
50
--
m
Low Side MOSFET On-resistance
VIN = 5V
--
35
--
m
7
9
--
A
VFB Rising (Good)
--
94
--
VFB Falling (Fault)
--
90
--
VFB Rising (Fault)
--
110
--
VFB Falling (Good)
--
106
--
Rising
--
165
--
C
--
20
--
C
Current Limit
Current Limit Threshold
Power Good
Power Good Range
(WDFN-12L 3x3 only)
% VREF
Over Temperature Protection
Thermal Shutdown
Thermal Shutdown Hysteresis
Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in
the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may
affect device reliability.
Note 2. θJA is measured at TA = 25°C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. θJC is
measured at the exposed pad of the package.
Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
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RT8073
Typical Application Circuit
VIN
VIN
CIN1
10µF
BOOT
RT8073
CIN2
10µF
RPG
100k
VOUT
L
LX
PGOOD
Chip Enable
CBOOT
0.1µF
COUT1
10µF
EN
PGND
SS
RT
CSS
10nF R
T
28.7k
RFB1
COUT3
47µF to
100µF
GND
COMP
CHF*
COUT2
10µF
RC
FB
CC
RFB2
* : Option
Table 1. Recommended Component Selection
VOUT (V)
RFB (k)
RFB2 (k)
RC (k)
CC (nF)
L (H)
COUT
3.3
75
24
33
0.33
0.47
Cer. 20F + E-Cap 100F
2.5
51
24
24
0.47
0.47
Cer. 20F + E-Cap 100F
1.8
30
24
18
0.56
0.47
Cer. 20F + E-Cap 100F
1.5
21
24
15
0.68
0.33
Cer. 20F + E-Cap 100F
1.2
12
24
12
1
0.33
Cer. 20F + E-Cap 100F
1
6
24
10
1
0.33
Cer. 20F + E-Cap 100F
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RT8073
Typical Operating Characteristics
Output Voltage vs. Input Voltage
1.20
90
1.18
80
1.16
70
Output Voltage (V)
Efficiency (%)
Efficiency vs. Load Current
100
VIN = 3.3V
VIN = 4V
VIN = 5V
60
50
40
30
1.14
1.12
1.10
1.08
1.06
20
1.04
10
1.02
VOUT = 1.1V
0
0.001
VOUT = 1.1V
1.00
0.01
0.1
1
10
2.5
3
3.5
Load Current (A)
4
4.5
5
5.5
Input Voltage (V)
Output Voltage vs. Temperature
Output Voltage vs. Output Current
1.16
1.18
1.15
1.16
1.14
Output Voltage (V)
Output Voltage (V)
1.14
1.13
1.12
1.11
1.10
1.09
1.12
1.10
VIN = 5V
VIN = 4V
VIN = 3.3V
1.08
1.06
1.08
1.04
1.07
VIN = 5V, VOUT = 1.1V, IOUT = 1.5A
VOUT = 1.1V
1.06
1.02
-50
-25
0
25
50
75
100
0.0
125
0.6
1.2
1.8
Temperature (°C)
Frequency vs. Input Voltage
3.0
3.6
4.2
4.8
5.4
6.0
Switching Frequency vs. Temperature
1.8
1.8
1.7
1.7
Switching Frequency (MHz)1
Frequency (MHz)1
2.4
Output Current (A)
1.6
1.5
1.4
1.3
1.2
1.1
1.6
1.5
1.4
1.3
1.2
1.1
VOUT = 1.1V, IOUT = 1.3A
VOUT = 1.1V, IOUT = 1.3A
1.0
1.0
2.5
3
3.5
4
4.5
5
Input Voltage (V)
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5.5
-50
-25
0
25
50
75
100
125
Temperature (°C)
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RT8073
Currrent Limit vs. Temperature
Currrent Limit vs. Input Voltage
10.0
12.0
11.5
9.5
Currrent Limit (A)
Currrent Limit (A)
11.0
10.5
10.0
9.5
9.0
8.5
8.0
9.0
8.5
8.0
7.5
7.5
VOUT = 1.1V
VIN = 5V, VOUT = 1.1V
7.0
7.0
-50
-25
0
25
50
75
100
2.5
125
3
3.5
4
4.5
5
Temperature (°C)
Input Voltage (V)
Load Transient Response
Load Transient Response
VOUT
(100mV/Div)
VOUT
(100mV/Div)
IOUT
(2A/Div)
IOUT
(2A/Div)
VIN = 5V, VOUT = 1.1V, IOUT = 0A to 3A
VIN = 5V, VOUT = 1.1V, IOUT = 0A to 6A
Time (100μs/Div)
Time (100μs/Div)
Output Ripple Voltage
Output Ripple Voltage
VOUT
(20mV/Div)
VOUT
(20mV/Div)
VLX
(5V/Div)
VLX
(5V/Div)
VIN = 5V, VOUT = 1.1V, IOUT = 6A
Time (250ns/Div)
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
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5.5
VIN = 5V, VOUT = 3.3V, IOUT = 6A
Time (250ns/Div)
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RT8073
Power On from VIN
Power Off from VIN
VIN
(5V/Div)
VIN
(5V/Div)
VOUT
(2V/Div)
VOUT
(2V/Div)
ILX
(5A/Div)
ILX
(5A/Div)
VIN = 5V, VOUT = 3.3V, IOUT = 6A
VIN = 5V, VOUT = 3.3V, IOUT = 6A
Time (1ms/Div)
Time (10ms/Div)
Power On from EN
Power Off from EN
VEN
(5V/Div)
VEN
(5V/Div)
VOUT
(2V/Div)
VOUT
(2V/Div)
ILX
(5A/Div)
ILX
(5A/Div)
VIN = 5V, VOUT = 3.3V, IOUT = 6A
Time (250μs/Div)
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VIN = 12V, VOUT = 1.05V, IOUT = 3A
Time (10ms/Div)
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RT8073
Application Information
The basic RT8073 application circuit is shown in Typical
Application Circuit. External component selection is
determined by the maximum load current and begins with
the selection of the inductor value and operating frequency
followed by CIN and COUT.
Output Voltage Setting
The output voltage is set by an external resistive divider
according to the following equation :
R
VOUT VREF 1 FB1
R
FB2
The operating frequency of the RT8073 is determined by
an external resistor that is connected between the SHDN/
RT pin and GND. The value of the resistor sets the ramp
current that is used to charge and discharge an internal
timing capacitor within the oscillator. The RT resistor value
can be determined by examining the frequency vs. RT
curve. Although frequency as high as 2MHz is possible,
the minimum on-time of the RT8073 imposes a minimum
limit on the operating duty cycle. The minimum on-time
is typically 80ns. Therefore, the minimum duty cycle is
equal to 100 x 80ns x f (Hz).
where VREF equals to 0.8V (typical)
VOUT
RFB1
FB
RT8073
RFB2
GND
Switching Frequency (MHz)1
The resistive divider allows the FB pin to sense a fraction
of the output voltage as shown in Figure 1.
3.0
2.5
2.0
1.5
1.0
0.5
Figure 1. Setting the Output Voltage
0.0
Soft-Start (SS)
An internal current source charges an external capacitor
to build the soft-start ramp voltage (VSS). The VFB voltage
will track the VSS during soft-start interval. The chip will
use internal soft-start if the SS pin is floating. The nominal
internal soft-start time is 800μs.
With external soft-start, the typical soft-start time can be
calculated as following equation :
tSS (ms) = 0.1 x CSS (nF)
For example, if CSS = 10nF, the soft-start time is 1ms.
0
20
40
60
80
100 120 140 160 180 200
RT (k Ω)
Figure 2
Chip Enable Operation
The EN pin is the chip enable input. Pulling the EN pin
low (1.5V, 5.5V) will turn on the
device again. For external timing control, the EN pin can
also be externally pulled high by adding a REN resistor
and CEN capacitor from the VIN pin (see Figure 3).
Operating Frequency
Selection of the operating frequency is a tradeoff between
efficiency and component size. High frequency operation
allows the use of smaller inductor and capacitor values.
Operation at lower frequency improves efficiency by
reducing internal gate charge and switching losses but
requires larger inductance and/or capacitance to maintain
low output ripple voltage.
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EN
VIN
REN
CEN
EN
RT8073
GND
Figure 3. Enable Timing Control
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RT8073
An external MOSFET can be added to implement digital
control on the EN pin when no system voltage above 1.5V
is available, as shown in Figure 4. In this case, the pull-up
resistor, REN, is connected between VIN and the EN pin.
MOSFET Q1 will be under logic control to pull down the
EN pin.
VIN
EN
Hiccup Mode
VOUT
(500mV/Div)
REN
EN
Q1
RT8073
ILX
(5A/Div)
GND
VOUT short to GND
Time (1ms/Div)
Figure 4. Digital Enable Control Circuit
Figure 5. Hiccup Mode Under Voltage Protection
Slope Compensation and Inductor Peak Current
Slope compensation provides stability in constant
frequency architectures by preventing sub-harmonic
oscillations at duty cycles greater than 50%. It is
accomplished internally by adding a compensating ramp
to the inductor current signal. Normally, the maximum
inductor peak current is reduced when slope compensation
is added. In the RT8073, however, separated inductor
current signals are used to monitor over current condition.
This keeps the maximum output current relatively constant
regardless of duty cycle.
Hiccup Mode
For the RT8073, it provides Hiccup Mode Under Voltage
Protection (UVP). When the output is shorted to ground,
the UVP function will be triggered to shut down switching
operation. If the under voltage condition remains for a
period, the RT8073 will retry automatically. When the under
voltage condition is removed, the converter will resume
operation. The UVP is disabled during soft-start period.
Inductor Selection
The inductor value and operating frequency determine the
ripple current according to a specific input and output
voltage. The ripple current ΔIL increases with higher VIN
and decreases with higher inductance.
V
V
IL = OUT 1 OUT
VIN
f L
Having a lower ripple current can reduce not only the ESR
losses in the output capacitors but also the output voltage
ripple. However, it requires a large inductor to achieve this
goal.
For the ripple current selection, the value of ΔIL = 0.4(IMAX)
will be a reasonable starting point. The largest ripple current
occurs at the highest VIN. To guarantee that the ripple
current stays below the specified maximum, the inductor
value should be chosen according to the following
equation :
VOUT
VOUT
L =
1
f
I
V
L(MAX)
IN(MAX)
The inductor's current rating (caused a 40°C temperature
rising from 25°C ambient) should be greater than the
maximum load current and its saturation current should
be greater than the short circuit peak current limit.
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RT8073
2.4
Maximum Power Dissipation (W)
Thermal Considerations
For continuous operation, do not exceed absolute
maximum junction temperature. The maximum power
dissipation depends on the thermal resistance of the IC
package, PCB layout, rate of surrounding airflow, and
difference between junction and ambient temperature. The
maximum power dissipation can be calculated by the
following formula :
PD(MAX) = (TJ(MAX) − TA) / θJA
where TJ(MAX) is the maximum junction temperature, TA is
the ambient temperature, and θJA is the junction to ambient
thermal resistance.
For recommended operating condition specifications, the
maximum junction temperature is 125°C. The junction to
ambient thermal resistance, θJA, is layout dependent. For
SOP-8 (Exposed Pad) packages, the thermal resistance,
θJA, is 49°C/W on a standard JEDEC 51-7 four-layer
thermal test board. For WDFN-12L 3x3 packages, the
thermal resistance, θJA, is 60°C/W on a standard JEDEC
51-7 four-layer thermal test board. The maximum power
dissipation at TA = 25°C can be calculated by the following
formulas :
PD(MAX) = (125°C − 25°C) / (49°C/W) = 2.041W for
SOP-8 (Exposed Pad) package
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DS8073-02 August 2014
2.0
1.8
1.6
1.4
WDFN-12L 3x3
1.2
1.0
0.8
0.6
0.4
0.2
0.0
0
25
50
75
100
125
Ambient Temperature (°C)
Figure 6. Derating Curve of Maximum Power Dissipation
Layout Considerations
Follow the PCB layout guidelines for optimal performance
of RT8073.
A ground plane is recommended. If a ground plane layer
is not used, the signal and power grounds should be
segregated with all small-signal components returning
to the GND pin at one point that is then connected to
the PGND pin close to the IC. The exposed pad should
be connected to GND.
Connect the terminal of the input capacitor(s), CIN, as
close as possible to the VIN pin. This capacitor provides
the AC current into the internal power MOSFETs.
LX node is with high frequency voltage swing and should
be kept within small area. Keep all sensitive small-signal
nodes away from the LX node to prevent stray capacitive
noise pick-up.
Flood all unused areas on all layers with copper.
Flooding with copper will reduce the temperature rise
of power components.
Connect the FB pin directly to the feedback resistors.
The resistor divider must be connected between VOUT
and GND.
PD(MAX) = (125°C − 25°C) / (60°C/W) = 1.667W for
WDFN-12L 3x3 package
The maximum power dissipation depends on the operating
ambient temperature for fixed T J(MAX) and thermal
resistance, θJA. The derating curves in Figure 6 allow the
designer to see the effect of rising ambient temperature
on the maximum power dissipation.
Four-Layer PCB
SOP-8 (Exposed Pad)
2.2
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RT8073
Connect the FB pin directly to feedback resistors. The
resistor divider must be connected between VOUT and GND.
CC
GND
RC
COMP
PGOOD
GND
CSS SS
EN
REN
VIN
VIN
CIN must be placed
between VIN and GND
as closer as possible.
1
2
3
4
5
6
12
11
10
9
8
7
PGND
RGOOD
RFB2
RFB1
13
FB
RT
GND
RT
LX
L
LX
LX
BOOT
CBOOT
VOUT
CIN
LX should be connected to
inductor by wide and short trace,
keep sensitive components away
from this trace.
COUT
Output capacitor
must be near RT8073
GND
Figure 7. PCB Layout Guide for WDFN-12L 3x3
Connect the FB pin directly to feedback resistors. The resistor
divider must be connected between VOUT and GND.
CC
GND
RC
RFB2
COMP
REN
CIN must be placed
between VIN and GND
as closer as possible.
GND
2
EN
3
VIN
4
PGND
8
FB
7
RT
6
LX
5
BOOT
9
RT
RFB1
VOUT
GND
L
LX should be connected to
inductor by wide and short trace,
keep sensitive components away
from this trace.
CBOOT
COUT
CIN
Output capacitor
must be near RT8073
GND
Figure 8. PCB Layout Guide for SOP-8 (Exposed Pad)
Recommended component selection for Typical Application
Table 2. Inductors
Component Supplier
Series
Inductance (H) DCR (m)
Wurth Elektronik
No.744308033
0.33
Wurth Elektronik
No.744355147
0.47
Current Rating (A)
Case Size
0.37
27
1070
0.67
30
1365
Table 3. Capacitors for CIN and COUT
Component Supplier
TDK
Part No.
C3225X5R0J226M
Capacitance (F)
22
Case Size
1210
TDK
C2012X5R0J106M
10
0805
Panasonic
ECJ4YB0J226M
22
1210
Panasonic
ECJ4YB1A106M
10
1210
TAIYO YUDEN
LMK325BJ226ML
22
1210
TAIYO YUDEN
JMK316BJ226ML
22
1206
TAIYO YUDEN
JMK212BJ106ML
10
0805
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
www.richtek.com
14
is a registered trademark of Richtek Technology Corporation.
DS8073-02 August 2014
RT8073
Outline Dimension
H
A
M
EXPOSED THERMAL PAD
(Bottom of Package)
Y
J
X
B
F
C
I
D
Dimensions In Millimeters
Dimensions In Inches
Symbol
Min
Max
Min
Max
A
4.801
5.004
0.189
0.197
B
3.810
4.000
0.150
0.157
C
1.346
1.753
0.053
0.069
D
0.330
0.510
0.013
0.020
F
1.194
1.346
0.047
0.053
H
0.170
0.254
0.007
0.010
I
0.000
0.152
0.000
0.006
J
5.791
6.200
0.228
0.244
M
0.406
1.270
0.016
0.050
X
2.000
2.300
0.079
0.091
Y
2.000
2.300
0.079
0.091
X
2.100
2.500
0.083
0.098
Y
3.000
3.500
0.118
0.138
Option 1
Option 2
8-Lead SOP (Exposed Pad) Plastic Package
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
DS8073-02 August 2014
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
15
RT8073
2
1
2
1
DETAIL A
Pin #1 ID and Tie Bar Mark Options
Note : The configuration of the Pin #1 identifier is optional,
but must be located within the zone indicated.
Symbol
D2
Dimensions In Millimeters
Min.
Max.
Min.
Max.
A
0.700
0.800
0.028
0.031
A1
0.000
0.050
0.000
0.002
A3
0.175
0.250
0.007
0.010
b
0.150
0.250
0.006
0.010
D
2.950
3.050
0.116
0.120
Option1
2.300
2.650
0.091
0.104
Option2
1.970
2.070
0.078
0.081
2.950
3.050
0.116
0.120
Option1
1.400
1.750
0.055
0.069
Option2
1.160
1.260
0.046
0.050
E
E2
Dimensions In Inches
e
L
0.450
0.350
0.018
0.450
0.014
0.018
W-Type 12L DFN 3x3 Package
Richtek Technology Corporation
14F, No. 8, Tai Yuen 1st Street, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: (8863)5526789
Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should
obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot
assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be
accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.
www.richtek.com
16
DS8073-02 August 2014
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