RT8101PSP

Preliminary RT8101/A 12V Synchronous Buck PWM DC-DC General Description The RT8101/A are DC/DC synchronous buck PWM controllers with embedded driver support up to 12V+12V boot-strapped voltage for high efficiency power driving. The parts are with full functions of voltage regulation, power monitoring and protection into a single small footprint packages SOP-8 and SOP-8 (Exposed Pad). The RT8101/A apply a high-gain voltage mode PWM control for simple application design. An internal 0.8V reference allows the output voltage to be precisely regulated to low voltage requirement. The parts are proposed with two type including RT8101 and RT8101A with fixed operating frequency of 300kHz and 600kHz respectively. Based on the features that RT8101/A offered, the parts provide an optimum solution between efficiency, total B.O.M. count, and cost. Features Single 12V Bias Supply Drives All Low Cost N-MOSFETs High-Gain Voltage Model PWM Control 300kHz/600kHz Fixed Frequency Oscillator Fast Transient Response : High-Speed GM Amplifier Full 0 to 100% Duty Ratio External Compensation in the Control Loop Internal Soft-Start Adaptive Non-Overlapping Gate Driver Over-Current Fault Monitor on MOSFET, No Current Sense Resistor Required RoHS Compliant and 100% Lead (Pb)-Free Applications Graphic Card Motherboard, Desktop Servers IA Equipments Telecomm Equipments High Power DC-DC Regulators Ordering Information RT8101/A Package Type S : SOP-8 SP : SOP-8 (Exposed Pad) Operating Temperature Range P : Pb Free with Commercial Standard G : Green (Halogen Free with Commercial Standard) 600kHz 300kHz Note : RichTek Pb-free and Green products are : RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020. Suitable for use in SnPb or Pb-free soldering processes. 100% matte tin (Sn) plating. Pin Configurations (TOP VIEW) BOOT UGATE GND LGATE 2 3 4 8 7 6 5 PHASE COMP FB VCC SOP-8 BOOT UGATE GND LGATE 2 3 4 GND 8 7 6 5 PHASE COMP FB VCC SOP-8(Exposed Pad) DS8101/A-01 March 2007 www.richtek.com 1 RT8101/A Typical Application Circuit 12V Preliminary RBOOT VIN(+3.3V/+5V/+12V) RT8101/A 1 5 6 3 BOOT VCC FB GND UGATE PHASE LGATE COMP 2 8 4 7 C PSC Q2 RUGATE Q1 CIN LOUT VOUT R COUT Functional Pin Description BOOT (Pin 1) Bootstrap supply for the upper gate driver. Connect the bootstrap capacitor between BOOT pin and the PHASE pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET. UGATE (Pin 2) Upper gate driver output. Connect to gate of the highside power N-Channel MOSFET. This pin is monitored by the adaptive shoot-through protection circuitry to determine when the upper MOSFET is turned off. GND (Pin 3) Signal ground for the IC. LGATE (Pin 4) Lower gate driver output. Connect to the gate of the lowside power N-Channel MOSFET. This pin is monitored by the adaptive shoot-through protection circuitry to determine when the lower MOSFET is turned off. VCC (Pin 5) Connect this pin to a well-decoupled 12V bias supply. It is also the positive supply for the lower gate driver, LGATE. FB (Pin 6) Buck converter feedback voltage. This pin is the inverting input of the error amplifier. FB senses the switcher output through an external resistor divider network. COMP (Pin 7) Buck converter external compensation. This pin is used to compensate the control loop of the buck converter. PHASE (Pin 8) Connect this pin to the source of the upper MOSFET and the drain of the lower MOSFET. This pin is monitored by the adaptive shoot-through protection circuitry to determine when the upper MOSFET is turned off. Exposed Pad Exposed pad should be soldered to PCB board and connected to GND. www.richtek.com 2 DS8101/A-01 March 2007 Preliminary Function Block Diagram VCC RT8101/A Voltage Reference Bias Enable Power On Reset (POR) 5V Regulator PH_M + 1.5V 5VDD + - POR 0.8V 0.4V Soft-Start & Fault Logic + - UV 30uA OC + 21.6k Driver Logic 0.4V SSE INHIBIT BOOT UGATE 0.8V FB + + EA - SS + + - PWM PHASE LGATE Oscillator COMP GND DS8101/A-01 March 2007 www.richtek.com 3 RT8101/A Absolute Maximum Ratings Preliminary (Note 1) Supply Voltage, VCC -------------------------------------------------------------------------------------- 16V BOOT, VBOOT - VPHASE ------------------------------------------------------------------------------------ 16V PHASE to GND DC ------------------------------------------------------------------------------------------------------------- −5V to 15V < 200ns ------------------------------------------------------------------------------------------------------ −10V to 30V BOOT to PHASE ------------------------------------------------------------------------------------------ 15V BOOT to GND DC ------------------------------------------------------------------------------------------------------------- −0.3V to VCC+15V < 200ns ------------------------------------------------------------------------------------------------------ −0.3V to 42V UGATE ------------------------------------------------------------------------------------------------------- VPHASE − 0.3V to VBOOT + 0.3V LGATE ------------------------------------------------------------------------------------------------------- GND − 0.3V to VCC + 0.3V Input, Output or I/O Voltage ----------------------------------------------------------------------------- GND − 0.3V to 7V Power Dissipation, PD @ TA = 25°C (Note 4) SOP-8 -------------------------------------------------------------------------------------------------------- 0.83W SOP-8 (Exposed Pad) ----------------------------------------------------------------------------------- 1.33W Package Thermal Resistance SOP-8, θJA -------------------------------------------------------------------------------------------------- 120°C/W SOP-8 (Exposed Pad), θJA ------------------------------------------------------------------------------ 75°C/W Junction Temperature ------------------------------------------------------------------------------------- 150°C Lead Temperature (Soldering, 10 sec.) --------------------------------------------------------------- 260°C Storage Temperature Range ---------------------------------------------------------------------------- −65°C to 150°C ESD Susceptibility (Note 2) HBM (Human Body Mode) ------------------------------------------------------------------------------ 2kV MM (Machine Mode) -------------------------------------------------------------------------------------- 200V Recommended Operating Conditions (Note 3) Supply Voltage, VCC -------------------------------------------------------------------------------------- 12V ± 10% Junction Temperature Range ---------------------------------------------------------------------------- −40°C to 125°C Ambient Temperature Range ---------------------------------------------------------------------------- −40°C to 85°C Electrical Characteristics (VCC = 12V, TA = 25°C, unless otherwise specified) Parameter S upply Input Supply Voltage Supply Current P ower-On Reset POR Threshold POR Hysteresis O scillator Free Running Frequency Symbol V CC ICC V CCRTH V CCHYS Test Conditions UGATE and LGATE Open VCC = 12V Min 10.8 -8 .8 -- Typ 12 3 9.6 0.8 300 600 Max 13.2 -10.4 1.6 350 700 Units V mA V V kHz kHz fOSC VCC = 1 2V, RT8101 VC C = 12V, RT8101A 250 500 To be continued www.richtek.com 4 DS8101/A-01 March 2007 Preliminary Parameter Ramp Amplitude Reference Voltage PWM Error Amplifier Reference E rror Amplifier O pen Loop DC Gain G ain-Bandwidth Product Slew Rate AO GBW SR V BOOT − VP HASE = 12V, V BOOT − V UGATE = 6V V BOOT − VP HASE = 12V, V BOOT − V UGATE = 1V V BOOT − V PHA SE = 12V, V UGATE − VPHASE = 1 V V CC = 12V, V LGATE = 6V V CC − VLG ATE = 1V V LGATE = 1V Measuring V FB VOC TSS M easuring V PHAS E ---VREF 0.792 Symbol ΔV OSC Test Conditions V CC = 12V Min -- RT8101/A Typ 1.5 0.8 88 15 6 Max -0.808 ---Units V P-P V dB MHz V/us P WM Controller Gate Drivers (V CC = 1 2V) Upper Gate Source Upper Gate Source Upper Gate Sink Lower Gate Source Lower Gate Source Lower Gate Sink P rotection Under Voltage Protection O ver Current Threshold Soft-Start Interval 0.3 −210 2 0.4 −250 3.2 0.5 −290 4.2 V mV ms IUGATE RUGATE RUGATE ILGATE RLGATE RLGATE ------300 7 4 500 4 2 -10 8 -6 4 mA Ω Ω mA Ω Ω Note 1. Stresses listed as the above "Absolute Maximum Ratings" may cause permanent damage to the device. These are for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. Note 2. Devices are ESD sensitive. Handling precaution recommended. Note 3. The device is not guaranteed to function outside its operating conditions. Note 4. θJA is measured in the natural convection at TA = 25°C on a high effective 4-layers thermal conductivity test board of JEDEC 51-7 thermal measurement standard. DS8101/A-01 March 2007 www.richtek.com 5 RT8101/A Preliminary Typical Operating Characteristics Efficiency vs. Output Current 1.00 100 0.8064 0.8043 Reference Voltage vs. Temperature Reference Voltage (V) 0.95 95 RT8101 0.8022 0.8001 0.7980 0.7959 0.7938 0.7917 Efficiency (%) 0.90 90 0.85 85 RT8101A 0.80 80 0.75 75 VCC = 12V VIN = 5V 0 2.5 5 7.5 10 12.5 15 17.5 20 22.5 25 VCC = 12V VIN = 5V -50 -25 0 25 50 75 100 125 Output Current (A) Temperature (°C) Output Voltage vs. Output Current 2.55 2.54 2.53 Output Voltage vs. Output Current 2.55 2.54 2.53 RT8101 RT8101A Output Voltage (V) 2.52 2.51 2.50 2.49 2.48 2.47 2.46 2.45 0 2.5 5 7.5 10 12.5 15 17.5 20 22.5 25 Output Voltage (V) 2.52 2.51 2.50 2.49 2.48 2.47 2.46 2.45 0 2.5 5 7.5 10 12.5 15 17.5 20 22.5 25 VIN = 12V VIN = 5V VIN = 12V VIN = 5V Output Current (A) Output Current (A) Frequency vs. Temperature 325 320 Frequency vs. Temperature 640 620 RT8101 RT8101A 315 Frequency (kHz) 310 305 300 295 290 Frequency (kHz) -40 -10 20 50 80 110 140 600 580 560 540 285 280 520 -40 -10 20 50 80 110 140 Temperature (°C) Temperature (°C) www.richtek.com 6 DS8101/A-01 March 2007 Preliminary RT8101/A Power Off from VCC Power On from VCC VOUT (2V/Div) VIN (10V/Div) V CC (10V/Div) UGATE (20V/Div) Time (5ms/Div) VOUT (2V/Div) VIN (10V/Div) V CC (10V/Div) UGATE (20V/Div) Time (5ms/Div) Power On from VIN Power On from VIN VOUT (2V/Div) VIN (10V/Div) VOUT (2V/Div) VIN (10V/Div) V CC (10V/Div) UGATE (20V/Div) Time (5ms/Div) Time (5ms/Div) V CC (10V/Div) UGATE (20V/Div) Dead Time (Rising) VCC = 12V VIN = 12V IOUT = 25A VCC = 12V VIN = 12V IOUT= 25A Dead Time (Falling) PHASE PHASE UGATE (5V/Div) LGATE (5V/Div) LGATE UGATE Time (50ns/Div) Time (25ns/Div) DS8101/A-01 March 2007 www.richtek.com 7 RT8101/A Preliminary Transient Response (Rising) RT8101, VCC = VIN = 12V, IOUT= 0A to 15A, f = 1/20ms, SR = 2.5A/us, L = 2.2uH, C = 2000uF Transient Response (Falling) RT8101, VCC = VIN = 12V, IOUT= 15A to 0A, f = 1/20ms, SR = 2.5A/us, L = 2.2uH, C = 2000uF VOUT (100mV/Div) VOUT (100mV/Div) UGATE (20V/Div) UGATE (20V/Div) IOUT (10A/Div) IOUT (10A/Div) Time (5μs/Div) Time (5μs/Div) Transient Response (Rising) RT8101A, VCC = VIN = 12V, IOUT= 0A to 15A, f = 1/20ms, SR = 2.5A/us, L = 2.2uH, C = 2000uF Transient Response (Falling) RT8101A, VCC = VIN = 12V, IOUT= 15A to 0A, f = 1/20ms, SR = 2.5A/us, L = 2.2uH, C = 2000uF VOUT (100mV/Div) VOUT (100mV/Div) UGATE (20V/Div) UGATE (20V/Div) IOUT (10A/Div) IOUT (10A/Div) Time (5μs/Div) Time (5μs/Div) www.richtek.com 8 DS8101/A-01 March 2007 Preliminary Application Information Power On Reset The RT8101/A automatically initializes upon applying of input power VCC. The power on reset function (POR) continually monitors the input bias supply voltage at the VCC pin. The POR trip level is typically 9.6V at VCC rising. VIN Detection After POR the RT8101/A continuously generates a 10kHz pulse train with 1μs pulse width to turn on the upper MOSFET for detecting the existence of VIN. RT8101/A keeps monitoring PHASE pin voltage during the detection period. As soon as the PHASE voltage crosses 1.5V two times, VIN existence is recognized and the RT8101/A initiates its soft start cycle as described in next section. VIN POR_H PHASE_M + 1.5V PHASE UGATE 1st 2nd PHASE waveform Internal Counter will count (VPHASE > 1.5V) two times (rising & falling) to recognize when VIN is ready. RT8101/A A 30μA current source flows through the internal resistor 21.6kΩ to PHASE pin causing 0.65V voltage drop across the resistor. OCP is triggered if the voltage at PHASE pin (drop of lower MOSFET VDS) is lower than −0.25V when low side MOSFET conducting. Accordingly inductor current threshold for OCP is a function of conducting resistance of lower MOSFET RDS(ON) as : IOCSET = 30μ A × 21.6k-0.4V RDS(ON) If MOSFET with RDS(ON) = 10mΩ is used, the OCP threshold current is about 25A. Once OCP is triggered, the RT8101/A enters hiccup mode and re-soft starts again. The RT8101/A shuts down after OCP hiccups twice. OCP UGATE (10V/Div) Figure 1 Soft Start A built-in soft-start is used to prevent surge current from VIN to VOUT during power on. After the existence of VIN is detected, soft-start (SS) begins automatically. The feedback voltage (VFB) is clamped by internal linear ramping up SS voltage, causing PWM pulse width increasing slowly and thus inducing little surge current. Soft-start completes when SS voltage exceeds internal reference voltage (0.8V), the time duration is about 3.2ms. Over Current Protection The RT8101/A senses the current flowing through lower MOSFET for over current protection (OCP) by sensing the PHASE pin voltage as shown in the Functional Block Diagram. IOUT (10A/Div) Time (2.5ms/Div) Figure 3. Power On then Shorted OCP UGATE (10V/Div) IOUT (10A/Div) Time (2.5ms/Div) Figure 4. Shorted then Power On DS8101/A-01 March 2007 www.richtek.com 9 RT8101/A Feedback Compensation Preliminary 1) Modulator Frequency Equations The modulator transfer function is the small-signal transfer function of VOUT/VCOMP (output voltage over the error amplifier output. This transfer function is dominated by a DC gain, a double pole, and a zero as shown in Figure 7. The DC gain of the modulator is the input voltage (VIN) divided by the peak to peak oscillator voltage VOSC. The output LC filter introduces a double pole, 40dB/decade gain slope above its corner resonant frequency, and a total phase lag of 180 degrees. The resonant frequency of the LC filter is expressed as below: fLC = 1 2π L OUT × C OUT The RT8101/A is a voltage mode controller. The control loop is a single voltage feedback path including a compensator and modulator as shown in Figure 5. The modulator consists of the PWM comparator and power stage. The PWM comparator compares error amplifier EA output (COMP) with oscillator (OSC) sawtooth wave to provide a pulse-width modulated (PWM) with an amplitude of VIN at the PHASE node. The PWM wave is smoothed by the output filter LOUT and COUT. The output voltage (VOUT) is sensed and fed to the inverting input of the error amplifier. A well-designed compensator regulates the output voltage to the reference voltage VREF with fast transient response and good stability. In order to achieve fast transient response and accurate output regulation, an adequate compensator design is necessary. The goal of the compensation network is to provide adequate phase margin (greater than 45 degrees) and the highest 0dB crossing frequency. It is also recommended to manipulate loop frequency response that its gain crosses over 0dB at a slope of −20dB/dec. VIN OSC PWM Comparator ΔVOSC + Driver Driver LOUT PHASE COUT ESR ZFB COMP EA + REF ZIN The ESR zero is contributed by the ESR associated with the output capacitance. Note that this requires that the output capacitor should have enough ESR to satisfy stability requirements. The ESR zero of the output capacitor is expressed as follows : fESR = 1 2π × COUT × ESR 2) Compensation Frequency Equations The compensation network consists of the error amplifier and the impedance networks ZC and ZF as shown in Figure 6. ZF C1 ZC R2 C2 R1 VOUT VOUT EA + COMP FB RF C2 C1 COMP EA + REF R2 ZFB C3 ZIN R3 R1 VOUT VREF Figure 6. Compensation Loop FB fZ1 = fP1 = 1 2π x R2 x C2 1 2π x R2 x C1 x C2 C1 + C2 Figure 5. Closed Loop www.richtek.com 10 DS8101/A-01 March 2007 Preliminary Figure 7 shows the DC-DC converter's gain vs. frequency. The compensation gain uses external impedance networks ZC and ZF to provide a stable, high bandwidth loop. High crossover frequency is desirable for fast transient response, but it often jeopardizes the system stability. In order to cancel one of the LC filter poles, place the zero before the LC filter resonant frequency. In the experience, place the zero at 75% LC filter resonant frequency. Crossover frequency should be higher than the ESR zero but less than 1/5 of the switching frequency. The second pole is placed at half of the switching frequency. 80 80 Loop Gain 60 40 40 20 Gain (dB) 0 -20 -4040 0 RT8101/A TS Vg1 Vg2 VIN - VOUT VL - VOUT TON TOFF IL ΔIL IL = IOUT Compensation Gain IS1 Modulator Gain IS2 -6060 1H 0z 10db(vo) v 10z 0H v b c m 2100l ) d(op) vb o d( 1k 10k Feuny r qe c Frequency (Hz) 10H .Kz 1Kz 0H 100k 1 0H 0Kz 10H .Mz 1M Figure 7. Bode Plot Component Selection 1) Inductor Selection The selection of output inductor is based on the considerations of efficiency, output power and operating frequency. Low inductance value has smaller size, but results in low efficiency, large ripple current and high output ripple voltage. Generally, an inductor that limits the ripple current (ΔIL) between 20% and 50% of the output current is appropriate. Figure 8 shows the typical topology of synchronous step-down converter and its related waveforms. iS1 L + VL iS2 S1 VIN S2 + VOR + Figure 8. The waveforms of synchronous step-down converter According to Figure 8 the ripple current of inductor can be calculated as follows : V ΔIL ; Δt = D ; D = OUT VIN Δt fs VOUT L = (VIN − VOUT ) × VIN × fs × ΔIL VIN − VOUT = L Where : VIN = Maximum input voltage VOUT = Output Voltage Δt = S1 turn on time (1) IL iC rC RL COUT IOUT + VOUT - ΔIL = Inductor current ripple fS = Switching frequency D = Duty Cycle rC = Equivalent series resistor of output capacitor + VOC - DS8101/A-01 March 2007 www.richtek.com 11 RT8101/A 2) Output Capacitor Preliminary 3) Input Capacitor The selection of input capacitor is mainly based on its maximum ripple current capability. The buck converter draws pulsewise current from the input capacitor during the on time of S1 as shown in Figure 8. The RMS value of ripple current flowing through the input capacitor is described as : Irms = IOUT D(1 - D) (A) IOUT TS The selection of output capacitor depends on the output ripple voltage requirement. Practically, the output ripple voltage is a function of both capacitance value and the equivalent series resistance (ESR) rC. Figure 9 shows the related waveforms of output capacitor. IL dIL VIN-VOUT = L dt VOUT dIL dt = L (6) The input capacitor must be capable of handling this ripple current. Sometimes, for higher efficiency the low ESR capacitor is necessarily. IC 1/2ΔIL 0 ΔIL Thermal Considerations For continuous operation, do not exceed absolute maximum operation junction temperature 125°C. The maximum power dissipation depends on the thermal resistance of IC package, PCB layout, the rate of surroundings airflow and temperature difference between junction to ambient. The maximum power dissipation can be calculated by following formula : PD(MAX) = ( TJ(MAX) − TA ) / θJA Where T J(MAX) i s the maximum operation junction temperature 125°C, TA is the ambient temperature and the θJA is the junction to ambient thermal resistance. For recommended operating conditions specification of RT8101/A, where T J(MAX) i s the maximum junction temperature of the die (125°C) and TA is the maximum ambient temperature. The junction to ambient thermal resistance θJA is layout dependent. The maximum power dissipation at TA = 25°C can be calculated by following formula : PD(MAX) = ( 125°C − 25°C) / (120°C/W) = 0.83W for SOP-8 packages PD(MAX) = ( 125°C − 25 °C) / (75°C/W) = 1.33W for PSOP-8 packages The maximum power dissipation depends on operating ambient temperature for fixed T J (MAX) and thermal resistance θJA. For RT8101/A packages, Figure 10 allows the designer to see the effect of rising ambient temperature on the maximum power allowed. VOC ΔVOC VOR ΔIL x rC 0 t1 t2 Figure 9. The related waveforms of output capacitor The AC impedance of output capacitor at operating frequency is quite smaller than the load impedance, so the ripple current (ΔIL) of the inductor current flows mainly through output capacitor. The output ripple voltage is described as : ΔVOUT = ΔVOR + Δ VOC ΔVOUT = ΔIL × rC + 1 CO (2) t2 ∫t1 IC dt (3) (4) ΔVOUT = ΔIL × Δ IL × rC + 2 1 VOUT (1 − D)TS 8 C OL where ΔVOR is caused by ESR and ΔVOC by capacitance. For electrolytic capacitor application, typically 90 to 95% of the output voltage ripple is contributed by the ESR of output capacitor. So Equation (4) could be simplified as : ΔVOUT = ΔIL x rC (5) Users could connect capacitors in parallel to get calculated ESR. www.richtek.com 12 DS8101/A-01 March 2007 Preliminary 1.4 RT8101/A PSOP-8 1.2 1 0.8 0.6 0.4 0.2 0 0 20 40 60 80 100 120 140 SOP-8 The power components and the PWM controller should be placed firstly. Place the input capacitors, especially the high-frequency ceramic decoupling capacitors, close to the power switches. Place the output inductor and output capacitors between the MOSFETs and the load. Also locate the PWM controller near by MOSFETs. A multi-layer printed circuit board is recommended. Figure 11 shows the connections of the critical components in the converter. Note that the capacitors CIN and COUT each of them represents numerous physical capacitors. Use a dedicated grounding plane and use vias to ground all critical components to this layer. Apply another solid layer as a power plane and cut this plane into smaller islands of common voltage levels. The power plane should support the input power and output power nodes. Use copper filled polygons on the top and bottom circuit layers for the PHASE node, but it is not necessary to oversize this particular island. Since the PHASE node is subjected to very high dV/dt voltages, the stray capacitance formed between these islands and the surrounding circuitry will tend to couple switching noise. Use the remaining printed circuit layers for small signal routing. The PCB traces between the PWM controller and the gate of MOSFET and also the traces connecting source of MOSFETs should be sized to carry 2A peak currents. IQ1 5V/12V Q1 IQ2 Q2 GND + + Power Dissipation (W) Ambient Temperature (°C) Figure 10. Derating Curves for RT8101/A Packages PCB Layout Considerations MOSFETs switch very fast and efficiently. The speed with which the current transitions from one device to another causes voltage spikes across the interconnecting impedances and parasitic circuit elements. The voltage spikes can degrade efficiency and radiate noise, that results in over-voltage stress on devices. Careful component placement layout and printed circuit design can minimize the voltage spikes induced in the converter. Consider, as an example, the turn-off transition of the upper MOSFET prior to turn-off, the upper MOSFET was carrying the full load current. During turn-off, current stops flowing in the upper MOSFET and is picked up by the low side MOSFET or schottky diode. Any inductance in the switched current path generates a large voltage spike during the switching interval. Careful component selections, layout of the critical components, and use shorter and wider PCB traces help in minimizing the magnitude of voltage spikes. There are two sets of critical components in a DC-DC converter using the RT8101/A. The switching power components are most critical because they switch large amounts of energy, and as such, they tend to generate equally large amounts of noise. The critical small signal components are those connected to sensitive nodes or those supplying critical bypass current. IL VOUT + LOAD GND LGATE VCC RT8101/A UGATE FB Figure 11. The connections of the critical components in the converter DS8101/A-01 March 2007 www.richtek.com 13 RT8101/A Outline Dimension Preliminary A H M J B F C I D Dimensions In Millimeters Symbol Min A B C D F H I J M 4.801 3.810 1.346 0.330 1.194 0.170 0.050 5.791 0.400 Max 5.004 3.988 1.753 0.508 1.346 0.254 0.254 6.200 1.270 Dimensions In Inches Min 0.189 0.150 0.053 0.013 0.047 0.007 0.002 0.228 0.016 Max 0.197 0.157 0.069 0.020 0.053 0.010 0.010 0.244 0.050 8-Lead SOP Plastic Package www.richtek.com 14 DS8101/A-01 March 2007 Preliminary RT8101/A A H M EXPOSED THERMAL PAD (Bottom of Package) Y J X B F C I D Dimensions In Millimeters Symbol Min A B C D F H I J M X Y 4.801 3.810 1.346 0.330 1.194 0.170 0.000 5.791 0.406 1.900 1.900 Max 5.004 4.000 1.753 0.510 1.346 0.254 0.152 6.200 1.270 2.700 3.600 Dimensions In Inches Min 0.189 0.150 0.053 0.013 0.047 0.007 0.000 0.228 0.016 0.075 0.075 Max 0.197 0.157 0.069 0.020 0.053 0.010 0.006 0.244 0.050 0.106 0.142 8-Lead SOP (Exposed Pad) Plastic Package Richtek Technology Corporation Headquarter 5F, No. 20, Taiyuen Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)5526789 Fax: (8863)5526611 Richtek Technology Corporation Taipei Office (Marketing) 8F, No. 137, Lane 235, Paochiao Road, Hsintien City Taipei County, Taiwan, R.O.C. Tel: (8862)89191466 Fax: (8862)89191465 Email: marketing@richtek.com DS8101/A-01 March 2007 www.richtek.com 15