®
RT8120E/F
Single-Phase Synchronous Buck PWM Controller
General Description
Features
The RT8120E/F is a single-phase synchronous buck PWM
DC-DC controller designed to drive two N-MOSFET.
It provides a highly accurate, programmable output voltage
precisely regulated to low voltage requirements with an
internal 0.8V ±1% ( option for 0.6V ±1.5%) reference. The
RT8120E/F uses a single feedback loop voltage mode
PWM control for fast transient response. An oscillator with
fixed frequency 300kHz reduces the external inductor and
capacitor component size for saving PCB board area. The
RT8120E/F provides fast transient response to satisfy high
current output applications while minimizing external
components. It is suitable for high performance graphic
processors, DDR and VTT power. The RT8120E/F
incorporates an externally compensated error amplifier
and an internal soft-start and output enable.
The RT8120E/F comes in SOP-8 and SOP-8 (Exposed
Pad) packages.
Wide Input Voltage Range : 3V to 13.2V
Embedded Switching Boot Diode
0.8V ±1%, 0.6V ±1.5% Internal Reference
Shoot-Through Protection and Short Pulse Free
Technology for Gate Drivers
Fixed Frequency 300kHz
Internal Soft-Start
Over Current Protection by Sensing MOSFET RDS(ON)
Enable/Shutdown Control
Drives Two N-MOSFETs
Full Duty Cycle : 0% to 85%
Fast Transient Response
Voltage Mode PWM Control with External
Feedback Loop Compensation
Pinless LGATE Over Current Setting (LGOCS)
Over Voltage Protection
Under Voltage Protection
SOP-8 and SOP-8 (Exposed Pad) Packages
RoHS Compliant and Halogen Free
Ordering Information
RT8120E/F
Applications
Package Type
S : SOP-8
SP : SOP-8 (Exposed-Pad-Option 1)
Lead Plating System
G : Green (Halogen Free and Pb Free)
Z : ECO (Ecological Element with
Halogen Free and Pb free)
Reference Voltage
E : 0.6V
F : 0.8V
Note :
Richtek products are :
System (Graphic, MB) with 5V or 12V Power
Graphic Cards (AGP 8X, 4X, PCI Express*16)
3.3V to 12V Input DC-DC Regulators
Low Voltage Distributed Power Supplies
Pin Configuration
(TOP VIEW)
8
BOOT
7
COMP/EN
GND
LGATE/OCSET
3
6
FB
4
5
VCC
8
PHASE
RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020.
PHASE
UGATE
2
SOP-8
Suitable for use in SnPb or Pb-free soldering processes.
BOOT
UGATE
2
GND
LGATE/OCSET
3
GND
7
COMP/EN
6
FB
5
VCC
9
4
SOP-8 (Exposed Pad)
Copyright © 2021 Richtek Technology Corporation. All rights reserved.
DS8120E/F-03
September 2021
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RT8120E/F
Marking Information
RT8120xGS
RT8120xZS
RT8120xGS : Product Number
RT8120x
GSYMDNN
RT8120xZS : Product Number
RT8120x
ZSYMDNN
X : E or F
YMDNN : Date Code
RT8120xGSP
X : E or F
YMDNN : Date Code
RT8120xZSP
RT8120xGSP : Product Number
RT8120x
GSPYMDNN
RT8120xZSP : Product Number
RT8120x
ZSPYMDNN
X : E or F
YMDNN : Date Code
Typical Application Circuit
VCC
VIN
CBypass
4.7µF
C1
0.1µF
R2
0
RT8120E/F
VCC
C4
22µF x 2
16V
BOOT
Q1
R3 0
IPD09N
03LA
UGATE
COMP/EN
VOUT
LOUT
0.68µH
PHASE
RC
13k
CP
22pF
CIN
1000µF
16V
CC
3.3nF
IPD06N03LA
LGATE/
OCSET
GND
FB
Q2
R4
1
RFB1
5k
C2
3.3nF
ROCSET
7.87k
R5
NC
C5
10µF x 2
6.3V
+
2N7002
EN
YMDNN : Date Code
+
R1
10
X : E or F
COUT
820µF x 2
2.5V
C3
NC
RFB2
16k
Functional Block Diagram
VCC
Internal
Regulator
POR
BOOT
UGATE
VREF
FB
+
Error
Amp
PWM
+
-
-
PHASE
Gate
Control
COMP/EN
VCC
LGATE/
OCSET
ramp
SS
Soft-Start/
Fault Logic
fault
GND
+
-
PHASE
VIN Detection
Oscillator
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Sample
/Hold
IOCSET
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DS8120E/F-03
September 2021
RT8120E/F
Functional Pin Description
SOP-8
Pin No.
SOP-8
(Exposed Pad)
Pin Name
1
1
BOOT
2
2
UGATE
3
3,
GND
9 (Exposed Pad)
Pin Function
Bootstrap Power Pin. This pin powers the upper gate driver.
Connect a bootstrap capacitor between the BOOT pin and
PHASE pin on the upper MOSFET.
Upper-Gate Driver Output. Connect to gate of the high side
power N-MOSFET. This pin is monitored by the adaptive
shoot-through protection circuitry to determine when the upper
MOSFET has turned off.
Ground for the IC. All voltage levels are measured with respect to
this pin. Connect this pin directly to the low side MOSFET source
and ground plane with the lowest impedance. The exposed pad
must be soldered to a large PCB and connected to GND for
maximum power dissipation.
Lower-Gate Driver Output. Connect to the gate of the low side
power N-MOSFET. It provides the PWM-controlled gate drive
(from VCC). This pin is also monitored by the adaptive
shoot-through protection circuitry to determine when the lower
LGATE/OCSET MOSFET has turned off. During a short period of time following
Power-On Reset (POR) or shutdown release, this pin is also used
to determine the over-current threshold of the converter
(LGOCS). Connect a resistor (ROCSET) from this pin to GND. See
the over current protection section for equations.
Supply Input Pin. Connect this pin to a well-decoupled 5V or 12V
VCC
bias supply. It is also the positive supply for the lower gate driver,
LGATE.
Feedback Input Pin. This pin is the inverting input of the error
FB
amplifier. FB senses the switch output through an external
resistor divider network.
4
4
5
5
6
6
7
7
COMP/EN
8
8
PHASE
Feedback Compensation. And could be used as EN pin, when
COMP < 0.4V, to disable entire chip.
Switch Node. Connect this pin to the source of the upper
MOSFET and the drain of the lower MOSFET.
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DS8120E/F-03
September 2021
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RT8120E/F
Absolute Maximum Ratings
(Note 1)
VCC to GND, VCC -------------------------------------------------------------------------------------- BOOT to PHASE, VBOOT−PHASE ---------------------------------------------------------------------- PHASE to GND
DC -----------------------------------------------------------------------------------------------------------< 20ns ----------------------------------------------------------------------------------------------------- UGATE to PHASE
DC -----------------------------------------------------------------------------------------------------------< 20ns ----------------------------------------------------------------------------------------------------- LGATE to GND
DC -----------------------------------------------------------------------------------------------------------< 20ns ----------------------------------------------------------------------------------------------------- Other Pins ------------------------------------------------------------------------------------------------- Power Dissipation, PD @ TA = 25°C
SOP-8 ------------------------------------------------------------------------------------------------------SOP-8 (Exposed Pad) --------------------------------------------------------------------------------- Package Thermal Resistance (Note 2)
SOP-8, θJA -----------------------------------------------------------------------------------------------SOP-8 (Exposed Pad), θJA ---------------------------------------------------------------------------SOP-8 (Exposed Pad), θJC --------------------------------------------------------------------------- Lead Temperature (Soldering, 10 sec.) ------------------------------------------------------------- Junction Temperature ----------------------------------------------------------------------------------- Storage Temperature Range -------------------------------------------------------------------------- ESD Susceptibility (Note 3)
HBM (Human Body Model) ----------------------------------------------------------------------------
Recommended Operating Conditions
15V
15V
−0.5V to 15V
−8V to 25V
−0.3V to (VBOOT−PHASE + 0.3V)
−5V to (VBOOT−PHASE + 5V)
−0.3V to (VCC + 0.3V)
−5V to (VCC + 5V)
−0.3V to 7V
0.53W
3.26W
188°C/W
30.6°C/W
3.4°C/W
260°C
150°C
−65°C to 150°C
2kV
(Note 4)
Supply Input Voltage, VIN ------------------------------------------------------------------------------ 3V to 13.2V
Control Input Voltage, VCC ---------------------------------------------------------------------------- 4.5V to 13.2V
Junction Temperature Range --------------------------------------------------------------------------- −40°C to 125°C
Ambient Temperature Range --------------------------------------------------------------------------- −40°C to 85°C
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is a registered trademark of Richtek Technology Corporation.
DS8120E/F-03
September 2021
RT8120E/F
Electrical Characteristics
( TA = 25°C, unless otherwise specified)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
Supply Current
ICC
UGATE, LGATE Open, VCC = 12V
--
1.5
--
mA
Shutdown Current
ISHDN
UGATE, LGATE Open, VCC = 12V
--
0.7
--
mA
3.9
4.1
4.3
V
Power On Reset Threshold VCCR_TH
VCC Rising
Power On Reset
Hysteresis
VCC_Hys
0.26
0.45
0.64
V
Switching Frequency
f SW
270
300
330
kHz
Ramp Amplitude
VOSC
--
1.3
--
VP-P
0
--
--
%
--
85
--
%
RT8120E
0.591
0.6
0.609
RT8120F
0.792
0.8
0.808
Minimum Duty Cycle
Maximum Duty Cycle
DMAX
Reference Voltage
VREF
Open Loop DC Gain
ADC
Guaranteed by Design
--
70
--
dB
Gain Bandwidth
GBW
Guaranteed by Design
--
10
--
MHz
Slew Rate
SR
Guaranteed by Design, CL = 10pF
--
6
--
V/s
Transconductance
gm
500
700
--
A/V
Output Source Current
ICOMPSK
VFB < VREF
80
120
--
A
Output Sink Current
ICOMPSC
VFB < VREF
80
120
--
A
Soft-Start Time
RT8120E
--
1.5
--
tSS
RT8120F
--
2
--
Upper Gate Sourcing
Ability
IUG_SRC
VBOOT VPHASE = 12V, max source current
--
1.2
--
A
Upper Gate RDS(ON)
Sinking
RUG_SNK VUGATE VPHASE = 0.1V
--
3
--
Lower Gate Sourcing
Ability
ILG_SRC
VCC = 12V, max source current
--
1.2
--
A
Lower Gate RDS(ON)
Sinking
RLG_INK
VLGATE = 0.1V
--
1.8
--
Deadtime between UGATE
Off to LGATE On
VUGATE VPHASE = 1.2V to VLGATE =1.2V
--
30
--
ns
Deadtime Between LGATE
Off to UGATE On
VUGATE VPHASE = 1.2V to VLGATE = 1.2V
--
30
--
ns
RBOOT
VCC to BOOT, 10mA
--
--
80
Under Voltage Protection
VUVP_FB
Relative to FB Pin Voltage
--
75
--
%
Pre-OVP Threshold
(Before POR)
VOVP1
VCC = 3V, FB Pin Voltage
--
1.3
--
V
V
ms
Internal BOOT Switch
Internal BOOT Switch
On-Resistance
Protection
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DS8120E/F-03
September 2021
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RT8120E/F
Parameter
OVP Threshold
(After POR)
Symbol
VOVP2
Test Conditions
VCC = 5V, Relative to FB Pin Voltage
LGATE OC Setting Current IOCSET
Over Current Threshold
VPHASE
Enable Threshold
VEN
ROCSET = Open
Min
Typ
Max
Unit
--
125
--
%
9
10
11
A
--
375
--
mV
0.3
0.4
0.55
V
Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in
the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may
affect device reliability.
Note 2. θJA is measured at TA = 25°C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. θJC is
measured at the exposed pad of the package.
Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
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DS8120E/F-03
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RT8120E/F
Typical Operating Characteristics
Output Voltage vs. Output Current
Efficiency vs. Output Current
1.500
100
95
1.495
Output Voltage (V)
Efficiency (%)
90
85
80
75
70
65
60
1.490
1.485
1.480
1.475
55
VIN = VCC = 12V, VOUT = 1.5V
VIN = VCC = 12V, VOUT = 1.5V
1.470
50
0
5
10
15
20
25
0
30
2
4
6
8
10
12
14
16
18
20
Output Current (A)
Output Current (A)
Reference Voltage vs. Temperature
Frequency vs. Temperature
300
0.820
290
0.810
Frequency (kHz)1
Reference Voltage (V)
0.815
0.805
0.800
0.795
0.790
280
270
260
0.785
VIN = VCC = 12V
VIN = VCC = 12V
250
0.780
-50
-25
0
25
50
75
100
125
-50
0
25
50
75
Temperature (C)
Power On
Power Off
VUGATE
(20V/Div)
VUGATE
(20V/Div)
VLGATE
(10V/Div)
VLGATE
(10V/Div)
V CC
(10V/Div)
VOUT
(1V/Div)
V CC
(10V/Div)
VOUT
(1V/Div)
VIN = VCC = 12V, VOUT = 1.05V, ILOAD = 10A
Time (2.5ms/Div)
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DS8120E/F-03
-25
Temperature (C)
September 2021
100
125
VIN = VCC = 12V, VOUT = 1.05V, ILOAD = 10A
Time (2.5ms/Div)
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RT8120E/F
COMP/EN Power On
COMP/EN Power Off
VUGATE
(20V/Div)
VUGATE
(20V/Div)
VLGATE
(10V/Div)
VLGATE
(10V/Div)
V COMP/EN
(1V/Div)
VOUT
(1V/Div)
V COMP/EN
(2V/Div)
VOUT
(2V/Div)
VIN = VCC = 12V, VOUT = 1.05V, ILOAD = 10A
VIN = VCC = 12V, VOUT = 1.05V, ILOAD = 10A
Time (500μs/Div)
Time (250μs/Div)
Load Transient Response
Load Transient Response
VUGATE
(20V/Div)
VUGATE
(20V/Div)
I LOAD
(10A/Div)
I LOAD
(10A/Div)
VOUT
(50mV/Div)
VOUT
(50mV/Div)
VIN = VCC = 12V, VOUT = 1.05V,
ILOAD = 0A to15A
VIN = VCC = 12V, VOUT = 1.05V,
ILOAD = 15A to 0A
Time (10μs/Div)
Time (10μs/Div)
Over Current Protection
Under Voltage Protection
VIN = VCC = 12V, VOUT = 1.05V
VUGATE
(20V/Div)
VLGATE
(20V/Div)
VUGATE
(10V/Div)
VLGATE
(10V/Div)
Inductor
Current
(20A/Div)
VOUT
(1V/Div)
ROCSET = 6.2kΩ
Low side MOSFET = IPD06N03 x 2
Time (25μs/Div)
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VFB
(500mV/Div)
VIN = VCC = 12V, VOUT = 1.05V, No Load
Time (2.5ms/Div)
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DS8120E/F-03
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RT8120E/F
Application Information
Function Description
The RT8120E/F is a single-phase synchronous buck PWM
controller with integrated N-MOSFET gate drivers. The
RT8120E/F can be used in a broad variety of applications,
with its wide input voltage range from 3V or 13.2V. It
provides single feedback loop, voltage mode control with
fast transient response. An internal 0.8V (option for 0.6V)
reference allows the output voltage to be precisely
regulated for low output voltage applications. A fixed
frequency (300kHz) oscillator is integrated to minimize
external components. Protection features include
programmable over current protection and Under Voltage
Lockout (UVLO).
Supply Voltage and Power On Reset (POR)
The input voltage range for VCC is from 4.5 V to 13.2 V
with respect to GND. An internal linear regulator regulates
the supply voltage for internal control logic circuit. A
minimum 0.1μF ceramic capacitor is recommended to
bypass the supply voltage. Place the bypassing capacitor
physically near the IC. VCC also supplies the integrated
MOSFET drivers. A bootstrap diode is embedded to
facilitate PCB design and reduce the total BOM cost. No
external Schottky diode is required in real applications.
The Power-On Reset (POR) circuit monitors the supply
voltage at the VCC pin. If VCC exceeds the POR rising
threshold voltage (typ. 4V), the controller resets and
prepares the PWM for operation. If VCC falls below the
POR falling threshold during normal operation, all
MOSFETs stop switching. The POR rising and falling
threshold has a hysteresis (typ.0.45V) to prevent
unintentional noise based reset.
Chip Enable and Disable
The COMP/EN pin of the RT8120E/F is a multiplexed pin.
During soft-start and normal converter operation, this pin
represents the output of the error amplifier. When COMP/
EN pin voltage falls or is pulled externally below the enable
level VEN, the chip shuts down. When the controller shuts
down, UGATE and LGATE signals will go low. When the
pull-down device is released and the COMP/EN pin rises
above the VEN trip point, the RT8120E/F will begin a new
Copyright © 2021 Richtek Technology Corporation. All rights reserved.
DS8120E/F-03
September 2021
initialization and soft-start cycle. This allows flexible power
sequence control for specified application. In practical
applications, connect a small-signal MOSFET to the
COMP/EN pin to implement the enable/disable function.
VIN Detection
Once VCC exceeds its power on reset (POR) rising
threshold voltage, UGATE will output continuous pulses
(~60kHz, 200ns), and LGATE will be forced low for
converter input voltage VIN detection. If the voltage pulses
at the PHASE pin exceed 1V when UGATE is turned on,
VIN is recognized as ready. Then, the controller will initiate
soft-start operation.
Internal Soft-Start
The RT8120E/F provides an internal soft-start function.
The soft-start function is used to prevent large inrush
current and output voltage overshoot while the converter
is being powered-up. The soft-start function automatically
begins once the chip is enabled. An internal current source
charges the internal soft-start capacitor such that the
internal soft-start voltage ramps up uniformly. The FB
voltage will track the internal soft-start voltage during the
soft-start interval. Therefore, the PWM pulse width
increases gradually to limit the input current. After the
internal soft-start voltage exceeds the reference voltage,
the FB voltage no longer tracks the soft-start voltage but
rather follows the reference voltage. Therefore, the duty
cycle of the UGATE signal as well as the input current at
power up are limited.
Over Current Protection (OCP)
The RT8120E/F provides lossless over current protection
by detecting the voltage drop across the low side MOSFET
when it is turned on. The over current trip threshold is set
by an external resistor, ROCSET, at LGATE. During the initial
stage when LGATE is turned on, the RT8120E/F samples
and holds the phase voltage. The sample-and-hold voltage
represents the valley inductor current and is compared to
the OCP threshold. If the sensed phase voltage is lower
than the OCP threshold, OCP will be triggered. Both
UGATE and LGATE will go low, and the controller will enter
the hiccup mode until the OCP condition is released.
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RT8120E/F
LGATE Over Current Setting (LGOCS)
Output Voltage Setting
Over current threshold is externally programmed by adding
a resistor (ROCSET) between LGATE and GND. Once VCC
exceeds the POR threshold, an internal current source
IOCSET flows through ROCSET. The voltage across ROCSET is
stored as the over current protection threshold VOCSET.
After that, the current source is switched off. ROCSET can
be determined using the following equation :
IVALLEY x RLGDS(ON)
ROCSET =
IOCSET
The RT8120E/F allows the output voltage of the DC-DC
converter to be adjusted from 0.8V (option for 0.6V) to
85% of VIN via an external resistor divider. It will try to
maintain the feedback pin at internal reference voltage
(0.8V, with option for 0.6V).
where IVALLEY represents the desired inductor OCP trip
current (valley inductor current).
If ROCSET is not present, there is no current path for IOCSET
to build the OCP threshold. In this situation, the OCP
threshold is internally preset to 375mV (typical).
Over Voltage Protection
The feedback voltage at FB pin is continuously monitored
for over voltage protection. When OVP is tripped, UGATE
will go low and LGATE will to high to discharge the output
capacitor. RT8120E/F provides over voltage protection
whenever soft-start completes or not. Over voltage
protection has two operating conditions : before VCC POR
completes and after VCC POR completes. Each condition
is described as follows.
Before VCC POR completes, the typical OVP threshold
is 162.5% of the internal reference voltage VREF. RT8120E/
F provides non-latched OVP before soft start completes.
The controller will return to normal operation if over voltage
condition is removed.
After VCC POR completes, however, the OVP threshold
is typically raised to 125% of VREF.
RT8120E/F provides latched OVP, which means UGATE
will to low and LGATE will go high. Under this condition,
the controller can only be reset if VCC POR is toggled.
Under Voltage Protection (UVP)
The voltage on the FB pin is monitored for under voltage
protection. If the FB voltage is lower than the UVP threshold
(typically 75% x VREF) during normal operation, UVP will
be triggered. When the UVP is triggered, both UGATE
and LGATE go low. The controller enters hiccup mode
until the UVP condition is removed.
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VOUT
RFB1
FB
RFB2
Figure 1. Output Voltage Setting
According to the resistor divider network above, the output
voltage is set as :
R
VOUT = VREF x 1 + FB1
R
FB2
MOSFET Drivers
The RT8120E/F integrates high current gate drivers for
the two N-MOSFETs to obtain high efficiency power
conversion in synchronous buck topology. A dead time is
used to prevent crossover conduction for the high side
and low side MOSFETs. Because both gate signals are
off during dead time, the inductor current freewheels
through the body diode of the low side MOSFET. The
freewheeling current and the forward voltage of the body
diode contribute to power loss. The RT8120E/F employs
constant dead time control scheme to ensure safe operation
without sacrificing efficiency. Furthermore, elaborate logic
circuit is implemented to prevent cross conduction.
For high output current applications, two or more power
MOSFETs are usually paralleled to reduce RDS(ON). The
gate driver needs to provide more current to switch on/off
these paralleled MOSFETs. Gate driver with lower source/
sink current capability result in longer rising/ falling time
in gate signals, and therefore higher switching loss.
The RT8120E/F embeds high current gate drivers to obtain
high efficiency power conversion. The embedded drivers
contribute to the majority of the power dissipation of the
controller. Therefore, SOP package is chosen for its power
dissipation rating. If no gate resistor is used, the power
dissipation of the controller can be approximately
calculated using the following equation :
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DS8120E/F-03
September 2021
RT8120E/F
PDRIVER = fSW x (QG x VBOOT +
QG_LOW SIDE x VDRIVER_LOW SIDE )
where VBOOT represents the voltage across the bootstrap
capacitor and fSW is the switching frequency.
It is important to ensure the package can dissipate the
switching loss and have enough room for safe operation.
Inductor Selection
The inductor plays an importance role in step-down
converters because it stores the energy from the input
power rail and then releases the energy to the load. From
the viewpoint of efficiency, the dc resistance (DCR) of the
inductor should be as small as possible to minimize the
conduction loss. In addition, the inductor covers a
significant proportion of the board space, so its size is
also important. Low profile inductors can save board space
especially when the height has a limitation. However, low
DCR and low profile inductors are usually cost ineffective.
Additionally, larger inductance results in lower ripple
current, which translates into the lower power loss.
However, the inductor current rising time increases with
inductance value. This means the transient response will
be slower. Therefore, the inductor design is a trade-off
between performance, size and cost.
In general, inductance is chosen such that the ripple
current ranges between 20% to 40% of the full load current.
The inductance can be calculated using the following
equation :
L(MIN) =
VIN VOUT
V
x OUT
fSW x k x IOUT_RATED
VIN
where k is the ratio between inductor ripple current and
rated output current.
Input Capacitor Selection
Voltage rating and current rating are the key parameters
when selecting an input capacitor. Conservatively speaking,
an input capacitor should have a voltage rating 1.5 times
greater than the maximum input voltage to be considered
a safe design.
The input capacitor is used to supply the input RMS
current, which can be approximately calculated using the
following equation :
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DS8120E/F-03
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VOUT
V
x 1 OUT
VIN
VIN
The next step is to select a proper capacitor for the RMS
current rating. Using more than one capacitor with low
Equivalent Series Resistance (ESR) in parallel to form a
capacitor bank is a good design. Placing the ceramic
capacitor close to the drain of the high side MOSFET can
also be helpful in reducing the input voltage ripple at
heavy load.
I RMS = IOUT x
Output Capacitor Selection
The output capacitor and the inductor form a low-pass filter
in the buck topology. In steady state condition, the ripple
current flowing into/out of the capacitor results in voltage
ripple. The output voltage ripples contains two
components, ΔVOUT_ESR and ΔVOUT_C.
VOUT_ESR = IL x ESR
VOUT_C = IL x
1
8 x COUT x fSW
When load transient occurs, the output capacitor supplies
the load current before controller can respond. Therefore,
the ESR will dominate the output voltage sag during load
transient. The output voltage sag can be calculated using
the following equation :
VOUT_SAG = ESR x ΔIOUT
For a given output voltage sag specification, the ESR value
can be determined.
Another parameter that has influence on the output voltage
sag is the equivalent series inductance (ESL). The rapid
change in load current results in di/dt during transient.
Therefore ESL contributes to part of the voltage sag. Using
a capacitor with low ESL will obtain better transient
performance. Generally, using several capacitors
connected in parallel will also have better transient
performance than just one single capacitor with the same
total ESR.
Unlike electrolytic capacitors, the ceramic capacitor has
relatively low ESR and can reduce the voltage deviation
during load transient. However, the ceramic capacitor can
only provide low capacitance value. Therefore, it is
suggested to use a mixed combination of electrolytic
capacitor and ceramic capacitor for achieving better
transient performance.
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RT8120E/F
MOSFET Selection
regulation with fast transient response. The RT8120E/F
uses a high gain operational transconductance amplifier
(EOTA) as the error amplifier. As Figure 2 shows, the EOTA
works as the voltage controlled current source. The
calculation of the transconductance is shown below :
I
GM = OUT , where VM = VIN+ VIN
VM
The majority of power loss in the step-down power
conversion is due to the loss in the power MOSFETs. For
low voltage high current applications, the duty cycle of
the high side MOSFET is small. Therefore, the switching
loss of the high side MOSFET is of concern. Power
MOSFETs with lower total gate charge are preferred in
such kind of application. However, the small duty cycle
means the low side MOSFET is on for most of the switching
cycle. Therefore, the conduction loss tends to dominate
the total power loss of the converter. To improve the overall
efficiency, MOSFETs with low RDS(ON) are preferred in the
circuit design. In some cases, more than one MOSFET
are connected in parallel to further decrease the on-state
resistance. However, this depends on the low side
MOSFET driver capability and the budget.
and VCOMP = IOUT x ZOUT
Figure 3 shows a typical buck control loop using a Type II
compensator. The control loop consists of the power stage,
PWM comparator and a compensator. The PWM
comparator compares VCOMP with the oscillator (OSC)
sawtooth wave to provide a Pulse-Width Modulated (PWM)
with an amplitude of VIN at the PHASE node. The PWM
wave is smoothed by the output filter LOUT and COUT. The
output voltage (VOUT) is sensed and fed to the inverting
input of the error amplifier.
It is recommended to bypass low side MOSFET with a
snubber circuit (R = 1Ω, C = 3.3nF).
The modulator transfer function is the small-signal transfer
function of VOUT/VCOMP (output voltage over the error
amplifier output). This transfer function is dominated by a
DC gain, a double pole, and an ESR zero as shown in
Figure 4.
Compensation Network Design
The RT8120E/F is a voltage mode controller and requires
external compensation to have an accurate output voltage
VIN+
+
VIN-
-
IOUT
GM
VCOMP
ZOUT
Figure 2. Operational Transconductance Amplifier, EOTA
VIN
PWM
Comparator
UGATE
Q1
+
Driver
Logic
-
VOSC
LOUT
PAHSE
VOUT
LGATE
Q2
FB
RFB1
COUT
VREF
+
GM
-
RFB2
COMP
VCOMP
CC
CP
RC
Figure 3. Typical Voltage Mode Buck Converter Control Loop
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is a registered trademark of Richtek Technology Corporation.
DS8120E/F-03
September 2021
RT8120E/F
80 80
Loop Gain
60
fP1
f LC
40 40
Gain (dB)
20
0
Compensation
Gain
f Z1
fP2
0
-20
Modulator
Gain
fESR
-40-40
-60-60
10Hz
10vdb(vo)
100Hz
vdb(comp2)100
vdb(lo)
1.0KHz
10KHz
1k
10k
Frequency (Hz)
Frequency
100KHz
100k
1.0MHz
1M
Figure 4. Typical Bode Plot of a Voltage Mode Buck
Converter
To determine the 0dB crossing frequency (fC, control loop
bandwidth) is the first step of compensator design. Usually,
the fC is set to 0.1 to 0.3 times the switching frequency.
The second step is to calculate the open loop modulator
gain and find out the gain loss at fC. The third step is to
design a compensator gain that can compensate the
modulator gain loss at fC. The final step is to design fZ1
and fP2 to allow the loop sufficient phase margin. fZ1 is
designed to cancel one of the double poles of modulator.
Usually, place fZ1 before fLC. fP2 is usually placed below
the switching frequency (typically, 0.5 to 1 times the
switching frequency) to cancel high frequency noise.
Thermal Considerations
The DC gain of the modulator is the input voltage (VIN)
divided by the peak-to-peak oscillator voltage VOSC.
VIN
GainMODULATOR =
VOSC
The output LC filter introduces a double pole, 40dB/decade
gain slope above its corner resonant frequency, and a total
phase lag of 180 degrees. The resonant frequency of the
LC filter is expressed as :
1
fLC =
2 LOUT x COUT
The ESR zero is contributed by the ESR associated with
the output capacitance. Note that this requires that the
output capacitor should have enough ESR to satisfy
stability requirements. The ESR zero of the output
capacitor is expressed as follows :
1
fESR =
2 x COUT x ESR
The goal of the compensation network is to provide
adequate phase margin (usually greater than 45 degrees)
and the highest bandwidth (0dB crossing frequency). It is
also recommended to manipulate loop frequency response
that its gain crosses over 0dB at a slope of −20dB/dec.
According to Figure 4, the compensation network
frequency is as below :
fP1 = 0
1
CC x Cp
2 x R C x
CC + CP
1
fZ1 =
2 x RC x CC
fP2 =
Copyright © 2021 Richtek Technology Corporation. All rights reserved.
DS8120E/F-03
September 2021
For continuous operation, do not exceed absolute
maximum junction temperature. The maximum power
dissipation depends on the thermal resistance of the IC
package, PCB layout, rate of surrounding airflow, and
difference between junction and ambient temperature. The
maximum power dissipation can be calculated by the
following formula :
PD(MAX) = (TJ(MAX) − TA ) / θJA
Where TJ(MAX) is the maximum junction temperature, TA
is the ambient temperature, and θJA is the junction to
ambient thermal resistance.
For recommended operating condition specifications, the
maximum junction temperature is 125°C. The junction to
ambient thermal resistance, θJA, is layout dependent. For
SOP-8 package, the thermal resistance, θJA, is 188°C/W
on a standard JEDEC 51-7 four-layer thermal test board.
For SOP-8 (Exposed Pad) package, the thermal
resistance, θJA, is 30.6°C/W on a standard JEDEC 51-7
four-layer thermal test board. The maximum power
dissipation at TA = 25°C can be calculated by the following
formulas :
PD(MAX) = (125°C − 25°C ) / (188°C/W) = 0.53W for
SOP-8 package
PD(MAX) = (125°C − 25°C ) / (30.6°C/W) = 3.26W for
SOP-8 (Exposed Pad) package
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RT8120E/F
The maximum power dissipation depends on operating
ambient temperature for fixed T J(MAX) and thermal
resistance, θJA. The derating curves in Figure 5 allow the
designer to see the effect of rising ambient temperature
on the maximum power dissipation.
Maximum Power Dissipation (W)
3.6
Minimize the trace length between the power MOSFETs
and its drivers.
Since the drivers use short, high current pulses to drive
the power MOSFETs, the driving traces should be as
short and wide as possible to reduce the trace
inductance. This is especially true for the low side
MOSFET, since this can reduce the possibility of the
shoot through.
Four-Layer PCB
3.2
SOP-8 (Exposed Pad)
2.8
2.4
Provide enough copper area around the power MOSFETs
2.0
and the inductors to aid in heat sinking. Using thick
copper PCB can also reduce the resistance and
inductance to improve efficiency.
1.6
1.2
0.8
SOP-8
The bank of the output capacitor should be placed
physically close to the load. This can minimize the
impedance seen by the load and then improve the
transient response.
Placing all the high frequency decoupling ceramic
capacitors close to their decoupling targets.
Small-signal components should be located as close
as possible to the IC. The small signal components
include the feedback components, current sensing
components, compensation components, function
setting components and any bypass capacitors.
0.4
0.0
0
25
50
75
100
125
Ambient Temperature (°C)
Figure 5. Derating Curve of Maximum Power Dissipation
Layout Considerations
Layout planning plays a critical role in modern highfrequency switching converter design. Circuit boards with
good layout can help the IC function properly and achieve
low losses, low switching noise, and stable operation with
improved performance. Without a good layout, the PCB
could radiate excessive noise, causing noise-induced IC
problems and converter instability. The following guidelines
is suggested have better IC performance.
These components belong to the high impedance circuit
loop and are inherently sensitive to noise pick-up.
Therefore, they must be located close to their respective
controller pins and away from the noisy switching nodes.
The power components should be placed first. Keep the
connection between power components as short as
possible.
A multi-layer PCB design is recommended. Make use
of one single layer as the power ground and have a
separate control signal ground as the reference of all
signals.
Input bulk capacitors should be placed close to the drain
of the high side MOSFET and the source of the low
side MOSFET.
Place the VCC bypass capacitor as close as possible to
the RT8120E/F.
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is a registered trademark of Richtek Technology Corporation.
DS8120E/F-03
September 2021
RT8120E/F
Outline Dimension
H
A
M
J
B
F
C
I
D
Dimensions In Millimeters
Dimensions In Inches
Symbol
Min
Max
Min
Max
A
4.801
5.004
0.189
0.197
B
3.810
3.988
0.150
0.157
C
1.346
1.753
0.053
0.069
D
0.330
0.508
0.013
0.020
F
1.194
1.346
0.047
0.053
H
0.170
0.254
0.007
0.010
I
0.050
0.254
0.002
0.010
J
5.791
6.200
0.228
0.244
M
0.400
1.270
0.016
0.050
8-Lead SOP Plastic Package
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DS8120E/F-03
September 2021
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RT8120E/F
H
A
M
EXPOSED THERMAL PAD
(Bottom of Package)
Y
J
X
B
F
C
I
D
Dimensions In Millimeters
Dimensions In Inches
Symbol
Min
Max
Min
Max
A
4.801
5.004
0.189
0.197
B
3.810
4.000
0.150
0.157
C
1.346
1.753
0.053
0.069
D
0.330
0.510
0.013
0.020
F
1.194
1.346
0.047
0.053
H
0.170
0.254
0.007
0.010
I
0.000
0.152
0.000
0.006
J
5.791
6.200
0.228
0.244
M
0.406
1.270
0.016
0.050
X
2.000
2.300
0.079
0.091
Y
2.000
2.300
0.079
0.091
X
2.100
2.500
0.083
0.098
Y
3.000
3.500
0.118
0.138
Option 1
Option 2
8-Lead SOP (Exposed Pad) Plastic Package
Richtek Technology Corporation
14F, No. 8, Tai Yuen 1st Street, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: (8863)5526789
Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should
obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot
assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be
accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.
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DS8120E/F-03
September 2021
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