®
RT8131B
5V High Efficiency Synchronous Buck PWM Controller
General Description
Features
The RT8131B is a high efficiency single phase
synchronous Buck DC-DC controller with 5V supply
voltage.
High Light Load Efficiency
Single 5V Driver Voltage
Integrated High Driving Capability N-MOSFET Gate
Drivers
300kHz Fixed Frequency Internal Oscillator
88% Maximum PWM Duty Cycle
Power Good Indicator
Enable/Disable Control
Internal Soft-Start
Lossless Low-Side MOSFET RDS(ON) Current Sensing
for Over-Current Fault Monitoring
LGATE Over-Current Setting (LGOCS)
OCP, UVP, OVP, OTP, UVLO
current sense technique for over-current protection with
adjustable threshold set by the LGATE pin (LGOCS).
Other features include power good indication, enable/
disable control and internal soft-start. The RT8131B also
provides fault protection functions to protect the power
stage output. With above functions, the IC provides
customers a cost-effective solution for high efficiency
power conversion. The RT8131B is available in the WDFN10L 3x3 package.
Ordering Information
Package Type
QW : WDFN-10L 3x3 (W-Type)
Lead Plating System
G : Green (Halogen Free and Pb Free)
Note :
Richtek products are :
RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020.
Applications
RT8131B
Motherboard, Memory/Chip-Set Power
Graphic Card, GPU/Memory Core Power
Low Voltage, High Current DC-DC Regulator
Pin Configuration
(TOP VIEW)
BOOT
PHASE
UGATE
LGATE
GND
1
2
3
4
5
GND
The RT8131B has embedded MOSFET gate driver with
high driving capability, supporting driving voltage up to 5V.
This device uses lossless low-side MOSFET RDS(ON)
11
10
9
8
7
6
PGOOD
VOS
FB
COMP/EN
VCC
WDFN-10L 3x3
Suitable for use in SnPb or Pb-free soldering processes.
Marking Information
KT= : Product Code
KT=YM
DNN
YMDNN : Date Code
Copyright © 2017 Richtek Technology Corporation. All rights reserved.
DS8131B-00 March 2017
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
1
RT8131B
Functional Pin Description
Pin No.
Pin Name
Pin Function
1
BOOT
Bootstrap supply for high-side gate driver. Connect this pin to a power source
VCC through a bootstrap diode, and connect a 0.1F or greater ceramic
capacitor from this pin to the PHASE pin to supply the power for high-side gate
driver.
2
PHASE
Switch node. Connect this pin to the switching node of Buck converter. This pin
is also the floating drive return of the high-side MOSFET gate driver.
3
UGATE
High-side MOSFET gate driver output. Connect this pin to the Gate of high-side
MOSFET for floating drive.
LGATE
Low-side MOSFET gate driver output. Connect this pin to the Gate of low-side
MOSFET. This pin is also used for Over-Current Protection (OCP) threshold
setting. Connect a resistor (ROCSET) from this pin to the GND pin to set the OCP
threshold.
4
5,
GND
11 (Exposed Pad)
Ground. The exposed pad must be soldered to a large PCB and connected to
GND for maximum power dissipation.
6
VCC
Supply voltage input. It is recommended to connect a 1F or greater ceramic
capacitor from this pin to the GND pin. VCC also powers the low-side gate driver.
7
COMP/EN
Compensation node. Connect R-C network between this pin and the FB pin for
PWM control loop compensation. This pin is also used for enable/disable control.
Connect a small signal MOSFET to this pin to implement enable/disable control.
8
FB
9
VOS
10
PGOOD
Feedback voltage input. This pin is used for output voltage feedback input and
it is also monitored for power good indication. Connect this pin to the converter
output through voltage divider resistors for output voltage regulation.
Voltage of output feedback sense input. This pin monitors output over-voltage
protection and under-voltage protection. Connect this pin to output through
voltage divider resistors.
Power good indicator output. This pin provides an open-drain output. Connect
this pin to a voltage source through a pull-up resistor. The PGOOD voltage goes
high to indicate the output voltage is in regulation. This pin can be left open if the
power good indication function is not used.
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is a registered trademark of Richtek Technology Corporation.
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RT8131B
Functional Block Diagram
COMP/EN
VCC
Regulator
BOOT
UGATE
FB
VREF
VREF
EA
+
+
CMP
UV_level
VOS
VCC
IOCSET
Control
Logic
+
UV
OV_level
PHASE
PWM
+
CMP
-
-
OV
OC
Current
Sense & OCP
Comparator
VCC
LGATE
+
PGH_level
GND
+
-
PGL_level
+
-1
PGOOD
Operation
The RT8131B is a high efficiency single-phase synchronous Buck controller with integrated MOSFET driver. The controller
has a fixed frequency control, a fixed frequency 300kHz oscillator is integrated to minimize external components.
Enable
The RT8131B remains in shutdown if the COMP/EN pin is lower than 0.3V (Max). When the COMP/EN pin rises above
the enable trip point, the RT8131B will begin a soft-start cycle.
Over-Current Threshold Setting
Current limit threshold is externally programmed by adding a resistor (ROCSET) between LGATE and GND. Once VCC
exceeds the POR threshold, an internal current source IOC flows through ROCSET. The voltage across ROCSET is stored as
the current limit protection threshold. After that, the current source is switched off.
Under-Voltage Protection
If the VOS voltage is lower than the UVP threshold during normal operation, UVP will be triggered. When the UVP is
triggered, both UGATE and LGATE go low until VCC is resupplied and exceeds the POR rising threshold voltage.
Over-Voltage Protection
If the VOS voltage is higher than the OVP threshold during normal operation, OVP will be triggered. When OVP is
triggered, UGATE will go low and LGATE will go high until VCC is resupplied and exceeds the POR rising threshold
voltage.
Copyright © 2017 Richtek Technology Corporation. All rights reserved.
DS8131B-00 March 2017
is a registered trademark of Richtek Technology Corporation.
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3
RT8131B
Absolute Maximum Ratings
(Note 1)
Supply Voltage, VCC ---------------------------------------------------------------------------------------------------- −0.3V to 7V
BOOT to PHASE
DC ---------------------------------------------------------------------------------------------------------------------------- −0.3V to 7V
< 100ns --------------------------------------------------------------------------------------------------------------------- −5V to 8.5V
PGOOD --------------------------------------------------------------------------------------------------------------------- −0.3V to 15V
Input, Output or I/O Voltage -------------------------------------------------------------------------------------------- −0.3V to 7V
PHASE to GND
DC ---------------------------------------------------------------------------------------------------------------------------- −0.3V to 30V
< 100ns --------------------------------------------------------------------------------------------------------------------- −10V to 36V
BOOT to GND
DC ---------------------------------------------------------------------------------------------------------------------------- −0.3V to 37V
< 100ns --------------------------------------------------------------------------------------------------------------------- −0.5V to 43V
UGATE to GND
DC ---------------------------------------------------------------------------------------------------------------------------- −0.3V to 37V
< 100ns --------------------------------------------------------------------------------------------------------------------- −5V to 43V
UGATE to PHASE
DC ---------------------------------------------------------------------------------------------------------------------------- −0.3V to 7V
< 100ns --------------------------------------------------------------------------------------------------------------------- −5V to 7V
LGATE to GND
DC ---------------------------------------------------------------------------------------------------------------------------- −0.3V to 7V
< 100ns --------------------------------------------------------------------------------------------------------------------- −5V to 7V
Power Dissipation, PD @ TA = 25°C (Note 2)
WDFN-10L 3x3 ------------------------------------------------------------------------------------------------------------ 3.27W
Package Thermal Resistance
WDFN-10L 3x3, θJA ------------------------------------------------------------------------------------------------------ 30.5°C/W
WDFN-10L 3x3, θJC ------------------------------------------------------------------------------------------------------ 7.5°C/W
Junction Temperature ---------------------------------------------------------------------------------------------------- 150°C
Lead Temperature (Soldering, 10 sec.) ------------------------------------------------------------------------------ 260°C
Storage Temperature Range ------------------------------------------------------------------------------------------- −65°C to 150°C
ESD Susceptibility (Note 3)
HBM (Human Body Model) --------------------------------------------------------------------------------------------- 2kV
Recommended Operating Conditions
(Note 4)
Power Input Voltage, VIN ----------------------------------------------------------------------------------------------Supply Input Voltage, VCC --------------------------------------------------------------------------------------------Output Voltage Setting, VOUT ---------------------------------------------------------------------------------------Junction Temperature Range ------------------------------------------------------------------------------------------Ambient Temperature Range -------------------------------------------------------------------------------------------
Copyright © 2017 Richtek Technology Corporation. All rights reserved.
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4
5.5V to 26.5V
4.5V to 6V
4.5V to 22V
−40°C to 125°C
−40°C to 85°C
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DS8131B-00 March 2017
RT8131B
Electrical Characteristics
(VCC = 5V, TA = 25°C, unless otherwise specified)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
4.5
--3.6
--0.793
5
2
4.1
3.8
0.3
17
0.8
6
-4.2
---0.807
V
mA
--
165
--
C
General
Supply Input Voltage
VCC Supply Current
VCC POR Threshold
VCC POR Hysteresis
Soft-Start Interval
Reference Voltage
VCC
ICC
VPORH
VRORL
tSS
VREF
No Load for UGATE/ LGATE
VCC rising
VCC falling
VFB from 10% to 90%
V
V
ms
V
Protection
Thermal Shutdown Limit
TSD
Over-Voltage Threshold
VOVP
Relative to VOS voltage
140
150
160
%
Under-Voltage Threshold
VUVP
Relative to VOS voltage
40
50
60
%
OVP Propagation Delay
tOVP_DLY
--
10
--
s
UVP Propagation Delay
tUVP_DLY
--
10
--
s
OC Current Source
IOC
9
10
11
A
OC Preset Trigger Voltage
VOC_Preset
ROCSET is not populated
--
0.6
--
V
From VCC > 4.5V to Soft-Start
--
--
25
ms
Over Current Setting Time Delay tOCP
MOSFET Gate Driver
UGATE Drive Source
IUGATEsr
VBOOT – VPHASE = 5V, Max
Source current
--
1.5
--
A
LGATE Drive Source
ILGATEsr
VLGATE = 5V, max source current
--
1.5
--
A
UGATE Drive Sink
RUGATEsk
VUGATE – VPHASE = 0.1V
--
1.8
--
LGATE Drive Sink
RLGATEsk
VLGATE = 0.1V
--
1.2
--
Dead Time
tDEAD
--
30
--
ns
PWM Controller
EA Open Loop Gain
GEA
(Note 5)
--
80
--
dB
EA Bandwidth
BW
(Note 5)
--
15
--
MHz
Maximum Duty
DMAX
--
88
--
%
--
0.9
--
V
--
0.7
--
V
--
--
0.3
V
270
300
330
kHz
Ramp Valley
Ramp Amplitude
VOSC
VIN = 12V
COMP/EN Disable Threshold
PWM Frequency
PGOOD Threshold
fOSC
VPGOOD_H
Relative to FB voltage
0.86
0.89
0.92
VPGOOD_L
Relative to FB voltage
0.68
0.71
0.74
V
PGOOD Low Level
VOL_PGOOD Sink current = 4mA
--
--
0.4
V
EN to Soft-Start Delay
tDELAY_EN
--
--
500
s
(Note 5)
Copyright © 2017 Richtek Technology Corporation. All rights reserved.
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is a registered trademark of Richtek Technology Corporation.
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5
RT8131B
Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in
the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may
affect device reliability.
Note 2. θJA is measured under natural convection (still air) at TA = 25°C with the component mounted on a high effectivethermal-conductivity four-layer test board on a JEDEC 51-7 thermal measurement standard. θJC is measured at the
exposed pad of the package.
Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
Note 5. Guaranteed by design.
Typical Application Circuit
VIN
DBOOT
VCC
5V
VPGOOD
R1
2.2
C1
NC
RPGOOD
10k
RT8131B
6
EN
RFB2
4.53k
CS
2.7nF
VCC
CBP
2.2µF
UGATE 3
RBOOT
0
RUGATE
0
CBOOT
0.1µF
PHASE 2
LGATE 4
10 PGOOD
7
RS
30k
BOOT 1
ROCSET
6.8k
COMP/EN
FB 8
CP
22pF
VOS
GND
5, 11 (Exposed Pad)
Q2
C4
10µF x 4
Q1
470µF x 2
VOUT
L1
6.8µH
RSNB
1
CSNB
2.2nF
RFB1
63.4k
R2
6.04k
C2
680pF
RVOS1
63.4k
RL
C5
10µF x 2
COUT
270µF
9
RVOS2
4.53k
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RT8131B
Typical Operating Characteristics
Reference Voltage vs. Temperature
803
95
802
90
801
Reference Voltage (V)
Efficiency (%)
Efficiency vs. Load Current
100
85
80
75
70
65
60
55
800
799
798
797
796
795
794
793
VIN = 20V, VCC = 5V, VOUT = 12V
50
VIN = 20V, VCC = 5V, No load
792
0
1
2
3
4
5
6
-50
-25
0
25
50
75
Load Current (A)
Temperature (°C)
Load Transient Response
Power On from VCC
100
125
VOUT
(200mV/Div)
VOUT
(10V/Div)
I LOAD
(5A/Div)
V CC
(5V/Div)
UGATE
(20V/Div)
UGATE
(20V/Div)
LGATE
(10V/Div)
LGATE
(10V/Div)
VIN = 20V, VCC = 5V, VOUT = 12V
VIN = 20V, VCC = 5V, VOUT = 12V, ILOAD = 5A
Time (100μs/Div)
Time (10ms/Div)
Power Off from VCC
Power On from COMP/EN
VOUT
(10V/Div)
VOUT
(5V/Div)
V CC
(5V/Div)
UGATE
(20V/Div)
LGATE
(10V/Div)
VIN = 20V, VCC = 5V, VOUT = 12V, ILOAD = 5A
Time (20ms/Div)
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COMP/EN
(1V/Div)
UGATE
(20V/Div)
LGATE
(10V/Div)
VIN = 20V, VCC = 5V, VOUT = 12V, ILOAD = 5A
Time (10ms/Div)
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RT8131B
Power Off from COMP/EN
OCP
PGOOD
(5V/Div)
VOUT
(5V/Div)
COMP/EN
(1V/Div)
IL
(5A/Div)
UGATE
(20V/Div)
LGATE
(10V/Div)
UGATE
(20V/Div)
LGATE
(10V/Div)
VIN = 20V, VCC = 5V, VOUT = 12V, ILOAD = 5A
VIN = 20V, VCC = 5V, VOUT = 12V, ROCSET = 3.9kΩ
Time (1ms/Div)
Time (10μs/Div)
Short OCP
UVP
PGOOD
(10V/Div)
PGOOD
(5V/Div)
IL
(4A/Div)
UGATE
(20V/Div)
LGATE
(10V/Div)
VIN = 20V, VCC = 5V, VOUT = 12V, ROCSET = 3.9kΩ
Time (5μs/Div)
VOS
(400mV/Div)
UGATE
(50V/Div)
LGATE
(10V/Div)
VIN = 20V, VCC = 5V, VOUT = 12V
Time (5ms/Div)
OVP
PGOOD
(5V/Div)
VOS
(800mV/Div)
UGATE
(50V/Div)
LGATE
(10V/Div)
VIN = 20V, VCC = 5V, VOUT = 12V
Time (500μs/Div)
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RT8131B
Application Information
Supply Voltage and Power-On Reset
Power Up with Pre-Bias Voltage
The VCC pin is the power supply pin of the RT8131B. The
input voltage range (VCC) is from 4.5V to 6V with respect
to the GND pin. An internal linear regulator regulates the
supply voltage for internal control logic circuit. The VCC
pin also supplies the power for the integrated low-side
MOSFET gate driver. A 1μF ceramic capacitor or greater
is recommended for the Vcc voltage de-coupling. Place
the de-coupling capacitor physically close to the VCC pin.
Conventionally, when the converter output capacitor has
been pre-charged to a non-zero positive voltage, the FB
pin voltage of the PWM controller is non-zero. If the
converter is powered up under this condition, the softstart function of PWM controller will turn on low-side
MOSFET with maximum duty ratio to rapidly discharge
the output capacitor so as to force the FB voltage to track
the internal soft-start voltage. Large current is then drawn
from the output capacitor while the discharge is taking
place. The discharge current depends on the inductance
and the output capacitance. Output voltage may oscillate
and go negative. The negative output voltage could damage
the load.
The Power-On Reset (POR) circuit monitors the VCC pin
voltage. If VCC exceeds the POR rising threshold, the
controller begins to work and prepares for soft-start
operation. If VCC falls below the POR falling threshold,
the controller stops working. All MOSFETs stop switching,
and all protections are reset. There is a hysteresis between
the POR rising and falling thresholds to prevent
inadvertently reset caused by noise.
Soft-Start
When the controller input voltage (VCC) rises and exceeds
the POR rising threshold at power up, the RT8131B
initiates soft-start operation after the tOCP time delay. The
soft-start function is used to prevent large inrush current
from input power source while converter is powered up.
The IC provides soft-start function internally. The FB voltage
will track the internal soft-start voltage, which ramps up
from zero in a monotone during the soft-start period.
Therefore, the duty cycle of PWM signal will increase
gradually and so does the input current.
Figure 1 shows the power-up operation of the RT8131B.
tSS
VCC POR
t = 2 x tSS
The RT8131B implements control circuits specifically to
prevent the negative voltage when the converter is powered
up with pre-biased voltage on the output capacitor.
In order to prevent the high inrush current at power up
beginning. The RT8131B control circuits specifically
design the pre-biased power up circuit. And it only can be
activated when VFB < 0.1V.
Figure 2 shows the waveform that converter is powered
up with pre-biased output voltage.
EN
(5V/Div)
VOUT
(5V/Div)
UGATE
(20V/Div)
LGATE
(10V/Div)
0.9xVOUT
Time (50ms/Div)
Figure 2. Power Up with Pre-biased Output Voltage
VCC
0.1xVOUT
VOUT
tOCP
UV Blanking Time
Figure 1. Power Up Operation
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RT8131B
Enable/Disable Function
The COMP/EN pin is used to enable or to disable the
controller. Because the COMP/EN pin is also the error
amplifier output, it is recommended to use a small signal
MOSFET with low capacitance C gd to minimize the
influence of the COMP/EN pin capacitance on loop
response. Use a small signal MOSFET or BJT to
implement the enable/disable control. Connect the Drain
of small signal MOSFET (or the Collector of BJT) to the
COMP/EN pin and its Source (or the Emitter of BJT) to
ground for enable/disable control. If the COMP/EN voltage
is pulled down below the enable level VEN, the controller
is disabled with both UGATE and LGATE go low after
about 700ns delay time. If the COMP/EN pin is released,
the COMP/EN voltage rises and then begins to soft-start.
Since COMP/EN directly affects the behavior of voltage
mode controller. Thus it should be pulled low as soon as
possible during shutdown procedure, less than 0.3μs is
recommended.
The OVP function belongs to a latch protection. The
RT8131B will not repeat the soft-start operation unless
the VCC voltage is toggled off and on to reset the OVP.
Under-Voltage Protection (UVP)
If the VOS voltage is lower than the UVP threshold during
normal operation, UVP will be triggered. When UVP is
triggered, both UGATE and LGATE will go low to protect
the load from under-voltage condition. Referring to Figure
1, the UVP function is not activated until three times softstart time completes. The UVP function belongs to a latch
protection, and it is masked during the period of three
times soft-start time. The RT8131B will not repeat the
soft-start operation unless the VCC voltage is toggled off
and on to reset the UVP.
A power on sequence should be concerned. When VCC
exceeds than POR threshold but VIN is not present, the
UVP will be triggered. So, the VIN sequence should be
earlier than VCC for successfully power up.
Power Good Indication
Over-Current Protection (OCP)
The RT8131B monitors the converter output voltage
through the FB pin for power good indication. The PGOOD
pin is an open-drain output, and it should be tied to a
voltage source VPGOOD no greater than 12V through a pull
The RT8131B utilizes low-side MOSFET RDS(ON) current
sense technique for over-current protection (OCP). After
low-side MOSFET is turned on, the controller monitors
the voltage across low-side MOSFET by sensing the
PHASE voltage. The RT8131B uses cycle-by-cycle
inductor valley current sense, the controller samples and
holds the PHASE voltage before low-side MOSFET is
turned off. This sampled PHASE voltage represents the
inductor valley current, and it is compared with the user
defined threshold voltage for OCP. When the inductor
current exceeds the user defined threshold level for two
consecutive PWM switching cycles, OCP will be
triggered. When OCP is triggered, both UGATE and LGATE
will go low to protect the load from over-current condition.
The OCP function belongs to a latch protection. The IC
will not repeat the soft-start operation unless the VCC
voltage is toggled off and on to reset the OCP.
up resistor RPGOOD. Referring to the typical application, it
is recommended to choose the RPGOOD to set maximum
1mA sink current into the PGOOD pin. If the FB pin voltage
stays within the voltage window of ±11.25% of VREF
(typical), the PGOOD voltage will go high to indicate that
the converter output voltage is in regulation. If the FB pin
voltage is out of the voltage window, the PGOOD voltage
goes low after about 10μs delay time to indicate that the
converter output voltage is out of regulation. If the power
good indication function is not used, the PGOOD pin can
be left open.
Over-Voltage Protection (OVP)
If the VOS voltage is higher than the OVP threshold during
normal operation, OVP will be triggered. When OVP is
triggered, UGATE will go low and LGATE will go high to
discharge the converter output capacitor to protect the
load from over voltage condition. When the FB pin voltage
falls below 0.1V, LGATE will go low to stop the discharge.
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LGATE Over-Current Protection Threshold Setting
(LGOCS)
The LGATE pin is not only for driving the low-side MOSFET,
but also is used to set the over-current protection (OCP)
threshold. Figure 3 shows the connection for OCP
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RT8131B
threshold setting, in which a resistor ROCSET connected
from the LGATE pin to the GND pin sets the OCP threshold.
Although the OCP threshold voltage is internally clamped
at 600mV when ROCSET is not connected, this preset
After the controller input voltage VCC exceeds the POR
rising threshold at power up, the IC waits for a period of
time for OCP setting before soft-start operation begins.
During this period, the UGATE output is low and the LGATE
output is in tri-state. An internal current source IOCSET is
switched on and then flows out of the LGATE pin to the
external resistor ROCSET to set the OCP threshold. The
voltage drop across ROCSET is stored by the controller as
the OCP threshold VOCSET. After that, the current source
is switched off, and the LGATE output leaves tri-state then
goes low. The resistance value of ROCSET is determined
by the following equation :
threshold voltage may be very high to most of applications.
Hence, it is recommended to keep the ROCSET always
well-connected to protect the converter from over-current
condition.
RDS(ON) IMAX
V
ROCSET OCSET
IOCSET
IOCSET
where IMAX represents the maximum inductor valley
current, RDS(ON) is the on state channel resistance of the
low-side MOSFET.
If the ROCSET is not connected, the internal current source
IOCSET will charge the Cgs of the low-side MOSFET during
the OCP threshold setting period. Under this condition,
the LGATE voltage may be high enough to turn on the
low-side MOSFET so that the output capacitor is
discharged. Although the LGATE voltage may be high
enough to turn on the low-side MOSFET, the OCP
threshold voltage is internally clamped at 600mV (typical)
and stored as the preset value.
Figure 4 shows the bootstrap circuit, which is used for
the high-side MOSFET driving. The CBOOT is used to store
and supply the energy for high-side MOSFET floating drive,
and the DBOOT is used for voltage blocking. Choose the
DBOOT with sufficient voltage rating to block the PHASE
peak voltage (consider switching spike) plus the voltage
V CC.
When the low-side MOSFET is on, the PHASE voltage is
pulled down to ground and the DBOOT conducts to charge
the CBOOT. When the high-side MOSFET driver is on, part
of the charge stored in the CBOOT is transferred to the
high-side MOSFET to turn it on. Use 0.1μF or greater
ceramic capacitor as the CBOOT to ensure the high-side
MOSFET gate driver operation. The CBOOT and DBOOT should
be placed physically close to the BOOT and PHASE pins
to minimize the trace parasitic components.
VGD
BOOT
DBOOT
VIN
CBOOT
MOSFET Driver
VCC
UGATE
RUGATE
High-Side
MOSFET
PHASE
IOCSET
Figure 4. Bootstrap Circuit
Control Logic
OC
Bootstrap Circuit
PHASE
Current Sense
and OCP
Comparator
x1
VCC
LGATE
ROCSET
Figure 3. OCP Threshold Setting
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L
MOSFET Gate Drivers
In synchronous rectified Buck topology, the dead-time is
utilized to prevent cross conduction of high-side and lowside MOSFETs. The RT8131B implements non-overlapping
MOSFET gate drivers with dead-time control scheme to
ensure a safe operation of MOSFET switching.
For high output current applications, multiple power
MOSFETs are usually paralleled to reduce the total
RDS(ON). The MOSFET gate driver needs to have higher
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RT8131B
driving capability to switch on/off these paralleled
MOSFETs. The RT8131B integrates MOSFET gate drivers
that have high current driving capability to have lower
switching loss and thus better performance of conversion
efficiency. The embedded MOSFET drivers contribute to
the majority of power dissipation of the controller. Therefore,
WDFN package is chosen because of its power dissipation
rating. If gate resistor is not used, the power dissipation
of the controller can be approximately calculated by the
following equation :
PSW = fSW (Qg_High x VBOOT-PHASE + Qg_Low x VCC)
where VBOOT-PHASE represents the voltage across the
bootstrap capacitor.
It is important to make sure that the controller can dissipate
the switching loss and have enough room for safe operation
when power MOSFETs are paralleled.
Input Capacitor Selection
Voltage rating and current rating are the key parameters
in selecting input capacitor. Generally, input capacitor has
a voltage rating 1.5 times greater than the maximum input
voltage is a conservatively safe design.
The input capacitor is used to supply the input RMS
current, which can be approximately calculated by the
following equation :
IRMS IOUT
VOUT
V
1 OUT
VIN
VIN
The next step is to select proper capacitor for RMS current
rating. Using more than one capacitor with low equivalent
series resistance (ESR) in parallel to form a capacitor
bank is a good design. Besides, placing ceramic capacitor
close to the Drain of the high-side MOSFET is helpful for
reducing the input voltage ripple at heavy load.
Inductor Selection
Inductor plays an important role in step-down converters
because the energy from the input power rail is stored in
it and then released to the load. From the viewpoint of
efficiency, the DC resistance (DCR) of inductor should be
as small as possible to minimize the conduction loss. In
addition, because inductor uses most of the board space,
its size is also important. Low profile inductors can save
board space especially when the height has limitation.
However, low DCR and low profile inductors are usually
cost ineffective.
Output Capacitor Selection
Additionally, larger inductance results in lower ripple
current, which means lower power loss. However, the
inductor current rising time increases with inductance value.
This means the transient response will be slower. Therefore,
the inductor design is a trade-off between performance,
size and cost.
VOUT_ESR IL x ESR
In general, inductance is designed so that the ripple
current ranges between 20% to 40% of full load current.
The inductance can be calculated by the following
equation :
LMIN
fSW
VIN VOUT
V
OUT ,
k IOUT_FULL LOAD
VIN
where k is 0.2 to 0.4
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The output capacitor and the inductor form a low-pass filter
in the Buck topology. The electrolytic capacitor is used
for this application because it can provide large capacitance
value. In steady state condition, the output capacitor
supplies only AC ripple current to the load, which means
the output capacitor must be able to handle the inductor
ripple current. The ripple current flows into/out of the
capacitor results in ripple voltage, which can be determined
by the following equation :
In addition, the output voltage ripple is also influenced by
the switching frequency and the capacitance value.
VOUT_C = IL
1
8 COUT fSW
Another parameter that has influence on the output voltage
sag is the equivalent series inductance (ESL). The rapid
change in load current results in di/dt during transient.
Therefore, ESL contributes to part of the voltage sag. Using
capacitors that have low ESL can obtain better transient
performance. Generally, using several capacitors
connected in parallel can have better transient performance
than using single capacitor for the same total ESR.
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RT8131B
Unlike the electrolytic capacitor, the ceramic capacitor has
relative low ESR and can reduce the voltage deviation during
load transient. However, the ceramic capacitor can only
provide low capacitance value. Therefore, using a mixed
combination of electrolytic capacitor and ceramic capacitor
can also have better transient performance.
PWM Feedback Loop Compensation
In continuous conduction mode, the RT8131B operates
with fixed frequency and uses voltage mode control for
output voltage regulation. The IC utilizes voltage error
amplifier with external compensation to provide flexibility
in feedback loop compensator design. Figure 5 shows
the voltage mode control loop of a Buck converter. The
control loop consists of the modulator, power stage and
the compensator.
LOUT
Q1
VIN
DCR VOUT
To Load
CIN
ESR
MOSFET
Driver
In order to obtain an accurate output voltage regulation
and fast transient response, a compensator is necessary.
Depending on the inductor and output capacitor, different
type of compensator can be used to finish the feedback
loop compensation. By inserting a well designed
compensator into the feedback loop, the closed loop
control-to-output transfer function can be shaped to have
adequate crossover frequency and sufficient phase margin.
The design goals are:
Obtain high gain at low frequency for DC regulation
accuracy
Obtain sufficient bandwidth for transient performance
(generally, 1/10 to 1/5 switching frequency)
Obtain sufficient phase margin for stability (generally
>45° )
Figure 6 shows the Type-III compensator, which is
composed of voltage error amplifier, impedance network
Z1 and Z2.
Z2
Q2
COUT
CP
RS
Z2
PWM
Comparator
+
-
CS
Z1
COMP
FB
EA
+
VREF
Z1
C2
RFB2
COMP
EA
+
FB
R2
RFB1
VOUT
Ramp
VREF
Figure 5. Voltage Mode Control Loop of Buck Converter
Output voltage of the converter is scaled by the divider
resistors and then compared to the reference voltage, which
is the regulation level seen by the controller. The error
amplifier output voltage VCOMP is compared to the sawtooth waveform from the oscillator to generate PWM signal.
The output voltage is then regulated according to the duty
cycle of the PWM signal.
Vˆ OUT
The system open loop gain ˆ
has two poles at
VCOMP
fLC and one zero at fESR. The frequency of fLC and fESR can
RFB2
Figure 6. Type-III Compensator
The Type-III compensator introduces three poles and two
zeros to the system. The first pole is located in low
frequency to increase the DC gain for voltage regulation
accuracy and is usually referred to as the pole at zero.
The location of rest of the two poles and two zeros can be
determined as follows :
fZ1
1
1
, fZ2
2 RS CS
2 R2 RFB1 C2
fP1
1
, fP2
2 R2 C2
be calculated by the following expressions :
fLC
1
2 LOUT COUT
fESR
1
1
C CP
2 RS S
CS CP
2 COUT ESR
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RT8131B
Figure 7 shows the system Bode plot. The close loop
gain is the sum of modulation gain and the compensation
gain. The modulation DC gain is determined by VIN/ΔVOSC,
where ΔVOSC is peak to peak voltage of the saw-tooth
ramp. In general, fZ1 is placed at half of fLC, and fZ2 is
placed at fLC to boost the large phase lag created by the
double pole especially when ESR is low. fP1 is typically
placed at fESR to obtain a −20dB/dec slope at crossover
frequency. fP2 is placed at half of the switching frequency
to increase the attenuation in high frequency.
After calculating the compensation values, draw the
system Bode plot to check the crossover frequency and
phase margin. Due to the circuit parasitic components
and the characteristic deviation in the inductor and output
capacitors, further tuning of the compensation value to
obtain the required crossover frequency and phase margin
is necessary.
(dB)
Compensation Gain
Freq.(Log)
Close Loop Gain
fP1
fZ2
PD(MAX) = (125°C − 25°C) / (30.5°C/W) = 3.27W for a
WDFN-10L 3x3 package
The maximum power dissipation depends on the operating
ambient temperature for the fixed TJ(MAX) and the thermal
resistance, θJA. The derating curves in Figure 8 allows
the designer to see the effect of rising ambient temperature
on the maximum power dissipation.
fESR
0
fZ1
For continuous operation, the maximum operating junction
temperature indicated under Recommended Operating
Conditions is 125°C. The junction-to-ambient thermal
resistance, θJA, is highly package dependent. For a
WDFN-10L 3x3 package, the thermal resistance, θJA, is
30.5°C/W on a standard JEDEC 51-7 high effective-thermalconductivity four-layer test board. The maximum power
dissipation at TA = 25°C can be calculated as below :
fP2
Modulation Gain
fCROSS
Figure 7. System Bode Plot
Thermal Considerations
The junction temperature should never exceed the
absolute maximum junction temperature TJ(MAX), listed
under Absolute Maximum Ratings, to avoid permanent
damage to the device. The maximum allowable power
dissipation depends on the thermal resistance of the IC
package, the PCB layout, the rate of surrounding airflow,
and the difference between the junction and ambient
temperatures. The maximum power dissipation can be
calculated using the following formula :
4.0
Maximum Power Dissipation (W)
fLC
where TJ(MAX) is the maximum junction temperature, TA is
the ambient temperature, and θJA is the junction-to-ambient
thermal resistance.
Four-Layers PCB
3.6
3.2
2.8
2.4
2.0
1.6
1.2
0.8
0.4
0.0
0
25
50
75
100
125
Ambient Temperature (°C)
Figure 8. Derating Curve of Maximum Power Dissipation
PD(MAX) = (TJ(MAX) − TA) / θJA
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DS8131B-00 March 2017
RT8131B
Layout Considerations
PCB layout plays an important role in high current, high frequency switching converter design. The general layout guide
line is listed as follows.
Minimize the high-current loop as short as possible. The current transition between MOSFETs usually causes di/dt
voltage spike and thus the EMI issue due to parasitic components on PCB trace and component lead. The PCB trace
parasitic components cause not only excessive voltage spike, but also power loss. To reduce the PCB trace parasitic,
place the high-side, low-side MOSFETs and the inductor with short current loop as possible.
Connect the controller and power MOSFETs with wide width and short length PCB traces. Because the RT8131B has
integrated high-current MOSFET gate drivers, the PCB trace for MOSFET driving should be sized to carry at least 2A
peak current.
For bootstrap circuit, place the bootstrap diode DBOOT close to the BOOT pin, and place the bootstrap capacitor CBOOT
physically close to BOOT pin and PHASE pin with wide and short copper trace connection.
Place the ceramic capacitor close to the VCC pin for noise de-coupling.
Place all the function setting and compensation components as close to their associated pins as possible. This
includes :
Place the compensation components close to the VOS pin, FB pin and COMP pin to avoid noise pickup. Voltage
divider resistors connected to the FB pin should be placed close to the controller.
Place the OCP setting resistor ROCSET close to the LGATE pin.
Place the small-signal MOSFET or BJT used for enable/disable function close to the COMP pin.
Place ceramic capacitor close to the drain of high-side MOSFET to decrease the input voltage ripple.
The output voltage feedback trace should be away from the switching node, power MOSFETs and inductor to avoid
noise pickup.
Place the bulk capacitors close to the load.
Place bootstrap circuit close to the BOOT pin.
MOSFET driver
trace : wide and short
RPGOOD
VIN
Enough copper
area to carry
load current.
VOUT
LOAD
BOOT
PHASE
UGATE
1
10
2
9
LGATE
GND
4
3
5
GND
Place CIN close
to MOSFET.
Via inner ground layer
To other circuit
DBOOT
CBOOT
8
7
11
6
PGOOD
VOS
FB
COMP/EN
VCC
EN
5V/12V
ROCSET
Via inner layer
Place noise
Place ROCSET close decoupling MLCC
to the LGATE pin.
close to the VCC pin.
Place COUT Place snubber
close to load. close to low-side
MOSFET.
Enough vias around
MOSFET lead to
inner ground layer.
Place disable
MOSFET close to
the COMP pin.
Keep voltage feedback trace away from noisy node.
Figure 9. PCB Layout Guide
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RT8131B
Outline Dimension
D2
D
L
E
E2
1
SEE DETAIL A
2
e
A
A1
1
2
1
b
DETAIL A
Pin #1 ID and Tie Bar Mark Options
A3
Note : The configuration of the Pin #1 identifier is optional,
but must be located within the zone indicated.
Symbol
Dimensions In Millimeters
Dimensions In Inches
Min
Max
Min
Max
A
0.700
0.800
0.028
0.031
A1
0.000
0.050
0.000
0.002
A3
0.175
0.250
0.007
0.010
b
0.180
0.300
0.007
0.012
D
2.950
3.050
0.116
0.120
D2
2.300
2.650
0.091
0.104
E
2.950
3.050
0.116
0.120
E2
1.500
1.750
0.059
0.069
e
L
0.500
0.350
0.020
0.450
0.014
0.018
W-Type 10L DFN 3x3 Package
Richtek Technology Corporation
14F, No. 8, Tai Yuen 1st Street, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: (8863)5526789
Richtek products are sold by description only. Customers should obtain the latest relevant information and data sheets before placing orders and should verify
that such information is current and complete. Richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek
product. Information furnished by Richtek is believed to be accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use;
nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent
or patent rights of Richtek or its subsidiaries.
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