®
RT8230A/B/C/D/E
Dual-Channel Synchronous DC/DC Step-Down Controller
with 5V/3.3V LDOs
General Description
Features
The RT8230A/B/C/D/E is a dual-channel step-down,
controller generating supply voltages for battery-powered
systems. It includes two Pulse-Width Modulation (PWM)
controllers adjustable from 2V to 5.5V, and two fixed 5V/
3.3V linear regulators. Each linear regulator provides up
to 100mA output current. The 5V linear regulator supplies
power to the PWM drivers. The RT8230A/B/C/D/E includes
on-board power-up sequencing, a power-good output,
internal soft-start, and soft-discharge output that prevents
negative voltage during shutdown.
A constant current ripple PWM control scheme operates
without sense resistors and provides 100ns response to
load transient. To eliminate noise in audio applications,
an ultrasonic mode is included, which maintains the
switching frequency above 25kHz. Moreover, the diodeemulation mode maximizes efficiency for light load
applications. The RT8230A/B/C/D/E is available in the
WQFN-20L 3x3 package.
Maximum Duty Up to 96%
CCRCOT Control with 100ns Load Step Response
Wide Input Voltage Range : 5V to 25V
Dual Adjustable Output :
CH1 : 2V to 5.5V
CH2 : 2V to 4V
Fixed 3.3V and 5V LDO Output : 100mA
1% Accuracy on 3.3V LDO Output
Frequency Adjustable Via TON Setting
4700ppm/ °C RDS(ON) Current Sensing
Adjustable Current Limit Combined with Enable
Control
Internal Soft-Start and Soft-Discharge
Thermal Shutdown
RoHS Compliant and Halogen Free
Applications
Notebook and Sub-Notebook Computers
2-Cell, 3-Cell and 4-Cell Li+ Battery-Powered Devices
Simplified Application Circuit
VIN
RT8230A/B/C/D/E
VIN
VIN
UGATE2
BOOT2
ENLDO/ENC
*
ENLDO/ENC
VIN
PHASE2
VOUT2
LGATE2
UGATE1
*
BOOT1
PHASE1
VOUT1
LGATE1
RTON
FB1
ENTRIP2
ENTRIP1
LDO3
3.3V
LDO5
5V
TON
BYP1
ENM/SECFB
FB2
ENM/SECFB
GND
PGOOD
PGOOD
* : optional
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
DS8230A/B/C/D/E-04 February 2014
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
1
RT8230A/B/C/D/E
Ordering Information
Pin Configurations
RT8230A/B/C/D/E
BYP1
BOOT1
UGATE1
PHASE1
LGATE1
(TOP VIEW)
Package Type
QW : WQFN-20L 3x3 (W-Type)
Pin Function With
A : ENM+ENLDO
B/D : SECFB+ENLDO
C/E : SECFB+ENC
20 19 18 17 16
FB1
ENTRIP1
TON
ENTRIP2
FB2
1
15
2
14
4
Suitable for use in SnPb or Pb-free soldering processes.
RT8230AGQW
2F= : Product Code
YMDNN : Date Code
8
9 10
BYP1
BOOT1
UGATE1
PHASE1
LGATE1
20 19 18 17 16
FB1
ENTRIP1
TON
ENTRIP2
FB2
1
15
2
14
GND
3
4
21
5
13
12
11
6
RT8230BGQW
2E= : Product Code
7
8
LDO3
LDO5
SECFB
ENLDO
VIN
9 10
RT8230B/D
YMDNN : Date Code
BYP1
BOOT1
UGATE1
PHASE1
LGATE1
2E=YM
DNN
7
PGOOD
BOOT2
UGATE2
PHASE2
LGATE2
2F=YM
DNN
12
RT8230A
ments of IPC/JEDEC J-STD-020.
Marking Information
13
11
6
Richtek products are :
RoHS compliant and compatible with the current require-
21
5
Note :
GND
3
LDO3
LDO5
ENM
ENLDO
VIN
PGOOD
BOOT2
UGATE2
PHASE2
LGATE2
Lead Plating System
G : Green
(Halogen Free and Pb Free)
20 19 18 17 16
RT8230CGQW
2D= : Product Code
2D=YM
DNN
YMDNN : Date Code
FB1
ENTRIP1
TON
ENTRIP2
FB2
1
15
2
14
GND
3
4
21
5
3C=YM
DNN
YMDNN : Date Code
7
8
9 10
PGOOD
BOOT2
UGATE2
PHASE2
LGATE2
3C= : Product Code
12
11
6
RT8230DGQW
13
LDO3
LDO5
SECFB
ENC
VIN
RT8230C/E
WQFN-20L 3x3
RT8230EGQW
3D= : Product Code
3D=YM
DNN
YMDNN : Date Code
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
www.richtek.com
2
is a registered trademark of Richtek Technology Corporation.
DS8230A/B/C/D/E-04 February 2014
RT8230A/B/C/D/E
Functional Pin Description
Pin No.
Pin Name
Pin Function
FB1
Feedback Voltage Input for Channel 1. Connect FB1 to a resistive voltage
divider from VOUT1 to GND to adjust output from 2V to 5.5V.
2
ENTRIP1
Enable and Current Limit Setting for Channel 1. There is an internal 5A
current source to the ENTRIP1 pin. Connect a resistor to GND to set the
threshold between 0.2V and 3V for channel 1 current limit. The GND
PHASE1 current limit threshold is 1/10th the voltage on the ENTRIP1 pin.
3
TON
Switching Frequency Setting. Connect a resistor to GND to adjust switching
frequency.
4
ENTRIP2
Enable and Current Limit Setting for Channel 2. There is an internal 5A
current source to the ENTRIP2 pin. Connect a resistor to GND to set the
threshold between 0.2V and 3V for channel 2 current limit. The GND
PHASE2 current limit threshold is 1/10th the voltage on the ENTRIP2 pin.
5
FB2
Feedback Voltage Input for Channel 2. Connect FB2 to a resistive
voltage-divider from VOUT2 to GND to adjust output from 2V to 4V.
6
PGOOD
Power Good Output for Channel 1 and Channel 2. (Logical AND)
7
BOOT2
Bootstrap Supply for Channel 2 High-Side Gate Driver. Connect to an external
capacitor according to the typical application circuits.
8
UGATE2
Gate Drive Output for Channel 2 High-Side MOSFET.
9
PHASE2
Switch Node of Channel 2 MOSFETs. PHASE2 is the return rail for the
UGATE2 high-Side gate driver.
LGATE2
(RT8230A/B/E)
Gate Drive Output for Channel 2 Low-Side MOSFET.
LGATE2
(RT8230C/D)
Gate Drive Output for Channel 2 Low-Side MOSFET and Charge Pump CLK.
The CLK frequency will become fast to pull up charge pump voltage when the
SECFB voltage is low to 2V.
VIN
Supply Voltage Input.
ENLDO
(RT8230A/B/D)
Master Enable Control Input. The LDO5/LDO3 are enabled if it is within logic
high level and disable if it is less than the logic low level.
ENC
(RT8230C/E)
Master Enable Control Input. The channels are enabled if it is within logic high
level and disable if it is less than the logic low level.
ENM
(RT8230A)
Mode Selection with Enable Control Input. Pull up to LDO5 (Ultrasonic mode)
or LDO3 (DEM) to turn on both switch channels. Short to GND for shutdown.
1
10
11
12
13
Feedback Voltage Input for Charge Pump. The SECFB is used to monitor the
SECFB
optional external 14V charge pump. Connect a resistive voltage divider from
(RT8230B/C/D/E)
14V charge pump output to GND to detect the output.
14
LDO5
5V Linear Regulator Output. It is also the supply voltage for the low-side
MOSFET driver and analog supply control circuits.
15
LDO3
3.3V Linear Regulator Output.
LGATE1
(RT8230A/C/D)
Gate Drive Output for Channel 1 Low-Side MOSFET.
LGATE1
(RT8230B/E)
Gate Drive Output for Channel 1 Low-Side MOSFET and Charge Pump CLK.
The CLK frequency will become fast to pull up charge pump voltage when the
SECFB voltage is low to 2V.
16
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
DS8230A/B/C/D/E-04 February 2014
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
3
RT8230A/B/C/D/E
Pin No.
Pin Name
Pin Function
17
PHASE1
Switch Node of Channel 1 MOSFETs. PHASE1 is the return rail for the
UGATE1 high-Side gate driver.
18
UGATE1
Gate Drive Output for Channel 1 High-Side MOSFET.
19
BOOT1
Bootstrap Supply for Channel 1 High-Side Gate Driver. Connect to an external
capacitor according to the typical application circuits.
20
BYP1
Switch Over Source Voltage Input for LDO5.
21
GND
(Exposed Pad)
Ground. The exposed pad must be soldered to a large PCB and connected to
GND for maximum power dissipation.
Function Block Diagram
TON
BOOT1
BOOT2
UGATE1
UGATE2
PHASE1
PHASE2
LDO5
LDO5
Channel1
Buck
Controller
LGATE1
Channel2
Buck
Controller
LGATE2
FB1
ENTRIP1
FB2
ENTRIP2
PGOOD
SW5
Threshold
BYP1
GND
Power-On
Sequence
Clear Fault Latch
ENLDO/ENC
ENM/SECFB
LDO5
LDO5
VIN
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
www.richtek.com
4
REF
LDO3
LDO3
BYP1
is a registered trademark of Richtek Technology Corporation.
DS8230A/B/C/D/E-04 February 2014
RT8230A/B/C/D/E
Operation
The RT8230A/B/C/D/E includes two constant on-time
synchronous step-down controllers and two linear
regulators.
Buck Controller
In normal operation, the high-side N-MOSFET is turned
on when the output is lower than VREF, and is turned off
after the internal one-shot timer expires. While the highside N-MOSFET is turned off, the low-side N-MOSFET is
turned on to conduct the inductor current until next cycle
begins.
Over-Voltage Protection (OVP) & Under-Voltage
Protection (UVP)
The two channel output voltages are continuously
monitored for over-voltage and under-voltage conditions.
When the output voltage exceeds OVP threshold (113%
of VOUT), UGATE goes low and LGATE is forced high;
when it is less than 52% of reference voltage, undervoltage protection is triggered and then both UGATE and
LGATE gate drivers are forced low. The controller is latched
until ENTRIP is reset or LDO5 is re-supplied.
LDO5 and LDO3
Soft-Start (SS)
For internal soft-start function, an internal current source
charges an internal capacitor to build the soft-start ramp
voltage. The output voltage will track the internal ramp
voltage during soft-start interval.
PGOOD
The power good output is an open-drain architecture.
When the two channels soft-start are both finished, the
PGOOD open-drain output will be high impedance.
When the VIN voltage exceed the POR rising threshold,
the LDO5 and LDO3 can be power on by ENLDO.
The linear regulator LDO5 and LDO3 provide 5V and 3.3V
regulated output.
Switching Over
The BYP1 is connected to the channel 1 output. After the
channel 1 output voltage exceeds the set threshold
(4.66V), the output will be bypassed to the LDO5 output
to maximize the efficiency.
Current Limit
The current limit circuit employs a unique “valley” current
sensing algorithm. If the magnitude of the current sense
signal at PHASE is above the current limit threshold, the
PWM is not allowed to initiate a new cycle. Thus, the
current to the load exceeds the average output inductor
current, the output voltage falls and eventually crosses
the under-voltage protection threshold, inducing IC
shutdown.
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
DS8230A/B/C/D/E-04 February 2014
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
5
RT8230A/B/C/D/E
Absolute Maximum Ratings
(Note 1)
VIN, ENLDO, ENC to GND ------------------------------------------------------------------------------------BOOTx to PHASEx ---------------------------------------------------------------------------------------------PHASEx to GND
DC ------------------------------------------------------------------------------------------------------------------- 5V, ILDO5 < 20mA
4.5
4.75
5.1
VIN = 12V, No Load
3.267
3.3
3.333
VIN > 7V, ILDO3 < 100mA
3.217
3.3
3.383
VIN > 5.5V, ILDO3 < 35mA
3.267
3.3
3.333
VIN > 5V, ILDO3 < 20mA
3.217
3.3
3.383
Switching Frequency
f SWx
Minimum Off-Time
T LGATEx
Ultrasonic Mode Frequency
kHz
Soft-Start
Soft-Start Time
Current Sense
VFBx = 2.05V, GND PHASEx
Internal Regulator
LDO5 Output Voltage
LDO3 Output Voltage
VLDO5
VLDO3
V
V
LDO5 Output Current
ILDO5
VLDO5 = 4.5V, VBYP1 = GND, VIN = 7.4V
100
175
--
mA
LDO3 Output Current
ILDO3
VLDO3 = 3V, VIN = 7.4V
100
175
--
mA
Rising Edge At BYP1 Regulation Point
4.4
4.66
4.79
V
LDO5 to BYP1, 10mA
--
1.5
3
Rising Edge
--
4.3
4.5
Falling Edge
3.7
3.9
4.1
Controllers Off
--
2.5
--
PGOOD Detect, VFBx Rising Edge
87
92.5
96
Hysteresis
--
8
--
PGOOD Leakage Current
High State, VPGOOD = 5.5V
--
--
1
A
PGOOD Output Low Voltage
ISINK = 4mA
--
--
0.3
V
109
113
117
%
--
1
--
s
LDO5 Switchover Threshold
VSWTH
to BYP1
LDO5 Switchover Equivalent
RSW
Resistance
UVLO
LDO5 UVLO Threshold
VUVLO5
LDO3 UVLO Threshold
VUVLO3
V
Power Good
PGOOD Threshold
VPGxTH
%
Fault Detection
OVP Trip Threshold
VOVP
FBx with Respect to Internal Reference
OVP Propagation Delay
UVP Trip Threshold
VUVP
UVP Detect, FBx Falling Edge
47
52
57
%
UVP Shutdown Blanking
Time
tSHDN_UVP
From ENTRIPx Enable
--
1.6
--
ms
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
DS8230A/B/C/D/E-04 February 2014
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
7
RT8230A/B/C/D/E
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
--
150
--
C
--
10
--
C
Controller On
0.2
--
3
Controller Off
4.5
--
--
Shutdown
--
--
0.4
Enable
1
--
--
1.6
2.4
3.3
VENLDO = 0.2V, Source
--
1
5
VENLDO = 5V, Sink
--
1
5
Shutdown
--
--
0.4
Enable
1
--
--
1.6
2.4
3.3
--
--
0.8
Buck Controller On Level, ASM Operation
(only for CH1, CH2 keep on DEM)
1.2
--
1.8
Buck Controller On Level, DEM Operation
2.3
--
3.6
Buck Controller On Level, ASM Operation
4.5
--
--
Buck Controller On Level, ASM Operation
(RT8230B/E for CH1, RT8230C/D for CH2)
1.2
--
1.8
Buck Controller On Level, DEM Operation
2.3
--
3.6
Buck Controller On Level, ASM Operation
4.5
--
--
LDO5 to BOOTx
--
80
--
High State, VBOOTx VUGATEx = 0.25V,
VBOOTx VPHASEx = 5V
--
3
--
Low State, VUGATEx VPHASEx = 0.25V,
VBOOTx VPHASEx = 5V
--
2
--
High State, VLDO5 VLGATEx = 0.25V,
VLDO5 = 5V
--
3
--
Low State, VLGATEx GND = 0.25V
--
1
--
LGATEx Rising
--
20
--
UGATEx Rising
--
30
--
Thermal Shutdown
Thermal Shutdown
T SHDN
Thermal Shutdown
Hysteresis
Logic Inputs
ENTRIPx Input Voltage
ENLDO Input Voltage
(RT8230A/B/D)
VENTRIPx
VENLDO
ENLDO Floating, Default Enable
ENLDO Current
(RT8230A/B/D)
ENC Input Voltage
(RT8230C/E)
I ENLDO
VENC
ENC Floating, Default Enable
Buck Controller Off Level
ENM Input Voltage
(RT8230A)
SECFB Input Voltage
(RT8230B/C/D/E)
VENM
VSECFB
V
V
A
V
V
V
Internal Boost Switch
Internal Boost Switch
On-Resistance
Power MOSFET Drivers
UGATEx On-Resistance
LGATEx On-Resistance
Dead-Time
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
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8
ns
is a registered trademark of Richtek Technology Corporation.
DS8230A/B/C/D/E-04 February 2014
RT8230A/B/C/D/E
Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in
the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may
affect device reliability.
Note 2. θJA is measured at TA = 25°C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. θJC is
measured at the exposed pad of the package.
Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
Note 5. Not production tested. Test condition is same with electrical characteristics using application circuit.
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
DS8230A/B/C/D/E-04 February 2014
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
9
RT8230A/B/C/D/E
Typical Application Circuit
VIN
5V to 25V
R1
C1
10µF
C2
0.1µF
R2*
BOOT2
+
19
1
RTON
BOOT1
L2
3.3µH
N4
C7
FB2 5
LGATE1
FB1
13 ENM
21 (Exposed Pad)
R9
ENTRIP1 2
LDO3 15
LDO5 14
GND
C8
4.7µF
C9
4.7µF
PGOOD 6
* : optional
R7
100k
R8
ENTRIP2 4
3 TON
VOUT2
3.3V
R6
66.5k
20 BYP1
Enable
C6
0.1µF
PHASE2 9
10
LGATE2
R3
150k
C14
1µF
R5*
17 PHASE1
16
N2
R4
100k
7
C5
10µF
N3
+
C4
0.1µF
L1
3.3µH
C3
UGATE2 8
18 UGATE1
N1
VOUT1
5V
RT8230A
11 VIN
12 ENLDO
3.3V
5V
PGOOD
VIN
5V to 25V
C1
10µF
R1
C2
0.1µF
R2*
+
C4
0.1µF
19
7
BOOT1
LGATE1
R3
150k
1
PHASE2 9
10
LGATE2
L2
3.3µH
RTON
N4
C10
0.1µF
ENTRIP2 4
R8
2
R9
ENTRIP1
R10
200k
On
15
C8
4.7µF
VCP
LDO5 14
13
PGOOD 6
SECFB
R11
39k
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
R7
100k
Off
LDO3
C11
0.1µF
C13
1µF
C7
FB2 5
FB1
3 TON
VOUT2
3.3V
R6
66.5k
C12
0.1µF
www.richtek.com
10
C6
0.1µF
20 BYP1
C14
1µF
* : optional
R5*
17 PHASE1
16
N2
R4
100k
BOOT2
C5
10µF
N3
+
L1
3.3µH
C3
UGATE2 8
18 UGATE1
N1
VOUT1
5V
RT8230B
11 VIN
12 ENLDO
GND
C9
4.7µF
3.3V
5V
PGOOD
21 (Exposed Pad)
is a registered trademark of Richtek Technology Corporation.
DS8230A/B/C/D/E-04 February 2014
RT8230A/B/C/D/E
VIN
5V to 25V
R1
C1
10µF
RT8230C
C2
0.1µF
R2*
+
19
N3
R5*
17 PHASE1
R3
150k
1
R4
100k
RTON
6
PGOOD
15
C8
4.7µF
N4
C9
4.7µF
C7
R6
66.5k
R7
100k
C10
0.1µF
FB1
C12
0.1µF
C11
0.1µF
BYP1
PGOOD
SECFB
LDO3
LDO5
ENTRIP2
21 (Exposed Pad)
VOUT2
3.3V
FB2 5
LGATE1
R10
200k
13
C13
1µF
R11
39k
14
5V Always On
L2
3.3µH
3 TON
20
3.3V Always On
PHASE2
BOOT1
C6
0.1µF
9
LGATE2 10
16
N2
C14
1µF
BOOT2
7
C5
10µF
+
C4
0.1µF
L1
3.3µH
C3
VIN
12 ENC
18 UGATE1
N1
VOUT1
5V
UGATE2 8
11
ENTRIP1
4
R8
2
R9
VCP
GND
* : optional
VIN
5V to 25V
R1
C1
10µF
RT8230D
C2
0.1µF
R2*
+
19
7
17 PHASE1
R3
150k
1
R4
100k
RTON
N3
6
PGOOD
5V
15
C8
4.7µF
14
C9
4.7µF
21 (Exposed Pad)
LGATE1
L2
3.3µH
N4
C10
0.1µF
C12
0.1µF
C11
0.1µF
PGOOD
SECFB
R10
200k
13
R11
39k
LDO5
ENTRIP2 4
R8
2
R9
ENTRIP1
GND
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
C7
R6
66.5k
R7
100k
BYP1
LDO3
VOUT2
3.3V
FB2 5
FB1
* : optional
DS8230A/B/C/D/E-04 February 2014
PHASE2
C6
0.1µF
9
3 TON
20
3.3V
BOOT1
C5
10µF
R5*
LGATE2 10
16
N2
C14
1µF
BOOT2
8
+
C4
0.1µF
L1
3.3µH
C3
UGATE2
18 UGATE1
N1
VOUT1
5V
11 VIN
12 ENLDO
C13
1µF
VCP
On
Off
is a registered trademark of Richtek Technology Corporation.
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11
RT8230A/B/C/D/E
VIN
5V to 25V
C1
10µF
R1
C2
0.1µF
R2*
+
19
BOOT1
PHASE2
1
RTON
LGATE1
L2
3.3µH
N4
C7
ENTRIP2 4
R8
2
R9
R7
100k
FB1
3 TON
ENTRIP1
15
LDO3
C11
0.1µF
LDO5 14
C8
4.7µF
PGOOD 6
13
VOUT2
3.3V
FB2 5
C10
0.1µF
R10
200k
C6
0.1µF
9
C12
0.1µF
VCP
R5*
R6
66.5k
20 BYP1
C13
1µF
C5
10µF
17 PHASE1
R3
150k
C14
1µF
7
N3
LGATE2 10
16
N2
R4
100k
BOOT2
8
+
C4
0.1µF
L1
3.3µH
C3
UGATE2
18 UGATE1
N1
VOUT1
5V
RT8230E
11 VIN
12 ENC
SECFB
R11
39k
GND
C9
4.7µF
3.3V Always On
5V Always On
PGOOD
21 (Exposed Pad)
* : optional
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DS8230A/B/C/D/E-04 February 2014
RT8230A/B/C/D/E
Typical Operating Characteristics
Efficiency vs. Load Current
Efficiency vs. Load Current
100
100%
100%
100
VOUT1
90
90%
80
80%
VOUT1
DEM
ASM
80%
80
70%
70
70%
70
Efficiency (%)
Efficiency(%)
90%
90
DEM
ASM
60%
60
50%
50
40
40%
30
30%
60%
60
50%
50
40%
40
30%
30
20%
20
20%
20
VIN = 7.4V, RTON = 100kΩ, ENLDO = 5V,
VENTRIP1 = 0.75V, VENTRIP2 = 5V
10%
10
0%0
0.001
0.01
0.1
1
VIN = 12V, RTON = 100kΩ, ENLDO = 5V,
VENTRIP1 = 0.75V, VENTRIP2 = 5V
10%
10
0%
0
0.001
10
0.01
Load Current (A)
VOUT1
DEM
ASM
DEM
ASM
80
80%
70%
70
Efficiency(%)
Efficiency (%)
VOUT2
90
90%
80%
80
60%
60
50%
50
40%
40
30%
30
70%
70
60%
60
50%
50
40
40%
30
30%
20%
20
20%
20
VIN = 20V, RTON = 100kΩ, ENLDO = 5V,
VENTRIP1 = 0.75V, VENTRIP2 = 5V
10%
10
0%
0
0.001
0.01
0.1
1
VIN = 7.4V, RTON = 100kΩ, ENLDO = 5V,
VENTRIP1 = VENTRIP2 = 0.75V
10%
10
0%
0
0.001
10
0.01
0.1
1
10
Load Current (A)
Load Current (A)
Efficiency vs. Load Current
Efficiency vs. Load Current
100%
100
VOUT2
90
90%
90%
90
DEM
ASM
80%
80
70%
70
60%
60
50%
50
40%
40
30%
30
20%
20
10%
10
0%
0
0.001
VOUT2
80
80%
Efficiency (%)
Efficiency (%)
10
Efficiency vs. Load Current
100
100%
90%
90
100%
100
1
Load Current (A)
Efficiency vs. Load Current
100%
100
0.1
DEM
ASM
70%
70
60%
60
50%
50
40
40%
30
30%
20%
20
VIN = 12V, RTON = 100kΩ, ENLDO = 5V,
VENTRIP1 = VENTRIP2 = 0.75V
0.01
0.1
1
Load Current (A)
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10
10%
10
0
0%
0.001
VIN = 20V, RTON = 100kΩ, ENLDO = 5V,
VENTRIP1 = VENTRIP2 = 0.75V
0.01
0.1
1
10
Load Current (A)
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RT8230A/B/C/D/E
Switching Frequency vs. Load Current
Switching Frequency vs. Load Current
200
300
VOUT1, VIN = 8V,
RTON = 100kΩ, ENLDO = VIN,
VENTRIP1 = 0.75V, VENTRIP2 = 5V
Switching Frequency (kHz)1
Switching Frequency (kHz)1
250
DEM
ASM
150
100
50
0
0.001
0.01
0.1
1
250
VOUT1, VIN = 12V,
RTON = 100kΩ, ENLDO = VIN,
VENTRIP1 = 0.75V, VENTRIP2 = 5V
200
150
100
50
0
0.001
10
0.01
Load Current (A)
VOUT1, VIN = 20V,
RTON = 100kΩ, ENLDO = VIN,
VENTRIP1 = 0.75V, VENTRIP2 = 5V
DEM
ASM
250
200
150
100
50
0
0.001
0.01
0.1
1
250
VOUT2, VIN = 8V,
RTON = 100kΩ, ENLDO = VIN,
VENTRIP1 = 5V, VENTRIP2 = 0.75V
100
50
0
0.001
10
0.01
150
100
50
1
Load Current (A)
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14
10
Switching Frequency vs. Load Current
Switching Frequency (kHz)1
Switching Frequency (kHz)1
DEM
ASM
200
0.1
1
400
250
0.01
0.1
Load Current (A)
VOUT2, VIN = 12V,
RTON = 100kΩ, ENLDO = VIN,
VENTRIP1 = 5V, VENTRIP2 = 0.75V
0
0.001
DEM
ASM
150
Switching Frequency vs. Load Current
300
10
200
Load Current (A)
350
1
Switching Frequency vs. Load Current
300
Switching Frequency (kHz)1
Switching Frequency (kHz)1
300
0.1
Load Current (A)
Switching Frequency vs. Load Current
350
DEM
ASM
10
350
VOUT2, VIN = 20V,
RTON = 100kΩ, ENLDO = VIN,
VENTRIP1 = 5V, VENTRIP2 = 0.75V
DEM
ASM
300
250
200
150
100
50
0
0.001
0.01
0.1
1
10
Load Current (A)
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RT8230A/B/C/D/E
Output Voltage vs. Load Current
Output Voltage vs. Load Current
3.36
5.05
VOUT2
VOUT1
5.04
DEM
Output Voltage (V)
Output Voltage (V)
DEM
3.35
5.03
5.02
5.01
ASM
5.00
4.99
4.98
4.97
3.34
3.33
ASM
3.32
VIN = 12V, RTON = 100kΩ, ENLDO = VIN,
VENTRIP1 = 5V, VENTRIP2 = 0.75V
VIN = 12V, RTON = 100kΩ, ENLDO = VIN,
VENTRIP1 = 0.75V, VENTRIP2 = 5V
4.96
4.95
0.001
0.01
0.1
1
3.31
0.001
10
0.01
0.1
Load Current (A)
1
10
Load Current (A)
LDO3 Output Voltage vs. Load Current
LDO5 Output Voltage vs. Load Current
3.343
5.05
5.04
3.332
Output Voltage (V)
Output Voltage (V)
5.03
5.02
5.01
5.00
4.99
4.98
4.97
3.321
3.310
3.299
3.288
4.96
VIN = 12V, ENLDO = VIN, VENTRIP1 = VENTRIP2 = 5V
VIN = 12V, ENLDO = VIN, VENTRIP1 = VENTRIP2 = 5V
3.277
4.95
0
10
20
30
40
50
60
70
80
90
0
100
10
20
Quiescent Current vs. Input Voltage
40
50
60
70
80
90
100
Standby Input Current vs. Input Voltage
60
ASM
1000
DEM
100
10
RTON = 100kΩ, ENLDO = VIN,
VENTRIP1 = VENTRIP2 = 0.75V, No Load
1
Standby Input Current (µA)1
10000
Quiescent Current (µA)
30
Load Current (mA)
Load Current (mA)
55
50
45
40
35
ENLDO = VIN, VENTRIP1 = VENTRIP2 = 5V,
No Load, Not Switching
30
5
7
9
11
13
15
17
19
21
23
Input Voltage (V)
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DS8230A/B/C/D/E-04 February 2014
25
5
7
9
11
13
15
17
19
21
23
25
Input Voltage (V)
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RT8230A/B/C/D/E
Shutdown Input Current vs. Input Voltage
Power On from ENLDO
Shutdown Input Current (µA)1
25
20
LDO5
(5V/Div)
15
LDO3
(2V/Div)
10
CP
(10V/Div)
5
ENLDO = GND,
VENTRIP1 = VENTRIP2 = 5V, No Load
ENLDO
(10V/Div)
VIN = 12V, RTON = 100kΩ, ENLDO = VIN,
VENTRIP1 = VENTRIP2 = 0.75V, No Load
0
5
7
9
11
13
15
17
19
21
23
25
Time (2ms/Div)
Input Voltage (V)
Power Off from ENM
Power On from ENM
VIN = 12V, VENM = 5V
VIN = 12V, VENM = 5V,
RTON = 100kΩ, ENLDO = VIN
VOUT1
(5V/Div)
VOUT1
(5V/Div)
VOUT2
(2V/Div)
VOUT2
(2V/Div)
PGOOD
(5V/Div)
PGOOD
(5V/Div)
ENM
(5V/Div)
RTON = 100kW, ENLDO = VIN,
VENTRIP1 = VENTRIP2 = 0.75V, No Load
ENM
(5V/Div)
Time (1ms/Div)
Time (10ms/Div)
Power On from ENTRIP1
Power Off from ENTRIP1
VOUT1
(5V/Div)
VOUT1
(5V/Div)
PGOOD
(5V/Div)
PGOOD
(5V/Div)
ENTRIP1
(5V/Div)
ENTRIP1
(5V/Div)
VIN = 12V, RTON = 100kΩ, ENLDO = VIN,
VENTRIP1 = VENTRIP2 = 0.75V, No Load
Time (1ms/Div)
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VENTRIP1 = VENTRIP2 = 0.75V, No Load
VIN = 12V, RTON = 100kΩ, ENLDO = VIN,
VENTRIP1 = VENTRIP2 = 0.75V, No Load
Time (20ms/Div)
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RT8230A/B/C/D/E
Power On from ENTRIP2
Power Off from ENTRIP2
VOUT2
(5V/Div)
VOUT2
(5V/Div)
PGOOD
(5V/Div)
PGOOD
(5V/Div)
ENTRIP2
(5V/Div)
ENTRIP2
(5V/Div)
VIN = 12V, RTON = 100kΩ, ENLDO = VIN,
VENTRIP1 = VENTRIP2 = 0.75V, No Load
VIN = 12V, RTON = 100kΩ, ENLDO = VIN,
VENTRIP1 = VENTRIP2 = 0.75V, No Load
Time (1ms/Div)
VOUT1 DEM-MODE Load Transient Response
Time (20ms/Div)
VOUT2 DEM-MODE Load Transient Response
VIN = 12V, RTON = 100kΩ
VIN = 12V, RTON = 100kΩ
VOUT1_AC
(100mV/Div)
VOUT2_AC
(100mV/Div)
UGATE1
(20V/Div)
UGATE1
(20V/Div)
IL1
(10A/Div)
IL2
(10A/Div)
ENLDO = VIN, IOUT1 = 1A to 6A
ENLDO = VIN, IOUT2 = 1A to 6A
Time (20μs/Div)
Time (20μs/Div)
OVP
UVP
VOUT1
(2V/Div)
VOUT1
(5V/Div)
PGOOD
(5V/Div)
PGOOD
(5V/Div)
VOUT2
(2V/Div)
UGATE1
(20V/Div)
LGATE1
(10V/Div)
VIN = 12V, RTON = 100kΩ, ENLDO = VIN, No Load
Time (10ms/Div)
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DS8230A/B/C/D/E-04 February 2014
VIN = 12V, RTON = 100kΩ, ENLDO = VIN
Time (100μs/Div)
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RT8230A/B/C/D/E
Application Information
The RT8230A/B/C/D/E is a dual-channel, low quiescent,
Mach Response TM DRVTM mode synchronous Buck
controller targeted for Ultrabook system power supply
solutions. Richtek's Mach Response TM technology
provides fast response to load steps. The topology solves
the poor load transient response timing problems of fixed
frequency current mode PWMs, and avoids the problems
caused by widely varying switching frequencies in CCR
(constant current ripple) constant on-time and constant
off-time PWM schemes. A special adaptive on-time control
trades off the performance and efficiency over wide input
voltage range. The RT8230A/B/C/D/E includes 5V (LDO5)
and 3.3V (LDO3) linear regulators. The LDO5 linear
regulator steps down the battery voltage to supply both
internal circuitry and gate drivers. The synchronous switch
gate drivers are directly powered by LDO5. When VOUT1
rises above 4.66V, an automatic circuit disconnects the
linear regulator and allows the device to be powered by
VOUT1 via the BYP1 pin.
PWM Operation
The Mach ResponseTM DRVTM mode controller relies on
the output filter capacitor's Effective Series Resistance
(ESR) to act as a current sense resistor, so that the output
ripple voltage provides the PWM ramp signal. Referring to
the RT8230A/B/C/D/E's Function Block Diagram, the
synchronous high-side MOSFET is turned on at the
beginning of each cycle. After the internal one-shot timer
expires, the MOSFET will be turned off. The pulse width
of this one-shot is determined by the converter's input
output voltages to keep the frequency fairly constant over
the entire input voltage range. Another one-shot sets a
minimum off-time (275ns typ.). The on-time one-shot will
be triggered if the error comparator is high, the low-side
switch current is below the current limit threshold, and
the minimum off-time one-shot has timed out.
PWM Frequency and On-time Control
on-time is inversely proportional to the input voltage as
measured by VIN and proportional to the output voltage.
The inductor ripple current operating point remains
relatively constant, resulting in easy design methodology
and predictable output voltage ripple. The frequency of 3V
output controller is set higher than the frequency of 5V
output controller. This is done to prevent audio frequency
“ beating” between the two sides, which switch
asynchronously for each side. The TON pin is connected
to GND through the external resistor RTON to set the
switching frequency.
The RT8230A/B/C/D/E adaptively changes the operation
frequency according to the input voltage. Higher input
voltage usually comes from an external adapter, so the
RT8230A/B/C/D/E operates with higher frequency to have
better performance. Lower input voltage usually comes
from a battery, so the RT8230A/B/C/D/E operates with
lower switching frequency for lower switching losses. For
a specific input voltage range, the switching cycle period
is given by :
For 5V VOUT,
Period (sec.) =
VIN (3.23 RTON + 3.4 104 )
10-11
1.36 VIN 5.16
For 3.3V VOUT,
Period (sec.) =
VIN (2.94 RTON + 3.4 104 )
1.36 VIN +1.46 10-5 RTON 5.3
10-11
where the VIN is in volt, RTON is in ohm.
The on-time guaranteed in the Electrical Characteristics
table is influenced by switching delays in the external
high-side power MOSFET.
Operation Mode Selection
The RT8230A/B/C/D/E supports two operation modes :
diode emulation mode and ultrasonic mode. The operation
mode can be set via the ENM pin for the RT8230A or the
SECFB pin for the RT8230B/C/D/E.
For each specific input voltage range, the Mach
ResponseTM control architecture runs with pseudo constant
frequency by feed forwarding the input and output voltage
into the on-time one-shot timer. The high-side switch
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is a registered trademark of Richtek Technology Corporation.
DS8230A/B/C/D/E-04 February 2014
RT8230A/B/C/D/E
Table 1. Operation Mode Setting
Part Number
RT8230A
RT8230B/E
RT8230C/D
Pin Name
ENM
SECFB
SECFB
Pin-13 Voltage Range
Mode State
4.5V to 5V
ASM
ASM
ASM
2.3V to 3.6V
DEM
DEM
DEM
1.2V to 1.8V
CH1 : ASM
CH2 : DEM
CH1 : ASM
CH2 : DEM
CH1 : DEM
CH2 : ASM
Below 0.8V
Shutdown
--
--
Diode Emulation Mode
In diode emulation mode, the RT8230A/B/C/D/E
automatically reduces switching frequency at light load
conditions to maintain high efficiency. This reduction of
frequency is achieved smoothly. As the output current
decreases from heavy load condition, the inductor current
is also reduced, and eventually comes to the point that
its current valley touches zero, which is the boundary
between continuous conduction and discontinuous
conduction modes. To emulate the behavior of diodes,
the low-side MOSFET allows only partial negative current
to flow when the inductor free wheeling current becomes
negative. As the load current is further decreased, it takes
longer and longer time to discharge the output capacitor
to the level that requires the next “ON” cycle. The ontime is kept the same as that in the heavy load condition.
In reverse, when the output current increases from light
load to heavy load, the switching frequency increases to
the preset value as the inductor current reaches the
continuous conduction. The transition load point to the
light load operation is shown in Figure 1. and can be
calculated as follows :
IL
Slope = (VIN - VOUT) / L
IPEAK
ILOAD = IPEAK / 2
0
tON
t
Figure 1. Boundary Condition of CCM/DEM
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DS8230A/B/C/D/E-04 February 2014
(VIN VOUT )
tON
2L
where tON is the on-time.
ILOAD(SKIP)
The switching waveforms may appear noisy and
asynchronous when light load causes diode emulation
operation. This is normal and results in high efficiency.
Trade offs in PFM noise vs. light load efficiency is made
by varying the inductor value. Generally, low inductor values
produce a broader efficiency vs. load curve, while higher
values result in higher full load efficiency (assuming that
the coil resistance remains fixed) and less output voltage
ripple. Penalties for using higher inductor values include
larger physical size and degraded load transient response
(especially at low input voltage levels).
In diode emulation mode, the FB voltage will rise to 2.015V
(typ.) naturally, because of the design circuit.
Ultrasonic Mode (ASM)
The RT8230A/B/C/D/E activates a unique type of diode
emulation mode with a minimum switching frequency of
25kHz, called ultrasonic mode. This mode eliminates
audio-frequency modulation that would otherwise be
present when a lightly loaded controller automatically
skips pulses. In ultrasonic mode, the low-side switch gate
driver signal is “OR”ed with an internal oscillator
(>25kHz). Once the internal oscillator is triggered, the
controller will turn on UGATE and give it shorter on-time.
When the on-time expired, LGATE turns on until the
inductor current goes to zero crossing threshold and keep
both high-side and low-side MOSFET off to wait for the
next trigger. Because shorter on-time causes a smaller
pulse of the inductor current, the controller can keep output
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RT8230A/B/C/D/E
voltage and switching frequency simultaneously. The ontime decreasing has a limitation and the output voltage
will be lifted up under the slight load condition. The
controller will turn on LGATE first to pull down the output
voltage. When the output voltage is pulled down to the
balance point of the output load current, the controller will
proceed the short on-time sequence as the above
description.
Linear Regulators (LDOx)
The RT8230A/B/C/D/E includes 5V (LDO5) and 3.3V
(LDO3) linear regulators. The regulators can supply up to
100mA for external loads. Bypass LDOx with a minimum
4.7μF ceramic capacitor. When VOUT1 is higher than the
switch over threshold (4.66V), an internal 1.5Ω P-MOSFET
switch connects BYP1 to the LDO5 pin while
simultaneously disconnects the internal linear regulator.
5μA (typ.) at room temperature. The current source has a
4700ppm/°C temperature slope to compensate the
temperature dependency of the RDS(ON). When the voltage
drop across the sense resistor or low-side MOSFET
equals 1/10 the voltage across the RILIM resistor, positive
current limit will be activated. The high-side MOSFET will
not be turned on until the voltage drop across the MOSFET
falls below 1/10 the voltage across the RILIM resistor.
Choose a current limit resistor according to the following
equation :
VLIMIT = (RLIMIT x 5μA) / 10 = ILIMIT x RDS(ON)
RLIMIT = (ILIMIT x RDS(ON)) x 10 / 5μA
Carefully observe the PC board layout guidelines to ensure
that noise and DC errors do not corrupt the current sense
signal at PHASEx and GND. Mount or place the IC close
to the low-side MOSFET.
Current Limit Setting (ENTRIPx)
Charge Pump (SECFB)
The RT8230A/B/C/D/E has cycle-by-cycle current limit
control. The current limit circuit employs a unique “valley”
current sensing algorithm. If the magnitude of the current
sense signal at PHASEx is above the current limit
threshold, the PWM is not allowed to initiate a new cycle
(Figure 2). The actual peak current is greater than the
current limit threshold by an amount equal to the inductor
ripple current. Therefore, the exact current limit
characteristic and maximum load capability are a function
of the sense resistance, inductor value, battery and output
voltage.
The external 14V charge pump is driven by LGATEx
(LGATE1 for RT8230B/E, LGATE2 for RT8230C/D). As
shown in Figure 3, when LGATEx is low, C1 will be charged
by VOUT1 through D1. C1 voltage is equal to VOUT1 minus
the diode drop. When LGATEx becomes high, C1 transfers
the charge to C2 through D2 and charges C2 voltage to
VLGATEX plus C1 voltage. As LGATEx transitions low on
the next cycle, C3 is charged to C2 voltage minus a diode
drop through D3. Finally, C3 charges C4 through D4 when
LGATEx switches high. Thus, the total charge pump
voltage, VCP, is :
IL
IPEAK
VCP = VOUT1 + 2 x VLGATEx − 4 x VD
ILOAD
where VLGATEx is the peak voltage of the LGATEx driver
which is equal to LDO5 and VD is the forward voltage
dropped across the Schottky diode.
ILIMIT
t
Figure 2. “Valley” Current Limit
The RT8230A/B/C/D/E uses the on resistance of the
synchronous rectifier as the current sense element and
supports temperature compensated MOSFET RDS(ON)
sensing. The RILIM resistor between the ENTRIPx pin and
GND sets the current limit threshold. The resistor RILIM is
connected to a current source from ENTRIPx which is
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20
The SECFB pin in the RT8230B/C/D/E is used to monitor
the charge pump via a resistive voltage divider to generate
approximately 14V DC voltage and the clock driver uses
VOUT1 as its power supply. In the Figure 3 when SECFB
drops below its feedback threshold, an ultrasonic pulse
will occur to refresh the charge pump driven by LGATEx.
If there is an overload on the charge pump in which SECFB
can not reach more than its feedback threshold, the
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DS8230A/B/C/D/E-04 February 2014
RT8230A/B/C/D/E
channel x controller will enter ultrasonic mode. Special
care should be taken to ensure that enough normal ripple
voltage is present on each cycle to prevent charge pump
shutdown.
SECFB
RCP2
LGATEx
C1
C3
RCP1
Charge Pump
VOUT1
D1
D2
D3
C2
D4
C4
Figure 3. Charge Pump Circuit Connected to SECFB
MOSFET Gate Driver (UGATEx, LGATEx)
The high-side driver is designed to drive high current, low
RDS(ON) N-MOSFET(s). When configured as a floating driver,
5V bias voltage is delivered from the LDO5 supply. The
average drive current is also calculated by the gate charge
at VGS = 5V times switching frequency. The instantaneous
drive current is supplied by the flying capacitor between
the BOOTx and PHASEx pins. A dead-time to prevent
shoot through is internally generated from high-side
MOSFET off to low-side MOSFET on and low-side
MOSFET off to high-side MOSFET on.
The low-side driver is designed to drive high current low
RDS(ON) N-MOSFET(s). The internal pull down transistor
that drives LGATEx low is robust, with a 1Ω typical onresistance. A 5V bias voltage is delivered from the LDO5
supply. The instantaneous drive current is supplied by an
input capacitor connected between LDO5 and GND.
Soft-Start
The RT8230A/B/C/D/E provides an internal soft-start
function to prevent large inrush current and output voltage
overshoot when the converter starts up. The soft-start (SS)
automatically begins once the chip is enabled. During softstart, it clamps the ramping of internal reference voltage
which is compared with FBx signal. The typical soft-start
duration is 0.8ms. A unique PWM duty limit control that
prevents output over-voltage during soft-start period is
designed specifically for FBx floating.
UVLO Protection
The RT8230A/B/C/D/E has LDO5 under-voltage lock out
protection (UVLO). When the LDO5 voltage is lower than
3.9V (typ.) and the LDO3 voltage is lower than 2.5V (typ.),
both switch power supplies are shut off. This is a nonlatch protection.
Power Good Output (PGOOD)
PGOOD is an open-drain output and requires a pull-up
resistor. PGOOD is actively held low in soft-start, standby,
and shutdown. It is released when both output voltages
are above 90% of the nominal regulation point for RT8230A.
For RT8230B/C/D/E, PGOOD is released when both output
voltages are above 92.5% of nominal regulation point, and
the SECFB threshold is also above 50% of nominal
regulation point. The PGOOD signal goes low if either
output turns off or is 15.5% below or 13% over its nominal
regulation point.
Output Over-Voltage Protection (OVP)
For high current applications, some combinations of high
and low-side MOSFETs may cause excessive gate drain
coupling, which leads to efficiency killing, EMI producing,
and shoot through currents. This is often remedied by
adding a resistor in series with BOOTx, which increases
the turn-on time of the high-side MOSFET without
degrading the turn-off time. See Figure 4.
VIN
UGATEx
BOOTx
RBOOT
The output voltage can be continuously monitored for overvoltage condition. If the output voltage exceeds 13% of
its set voltage threshold, the over-voltage protection is
triggered and the LGATEx low-side gate drivers are forced
high. This activates the low-side MOSFET switch, which
rapidly discharges the output capacitor and pulls the output
voltage downward. In addition, the BYP1 pin also has the
OVP function.
When detect BYP1 Voltage over 6V, RT8230A/B/C/D/E
will active OVP function immediately.
PHASEx
Figure 4. Increasing the UGATEx Rise Time
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RT8230A/B/C/D/E
The RT8230A/B/C/D/E is latched once OVP is triggered
and can only be released by either toggling ENLDO,
ENTRIPx or cycling VIN. There is a 1μs delay built into
the over-voltage protection circuit to prevent false transition.
Note that latching LGATEx high will cause the output
voltage to dip slightly negative due to previously stored
energy in the LC tank circuit. For loads that cannot tolerate
a negative voltage, place a power Schottky diode across
the output to act as a reverse polarity clamp.
If the over-voltage condition is caused by a shorted in
high-side switch, turning the low-side MOSFET on 100%
will create an electrical shorted circuit between the battery
and GND to blow the fuse and disconnecting the battery
from the output.
Output Under-Voltage Protection (UVP)
The output voltage can be continuously monitored for undervoltage condition. If the output is less than 52% (typ.) of
its set voltage threshold, the under-voltage protection will
be triggered and then both UGATEx and LGATEx gate
drivers will be forced low. The UVP is ignored for at least
3ms (typ.) after a start-up or a rising edge on ENTRIPx.
Toggle ENTRIPx or cycle VIN to reset the UVP fault latch
and restart the controller.
Thermal Protection
The RT8230A/B/C/D/E features thermal shutdown to
prevent damage from excessive heat dissipation. Thermal
shutdown occurs when the die temperature exceeds
150°C. All internal circuitries are turned off during thermal
shutdown. The RT8230A/B/C/D/E triggers thermal
shutdown if LDOx is not supplied from VOUTx, while input
voltage on VIN and drawing current from LDOx are too
high. Nevertheless, even if LDOx is supplied from VOUTx,
overloading LDOx can cause large power dissipation on
automatic switches, which may still result in thermal
shutdown.
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Discharge Mode (Soft Discharge)
When ENTRIPx is high and a transition to standby or
shutdown mode occurs, or the output under-voltage fault
latch is set, the output discharge mode will be triggered.
During discharge mode, an internal switch creates a path
for discharging the output capacitors' residual charge to
GND.
Shutdown Mode
SMPS1, SMPS2, LDO3 and LDO5 all have independent
enabling control. Drive ENLDO (RT8230A/B/D), ENC
(RT8230C/E), ENTRIP1 and ENTRIP2 below the precise
input falling edge trip level to place the device in its low
power shutdown state. The RT8230A/B/C/D/E consumes
only 10μA of input current while in shutdown. When
shutdown mode is activated, the reference turns off. The
0.4V falling edge threshold on ENLDO/ENC can be used
to detect a specific analog voltage level and to shutdown
the device. Once in shutdown, the 1V rising edge threshold
activates, providing sufficient hysteresis for most
applications.
Power-Up Sequencing and On/Off Controls
(ENTRIPx, ENM)
ENTRIP1 and ENTRIP2 control the power-up sequencing
of the two channels of the Buck converter. When the
RT8230A/B/C/D/E is applied in the single-channel mode,
ENTRIPx disables the respective output when ENTRIPx
voltage rises above 4.5V. Furthermore, when the RT8230A
is applied in the dual-channel mode, the outputs are
enabled when ENM connects to LDO3 for DEM operation.
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RT8230A/B/C/D/E
Table 2. Operation Mode Truth Table
Mode
LDO Over
Current Limit
Run
Over-Voltage
Protection
Condition
Comment
Transitions to discharge mode after VIN POR LDO5
and LDO3 remain active.
LDOx < UVLO threshold
ENLDO/ENC = high, VOUT1 or VOUT2 are
Normal Operation.
enabled
LGATEx is forced high. LDO3 and LDO5 are active.
Either output >113% of the nominal level. Exit by VIN POR or by toggling ENLDO/ENC,
ENTRIPx, and ENM.
Under-Voltage
Protection
Both UGATEx and LGATEx are forced low and enter
Either output < 52% of the nominal level
discharge mode. LDO3 and LDO5 are active. Exit by
after 3ms time-out expires and output is
VIN POR or by toggling ENLDO/ENC, ENTRIPx,
enabled
and ENM.
Discharge
During discharge mode, there is one path to
Either output is still high in standby mode
discharge the output capacitors’ residual charge to
or shutdown mode
GND via an internal switch.
Standby
ENTRIPx > startup threshold or ENM <
LDO3 and LDO5 are active.
startup threshold, ENLDO/ENC = high.
Shutdown
ENLDO/ENC = low
All circuitries are off. LDO3 and LDO5 are kept
active for RT8230C/E only.
Thermal
Shutdown
TJ > 150°C
All circuitries are off. Exit by VIN POR or by toggling
ENLDO/ENC, ENTRIPx, and ENM.
Table 3. Power-Up Sequencing (RT8230A)
ENLDO (V)
ENM (V)
ENTRIP1
(V)
ENTRIP2
(V)
LDO5
LDO3
SMPS1
SMPS2
Low
Low
X
X
Off
Off
Off
Off
“>1V”
=> High
Low
X
X
On
On
Off
Off
“>1V”
=> High
“>2.3V”
=> High
Off
Off
On
On
Off
Off
“>1V”
=> High
“>2.3V”
=> High
Off
On
On
On
Off
On
“>1V”
=> High
“>2.3V”
=> High
On
On
On
On
On
On
“>1V”
=> High
“>2.3V”
=> High
On
Off
On
On
On
Off
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RT8230A/B/C/D/E
Output Voltage Setting (FBx)
Output Capacitor Selection
Connect a resistive voltage divider at the FBx pin between
VOUTx and GND to adjust the output voltage from 2V to
5.5V for CH1 and 2V to 4V for CH2 as shown in
Figure 5. Choose R2 to be approximately 10kΩ, and solve
for R1 using the equation below :
The capacitor value and ESR determine the amount of
output voltage ripple and load transient response. Thus,
the capacitor value must be greater than the largest value
calculated from the equations below :
R1
VOUT VFBx 1 +
R2
where VFBx is 2V (typ.).
VSAG
2 COUT VIN tON VOUTx (tON + tOFF(MIN) )
VSOAR
VIN
UGATEx
VOUTx
PHASEx
LGATEx
(ILOAD )2 L (tON + tOFF(MIN) )
R1
PGND
FBx
R2
GND
(ILOAD )2 L
2 COUT VOUTx
1
VPP LIR ILOAD(MAX) ESR +
8
C
f
OUT
where VSAG and VSOAR are the allowable amount of
undershoot and overshoot voltage during load transient,
Vp-p is the output ripple voltage, and tOFF(MIN) is the
minimum off-time.
Thermal Considerations
Figure 5. Setting VOUTx with a resistive voltage divider
Output Inductor Selection
The switching frequency (on-time) and operating point
(% ripple or LIR) determine the inductor value as shown
below :
t (VIN VOUTx )
L ON
LIR ILOAD(MAX)
where LIR is the ratio of the peak-to-peak ripple current to
the average inductor current.
Find a low-loss inductor having the lowest possible DC
resistance that fits in the allotted dimensions. Ferrite cores
are often the best choice, although powdered iron is
inexpensive and can work well at 200kHz. The core must
be large enough not to saturate at the peak inductor
current, IPEAK :
IPEAK = ILOAD(MAX) + [ (LIR / 2) x ILOAD(MAX) ]
The calculation above shall serve as a general reference.
To further improve transient response, the output
inductance can be further reduced. Of course, besides
the inductor, the output capacitor should also be
considered when improving transient response.
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For continuous operation, do not exceed absolute
maximum junction temperature. The maximum power
dissipation depends on the thermal resistance of the IC
package, PCB layout, rate of surrounding airflow, and
difference between junction and ambient temperature. The
maximum power dissipation can be calculated by the
following formula :
PD(MAX) = (TJ(MAX) − TA) / θJA
where TJ(MAX) is the maximum junction temperature, TA is
the ambient temperature, and θJA is the junction to ambient
thermal resistance.
For recommended operating condition specifications, the
maximum junction temperature is 125°C. The junction to
ambient thermal resistance, θJA, is layout dependent. For
WQFN-20L 3x3 package, the thermal resistance, θJA, is
30°C/W on a standard JEDEC 51-7 four-layer thermal test
board. The maximum power dissipation at TA = 25°C can
be calculated by the following formula :
P D(MAX) = (125°C − 25°C) / (30°C/W) = 3.33W for
WQFN-20L 3x3 package
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RT8230A/B/C/D/E
Maximum Power Dissipation (W)1
The maximum power dissipation depends on the operating
ambient temperature for fixed T J(MAX) and thermal
resistance, θJA. The derating curve in Figure 6 allows the
designer to see the effect of rising ambient temperature
on the maximum power dissipation.
4.0
Layout Considerations
Layout is very important in high frequency switching
converter design. Improper PCB layout can radiate
excessive noise and contribute to the converter’s
instability. Certain points must be considered before
starting a layout with the RT8230A/B/C/D/E.
Four-Layer PCB
3.5
Place the filter capacitor close to the IC, within 12mm
(0.5 inch) if possible.
Keep current limit setting network as close as possible
to the IC. Routing of the network should avoid coupling
to high-voltage switching node.
Connections from the drivers to the respective gate of
the high-side or the low-side MOSFET should be as
short as possible to reduce stray inductance. Use
0.65mm (25 mils) or wider trace.
All sensitive analog traces and components such as
FBx, ENTRIPx, PGOOD, and TON should be placed
away from high voltage switching nodes such as
PHASEx, LGATEx, UGATEx, or BOOTx nodes to avoid
coupling. Use internal layer(s) as ground plane(s) and
shield the feedback trace from power traces and
components.
Place ground terminal of VIN capacitor(s), V OUTx
capacitor(s), and Source of low-side MOSFETs as close
to each other as possible. The PCB trace of PHASEx
node, which connects to Source of high-side MOSFET,
Drain of low-side MOSFET and high voltage side of the
inductor, should be as short and wide as possible.
3.0
2.5
2.0
1.5
1.0
0.5
0.0
0
25
50
75
100
125
Ambient Temperature (°C)
Figure 6. Derating Curve of Maximum Power Dissipation
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25
RT8230A/B/C/D/E
Outline Dimension
1
1
2
2
DETAIL A
Pin #1 ID and Tie Bar Mark Options
Note : The configuration of the Pin #1 identifier is optional,
but must be located within the zone indicated.
Dimensions In Millimeters
Dimensions In Inches
Symbol
Min
Max
Min
Max
A
0.700
0.800
0.028
0.031
A1
0.000
0.050
0.000
0.002
A3
0.175
0.250
0.007
0.010
b
0.150
0.250
0.006
0.010
D
2.900
3.100
0.114
0.122
D2
1.650
1.750
0.065
0.069
E
2.900
3.100
0.114
0.122
E2
1.650
1.750
0.065
0.069
e
L
0.400
0.350
0.016
0.450
0.014
0.018
W-Type 20L QFN 3x3 Package
Richtek Technology Corporation
14F, No. 8, Tai Yuen 1st Street, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: (8863)5526789
Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should
obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot
assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be
accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.
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DS8230A/B/C/D/E-04 February 2014
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