RT8800AGQV

RT8800A General Purpose 3-Phase PWM Controller for High-Density Power Supply General Description The RT8800A is a general-purposed multi-phase synchronous buck controller dedicating for high power density applications. The RT8800A operates with 2 or 3 synchronous buck switching stages in interleaved phase set automatically. The multiphase architecture provides high output current while maintaining low power dissipation on power devices and low stress on input and output capacitors. The output voltage is precisely regulated to the external reference voltage at PI pin. The RT8800A can provide Intel® VRD10.x or AMD® K8 compliant output voltage when companioned with DAC generator RT9401A/B. The RT8800A adopts innovative time-sharing DCR current sensing technique for channel current balance, droop tuning, and over current protection. Using one common GM amplifier for current sensing eliminates offset errors and linearity variation between GMs. As sub-milli-ohmgrade inductors are widely used in modern mother boards, slight mismatch of GM amplifiers offset and linearity results in considerable current shift between phases. The timesharing DCR current sensing technique is extremely important to guarantee phase current balance at mass production. Other features include overvoltage protection, undervoltage protection and internal softstart. The RT8800A comes to a VQFN-16L 3x3 package. Features 5V Power Supply Voltage 2/3-Phase Power Conversion with Automatic Phase Selection Output Voltage Controlled by External Reference Voltage Precise Core Voltage Regulation Power Stage Thermal Balance by DCR Current Sensing Extreme Low-Cost, Lossless Time Sharing Current Sensing Internal Soft-Start Hiccup Mode Over-Current Protection Over-Voltage Protection Adjustable Operating Frequency and Typical at 300kHz Per Phase Power Good Indication Small 16-Lead VQFN Package RoHS Compliant and 100% Lead (Pb)-Free Applications Desktop CPU Core Power L ow Output Voltage, High Power Density DC-DC Converters Voltage Regulator Modules Marking Information Ordering Information RT8800A Package Type QV : VQFN-16L 3x3 (V-Type) Operating Temperature Range P : Pb Free with Commercial Standard G : Green (Halogen Free with Commercial Standard) For marking information, contact our sales representative directly or through a Richtek distributor located in your area, otherwise visit our website for detail. Note : Richtek Pb-free and Green products are : RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020. Suitable for use in SnPb or Pb-free soldering processes. 100% matte tin (Sn) plating. All brand name or trademark belong to their owner respectively DS8800A-04 August 2007 www.richtek.com 1 RT8800A Pin Configurations (TOP VIEW) PWM3 PWM2 PWM1 12 ISP1 11 ISP2 10 ISP3 9 8 IMAX VID125 FB DVD 1 2 3 4 5 6 7 VDD 16 15 14 13 GND 17 PGOOD PI RT VQFN-16L 3x3 Functional Pin Description IMAX (Pin 1) Over current protection setting. VID125 (Pin 2) Connect a resistor from this pin to GND can raise VOUT. FB (Pin 3) The pin is defined as the inverting input of internal error amplifier. DVD (Pin 4) The pin is defined as a programmable power UVLO detection input. Trip threshold = 0.8V at VDVD rising. COMP (Pin 5) The pin is defined as the output of the error amplifier and the input of all PWM comparators. PI (Pin 6) The pin is defined as the positive input of the error amplifier. RT (Pin 7) Switching frequency setting. Connect this pin to GND with a resistor to set the frequency. VDD (Pin 16) Chip power supply. Connect this pin to a 5V supply. GND [Exposed Pad (17)] The exposed pad must be soldered to a large PCB and connected to GND for maximum power dissipation. PGOOD (Pin 9) Output power-good indication. The signal is implemented as an output signal with open-drain type. ISP1 , ISP2 , ISP3 (Pin 12, Pin 11, Pin 10) Current sense positive inputs for individual converter channel current sense. PWM1 , PWM2 , PWM3 (Pin 13, Pin 14, Pin 15) PWM outputs for each phase switching drive. ICOMMON (Pin 8) Common negative input of current sense amplifiers for all three channels. All brand name or trademark belong to their owner respectively www.richtek.com 2 DS8800A-04 August 2007 ICOMMON COMP PHASE2 L1 0.5uH 12V VIN Q3 Q1 Q2 C17 R13 0 12V 1uF R15 0 C25 to C36 1000uF x 12 D1 C11 to C14 1500uF x 4 C15 1uF 1uH C9 1000uF C10 1uF 5V C5 4.7uF R14 2.2 C16 3.3uF Typical Application Circuit PVCC2 UGATE2 PHASE2 LGATE2 R1 15k C2 10nF R3 3k TS PHASE1 PVCC1 LGATE1 ICOMMON 3.3V DVD 4 RT 7 12V R8 3k R12 PHASE1 D2 Q4 12V VIN R C8 1uF RCOMM Optional RCSN DSKY Optional 430 R9 16k C7 1uF R C18 1uF R16 0 R7 27k 12V Optional R11 PHASE2 1 UGATE1 24 22 23 C19 1uF 8 R19 10 R18 0 C20 1uF VDD DS8800A-04 August 2007 3-phase with RT9401A/B DAC generator C1 33pF Optional C3 R2 17 19 21 20 3 Q7 PHASE3 C24 3.3nF Q8 R22 2.2 R21 0 L2 0.5uH 16 5 16 BOOT2 RT9605 PVCC3 GND PHASE3 UGATE3 10 BOOT3 9 C23 1uF 12V 3 LGATE3 15 11 12V 14 C22 1uF R20 0 C37 to C40 10uF x 4 FB 7 15 5 PWM2 PWM1 BOOT1 4 R10 Optional PHASE3 R C6 1uF VDD 13 PWM1 COMP RADJ 6 RT8800A GND ISP3 2 ISP2 ISP1 11 10 PWM2 14 PWM3 PI PWM3 C4 10nF R4 10k 1 IMAX VCORE Q9 R5 16k 2 VID125 R6 10k 9 PGOOD VIN 12 8 5VSB PHASE1 L3 0.5uH Q5 R17 2.2 C21 3.3nF Q6 1 RT9401A/B VID2 VID3 8 All brand name or trademark belong to their owner respectively RCS VCORE 2 VID1 VID4 7 3 VDA GND 6 5V 4 VDD VID0 5 RT8800A www.richtek.com 3 Function Block Diagram Oscillator & Ramp Generator PWM Logic & Driver + + PWMCP INH PWM Logic & Driver + + + + + + EA + - FB PI 500mV OVP 0.8V VREF + Mux OCP Sample & Hold Sample & Hold Mux Sample & Hold MAJ SUM/N & OCP Detection - All brand name or trademark belong to their owner respectively INH Power On Reset Soft Start + + PWMCP INH PWM Logic & Driver + + VID125 DS8800A-04 August 2007 IMAX GND + GM - www.richtek.com 4 PGOOD VDD DVD RT PWM1 PWM2 PWM3 PWMCP ICOMMON ISP1 ISP2 ISP3 RT8800A COMP RT8800A Absolute Maximum Ratings (Note 1) Supply Voltage, VDD ------------------------------------------------------------------------------------------- 7V Input, Output or I/O Voltage ---------------------------------------------------------------------------------- GND − 0.3V to VDD + 0.3V Power Dissipation, PD @ TA = 25°C VQFN-16L 3x3 -------------------------------------------------------------------------------------------------Package Thermal Resistance (Note 4) VQFN-16L 3x3, θJA --------------------------------------------------------------------------------------------Junction Temperature -----------------------------------------------------------------------------------------Lead Temperature (Soldering, 10 sec.) -------------------------------------------------------------------Storage Temperature Range --------------------------------------------------------------------------------ESD Susceptibility (Note 2) HBM (Human Body Mode) ----------------------------------------------------------------------------------MM (Machine Mode) ------------------------------------------------------------------------------------------1.47W 68°C/W 150°C 260°C −65°C to 150°C 2kV 200V Recommended Operating Conditions (Note 3) Supply Voltage, VDD ------------------------------------------------------------------------------------------- 5V ± 10% Ambient Temperature Range --------------------------------------------------------------------------------- 0°C to 70°C Junction Temperature Range --------------------------------------------------------------------------------- 0°C to 125°C Electrical Characteristics (VDD = 5V, TA = 25°C, unless otherwise specified) Parameter VDD Supply Current Nominal Supply Current Power-On Reset VDD Threshold Rising Hysteresis Symbol Test Conditions Min Typ Max Units IDD PWM 1,2,3 Open -- 5 4.2 0.5 0.8 65 -4.5 -0.85 -- mA V V V mV 4.0 0.2 0.75 -RRT = 16kΩ RRT = 16kΩ DVD Rising Threshold DVD Hysteresis Oscillator Free Running Frequency Frequency Adjustable Range Ramp Amplitude Ramp Valley Maximum On-Time of Each Channel RT Pin Voltage Reference Voltage IMAX Reference Voltage VID125 Reference Voltage VIMAX VVID125 RIMAX = 16kΩ RVID125 = 16kΩ VRT RRT = 16kΩ fOSC fOSC_ADJ ΔVOSC VRV 170 50 --62 0.77 200 -1.7 1.0 66 0.82 230 400 --75 0.87 kHz kHz V V % V 0.75 0.75 0.8 0.8 0.85 0.85 V V To be continued All brand name or trademark belong to their owner respectively DS8800A-04 August 2007 www.richtek.com 5 RT8800A Parameter Error Amplifier DC Gain Gain-Bandwidth Product Slew Rate Current Sense GM Amplifier Recommended Full Scale Source Current Protection Over-Voltage Trip (VFB – VPI) Power Good PGOOD Output Low Voltage PGOOD Delay VPGOOD IPGOOD = 4mA -4 --0.2 8 V ms -500 -mV 100 --μA GBW SR CL = 10pF CL = 10pF ---65 10 8 ---dB MHz V/μs Symbol Test Conditions Min Typ Max Units TPGOOD_Delay 90% * VOUT to PGOOD_H Note 1. Stresses listed as the above "Absolute Maximum Ratings" may cause permanent damage to the device. These are for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. Note 2. Devices are ESD sensitive. Handling precaution recommended. Note 3. The device is not guaranteed to function outside its operating conditions. Note 4. θJA is measured in the natural convection at T A = 25 °C on a low effective thermal conductivity test board of JEDEC 51-3 thermal measurement standard. All brand name or trademark belong to their owner respectively www.richtek.com 6 DS8800A-04 August 2007 RT8800A Typical Operating Characteristics Load Line 1.4 1.38 Efficiency vs. Output Current 100 90 80 RLL = 1.5mΩ, RCSN = 10kΩ, RADJ = 100Ω VIN = 12V VIN = 12V, VOUT = 1.4V Output Voltage (V) 1.36 1.34 1.32 1.3 1.28 1.26 1.24 0 10 20 30 40 50 60 70 80 90 100 Efficiency (%) 70 60 50 40 30 20 10 0 0 10 20 30 40 50 60 Driver RT9605 70 80 90 100 Output Current (A) Output Current (A) Frequency vs. RRT 1000 900 800 90 80 70 60 GM RCOMM = 430Ω Frequency (kHz) 700 I ADJ (uA) 600 500 400 300 200 100 0 0 5 10 15 20 25 30 35 40 45 50 55 60 50 40 30 20 10 0 0 10 20 30 40 50 60 70 80 GM3 GM2 GM1 90 100 110 RRT (k Ω) (k ) VC (mV) VVID125 v s. Temperature 0.815 0.81 350 300 Frequency vs. Temperature Frequency (kHz) 0.805 250 200 150 100 50 V VID125 (V) 0.8 0.795 0.79 0.785 0.78 -25 -10 5 20 35 50 65 80 95 110 125 RRT = 16kΩ 0 -25 -10 5 20 35 50 65 80 95 110 125 Temperature (°C) Temperature (°C) All brand name or trademark belong to their owner respectively DS8800A-04 August 2007 www.richtek.com 7 RT8800A Load Transient Response V CORE (200mV/Div) V CORE (200mV/Div) Load Transient Response UGATE1 (20V/Div) UGATE2 (20V/Div) UGATE3 (20V/Div) UGATE1 (20V/Div) UGATE2 (20V/Div) UGATE3 (20V/Div) phase 1, IOUT = 5A to 85A @SR = 93A/us) phase2, IOUT = 5A to 85A @SR = 93A/us) Time (2.5μs/Div) Time (2.5μs/Div) Load Transient Response V CORE (200mV/Div) Over Current Protection Short While Turn_On UGATE1 (20V/Div) UGATE2 (20V/Div) UGATE3 (20V/Div) phase 3, IOUT = 5A to 85A @SR = 93A/us) IL1+IL2 (50A/Div) V CORE (1V/Div) PWM1 (10V/Div) VCOMP (2V/Div) Time (10ms/Div) Time (2.5μs/Div) Over Current Protection Short After Turn_On VID On the Fly Falling IOUT = 5A IL1+IL2 (50A/Div) V CORE (1V/Div) PWM1 (10V/Div) VCOMP (2V/Div) Time (10ms/Div) PWM (5V/Div) V CORE (100mV/Div) VFB (200mV/Div) VID0 (2V/Div) Time (25μs/Div) All brand name or trademark belong to their owner respectively www.richtek.com 8 DS8800A-04 August 2007 RT8800A VID On the Fly Falling V CORE (50mV/Div) PWM (5V/Div) VFB (200mV/Div) IOUT = 90A VID On the Fly Rising IOUT = 5A PWM (5V/Div) V CORE (200mV/Div) VFB (200mV/Div) VID0 (2V/Div) Time (25μs/Div) VID0 (2V/Div) Time (10μs/Div) VID On the Fly Rising IOUT = 90A PWM (5V/Div) V CORE (200mV/Div) VFB (200mV/Div) VID0 (2V/Div) Time (10μs/Div) All brand name or trademark belong to their owner respectively DS8800A-04 August 2007 www.richtek.com 9 RT8800A Applications Information The RT8800A is a general-purposed multi-phase synchronous buck controller dedicating for high power density applications. The RT8800A operates with 2 or 3 synchronous buck switching stages in interleaved phase set automatically. The multiphase architecture provides high output current while maintaining low power dissipation on power devices and low stress on input and output capacitors. Initialization The RT8800A initiates after 2 pins are ready : VDD pin power on reset (POR) and DVD pin is higher than 1V. VDD POR is to make sure RT8800A is powered by a voltage high enough for normal work. The rising threshold voltage of VDD POR is 4.2V typically. At VDD POR, RT8800A checks PWM3 status to determine phase number of operation. Pull high PWM3 for two-phase operation. The unused current sense pins should be connected to GND or left floating. DVD is to make sure that ATX12V is ready for the companion MOSFET drivers to work normally. Connect a voltage divider from ATX12V to DVD pin as shown in the Typical Application Circuit. Make sure that DVD pin voltage is below its threshold voltage before drivers are ready and above its threshold voltage for minimum ATX12V during normal operation. If one of VDD and DVD is not ready, RT8800A keeps its PWM outputs high impedance and the companion drivers turn off both upper and lower MOSFETs. Soft-Start After VDD and DVD are ready, RT8800A initiates its soft start cycle as shown in Figure 1. The error amplifier and PWM comparator are triple-input devices. The non-inverting input whichever is smaller dominates the behavior of the device. The soft start function generates SS and SSE for the non-inverting input of PWM comparator and error amplifier respectively where SSE = SS - VGS. VGS is threshold voltage of internal MOSFET. The typical softstart duration is 3ms. The soft start can be sliced to several time frames with specific operation respectively. 1) Mode 1 (SS < VRAMP_Valley) Initially the COMP stays in the positive saturation due to offset of the error amplifier. Since SS < VRAMP_Valley, the PWM comparator keeps its output low and VOUT is zero. 2) Mode 2 (VRAMP_Valley < SS < Cross-over) Since VRAMP_Valley < SS < Cross-over, SS dominates the non-inverting inputs of the PWM comparators. The PWM duty cycles increase according to the ramping up SS signal. The output voltage ramps up accordingly. However as VOUT increases, the difference between VOUT and SSE (SS - VGS) is reduced and COMP leaves the saturation and declines. The takeover of SS lasts until it meets the COMP. During this interval, since the feedback path is broken, the converter is operated in the open loop. 3) Mode3 (Cross-over < SS < VGS + VPI) When the VCOMP takes over the non-inverting input for PWM Amplifier and when SSE (SS - VGS) < VPI, the output of the converter follows the ramp input, SSE (SS - VGS). Before the crossover, the output follows SS signal. And when VCOMP takes over SS, the output is expected to follow SSE (SS - VGS). Therefore the deviation of VGS is represented as the falling of VOUT for a short while. The COMP is observed to keep its decline when it passes the cross-over, which shortens the duty width and hence the falling of VOUT happens. Since there is a feedback loop for the error amplifier, the output's response to the ramp input, SSE (SS - VGS) is lower than that in Mode 2. 4) Mode 4 (SS > VGS + VPI) When SS > VGS + VPI, the output of the converter follows the desired VPI signal and the soft start completes. However, the SS keeps ramping up to 3.3V and stays there. The PGOOD pin trips to high impedance as SS reaches 3.3V. Soft Start SSE FB PI + -EA + SS + + - PWM Figure 1. Soft Start Block Diagram. All brand name or trademark belong to their owner respectively www.richtek.com 10 DS8800A-04 August 2007 RT8800A LX RLX ILX RX COMP CX + VX VOUT VRAMP_Valley Cross-over S/H CKT + - T1 SS_Internal V CORE SSE_Internal IX + T3 Figure 2 T2 Time-Sharing DCR Current Sensing RT8800A adopts an innovative time-sharing DCR current sensing technique to sense the phase currents for phase current balance (phase thermal balance), over current protection and load line regulation as shown in Figure 3. The current sensing amplifier GM samples and holds voltages VX across the current sensing capacitor CX by turns in a switching cycle. According to the Basic Circuit Theory, if LX = R X × C X then VX = ILX × RLX RLX RCOMM Figure 3 Figure 4 and 5 show the linearity of GM amplifier and its test circuit respectively. A voltage source is applied to ISPx while other ISPx pins are short to VOUT. The voltage VADJ across resistor RADJ is measured. It is observed from Figu re 5 shows that a ll ISPx share the same transconductance linearity and voltage offset. 70 60 50 GM GM3 Consequently, the sensing current IX is proportional to inductor current ILX and is expressed as I ADJ (uA) ILX × RLX IX = R COMM GM2 40 30 20 10 0 0 20 40 60 80 100 The sensed current IX is used for current balance, over current protection, and droop tuning as described as followed. Since all phases share one common GM, GM offset and linearity variation effect are eliminated in practical applications. As sub-milli-ohmgrade inductors are widely used in modern motherboards, slight mismatch of GM amplifiers offset and linearity results in considerable current shift between phases. The time sharing DCR current sensing technical is extremely important to guarantee phase current balance at mass production. GM1 VX (mV) C Figure 4. The Linearity of GMx All brand name or trademark belong to their owner respectively DS8800A-04 August 2007 www.richtek.com 11 RT8800A IADJ RADJ + VADJ DAC_OUT RT9401 S/H MUX + GM IX PI EA + Over Current Protection ISP1 MUX ISP2 ISP3 VX SUM/N + - PWM (5V/Div) ICOMMON VCORE Figure 5. Test Circuit of GM. Phase Current Balance The sampled and held phase current IX are injected to the corresponding saw tooth waveforms of PWM comparators. If phase current IX is larger than other phase currents, its saw tooth waveform will be lift higher than the others. The RT8800A reduces the duty cycle of corresponding phase to decrease the phase current accordingly, vice versa. Over Current Protection RT8800A uses an external resistor RIMAX connected to IMAX pin to generate a reference current IIMAX for over current protection: IIMAX = VIMAX RIMAX IL (5V/Div) Time (25ms/Div) Figure 7. The Over Current Protection in the interval Over Current Protection PWM (5V/Div) where VIMAX is 0.8V typical. OCP comparator compares each sensed phase current IX with this reference current as shown in Figure 6. Equivalently, the maximum phase current is calculated as : ILX(MAX) 3 VIMAX R COMM = 2 RIMAX RLX OCP Comparator + 1/3 IX 1/2 IIMAX VSS (5V/Div) Time (25ms/Div) Figure 8. Over Current Protection at steady state Voltage Reference for Converter Output & Load Droop The output voltage is sensed at FB pin. The RT8800A receives an external reference voltage at PI pin as the non-inverting of the error amplifier and precisely regulates the FB voltage to this reference voltage. The RT8800A can provide Intel® VRD10.x or AMD® K8 compliant output voltage when companioned with DAC generator RT9401A/B as shown in Figure 9. The RT9401A/B receives VID[0:4] and produces DAC_OUT that complies with VRD10.x or K8 VID table. The DAC_OUT is fed to PI pin through a resistor RADJ as the reference voltage of the error amplifiers. The VID125 provides a 12.5mV offset for full compliance of VRD10.x table. DS8800A-04 August 2007 Figure 6. Over Current Comparator. The RT8800A uses hiccup mode to eliminate nuisance detection of OCP or reduce output current when output is shorted to ground as shown in Figure 7 and 8. The RT8800A shuts down and latches off after 3 time OCP hiccups. It can only restart by resetting one of VDD or DVD pin. www.richtek.com 12 All brand name or trademark belong to their owner respectively RT8800A COMP VCORE VCORE Load Line DAC_OUT FB PI RADJ DAC_OUT 500mV OVP 0.8V VREF + + VOFFSET 1 sum(I X ) 3 SUM/N IX VID [0 : 4] RT9401 VID125 - Spec_High RCSN > RCSN = RCSN < Spec_Low VID125 ICORE Figure 9 Droop and Load Lind Setting The sampled and held phase current IX are summed to get sum(IX). RT8800A then sinks a current that is 1/3 sum(IX) and produces a droop voltage that is proportional to the average phase voltage. VADJ = 1/3 sum(IX) x RADJ VADJ is then subtracted form DAC generator output as the real reference voltage at non-inverting input of the error amplifier. Consequently, load line slope is calculated as: Load Line = ΔVCORE R x RLX = − ADJ ΔICORE 3 x R COMM IX Figure 10 IL RX + VX CX LX RL_X VCORE DSKY VCORE - VF RCS + RCOMM RCSN Figure 11 Referring to Figure 11, the Schottky diode provides a constant voltage drop VF with enough bias current. IX is expressed as: IX = VF + ILX_Valley × RLX ILX_Valley × RLX + R CSN R COMM Dead Zone Elimination and Output Voltage Offset Function RT8800A samples and holds inductor valley current by time-sharing sourcing a current IX to RCOMM. At light load condition the inductor valley current and consequently the voltage VX across the sensing capacitor may be negative. A negative IX is required to correctly sense the negative voltage. However, the RT8800A CANNOT provide a negative IX and consequently cannot sense negative inductor current. This results in dead zone of load line performance as shown in Figure 10. Therefore a technique as shown in Figure 11 is required to eliminate the dead zone of load line at light load condition. (1) To make sure RT8800A could sense the inductor current, right hand side of Equation (1) should always be positive: VF + ILX_Valley × RLX ILX_Valley × RLX + ≥0 R CSN R COMM (2) Since VF >> (ILX_Valley x RLX) in practical application, Equation (2) could be simplified as: ILX_Valley × RLX VF ≥ R CSN R COMM (3) All brand name or trademark belong to their owner respectively DS8800A-04 August 2007 www.richtek.com 13 RT8800A Rewriting Equation (3), we get VF × R COMM ≥ R CSN ILX_Valley × RLX (4) Over Voltage Protection (OVP) The RT8800A continuously monitors voltage at FB pin. OVP is triggered if FB voltage is 500mV higher than the voltage at PI pin. RT8800A latches off and turns on lower MOSFET to protect the load from damage upon on OVP trip. It can only be reset by DVD and VDD pins. Current Ratio Setting Current ratio adjustment is possible as described below. It is important for achieving thermal balance in practical application where thermal conditions between phases are not identical. Figure 13 shows the application circuit of GM for current ratio requirement. According to Basic Circuit Theory, if The technique mentioned above also provides output voltage offset function specified by Intel ® VRD10.x. The offset voltage level is calculated as: R ADJ VOFFSET = VF R CSN Enough bias current is required for a Schottky to act like a voltage source. Users should choose the appropriate R CS b ased on the IV characteristic of the diode (Figure 12) I IV Characteristic LX = (R SX //RPX ) × C X then RLX VX = RPX × ILX × RLX R SX + RPX Zone 1 Zone 2 V Figure 12 According to Figure 12, the forward voltage of diode will be different results from the different conduction current. So when the characteristic of diode in the circuit you design is in zone 1, this will result in Spec. mis-met. It is because when the VCORE is changed during DVID, the node VCORE - VF is also changed to produce the differential conduction current of diode ΔI and the ΔI will result in producing the differential forward voltage of diode ΔVF Referring to Equation (1). The ΔVF would get ΔIX. Then the VCORE must be subtracted the extra voltage V(EXT)(ΔIX x RADJ ) during DVID. So you will get the ΔVCORE = V(MAX) - V(MIN) - V(EXT) during DVID tests. In order to reduce the effect results from diode. The better choice is to decrease the Rcs to increase the conduction current of diode I to get better V characteristic of diode in Zone 2. With other phase kept unchanged, this phase would share (RPX+RSX)/RPX times current than other phases. Figure 14 and 15 show different current ratio setting for the power stage when Phase 3 is programmed 2 times current than other phases. Figure 16 and 17 compare the above current ratio setting results. LX RSX T RLX CX + VX RPX ILX VOUT + T Figure 13 All brand name or trademark belong to their owner respectively www.richtek.com 14 DS8800A-04 August 2007 RT8800A Current Ratio Function IL3 1.5uH 1m 45 40 35 30 IL3 I LX (A) 3k 1uF 3k 25 20 15 10 5 IL2 IL1 Figure 13. GM4 Setting for current ratio function. IL1 to L2 1.5uH 1m 0 0 15 30 45 60 75 90 I CORE (A) Figure 16 1.5k 1uF Figure 14. GM1 to GM3 Setting for current ratio function. 40 35 30 25 Current Balance Function IL3 IL2 IL1 I LX (A) 20 15 10 5 0 0 20 40 60 80 100 I CORE (A) Figure 15 All brand name or trademark belong to their owner respectively DS8800A-04 August 2007 www.richtek.com 15 RT8800A Design Procedure Suggestion a.Output filter pole and zero (Inductor, output capacitor value & ESR). b.Error amplifier compensation & sawtooth wave amplitude (compensation network). Current Loop Setting a.GM amplifier S/H current (current sense component DCR, ICOMMON pin external resistor value). b.Over-current protection trip point (RICOMMON1 resistor). VRM Load Line Setting a.Droop amplitude (PI pin resistor). b.No load offset (RICOMMON2) Power Sequence & SS DVD pin external resistor and SS pin capacitor. 2. Over-Current Protection Setting PCB Layout a.Sense for current sense GM amplifier input. b.Refer to layout guide for other items. Voltage Loop Setting Design Example Given: Apply for four phase converter VIN = 12V VCORE = 1.5V ILOAD(MAX) = 100A VDROOP = 100mV at full load (1mΩ Load Line) OCP trip point set at 35A for each channel (S/H) DCR = 1mΩ of inductor at 25°C L = 1.5μH COUT = 8000μF with 5mΩ equivalent ESR. 1. Compensation Setting a. Modulator Gain, Pole and Zero: From the following formula: Modulator Gain =VIN/VRAMP =12/2.4=5 (i.e 14dB) where VRAMP : ramp amplitude of saw-tooth wave All brand name or trademark belong to their owner respectively www.richtek.com 16 DS8800A-04 August 2007 RB1 4.7k LC Filter Pole = 1.45kHz and ESR Zero =3.98kHz b. EA Compensation Network: Select R1 = 4.7k, R2 = 15k, C1 = 12nF, C2 = 68pF and use the Type 2 compensation scheme shown in Figure 21. By calculation, the F Z = 0 .88kHz, FP = 322kHz and Middle Band Gain is 3.19 (i.e 10.07dB). C2 68pF RB2 C1 15k 12nF EA + Figure 17. Type 2 compensation network of EA Consider the temperature coefficient of copper 3900ppm/°C, IL × DCR = 150 μA RICOMMON1 IL × 1.39m Ω = 150 μA 330Ω IL = 35.6A RT8800A Layout Guide Place the high-power switching components first, and separate them from sensitive nodes. 1. Most critical path: The current sense circuit is the most sensitive part of the converter. The current sense resistors tied to ISP1,2,3 and ICOMMON should be located not more than 0.5 inch from the IC and away from the noise switching nodes. The PCB trace of sense nodes should be parallel and as short as possible. R&C filter of choke should place close to PWM and the R & C connect directly to the pin of each output choke, use 10 mil differencial pair, and 20 mil gap to other phase pair. Less via as possible. 2. Switching ripple current path: a. Input capacitor to high side MOSFET. b. Low side MOSFET to output capacitor. c. The return path of input and output capacitor. d. Separate the power and signal GND. e. The switching nodes (the connection node of high/low side MOSFET and inductor) is the most noisy points.Keep them away from sensitive small-signal node. f . Reduce parasitic R, L by minimum length, enough copper thickness and avoiding of via. 3. MOSFET driver should be closed to MOSFET. SW1 L1 VIN RIN CIN VOUT COUT RL V SW2 L2 Figure 18. Power Stage Ripple Current Path All brand name or trademark belong to their owner respectively DS8800A-04 August 2007 www.richtek.com 17 RT8800A Next to IC +12V 0.1uF VCC BST DRVH VIN SW CBOOT LO1 CIN +12V or +5V PWM RT GND VCC CBP +5VIN Next to IC VCORE COUT RICOM COMP CC RC FB RFB Locate next to FB Pin RT8800A ICOMMON RT9603 DRVL GND Locate near MOSFETs CSPx GND PI RDRD Figure 19. Layout Consideration Figure 20 All brand name or trademark belong to their owner respectively www.richtek.com 18 DS8800A-04 August 2007 RT8800A Figure 21 Figure 22 All brand name or trademark belong to their owner respectively DS8800A-04 August 2007 www.richtek.com 19 RT8800A Figure 23 All brand name or trademark belong to their owner respectively www.richtek.com 20 DS8800A-04 August 2007 RT8800A Outline Dimension SEE DETAIL A L 1 D D2 E E2 1 1 2 e A A1 A3 b 2 DETAIL A Pin #1 ID and Tie Bar Mark Options Note : The configuration of the Pin #1 identifier is optional, but must be located within the zone indicated. Symbol A A1 A3 b D D2 E E2 e L Dimensions In Millimeters Min 0.800 0.000 0.175 0.180 2.950 1.300 2.950 1.300 0.500 0.350 0.450 Max 1.000 0.050 0.250 0.300 3.050 1.750 3.050 1.750 Dimensions In Inches Min 0.031 0.000 0.007 0.007 0.116 0.051 0.116 0.051 0.020 0.014 0.018 Max 0.039 0.002 0.010 0.012 0.120 0.069 0.120 0.069 V-Type 16L QFN 3x3 Package Richtek Technology Corporation Headquarter 5F, No. 20, Taiyuen Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)5526789 Fax: (8863)5526611 Richtek Technology Corporation Taipei Office (Marketing) 8F, No. 137, Lane 235, Paochiao Road, Hsintien City Taipei County, Taiwan, R.O.C. Tel: (8862)89191466 Fax: (8862)89191465 Email: marketing@richtek.com All brand name or trademark belong to their owner respectively DS8800A-04 August 2007 www.richtek.com 21