RT8805CPQV

Preliminary RT8805C Two Phase General Purpose PWM Controller General Description The RT8805C is the most compact dual-phase synchronous buck controller in the industry specifically designed for high power density applications. This part is capable of delivering up to 60A output current due to its embedded bootstrapped drivers that support 12V + 12V driving capability. The phase currents are sensed by innovative time sharing RDS(ON) current sensing technique for current balance and over current balance. Using one common GM amplifier to sense two phase currents eliminates offset and nonlinearity of the GM amplifier and yields good current balance. Other features include adjustable operation frequency from 50kHz to 1MHz, adjustable soft-start, PGOOD, external compensation, enable/shutdown for various application and performance consideration. The RT8805C comes to a tiny footprint package of VQFN-16L 3x3 and VQFN-24L 4x4 packages. Features 12V Power Supply Voltage 2 Phase Power Conversion Embedded 12V Boot Strapped Driver Precise Core Voltage Regulation Low Side MOSFET RDS(ON) Current Sensing for Power Stage Current Balance External Compensation Adjustable Soft-Start Adjustable Frequency and Typical at 300kHz Per Phase Power Good Indication Adjustable Over Current Protection External Reference Voltage Tracking (RT8805CxQVA) Small 16-Lead and 24-Lead VQFN Packages RoHS Compliant and 100% Lead (Pb)-Free Applications Middle-High End GPU Core Power High End Desktop PC Memory Core Power Low Output Voltage, High Power Density DC-DC Converters Voltage Regulator Modules Ordering Information RT8805C Package Type QV : VQFN-16L 3x3 (V-Type) QVA : VQFN-24L 4x4 (V-Type) Operating Temperature Range P : Pb Free with Commercial Standard G : Green (Halogen Free with Commercial Standard) Marking Information For marking information, contact our sales representative directly or through a Richtek distributor located in your area, otherwise visit our website for detail. Note : Richtek Pb-free and Green products are : RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020. Suitable for use in SnPb or Pb-free soldering processes. 100% matte tin (Sn) plating. DS8805C-03 August 2007 www.richtek.com 1 RT8805C Pin Configurations Preliminary (TOP VIEW) PHASE2 19 18 17 16 LGATE1 PHASE1 LGATE1 VCC LGATE2 24 23 22 VCC 21 16 15 14 13 12 PHASE1 PHASE2 UGATE2 BOOT2 PGOOD LGATE2 20 VCC NC 1 2 3 4 5 6 7 8 9 10 11 25 12 UGATE2 BOOT2 PGOOD PI FB COMP UGATE1 BOOT1 AGND IMAX 1 2 3 4 5 6 UGATE1 BOOT1 AGND IMAX NC GND 17 7 8 11 10 9 GND 15 14 13 COMP SS RT FB GND NC NC VQFN-16L 3x3 VQFN-24L 4x4 Typical Application Circuit V IN 3.3V CC 12V CC R8 R9 9 14 C9 RT8805CxQV 2 PGOOD BOOT1 VCC UGATE1 1 PHASE1 16 LGATE1 15 10 11 R BOOT1 C4 R UGATE1 C5 Q1 L1 R PHASE1 Q2 C PHASE1 C8 V OUT R1 R2 5 4 3 8 RT IMAX AGND FB COMP C1 C2 R3 7 BOOT2 UGATE2 R BOOT2 C6 R UGATE2 C7 L2 R PHASE2 C PHASE2 Q3 6 EN Q5 C3 SS GND PHASE2 LGATE2 12 13 Q4 NC SS RT R4 R C R5 Figure A. Application Circuit for RT8805CxQV (VQFN-16L 3x3) www.richtek.com 2 DS8805C-03 August 2007 Preliminary V IN RT8805C C5 C4 3.3V CC 12V CC R8 R9 C9 R1 R2 16 21 VCC 22 15 7 5 4 14 PI RT RT8805CxQVA 3 PGOOD BOOT1 UGATE1 2 PHASE1 1 LGATE1 23 17 R BOOT1 R UGATE1 Q1 L1 R PHASE1 Q2 C PHASE1 C8 V OUT IMAX AGND FB COMP SS BOOT2 UGATE2 PHASE2 LGATE2 R BOOT2 C6 C7 L2 R PHASE2 C PHASE2 C1 C2 R3 13 12 18 R UGATE2 19 20 Q3 EN Q5 C3 11 GND Q4 R4 R C R5 Figure B. Application Circuit for RT8805CxQVA (VQFN-24L 4x4)-Standalone Mode (PI Disabled) V IN 3.3V CC 12V CC R8 R9 C9 R1 R2 16 21 VCC 22 15 PI 7 RT 5 4 14 RT8805CxQVA 3 PGOOD BOOT1 UGATE1 2 PHASE1 1 LGATE1 23 17 R BOOT1 C4 R UGATE1 C5 Q1 L1 R PHASE1 Q2 C PHASE1 C8 V OUT R10 IMAX AGND FB COMP SS BOOT2 UGATE2 PHASE2 LGATE2 R BOOT2 C6 C7 L2 R PHASE2 C PHASE2 C1 C2 R3 13 12 18 R UGATE2 19 20 Q3 EN Q5 C3 11 GND Q4 R4 R C R5 Figure C. Application Circuit for RT8805CxQVA (VQFN-24L 4x4)-Tracking Mode (PI Enabled) DS8805C-03 August 2007 www.richtek.com 3 RT8805C Function Block Diagram RT8805CxQV (VQFN-16L 3x3) Preliminary VCC PGOOD 0.8V FB COMP External Soft Start SS CLK1 AGND RAMP1 RAMP2 CLK2 + PWMCP PWM2 Logic + EA VCC + PWMCP PWM1 Logic VCC BOOT1 UGATE1 PHASE1 LGATE1 BOOT2 UGATE2 VCC PHASE2 LGATE2 Current Balance S/H OCP Reg VDD CLK1 CLK2 OC GM + MUX PHASE2 PHASE1 IMAX VCC To PWM Logic Central Logic OC GND PGOOD RT Clock RT8805CxQVA (VQFN-24L 4x4) VCC PGOOD 0.8V PI FB COMP External Soft Start SS CLK1 AGND RAMP1 RAMP2 CLK2 + PWMCP PWM2 Logic VREF_SEL + EA VCC + PWMCP PWM1 Logic VCC BOOT1 UGATE1 PHASE1 LGATE1 BOOT2 UGATE2 VCC PHASE2 LGATE2 Current Balance S/H OCP Reg VDD CLK1 CLK2 OC GM + MUX PHASE2 PHASE1 IMAX VCC To PWM Logic Central Logic OC GND PGOOD RT Clock www.richtek.com 4 DS8805C-03 August 2007 Preliminary Functional Pin Description Pin No. VQFN-16L 3x3 16 12 1 11 2 10 3 4 -5 Exposed Pad (17) 6 7 8 VQFN-24L 4x4 1 19 2 18 3 17 4 5 6, 8, 9, 10, 24 7 Pin Name PHASE1 PHASE2 UGATE1 UGATE2 BOOT1 BOOT2 AGND IMAX NC RT Pin Function RT8805C These pins are return nodes of the high-side driver. Connect These pins to high-side MOSFET sources together with the low-side MOSFET drains and the inductors. Upper Gate Drive. These pins drive the gates of the high side MOSFETs. Bootstrap Power Pin. These pins power the high-side MOSFET drivers. Connect These pins to the junctions of the bootstrap capacitors. Chip Analog Ground. Maximum Current Setting. This pin sets the current limiting level. Connect this pin with resistor to ground to set the current limit. No Internal Connection. Timing Resistor. Connect a resistor from RT to AGND to set the clock frequency. The exposed pad must be soldered to a large PCB and connected to GND for maximum power dissipation. Soft-Start Pin. This pin provides soft-start function for controller. The COMP voltage of the converter follows the ramping voltage on the SS pin. Compensation Pin. This pin is output node of the error amplifier. Feedback Pin. This pin is negative input pin of the error amplifier. Power Good. PGOOD is an open drain output used to indicate the status of the voltages on SS pin and FB pin. PGOOD will go high impedance when SS > 3.7V and FB > 0.6V. Lower Gate Drive. These pins drive the gate of the lowside MOSFETs. The VCC pin is the external 12V power. Internal 5V power (VDD) is regulated from this pin. This pin also powers the low side MOSFET drivers. External reference voltage pin. This pin sets the voltage of FB pin when close loop. 11, GND Exposed Pad (25) 12 13 14 SS COMP FB 9 15 13 14 -- 16 23 20 21, 22 15 PGOOD LGATE1 LGATE2 VCC PI DS8805C-03 August 2007 www.richtek.com 5 RT8805C Absolute Maximum Ratings Preliminary (Note 1) Supply Voltage, VCC -------------------------------------------------------------------------------------------------- −0.3V to 16V PHASE to GND DC ------------------------------------------------------------------------------------------------------------------------- −5V to 15V < 200ns ------------------------------------------------------------------------------------------------------------------ −10V to 30V BOOT to PHASE ------------------------------------------------------------------------------------------------------ 15V BOOT to GND DC ------------------------------------------------------------------------------------------------------------------------- −0.3V to VCC+15V < 200ns ------------------------------------------------------------------------------------------------------------------ −0.3V to 42V Input, Output or I/O Voltage ----------------------------------------------------------------------------------------- GND-0.3V to 7V Power Dissipation, PD @ TA = 25°C VQFN−16L 3x3 --------------------------------------------------------------------------------------------------------- 1.47W VQFN−24L 4x4 --------------------------------------------------------------------------------------------------------- 1.923W Package Thermal Resistance (Note 4) VQFN−16L 3x3, θJA --------------------------------------------------------------------------------------------------- 68°C/W VQFN−24L 4x4, θJA --------------------------------------------------------------------------------------------------- 52°C/W Junction Temperature ------------------------------------------------------------------------------------------------- 150°C Lead Temperature (Soldering, 10 sec.) --------------------------------------------------------------------------- 260°C ESD Susceptibility (Note 2) HBM (Human Body Mode) ------------------------------------------------------------------------------------------ 1.5kV MM (Machine Mode) -------------------------------------------------------------------------------------------------- 200V Recommended Operating Conditions (Note 3) Supply Voltage --------------------------------------------------------------------------------------------------------- 9V to 14V Junction Temperature Range ---------------------------------------------------------------------------------------- −40°C to 125°C Ambient Temperature Range ---------------------------------------------------------------------------------------- −40°C to 85°C Electrical Characteristics (VIN = 12V, TA = 25°C, unless otherwise specified) Parameter Supply Input Power Supply Voltage Power On Reset Power On Reset Hysteresis Power Supply Current PI Threshold Soft Start Soft Start Current Oscillator Free Running Frequency Frequency Variation Frequency Range Maximum Duty Cycle www.richtek.com 6 Symbol VCC VCC IVCC VEN VEN ISS fOSC Test Conditions Min -5.4 -- Typ 12 5.9 0.3 10 0.3 50 10 300 -300 75 Max 15 6.5 ----15 345 15 1000 80 Units V V V mA V mV μA kHz % kHz % VSS = 0V ---8 ON Hysteresis RT = 33kΩ 255 -15 50 70 To be continued DS8805C-03 August 2007 Preliminary Parameter Ramp Amplitude Reference Voltage Feedback Voltage Error Amplifier DC Gain G ain-Bandwidth Product Trans-conductance MAX Current (Source & Sink) Current Sense GM Amplifier OC G ate Driver Maximum Upper Drive Source Upper Drive Sink Maximum Lower Drive Source Lower Drive Sink P rotection Under Voltage Protection Power Sequence Power Good Threshold Power Good Output Low Voltage Measure SS Voltage IP GOOD = 4mA 3.4 -0.55 IUGATE(MAX) RUGATE ILGA TE(MAX) RLGA TE BOOT − P HASE = 12V VUGATE = 1V PV CC = 12V VLGATE = 1V 1 -1 -V PHASE RIMAX = 33kΩ -GBW GM ICOMP CLOAD = 5pF RLOAD = 20k Ω VCOMP = 2 .5V 60 6 6 00 300 V FB VFB = 0.8V 0.792 Symbol Test Conditions Min -- RT8805C Typ 1.6 Max -Units V 0.8 0.808 V 70 10 660 360 ----- dB MHz μA/V μA -220 -- mV -3.5 -2 -7 -4 A Ω A Ω 0.6 0.65 V 3.8 0.05 4.2 0.2 V V Note 1. Stresses listed as the above "Absolute Maximum Ratings" may cause permanent damage to the device. These are for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. Note 2. Devices are ESD sensitive. Handling precaution recommended. Note 3. The device is not guaranteed to function outside its operating conditions. Note 4. θJA is measured in the natural convection at TA = 25°C on a high effective four layers thermal conductivity test board of JEDEC 51-7 thermal measurement standard. DS8805C-03 August 2007 www.richtek.com 7 RT8805C Preliminary Typical Operating Characteristics Phase Loading vs. Output Loading 30 25 VREF v s. Temperature 0.7945 0.794 0.7935 0.793 Low-Side : IPD06N03 High-Side : IPD09N03 Phase Loading (A) 20 15 V REF (V) 40 45 50 PHASE2 0.7925 0.792 0.7915 0.791 0.7905 0.79 PHASE1 10 5 0 5 10 15 20 25 30 35 0.7895 -40 -25 -10 5 20 35 50 65 80 95 110 125 Output Loading (A) Temperature (°C) FOSC v s. Temperature 306 304 302 300 298 296 294 -40 -25 -10 5 20 35 50 65 80 95 110 125 Dead Time RRT = 33k Low-Side : IPD06N03 High-Side : IPD09N03 UGATE No Load F OSC (kHz) PHASE LGATE UGATE-PHASE (5V/Div) Temperature (°C) Time (100ns/Div) OCP OCP Start up then Short, CSS = 0.1μF VOUT (100mV/Div) VOUT (1V/Div) SS (5V/Div) IL (10A/Div) SS (2V/Div) IL (20A/Div) UGATE (20V/Div) Time (25ms/Div) Short then Start up, CSS = 0.1μF Time (25ms/Div) www.richtek.com 8 DS8805C-03 August 2007 Preliminary RT8805C Power On No Load Power Off IOUT = 3A VOUT (1V/Div) UGATE (20V/Div) LGATE (10V/Div) IL (5A/Div) Time (100μs/Div) VOUT (1V/Div) UGATE (20V/Div) LGATE (10V/Div) IL (5A/Div) Time (1ms/Div) Short Pulse Low-Side : IPD06N03 High-Side : IPD09N03 During Soft Start No Load Shutdown by SS Pin UGATE UGATE-PHASE PHASE LGATE VOUT (500mV/Div) UGATE (10V/Div) LGATE (10V/Div) (5V/Div) Time (100ns/Div) Time (100μs/Div) Start Up by SS Pin No Load, CSS = 0.1μF VIN = 0V, CSS = 0.1μF UVP VOUT (1V/Div) LGATE (10V/Div) UGATE (10V/Div) SS (1V/Div) Time (5ms/Div) VOUT (20mV/Div) SS (2V/Div) LGATE (10V/Div) UGATE (1V/Div) Time (50ms/Div) DS8805C-03 August 2007 www.richtek.com 9 RT8805C Applications Information Power On Reset Preliminary Frequency setting The converter switching frequency is programmed by connecting a resistor from the RT pin to GND. Figure 2 illustrates switching frequency vs. RRT. Switching Frequency (kHz) RT8805C operates with input voltage at VCC pin ranging from 5.9V to 15V. An internal linear regulator regulates the input voltage to 5V for internal control circuit use. The POR (power on reset) circuitry monitors the supply voltage to make sure the supply voltage is high enough for RT8805C normal work. When the regulated power exceeds 4.2V typically, the RT8805C releases the reset state and works according to the setting. Once the regulated voltage is lower than 4.0V, POR circuitry resets the chip. Hysteresis between the rising and falling thresholds assure that once enabled, the RT8805C will not inadvertently turn off unless the bias voltage drops substantially (see Electrical Specifications). Enable, Soft Start and Power Good Once POR releases, the RT8805C begins its soft start cycle as shown in Figure 1. A 10μA source current charges the capacitor CSS connected to SS to control the soft start behavior of RT8805C. During soft start, SS voltage increases linearly and clamps the error amplifier output. Duty cycle and output voltage increase accordingly. The soft start limits inrush current from input capacitors. The RT8805C regards SS pin voltage higher than 3.7V as the end of soft start cycle. Then RT8805C trip PGOOD to high impedance if no fault occurs indicating power good. The SS pin also act as the timer during OCP and UVP hiccup as described in the later sections. Switching Frequency vs. RT Resistance 1200 1000 800 600 400 200 0 0 20 40 60 80 100 RT Resistance (k Ω) Figure 2. Switching Frequency vs. RRT. Voltage Control The voltage control loop consists of error amplifier, multiphase pulse width modulator, drivers and power components. As conventional voltage mode PWM controller, the output voltage is locked at the positive input of error amplifier and the error signal is used as the control signal of pulse width modulator. The PWM signals of different channels are generated by comparison of EA output and split-phase sawtooth wave. Power stage transforms VIN to output by PWM signal on-time ratio. Current Sensing Setting RT8805C senses the current of low side MOSFET in each synchronous rectifier when it is conducting for channel current balance and OCP detecting. The multiplexer and sensing GM amplifier converts the voltage on the sense component (can be a sense resistor or the RDS(ON) of the low side MOSFET) to current signal into internal circuit (see Figure 3). VDD POR SS SSH FB PGOOD > 0.6V > 3.7V Figure 1. Power Sequence www.richtek.com 10 DS8805C-03 August 2007 Preliminary Current Balance PHASE1 PHASE2 CLK1 RAMP1 RAMP2 CLK2 MUX RT8805C Current Balance S/H OCP OC GM + RT8805C senses the voltage drop of the low-side MOS and translates this to control the ramp signal. We can see that the voltage signal finally injected to channel one is proportional to (IL1 - IL2). Channel two is proportional to (IL2 - IL1). In steady state and current balance situation, there is no sensed signal injected into the ramp. If IL1 > IL2, the ramp bottom of channel 1 will be lifted up and decreased the duty of UGATE1. On the other hand, the ramp bottom of channel 2 will be pulled low to increase the duty of UGATE2. Finally, the loop will be back to the balance state through above mentioned negative feedback scheme. Figure 5 shows this scheme. VREF RAMP2 + + COMP Logic & Driver k2 = k x RON2 −1 2 VIN2 IL2 L2 VON2 CL VIN1 + RAMP1 Logic & Driver k1 = k x RON1 IL1 L1 VON1 VOUT IMAX Figure 3. Current Sensing Loop The sensing circuit gets IX = IL(S/H) x RDS(ON) x GM by local feedback. IX is sampled and held just before low side MOSFET turns off (See Figure 4). Therefore, IX(S/H) = IL(S/H) x RDS(ON) x GM IL(S/H) = IL(AVG) − VOUT × TOFF , L 2 TOFF = ⎡ VIN − VOUT ⎤ × 5 μs, ⎥ ⎢ VIN ⎦ ⎣ VCSO2 = k2 x IL2 = k x VON2 RL FSW = 200kHz ⎡ ⎤ VOUT × ⎛ VIN − VOUT ⎞ × 5 μs ⎥ ⎜ ⎟ ⎢ VIN ⎝ ⎠ I X (S/H) = ⎢IL(AVG) − ⎥ 2L ⎢ ⎥ ⎢ ⎥ ⎣ ⎦ × RDS(ON) × GM VCSO1 = k1 x IL1 = k x V ON1 Figure 5. Current Balance Falling Slope = VOUT/L IL IL(AVG) Inductor Current IL(S/H) Gate control a. Before SS signal reach the valley of the ramp voltage, UGATE and LGATE will be off. b. If SS pin is pulled down 0.4V, UGATE and LGATE will be off. c. UV protect function caused by FB < 0.6V and SS > 3.7V, and controller will trigger Always Hiccup Mode. d. When OC function occurs and SS > 3.7V, a constant current of 10 μA starts to discharge the capacitor connected to SS pin right away. When OC occurs, UGATE and LGATE will be off. When the voltage at the capacitor connected to SS pin pass about 0.4V, a constant current of 10μA starts to charge the capacitor. The PWM signal is enable to pass to UGATE and www.richtek.com 11 High Side MOSFET Gate Signal Low Side MOSFET Gate Signal Figure 4. Inductor Current and Gate signals DS8805C-03 August 2007 RT8805C Preliminary The first step is to calculate the complex conjugate poles contributed by the LC output filter. The output LC filter introduces a double pole, 40dB/decade gain slope above its corner resonant frequency, and a total phase lag of 180 degrees. The resonant frequency of the LC filter expressed as follows : FP(LC) = 1 2π × L OUT × COUT LGATE. OCP function monitors both channels, either one can activate OCP. If the OC protection occurs three times, OCSD (Over Current Shut Down) will be activated and shut down the chip. e. When fault conditions occur or SS < 0.4V, the current sense function will be disabled. Power Good PGOOD goes high when soft-start voltage > 3.7V, and no fault conditions. Feedback Loop Compensation The RT8805C is a voltage mode controller ; the control loop is a single voltage feedback path including an error amplifier and PWM comparator. In order to achieve fast transient response and accurate output regulation, an adequate compensator design is necessary. The goal of the compensation network is to provide adequate phase margin (greater than 45 degrees) and the highest 0dB crossing frequency. To manipulate loop frequency response under its gain crosses over 0dB at a slope of -20dB/ decade. 1) Modulator Frequency Equations RT8805C is a voltage mode buck converter using the high gain error amplifier with transconductance (OTA, Operational Transconductance Amplifier), as Figure 6 shown. The Transconductance: GM = ΔIOUT ΔVM Δ VM = (EA+) - (EA-) ; Δ IOUT = E/A output current. VOUT EA+ EA+ GM ROUT The next step of compensation design is to calculate the ESR zero. The ESR zero is contributed by the ESR associated with the output capacitance. Note that this requires that the output capacitor should have enough ESR to satisfy stability requirements. The ESR zero of the output capacitor expressed as follows : 1 FZ(ESR) = 2π × COUT × ESR 2) Compensation Frequency Equations The compensation network consists of the error amplifier and the impedance networks as Figure 7 shown. R1 VREF + GM VCOMP C2 R2 C1 VOUT FB RF Figure 7. Compensation Loop FZ1 = 1 2π × R2 × C2 1 2π × R2 × ⎜ FP1 = 0 FP2 = Figure 6. OTA Topology This transfer function of OTA is dominated by a higher DC gain and the output filter (LOUT and COUT) with a double pole frequency at FLC and a zero at FESR. The DC gain of the modulator is the input voltage (VIN) divided by the peak to peak oscillator voltage VRAMP. www.richtek.com 12 Figure 8 shows the DC-DC converter's gain vs. frequency. The compensation gain uses external impedance networks to provide a stable, high bandwidth loop. High crossover frequency is desirable for fast transient response, but often jeopardize the system stability. In order to cancel one of the LC filter poles, place FZ1 before the LC filter resonant frequency. In the experience, place FZ1 at 10% LC filter resonant frequency. Crossover frequency should be higher than the ESR zero but less than 1/5 of the switching frequency. The FP2 should be place at half the switching frequency. DS8805C-03 August 2007 ⎛ C1 × C2 ⎞ ⎟ ⎝ C1+C2 ⎠ Preliminary 80 80 Loop Gain 60 40 40 20 Gain (dB) 0 -20 -4040 0 RT8805C Type 3 will induce additional one pole and one zero. Zeros : Compensation Gain FZ2 = Poles : FP3 = 1 2π × (R1 + R3) × C3 Modulator Gain 1 2π × R3 × C3 -6060 1H 0z 10db(vo) v 10z 0H v b c m 2100l ) d(op) vb o d( 1k 10k Feuny rqec Frequency (Hz) 10H .Kz 1Kz 0H 100k 10H 0Kz 10H .Mz 1M which is in the origin. We recommend FZ1 placed in 0.5 x FP(LC); FZ2 placed in FP(LC); FP3 placed in FESR and FP2 placed in 0.5 x FSW. Figure 11 shows Type 3 Bode Plot. Figure 8. Type 2 Bode Plot There is another type of compensation called Type 3 compensation that adds a pole-zero pair to the Type 2 network. It's used to compensate output capacitor whose ESR value is much lower (pure MLCC or OSCON Capacitors). As shown in Figure 9, to insert a network between VOUT and FB in the original Type 2 compensation network can result in Type 3 compensation. Figure 10 shows the difference of their AC response. Type 3 compensation has an additional pole-zero pair that causes a gain boost at the flat gain region. But the gain boosted is limited by the ratio (R1+R4)/R4; if R3 3.7V, a constant current of 10μA starts to discharge the capacitor connected to SS pin right away. When OC occurs, UGATE and LGATE will be off. F Z1 F Z2 F P2 Original Type 2 compensation Figure 10. AC Response Curves of Type 2 and 3 DS8805C-03 August 2007 www.richtek.com 13 RT8805C Preliminary UVP VIN = 0V When the voltage at the capacitor connected to SS pin pass about 0.4V, a constant current of 10μA starts to charge the capacitor. The PWM signal is enabled to pass to the UGATE and LGATE. OCP function monitors both channels, either one can activate OCP. If the OC protection occurs three times, the chip will shut down and the state will only be released by POR. RT8805C uses an external resistor R IMAX t o set a programmable over current trip point. OCP comparator compares each inductor current with this reference current. RT8805C uses hiccup mode to eliminate fault detection of OCP or reduce output current when output is shorted to ground. The OCP comparator compares the difference between IX and IIMAX. OCP Comparator IIMAX IX + - VOUT (20mV/Div) SS (2V/Div) LGATE (10V/Div) UGATE (1V/Div) Time (50ms/Div) Figure 12. UVP (Always Hiccup Mode) OTP Monitor the temperature near the driver part within the chip. Shutdown the chip when OTP (Typical trip point : 170°C). General Design Guide This design guide is intended to provide a high-level explanation of the steps necessary to create a multi-phase power converter. It is assumed that the reader is familiar with many of the basic skills and techniques referenced below. Power Stages Designing a multi-phase converter is to determine the number of phases. This determination depends heavily on the cost analysis which in turn depends on system constraints that differ from one design to the next. Principally, the designer will be concerned with whether components can be mounted on both sides of the circuit board, whether through-hole components are permitted, the total board space available for power-supply circuitry, and the maximum amount of load current. Generally speaking, the most economical solutions are those in which each phase handles between 20 to 25 A (One Upper and one Lower MOSFET). All surface-mount designs will tend toward the lower end of this current range. If through-hole MOSFETs and inductors can be used, higher per-phase currents are possible. In cases where DS8805C-03 August 2007 For example: From Electrical Specifications : RIMAX = 33kΩ VPHASE = -220mV Assume Low side MOSFET RDS(ON) = 3mΩ. Get the OCP setting current is 220mV =73A per PHASE 3mΩ (the valley of inductor's current). Change the setting current which you want from 73A per PHASE to 50A per PHASE. Following below steps: 1. Calculate phase voltage. If Low side MOSFET RDS(ON) = 3mΩ, VPHASE_new = -150mV. 2. RIMAX_new = -220mV × 33k Ω VPHASE_new RIMAX_new = 48.4k Ω UVP By detecting voltage at FB pin when SS > 3.7V. If FB < 0.6V, the chip will trigger the always Hiccup mode and a constant current source 10μA starts to charge capacitor at SS pin when SS pass 0.4V and discharge Css when SS > 3.7V. As Figure 12 shown. www.richtek.com 14 Preliminary board space is the limiting constraint, current can be pushed as high as 40A per phase, but these designs require heat sinks and forced air to cool the MOSFETs, inductors and heat dissipating surfaces. MOSFETs The choice of MOSFETs depends on the current each MOSFET will be required to conduct, the switching frequency, the capability of the MOSFETs to dissipate heat, and the availability and nature of heat sinking and air flow. Package Power Dissipation When choosing MOSFETs it is important to consider the amount of power being dissipated in the integrated drivers located in the controller. Since there are a total of two drivers in the controller package, the total power dissipated by both drivers must be less than the maximum allowable power dissipation for the VQFN package. Calculating the power dissipation in the drivers for a desired application is critical to ensure safe operation. Exceeding the maximum allowable power dissipation level will push the IC beyond the maximum recommended operating junction temperature of 125°C. The maximum allowable IC power dissipation for the 3x3 VQFN package is approximately 1.47W at room temperature. According below equations at two phases operation, it’ s clear to describe that the junction temperature of the chip is directly proportional to the total CISS (including CUGATE and CLGATE) of all external MOSFETs. PD = ( CUGATE x VBOOT-PHASE2 x f ) + ( CLGATE x VCC2 x f ) + RT8805C operated under or over maximum (~125°C) operation rating. Layout Considerations Layout is very important in high frequency switching converter design. If designed improperly, the PCB could radiate excessive noise and contribute to the converter instability. First, place the PWM power stage components. Mount all the power components and connections in the top layer with wide copper areas. The MOSFETs of Buck, inductor, and output capacitor should be as close to each other as possible. This can reduce the radiation of EMI due to the high frequency current loop. If the output capacitors are placed in parallel to reduce the ESR of capacitor, equal sharing ripple current should be considered. Place the input capacitor directly to the drain of high-side MOSFET. In multi-layer PCB, use one layer as power ground and have a separate control signal ground as the reference of the all signal. To avoid the signal ground is effect by noise and have best load regulation, it should be connected to the ground terminal of output. Furthermore, follows below guidelines can get better performance of IC : 1. A multi-layer printed circuit board is recommended. 2. Use a middle layer of the PC board as a ground plane and making all critical component ground connections through vias to this layer. 3. Use another solid layer as a power plane and break this plane into smaller islands of common voltage levels. 4. Keep the metal running from the PHASE terminal to the output inductor short. 5. Use copper filled polygons on the top and bottom circuit layers for the phase node. 6. The small signal wiring traces from the LGATE and UGATE pins to the MOSFET gates should be kept short and wide enough to easily handle the several Amperes of drive current. 7. The critical small signal components include any bypass capacitors, feedback components, and compensation components. Position those components close to their pins with a local GND connection, or via directly to the ground plane. www.richtek.com 15 χ TJ = TA + ( θJA x PD ) (χ is the minor factor and could be ignored) For example, according to the application we evaluated on board, the CUGATE = 1nF, CLGATE = 5nF (dual MOSFETs in parallel), VCC = 12V, VBOOT-PHASE = 12V, and operation frequency = 300kHz. PD ≈ 1nF x 122 x 300kHz + 2 x 5nF x 122 x 300kHz = 475mW / PHASE TJ = 30°C+ 68°C/W x 0.475W x 2 = 94.6°C That means the junction temperature is most likely to be DS8805C-03 August 2007 RT8805C Preliminary 8. RT and RIMAX resistors should be near the RT and RIMAX pin respectively, and their GND return should be short, and kept away from the noisy MOSFET GND. 9. Place the compensation components close to the FB and COMP pins. 10. The feedback resistors for both regulators should also be located as close as possible to the relevant FB pin with vias tied straight to the ground plane as required. 11. Minimize the length of the connections between the input capacitors, CIN and the power switches by placing them nearby. 12. Position both the ceramic and bulk input capacitors as close to the upper MOSFET drain as possible, and make the GND returns (From the source of lower MOSFET to VIN, CVIN, GND) short. 13. Position the output inductor and output capacitors between the upper MOSFET and lower MOSFET and the load. 14. AGND should be on the clearer plane, and kept away from the noisy MOSFET GND. www.richtek.com 16 DS8805C-03 August 2007 Preliminary Outline Dimension SEE DETAIL A L 1 RT8805C D D2 E E2 1 1 2 e A A1 A3 b 2 DETAIL A Pin #1 ID and Tie Bar Mark Options Note : The configuration of the Pin #1 identifier is optional, but must be located within the zone indicated. Symbol A A1 A3 b D D2 E E2 e L Dimensions In Millimeters Min 0.800 0.000 0.175 0.180 2.950 1.300 2.950 1.300 0.500 0.350 0.450 Max 1.000 0.050 0.250 0.300 3.050 1.750 3.050 1.750 Dimensions In Inches Min 0.031 0.000 0.007 0.007 0.116 0.051 0.116 0.051 0.020 0.014 0.018 Max 0.039 0.002 0.010 0.012 0.120 0.069 0.120 0.069 V-Type 16L QFN 3x3 Package DS8805C-03 August 2007 www.richtek.com 17 RT8805C Preliminary D D2 SEE DETAIL A L 1 E E2 1 2 1 2 e A A3 A1 b DETAIL A Pin #1 ID and Tie Bar Mark Options Note : The configuration of the Pin #1 identifier is optional, but must be located within the zone indicated. Symbol A A1 A3 b D D2 E E2 e L Dimensions In Millimeters Min 0.800 0.000 0.175 0.180 3.950 2.300 3.950 2.300 0.500 0.350 0.450 Max 1.000 0.050 0.250 0.300 4.050 2.750 4.050 2.750 Dimensions In Inches Min 0.031 0.000 0.007 0.007 0.156 0.091 0.156 0.091 0.020 0.014 0.018 Max 0.039 0.002 0.010 0.012 0.159 0.108 0.159 0.108 V-Type 24L QFN 4x4 Package Richtek Technology Corporation Headquarter 5F, No. 20, Taiyuen Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)5526789 Fax: (8863)5526611 Richtek Technology Corporation Taipei Office (Marketing) 8F, No. 137, Lane 235, Paochiao Road, Hsintien City Taipei County, Taiwan, R.O.C. Tel: (8862)89191466 Fax: (8862)89191465 Email: marketing@richtek.com www.richtek.com 18 DS8805C-03 August 2007