RT9005APSP

Preliminary RT9005A/B DDR VDDQ and Termination Voltage Regulator General Description The RT9005A/B is a dual-output linear regulator for DDRSDRAM VDDQ supply and termination voltage VTT supply. The Regulator is capable of actively sinking or sourcing up to 2A. The output termination voltage can be tightly regulated to track 1/2 VDDQ by two external voltage divider resistors. Features Ideal for DDR-I and DDR-II VDDQ, VTT Applications Integrated Power MOSFETs G enerates Termination Voltage for SSTL_2, SSTL _18, HSTL, SCSI-2 and SCSI-3 Interfaces High Accuracy Output Voltage at Full-Load VOUT2 Sink and Source 2A Continuous Current VOUT2 Adjustment by Two External Resistors Shutdown for Suspend to RAM (STR) Functionality with High-Impedance Output Current Limiting Protection On-Chip Thermal Protection Available in SOP-8 (Exposed Pad) Packages RoHS Compliant and 100% Lead (Pb)-Free Ordering Information RT9005 Package Type SP : SOP-8 (Exposed Pad-Option 2) Operating Temperature Range P : Pb Free with Commercial Standard G : Green (Halogen Free with Commercial Standard) VOUT1 Output Voltage A : 2.5V B : 1.8V Note : Richtek Pb-free and Green products are : RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020. Suitable for use in SnPb or Pb-free soldering processes. 100% matte tin (Sn) plating. Applications Desktop PCs, Notebooks, and Workstations Graphics Card Memory Termination Set Top Boxes, Digital TVs, Printers Embedded Systems Active Termination Buses DDR-I and DDR-II Memory Systems Pin Configurations (TOP VIEW) BP VIN1 VIN2 VCNTL 2 3 4 8 GND 6 9 5 7 VOUT1 GND VOUT2 VREFEN SOP-8 (Exposed Pad) DS9005A/B-01 September 2007 www.richtek.com 1 RT9005A/B Typical Application Circuit VIN1 CIN1 2.2uF CBP 10nF Preliminary VIN2 2 VIN1 1 BP 8 VOUT1 R1 COUT1 2.2uF RT9005A/B VOUT2 6 COUT2 470uF 3 VIN2 VCNTL 4 CIN2 470uF VCTNL = 3.3V CVCNTL 47uF RTT VOUT1 2N7002 EN R2 CSS 1uF 5 VREFEN GND 7, Exposed Pad(9) GND Note : If there is any application need to use 10μF ceramic capacitor in front of RTT, please shut one 1000μF (Aluminum eletrolytic capacitor). Functional Pin Description Pin No. 1 7, Exposed Pad (9) 2 Pin Name BP Pin Function Noise Reduction. Connecting a 10nF capacitor to GND to reduce output noise. Common Ground (T he exposed pad must be soldered to a large PCB and GND connected to GND for maximum power dissipation). The GND pad are a should be as large as possible and using many vias to conduct the heat into the buried GND plate of PCB layer. V IN1 Linear Regulator Power Input Voltage. Input voltage which supplies current to the output pin. Connect this pin to a 3 V IN2 well-decoupled supply voltage. To prevent the input rail from dropping during large load transient, a large, low ESR capacitor is recommended to use. The capacitor should be placed as close as possible to the VIN2 pin. VCNTL supplies the internal control circuitr y and provides the drive voltage. The driving capability of output current is proportioned to the VCNTL. Connect this pin to 3.3V bias supply to handle large output current with at least 10uF capacitor from this pin to GND. Reference voltage input and active low VOUT2 shutdown control pin. Two resistors 5 V REFEN dividing down the VIN voltage on the pin to create the regulated output voltage. Pulling the pin to ground turns off the device by an open-drain, such as 2N7002, signal N-MOSFET. Regulator Output. VOUT2 is regulated to REFEN voltage that is used to terminate the bus resistors. It is capable of sinking and sourcing current while regulating the 6 V OUT2 output rail. To maintain adequate large signal transient response, typical value of 1000μ F AL electrolytic capacitor with 10μF ceramic capacitors are recommended to 8 www.richtek.com 2 4 V CNTL V OUT1 reduce the effects of current transients on V OUT . Regulator 2.5V/1.8/1.5V Output. DS9005A/B-01 September 2007 Preliminary Function Block Diagram VIN1 Current Limit Sensor + Error Amplifier + VCNTL VOUT1 T hermal Shutdown RT9005A/B BP 0.8V Reference VCNTL VIN2 Current Limit Thermal Protection GND + VREFEN VOUT2 - DS9005A/B-01 September 2007 www.richtek.com 3 RT9005A/B Absolute Maximum Ratings Preliminary (Note 1) Supply Input Voltage, VIN -------------------------------------------------------------------------------------------- 6V Power Dissipation, PD @ TA = 25°C SOP-8 (Exposed) ----------------------------------------------------------------------------------------------------- 1.33W Package Thermal Resistance (Note 4) SOP-8 (Exposed), θJA ------------------------------------------------------------------------------------------------ 75°C/W SOP-8 (Exposed), θJC ----------------------------------------------------------------------------------------------- 28°C/W Junction Temperature ------------------------------------------------------------------------------------------------- 150°C Lead Temperature (Soldering, 10sec.) ---------------------------------------------------------------------------- 260°C Storage Temperature Range ---------------------------------------------------------------------------------------- −65°C to 150°C ESD Susceptibility (Note 2) HBM (Human Body Mode) ------------------------------------------------------------------------------------------ 2kV MM (Machine Mode) -------------------------------------------------------------------------------------------------- 200V Recommended Operating Conditions (Note 3) Supply Input Voltage, VIN1 ------------------------------------------------------------------------------------------ 5V to 2.5V Supply Input Voltage, VIN2 ------------------------------------------------------------------------------------------ 3.6V to 1.5V Control Voltage, VCNTL ----------------------------------------------------------------------------------------------- 5V to 3.1V Junction Temperature Range ---------------------------------------------------------------------------------------- −40°C to 125°C Ambient Temperature Range ---------------------------------------------------------------------------------------- −40°C to 85°C Electrical Characteristics (VIN1 =3.3V , VIN1 = VOUT + 1V, CIN1 = COUT1 = 2.2μF (Ceramic) & CBP = 10nF; VIN2 = 2.5V/1.8/1.5V, VCNTL = 3.3V, VREFEN = 1.25V/ 0.9/0.75V, CIN2 = 470μF, CVCNTL= 47μF, COUT2 = 1000μF(Electrolytic), TA = 25°C, unless otherwise specified) Parameter Input Operation Current Standby Current VOUT1 (VDDQ) VOUT1 Accuracy VOUT1 Current Limit VOUT1 Dropout Voltage (Note 6) Line Regulation Load Regulation VOUT2 (VTT) Output Offset Voltage (Note 7) (Note 5) Symbol IVCNTL ISTBY2 IOUT = 0A Test Conditions Min --- Typ 1.5 50 Max 3.0 90 Units mA μA VREFEN < 0.2V (Shutdown), RLOAD = 180Ω IOUT = 10mA RLOAD = 0.5Ω, VIN1 = 3.3V IOUT = 0.5A IOUT = 1.0A VIN1 = (VOUT1 + 0.5V) to 5.5V IOUT1 = 1mA VIN1 = (VOUT1 + 0.5V) 10mA < IOUT1 < 1A IOUT = 0A ΔVOUT ILIM1 VDROP ΔVLINE ΔVLOAD −2 2 ----- -2.8 120 240 -0.4 +2 3 180 360 0.3 -- V A mV % %/A (Note 8) VOS −20 -- +20 mV To be continued www.richtek.com 4 DS9005A/B-01 September 2007 Preliminary Parameter Load Regulation (Note 7) Symbol ΔVLOAD ILIM2 Test Conditions IOUT = +2A IOUT = −2A RT9005A/B Min −20 2.2 --Typ --170 35 --Max +20 ----0.2 Units mV A °C °C VOUT2 Current Limit Protection Thermal Shutdown Temperature TSD Thermal Shutdown Hysteresis REFEN Shutdown Shutdown Threshold VIH VIL Enable Shutdown ΔTSD 0.6 -- V Note 1. Stresses listed as the above "Absolute Maximum Ratings" may cause permanent damage to the device. These are for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. Note 2. Devices are ESD sensitive. Handling precaution recommended. Note 3. The device is not guaranteed to function outside its operating conditions. Note 4. θJA is measured in the natural convection at TA = 25°C on a high effective thermal conductivity test board (4 Layers, 2S2P) of JEDEC 51-7 thermal measurement standard. The case point of θJC is on the expose pad for SOP-8 (Exposed Pad) package. Note 5. VOUT2 Standby current is the input current drawn by a regulator when the output voltage is disabled by a shutdown signal on REFEN pin (VIL < 0.2V). It is measured with VIN2 = VCNTL = 5V. Note 6. The dropout voltage is defined as VIN -VOUT, which is measured when VOUT is VOUT(NORMAL) − 100mV. Note 7. Regulation is measured at constant junction temperature by using a 5ms current pulse. Devices are tested for load regulation in the load range from 0A to 2A. Note 8. VOS offset is the voltage measurement defined as VOUT subtracted from VREFEN. DS9005A/B-01 September 2007 www.richtek.com 5 RT9005A/B Preliminary Typical Operating Characteristics Output Voltage vs. Temperature 3.0 VIN2 Current vs. Temperature 5 4.5 VIN1 = VIN2 = VCNTL = 3.3V Output Voltage (V) VOUT1 = 2.5V V IN2 Current (mA) 2.5 VIN2 VIN2 = 1.8V, VCNTL = 3.3V VIN2 = 1.8V, VCNTL = 5V = 2.5V, VCNTL = 3.3V 4 3.5 3 VIN2 = 2.5V, VCNTL = 5V 2.0 1.5 VOUT1 = 1.25V VIN2 = 1.5V, VCNTL = 5V 2.5 2 VIN2 = 1.5V, VCNTL = 3.3V 1.0 -50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125 Temperature (°C) Temperature (°C) VCNTL Current vs. Temperature 0.6 0.55 REFEN Threshold vs. Temperature 0.6 0.55 REFEN Threshold (V) V CNTL Current (mA) VIN2 0.5 0.45 0.4 0.35 0.3 -50 VIN2 = 1.8V, VCNTL = 3.3V VIN2 = 1.8V, VCNTL = 5V VIN2 = 2.5V, VCNTL = 3.3V = 2.5V, VCNTL = 5V VCNTL = 5V, Turn On VCNTL = 5V, Turn Off 0.5 0.45 0.4 0.35 VCNTL = 3.3V, Turn On VCNTL = 3.3V, Turn Off VIN2 = 1.5V, VCNTL = 5V VIN2 = 1.5V, VCNTL = 3.3V 0.3 0.25 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125 Temperature (°C) Temperature (°C) VOUT1 Short Circuit VOUT2 Short Circuit VOUT1 (1V/Div) VOUT2 (1V/Div) IOUT1 (1A/Div) VIN1 = VIN2 = VCNTL = 3.3V IOUT2 (2A/Div) VIN1 = VIN2 = VCNTL = 3.3V Time (1ms/Div) Time (1ms/Div) www.richtek.com 6 DS9005A/B-01 September 2007 Preliminary RT9005A/B VOUT1 @ 1A Load Transient Response Line Transient Response VIN1 4.3 (V) 3.3 IOUT1 (1A/Div) VOUT1 (50mV/Div) VOUT2 (50mV/Div) VIN2 = VCNTL = 3.3V, ILOAD = 1A VIN1 = VIN2 = VCNTL = 3.3V, IOUT1 = 50mA to 1A VOUT1 (100mV/Div) VOUT2 (100mV/Div) Time (500μs/Div) Time (500μs/Div) VOUT1 @ 1.5A Load Transient Response IOUT1 (1A/Div) VOUT1 (100mV/Div) VOUT2 (100mV/Div) VIN1 = VIN2 = VCNTL = 3.3V, IOUT1 = 50mA to 1.5A VOUT2 @ 2A Load Transient Response Sink IOUT2 (2A/Div) VOUT1 (20mV/Div) VOUT2 (20mV/Div) VIN1 = VIN2 = VCNTL = 3.3V, IOUT2 = 50mA to 2A Time (500μs/Div) Time (500μs/Div) VOUT2 @ 2A Load Transient Response Source IOUT2 (2A/Div) VOUT1 (20mV/Div) VOUT2 (20mV/Div) VIN1 = VIN2 = VCNTL = 3.3V, IOUT2 = 50mA to 2A Time (500μs/Div) DS9005A/B-01 September 2007 www.richtek.com 7 RT9005A/B Application Information Thermal Consideration Preliminary RGOLD-LINE path 1 RDIE RLEAD FRAME RPCB RT9005A/B regulators have internal thermal limiting circuitry designed to protect the device during overload conditions. For continued operation, do not exceed maximum operation junction temperature 125°C. The power dissipation definition in device is : PD = (VIN - VOUT) x IOUT + VIN x IQ The maximum power dissipation depends on the thermal resistance of IC package, PCB layout, the rate of surroundings airflow and temperature difference between junction to ambient. The maximum power dissipation can be calculated by following formula : PD(MAX) = ( TJ(MAX) -TA ) /θJA Where T J(MAX) i s the maximum operation junction temperature 125°C, TA is the ambient temperature and the θJA is the junction to ambient thermal resistance. The junction to ambient thermal resistance (θJA is layout dependent) for SOP-8 package (Exposed Pad) is 75°C/ W on standard JEDEC 51-7 (4 layers, 2S2P) thermal test board. The maximum power dissipation at TA = 25°C can be calculated by following formula : PD(MAX) = (125°C - 25°C) / 75°C/W = 1.33W Figure 2 show the package sectional drawing of SOP-8 (Exposed Pad). Every package has several thermal dissipation paths. As show in Figure 2, the thermal resistance equivalent circuit of SOP-8 (Exposed Pad). The path 2 is the main path due to these materials thermal conductivity. We define the exposed pad is the case point of the path 2. Ambient Molding Compound Gold Line Junction RDIE-ATTACH RDIE-PAD path 2 RPCB Case (Exposed Pad) Ambient RMOLDING-COMPOUND path 3 Figure 2. Thermal Resistance Equivalent Circuit The thermal resistance θJA of SOP-8 (Exposed Pad) is determined by the package design and the PCB design. However, the package design has been decided. If possible, it's useful to increase thermal performance by the PCB design. The thermal resistance can be decreased by adding copper under the expose pad of SOP-8 package. About PCB layout, the Figure 3 show the relation between thermal resistance θJA and copper area on a standard JEDEC 51-7 (4 layers, 2S2P) thermal test board at TA = 25°C.We have to consider the copper couldn't stretch infinitely and avoid the tin overflow. We use the “dog-bone” copper patterns on the top layer as Figure 4. As shown in Figure 5, the amount of copper area to which the SOP-8 (Exposed Pad) is mounted affects thermal performance. When mounted to the standard SOP-8 (Exposed Pad) pad of 2 oz. copper (Figure 5.a), θJA is 75°C/W. Adding copper area of pad under the SOP-8 (Exposed Pad) (Figure 5.b) reduces the θJA to 64°C/W. Even further, increasing the copper area of pad to 70mm2 (Figure 5.e) reduces the θJA to 49°C/W. Lead Frame Die Pad Case (Exposed Pad) Figure 1. SOP-8 (Exposed Pad) Package Sectional Drawing www.richtek.com 8 DS9005A/B-01 September 2007 Preliminary θJA v s. Copper Area 100 90 80 RT9005A/B θ JA (°C/W) 70 60 50 40 30 0 10 20 30 40 50 2 Figure 5 (c). Copper Area = 30mm2, θJA = 54°C/W 60 70 Copper Area (mm ) Figure 3 Figure 5 (d). Copper Area = 50mm2, θJA = 51°C/W Exposed Pad W≦2.28mm Figure 5 (e). Copper Area = 70mm2, θJA = 49°C/W Figure 4. Dog-Bone layout Figure 5. Thermal Resistance vs. Different Cooper Area Layout Design Figure 5 (a). Minimum Footprint, θJA = 75°C/W Figure 5 (b). Copper Area = 10mm2, θJA = 64°C/W DS9005A/B-01 September 2007 www.richtek.com 9 RT9005A/B Outline Dimension Preliminary A H M EXPOSED THERMAL PAD (Bottom of Package) Y J X B F C I D Symbol A B C D F H I J M O ption 1 X Y X Y Dimensions In Millimeters M in 4.801 3.810 1.346 0.330 1.194 0.170 0.000 5.791 0.406 2.000 2.000 2.100 3.000 Max 5.004 4.000 1.753 0.510 1.346 0.254 0.152 6.200 1.270 2.300 2.300 2.500 3.500 Dimensions In Inches Min 0.189 0.150 0.053 0.013 0.047 0.007 0.000 0.228 0.016 0.079 0.079 0.083 0.118 Max 0.197 0.157 0.069 0.020 0.053 0.010 0.006 0.244 0.050 0.091 0.091 0.098 0.138 O ption 2 8-Lead SOP (Exposed Pad) Plastic Package Richtek Technology Corporation Headquarter 5F, No. 20, Taiyuen Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)5526789 Fax: (8863)5526611 Richtek Technology Corporation Taipei Office (Marketing) 8F, No. 137, Lane 235, Paochiao Road, Hsintien City Taipei County, Taiwan, R.O.C. Tel: (8862)89191466 Fax: (8862)89191465 Email: marketing@richtek.com www.richtek.com 10 DS9005A/B-01 September 2007