Preliminary
RT9024
Low-Dropout Linear Regulator Controller with PGOOD Indication
General Description
The RT9024 is a low-dropout voltage regulator controller with a specific PGOOD indicating scheme. The part could drive an external N-MOSFET for various applications. The part is operated with VCC power ranging from 3.8V to 13.5V. With such a topology, it's with advantages of flexible and cost-effective. The part comes to a small footprint package of SOT-23-6.
Features
3.8V to 13.5V Operation Voltage 0.8V ± 2% High Accuracy Voltage Reference Quick Transient Response Power Good Indicator with Delay Enable Control Small Footprint Package SOT-23-6 RoHS Compliant and 100% Lead (Pb)-Free
Ordering Information
RT9024 Package Type E : SOT-23-6 Operating Temperature Range P : Pb Free with Commercial Standard G : Green (Halogen Free with Commercial Standard)
Note : RichTek Pb-free and Green products are : RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020. Suitable for use in SnPb or Pb-free soldering processes. 100%matte tin (Sn) plating.
Applications
DSC DSLR
Pin Configurations
(TOP VIEW)
VCC 6 1 EN DRI PGOOD 5 2 GND 4 3 FB
SOT-23-6
Marking Information
For marking information, contact our sales representative directly or through a RichTek distributor located in your area, otherwise visit our website for detail.
Note : There is no pin1 indicator on top mark for SOT-23-6 type, and pin 1 will be lower left pin when reading top mark from left to right.
Typical Application Circuit
VCC VIN
Chip Enable
Ccc 1 EN 2 3 GND FB RT9024 VCC DRI 6 5 4 RPGOOD CIN Q1 VOUT
PGOOD
R1 PGOOD
COUT
R2
VOUT = 0.8
R1 + R2 R2
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RT9024
Test Circuit
V CC 12V V IN
Preliminary
V CC 12V
Chip Enable 1 EN 2 GND VCC 6 R T9024 DRI 5 PGOOD 4 PGOOD 100k R PGOOD R1 1k R2 2k Ccc 1 uF C IN 100uF Q1 PHD3055 V OUT C OUT 100uF
C hip Enable 5V 1 EN 2 V FB C FB GND R T9024 VCC 6
Ccc 1 uF
3 FB
DRI 5 4
A
V DRI
3 FB
PGOOD
V O U T = 0.8
R1 + R2 R2
V FB = 1 V for current sink at DRI V FB = 0 .6V for current source at DRI
Figure 1. Typical Test Circuit
Figure 2. DRI Source/Sink Current Test Circuit
Functional Pin Description
Pin No. 1 2 3 4 5 6 Pin Name EN G ND FB P GOOD DRI V CC Pin Function Chip Enable (Active High). Ground. Output Voltage Feedback. Power Good Open Drain Output. Driver Output. Power Supply Input.
Function Block Diagram
EN VCC Reference 0.8V Voltage 0.7V PGOOD 3ms Delay GND
+ + -
DRI
Driver
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-
FB
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Preliminary Absolute Maximum Ratings
(Note 1)
RT9024
Supply Input Voltage, VCC ------------------------------------------------------------------------------------------- 15V Enable Voltage --------------------------------------------------------------------------------------------------------- 7V Power Good Output Voltage ---------------------------------------------------------------------------------------- 7V Power Dissipation, PD @ TA = 25°C SOT-23-6 ---------------------------------------------------------------------------------------------------------------- 0.4W Package Thermal Resistance (Note 4) SOT-23-6, θJA ----------------------------------------------------------------------------------------------------------- 250°C/W Lead Temperature (Soldering, 10 sec.) --------------------------------------------------------------------------- 260°C Junction Temperature ------------------------------------------------------------------------------------------------- 150°C Storage Temperature Range ---------------------------------------------------------------------------------------- −65°C to 150°C ESD Susceptibility (Note 2) HBM (Human Body Mode) ------------------------------------------------------------------------------------------ 2kV MM (Machine Mode) -------------------------------------------------------------------------------------------------- 200V
Recommended Operating Conditions
(Note 3)
Supply Input Voltage, VCC ------------------------------------------------------------------------------------------- 3.8V to 13.5V Enable Voltage --------------------------------------------------------------------------------------------------------- 0V to 5.5V Junction Temperature Range ---------------------------------------------------------------------------------------- −40°C to 125°C Ambient Temperature Range ---------------------------------------------------------------------------------------- −40°C to 85°C
Electrical Characteristics
(VCC = 5V/12V, TA = 25°C, unless otherwise specified)
Parameter V CC O peration Voltage Range P OR Threshold P OR Hysteresis V CC S upply Current D river Source Current D river Sink Current R eference Voltage (V FB) R eference Line Regulation (V FB ) A mplifier Voltage Gain P SRR at 100Hz, No Load P ower Good R ising Threshold H ysteresis S ink Capability D elay Time Falling Delay
Symbol
Test Conditions VCC I nput Range VCC R ising VCC Falling VCC = 1 2V VCC = 1 2V, VDRI = 6V VCC = 1 2V, VDRI = 6V VCC = 1 2V, VDRI = 5V VCC = 4.5V to 15V VCC = 1 2V, No Load VCC = 1 2V, No Load VCC = 1 2V VCC = 1 2V VCC = 1 2V @ 1mA VCC = 1 2V VCC = 1 2V
Min 3.8 3.15 0.1 -5 5 0.784 --50
Typ -3.4 0.2 0.3 --0.8 3 70 --
Max 13.5 3.65 0.3 0.8 --0.816 6 ---
Units V V V mA mA mA V mV dB dB
85 --1 --
90 15 0.2 3 15
95 -0.4 10 20
% % V ms us
To be Continued
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RT9024
Parameter C hip Enable E N Rising Threshold E N Hysteresis S tandby Current
Preliminary
Test Conditions VCC = 1 2V VCC = 1 2V VCC = 1 2V, VEN = 0V M in ---Typ 0.7 30 -Max 1 -5 Units V mV uA
Note 1. Stresses listed as the above “ Absolute Maximum Ratings” may cause permanent damage to the device. These are for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. Note 2. Devices are ESD sensitive. Handling precaution recommended. Note 3. The device is not guaranteed to function outside its operating conditions. Note 4. θJA i s measured in the natural convection at T A = 25 °C on a low effective thermal conductivity test board of JEDEC 51-3 thermal measurement standard.
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Preliminary Typical Operating Characteristics
Quiescent Current vs. Temperature
0.50
RT9024
Feedback Voltage vs. Temperature
0.9
Refer to Test Circuit Figure 1
0.48
0.45 0.43 0.40 0.38 0.35 0.33 0.30 -50 -25 0 25 50 75 100
0.85
0.8
0.75
VIN = 1.5V, VCC = 12V, RPGOOD = 100k CIN = COUT = 100uF, R1 = 1k, R2 = 2k
VIN = 1.5V, VCC = 12V, RPGOOD = 100k CIN = COUT = 100uF, R1 = 1k, R2 = 2k
0.7 -50 -25 0 25 50 75 100
125
125
Temperature (°C)
Temperature (°C)
DRI Source Current vs. Temperature
60
DRI Sink Current vs. Temperature
30
Refer to Test Circuit Figure 2
DRI Source Current (mA)
DRI Sink Current (mA)
55
27 24 21 18 15
50
45
40
VFB = 1V, VCC = 12V, VDRI = 6V
35 -50 -25 0 25 50 75 100 125
VFB = 0.6V, VCC = 12V, VDRI = 6V
12 -50 -25 0 25 50 75 100 125
Temperature (°C)
Temperature (°C)
Sink Current vs. DRI Voltage DRI Sink Current vs. DRI Voltage
25
4
PGOOD Delay Time vs. Temperature
Refer to Test Circuit Figure 2 Refer to Test Circuit Figure 1
50 75 100 125
PGOOD Delay Time (ms)
20
3.5
VIN = 1.5V, VCC = 12V RPGOOD = 100k R1 = 1k, R2 = 2k
Sink Current (mA)
15
3
10
2.5
5
2
TA = 25°C
0 0 0.5 1 1.5 2 2.5 3
1.5 -50 -25 0 25
DRI Voltage (V)
Temperature (°C)
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Refer to Test Circuit Figure 2
Refer to Test Circuit Figure 1
Quiescent Current (mA)
Feedback Voltage (V)
RT9024
PGOOD Delay Time
Preliminary
PGOOD Delay Time
Refer to Test Circuit Figure 1 Refer to Test Circuit Figure 1 Refer to Test Circuit Figure 1 Refer to Test Circuit Figure 1
VCC = 12V, ILOAD = 1A CIN = COUT = 100uF
VCC = 12V, CIN = COUT = 100uF, ILOAD = 100mA
V OUT ILoad (A) VPGOOD
V OUT VPGOOD
VEN (V)
VEN (V)
Time (500us/Div)
Time (500us/Div)
PGOOD Off
Refer to Test Circuit Figure 1
V OUT
Enable Threshold Voltage vs. Temperature
1
Enable Threshold Voltage (V)
VCC = 12V CIN = COUT = 100uF
0.95 0.9 0.85 0.8 0.75 0.7 0.65 0.6
VIN = 1.5V, VCC = 12V, RPGOOD = 100kΩ CIN = COUT = 100uF, R1 = 1k, R2 = 2k Turn on
ILoad (A)
Turn off
VPGOOD VEN (V)
Time (50us/Div)
-50
-25
0
25
50
75
100
125
Temperature (°C)
Load Transient Response
Refer to Test Circuit Figure 1 FB Voltage Deviation (mV)
VIN = 2.5V, VOUT = 1.2V CIN = COUT = 100uF 20 0 -20
Line Transient Response
FB Voltage Deviation (mV)
VIN = 1.5V to 2.5V, ILOAD = 100mA CIN = 2.2uF, COUT = 100uF 10 0 -10
5 0
Input Voltage Deviation (V)
Load Current(A)
2.5 1.5
Time (250us/Div)
Time (100us/Div)
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DS9024-01 March 2007
Preliminary Application Information
Capacitors Selection Careful selection of the external capacitors for RT9024 is highly recommended in order to remain high stability and performance. Regarding the supply voltage capacitor, connecting a capacitor which is ≥ 1μF between VCC and ground is a must. The capacitor improves the supply voltage stability for proper operation. Regarding the input capacitor, connecting a capacitor which ≥ 100μF between VIN and ground is recommended to increase stability. With large value of capacitance could result in better performance for both PSRR and line transient response. When driving external pass element, connecting a capacitor ≥ 1 00 μ F between V OUT and ground is recommended for stability. With larger capacitance can reduce noise and improve load transient response and PSRR. Output Voltage Setting The RT9024 develops a 0.8V reference voltage; especially suitable for low voltage application. As shown in application circuit, the output voltage could easy set the output voltage by R1 & R2 divider resistor. Power Good Function The RT9024 has the power good function with delay. The power good output is an open drain output. Connect a 100kΩ pull up resistor to VOUT to obtain an output voltage. When the output voltage arrives 90% of normal value. PGOOD will become active and be pulled high by external circuits with typically 3ms delay. Chip Enable Operation Pull the EN pin low to drive the device into shutdown mode. During shutdown mode, the standby current drops to 5μA(MAX). The external capacitor and load current determine the output voltage decay rate. Drive the EN pin high to turn on the device again. MOSFET Selection
RT9024
The RT9024 are designed to driver external N-MOSFET pass element. MOSFET selection criteria include threshold voltage VGS (VTH), maximum continuous drain current ID, on-resistance RDS(ON) ,maximum drain-tosource voltage VDS and package thermal resistance θ(JA). The most critical specification is the MOSFET RDS(ON). Calculate the required RDS(ON) from the following formula: V -V N − MOSFET RDS(ON) = IN OUT ILOAD For example, the MOSFET operate up to 2A when the input voltage is 1.5V and set the output voltage is 1.2V, R ON = ( 1.5V-1.2V) / 2A = 150m Ω , the MOSFET's RON must be lower than 150m Ω. Philip PHD3055E MOSFET with an RDS(ON) of 120mΩ(typ.) is a suitable solution. The power dissipation is calculate as : PD = (VIN − VOUT) x ILOAD The thermal resistance from junction to ambient θ(JA) is : (T − T ) θ (JA) = J A PD In this example, PD = (1.5V − 1.2V) x 2A = 0.6W. The PHD3055E's θ(JA) is 75°C/W for its D-PAK package, which translates to a 45°C temperature rise above ambient. The package provides exposed backsides that directly transfer heat to the PCB board. PNP Transistor Selection The RT9024 could driver the PNP transistor to sink output current. PNP transistor selection criteria include DC current gain hFE, threshold voltage VEB, collector-emitter voltage VEN, maximum continues collector current IC, package thermal resistance θ(JA). For example, the PNP transistor operates sink current up to 0.5A when the input voltage is 1.5V and set the output voltage is 1.2V. As show in Figure 3. A KSB772 PNP transistor, the VEN = 1.2V, VBE = -1V, IC = 0.5A, IB = 0.5/ 160 ≥ 3.125mA, when the DRI pin voltage is 0.2V could sink 6.8mA(MAX) is a close match.
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RT9024
VIN
Preliminary
Sink Current vs. DRI Voltage DRI Sink Current vs. DRI Voltage
25
PGOOD
20
Q1
VCC
VCC Ccc GND
DRI PGOOD RT9024 FB Q2 RPGOOD
Sink Current (mA)
CIN
15
VOUT R1 COUT
Chip Enable
EN
10
5
R2
TA = 25°C
0 0 0.5 1 1.5 2 2.5 3
Figure 3
DRI Voltage (V)
Figure 4 Layout Considerations There are three critical layout considerations. One is the divider resistors should be located to RT9024 as possible to avoid inducing any noise. The second is capacitors place. The CIN and COUT have to put at near the N-MOSFET for improve performance. The third is the copper area for pass element. We have to consider when the pass element operating under high power situation that could rise the junction temperature. In addition to the package thermal resistance limit, we could add the copper area to improve the power dissipation. As show in Figure 5 and Figure 6.
VIN
VIN
PGOOD CIN
+
VCC
VCC Ccc GND
DRI PGOOD RT9024 FB RPGOOD
Q1 VOUT
GND
Chip Enable
EN
VCC
R1 COUT
+
PGOOD VOUT EN FB
+
R2
GND
Figure 5
Figure 6
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P reliminary Outline Dimension
RT9024
H D L C B
b A A1 e
Symbol A A1 B b C D e H L
Dimensions In Millimeters Min 0.889 0.000 1.397 0.250 2.591 2.692 0.838 0.080 0.300 Max 1.295 0.152 1.803 0.560 2.997 3.099 1.041 0.254 0.610
Dimensions In Inches Min 0.031 0.000 0.055 0.010 0.102 0.106 0.033 0.003 0.012 Max 0.051 0.006 0.071 0.022 0.118 0.122 0.041 0.010 0.024
SOT-23-6 Surface Mount Package
Richtek Technology Corporation
Headquarter 5F, No. 20, Taiyuen Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)5526789 Fax: (8863)5526611
Richtek Technology Corporation
Taipei Office (Marketing) 8F, No. 137, Lane 235, Paochiao Road, Hsintien City Taipei County, Taiwan, R.O.C. Tel: (8862)89191466 Fax: (8862)89191465 Email: marketing@richtek.com
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