®
RT9089A
DDR Termination Regulator
General Description
Features
The RT9089A is a sink/source tracking termination
regulator. It is specifically designed for low-cost and lowexternal component count systems. The RT9089A
possesses a high speed operating amplifier that provides
fast load transient response and only requires a minimum
10μF ceramic output capacitor. The RT9089A supports
remote sensing functions and all features required to power
the DDRI/DDRII/DDRIII/DDRIV/LPDDRII/LPDDRIII VTT bus
termination according to the JEDEC specification.
The RT9089A is available in the thermal efficient package,
WDFN-10L 2x2.
VIN Input Voltage Range : 1.1V to 3.5V
VCNTL Input Voltage Range : 2.9V to 5.5V
Support Ceramic Capacitors
10mA Source/Sink Reference Output
Meet DDRI, DDRII JEDEC Spec
Support DDRIII, DDRIV, LPDDRII and LPDDRIII
Applications
Soft-Start Function
UVLO and OCP Protection
Thermal Shutdown
Applications
Ordering Information
RT9089A
Notebook/Desktop/Server
Telecom/Datacom, GSM Base Station, LCD-TV/PDPTV, Copier/Printer, Set-Top Box
Marking Information
Pin 1 Orientation***
(2) : Quadrant 2, Follow EIA-481-D
2N : Product Code
Package Type
QW : WDFN-10L 2x2 (W-Type)
2NW
Lead Plating System
G : Green (Halogen Free and Pb Free)
W : Date Code
Pin Configuration
Note :
VDDQSNS
VIN
VOUT
PGND
SENSE
Richtek products are :
RoHS compliant and compatible with the current require-
1
2
3
4
5
PAD
(TOP VIEW)
***Empty means Pin1 orientation is Quadrant 1
11
10
9
8
7
6
VCNTL
S5
GND
S3
REFOUT
ments of IPC/JEDEC J-STD-020.
WDFN-10L 2x2
Suitable for use in SnPb or Pb-free soldering processes.
Simplified Application Circuit
RT9089A
VIN
VCNTL
VIN
VCNTL
C4
C3
VDDQSNS
S5
REFOUT
REFOUT
C3
S3
S5
VOUT
SENSE
VOUT
C5
PGND
S3
GND
Copyright © 2020 Richtek Technology Corporation. All rights reserved.
DS9089A-05 February 2020
is a registered trademark of Richtek Technology Corporation.
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1
RT9089A
Functional Pin Description
Pin No.
Pin Name
Pin Function
1
VDDQSNS
Reference input.
2
VIN
Power input of the regulator.
3
VOUT
Power output of the regulator.
4
PGND
Power ground of the regulator.
5
SENSE
Voltage sense input for the regulator. Connect to positive terminal of the output
capacitor or the load.
6
REFOUT
Reference output. Connect to GND through a 0.1μF ceramic capacitor.
7
S3
S3 signal input.
8
GND
Analog ground. Connect to negative terminal of the output capacitor.
9
S5
S5 signal input.
10
VCNTL
Control voltage input. Connect this pin to the 3.3V or 5V power supply. A 4.7μF
ceramic decoupling capacitor is required.
Exposed pad. The exposed pad is internally unconnected and must be
soldered to a large PGND plane. Connect this PGND plane to other layers with
thermal vias to help dissipate heat from the device.
11 (Exposed Pad) PAD
Functional Block Diagram
REFOUT
VIN
S3
OTP
+
OCP
-
S5
VCNTL
UVLO
VDDQSNS
+
-
SENSE
GND
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2
EN_VTT
VOUT
+
+
OCP
PGND
is a registered trademark of Richtek Technology Corporation.
DS9089A-05 February 2020
RT9089A
Operation
The RT9089A is a linear sink/source DDR termination
regulator with current capability up to 2A. The RT9089A
builds in a high-side N-MOSFET which provides current
sourcing and a low-side N-MOSFET which provides current
sinking. All the control circuits are supplied by the power
VCNTL. In normal operation, the error amplifier OP adjusts
the gate driving voltage of the power MOSFET to achieve
SENSE voltage well tracking the VDDQSNS/2 voltage.
Thermal Protection
Both the high-side and low-side power MOSFETs will be
turned off when the junction temperature is higher than
typically 160°C, and be released to normal operation when
junction temperature falls below 120°C typically.
Power State Control
The input pins S3 and S5 of RT9089A, provide simple
control of the power state. Table 1 describes S3/S5
terminal logic state and corresponding state of REFOUT/
VOUT outputs. VOUT is turn-off and discharged to GND
in state S3. When both S5 and S3 pins are LOW, the
power state is set to S4/S5. In S4/S5 state, all the outputs
are turn-off and discharged to GND.
Both the source and sink currents are detected by the
internal sensing resistor, and the OCP function will work
to limit the current to a designed value when overload
happens. Furthermore, the current will be folded back to
be one half if VOUT is out of the power good window.
Buffer
This function provides REFOUT output level which is equal
to VDDQSNS/2 with 10mA source/sink current capability.
Control Logic
This block includes VCNTL UVLO, VDDQSNS UVLO and
Enable/Disable functions, and provides logic control to
the whole chip.
Table 1. S3 and S5 Control Table
STATE
S3
S5
REFOUT
VOUT
S0
HI
HI
ON
ON
S3
LO
HI
ON
OFF (Discharge)
S4/S5
LO
LO
OFF (Discharge)
OFF (Discharge)
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RT9089A
Absolute Maximum Ratings
(Note 1)
Supply Voltage, VIN, VCNTL ------------------------------------------------------------------------------------------Input Voltage, S3, VDDQSNS, SENSE, S5 -----------------------------------------------------------------------Output Voltage, VOUT, REFOUT -------------------------------------------------------------------------------------Power Dissipation, PD @ TA = 25°C
WDFN-10L 2x2 ------------------------------------------------------------------------------------------------------------Package Thermal Resistance (Note 2)
WDFN-10L 2x2, θJA ------------------------------------------------------------------------------------------------------WDFN-10L 2x2, θJC ------------------------------------------------------------------------------------------------------Lead Temperature (Soldering, 10 sec.) ------------------------------------------------------------------------------Junction Temperature ----------------------------------------------------------------------------------------------------Storage Temperature Range -------------------------------------------------------------------------------------------ESD Susceptibility (Note 3)
HBM (Human Body Model) ----------------------------------------------------------------------------------------------
Recommended Operating Conditions
−0.3V to 6V
−0.3V to 6V
−0.3V to 6V
1.25W
80°C/W
7°C/W
260°C
150°C
−65°C to 150°C
2kV
(Note 4)
Control Input Voltage, VCNTL -----------------------------------------------------------------------------------------Supply Input Voltage, VIN ----------------------------------------------------------------------------------------------Junction Temperature Range -------------------------------------------------------------------------------------------Ambient Temperature Range --------------------------------------------------------------------------------------------
2.9V to 5.5V
1.1V to 3.5V
−40°C to 125°C
−40°C to 85°C
Electrical Characteristics
(VIN = VVDDQSNS = 1.5V, VCNTL = 3.3V, VSENSE = 0.75V, COUT = 10μF x 1, TA = 25°C, unless otherwise specified)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
VS3 = VCNTL, VS5 = VCNTL, no load
--
0.7
1
mA
VS3 = 0V, VS5 = 0V, no load
--
65
80
μA
VS3 = 0V, VS5 = VCNTL, no load
--
200
400
μA
Supply Current
VCNTL Supply Current
IVCNTL
VCNTL Shutdown
Current
ISHDN_VCNTL
VIN Supply Current
IVIN
VS3 = VCNTL, VS5 = VCNTL, no load
--
1
50
μA
VIN Shutdown Current
ISHDN_VIN
VS3 = 0V, VS5 = 0V, no load
--
0.1
50
μA
VIN = 1.5V, VVDDQSNS = 1.5V,
IOUT = 0A
--
0.75
--
V
VIN = 1.35V, VVDDQSNS = 1.35V,
IOUT = 0A
--
0.675
--
V
VIN = 1.2V, VVDDQSNS = 1.2V,
IOUT = 0A
--
0.6
--
V
IOUT = ±2A, VIN = 1.5V,
VREFOUT = 0.75V
−25
--
25
IOUT = ±2A, VIN = 1.35V,
VREFOUT = 0.675V
−25
--
25
IOUT = ±2A, VIN = 1.2V,
VREFOUT = 0.6V
−25
--
25
Output
VOUT Output Voltage
VOUT Output Voltage
Offset
VOUT
VOUT_OS
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DS9089A-05 February 2020
RT9089A
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
VOUT Source Current Limit
ILIM_VOUT_SR
VOUT in PGOOD window
2
--
--
A
VOUT Sink Current Limit
ILIM_VOUT_SK
VOUT in PGOOD window
2
--
--
A
VOUT Discharge
Resistance
RDISCHARGE
VVDDQSNS = 0V, VOUT = 0.3V,
VS3 = 0V
--
18
25
Ω
VDDQSNS Input Current
IVDDQSNS
VVDDQSNS = 1.8V
--
30
--
μA
VDDQSNS Voltage Range
VVDDQSNS
0.5
--
1.8
V
−10mA < IREFOUT < 10mA,
VVDDQSNS = 1.5V
−15
--
15
−10mA < IREFOUT < 10mA,
VVDDQSNS = 1.35V
−15
--
15
−10mA < IREFOUT < 10mA,
VVDDQSNS = 1.2V
−12
--
12
ILIM_REFOUT_SR
VREFOUT = 0V
10
40
--
mA
ILIM_REFOUT_SK
VREFOUT = VDDQSNS / 2 + 1V
10
40
--
mA
Rising
2.5
2.7
2.85
V
--
120
--
mV
1.7
--
--
--
--
0.3
Shutdown temperature
--
160
--
Hysteresis
--
15
--
VDDQSNS and REFOUT
REFOUT Voltage Tolerance
to VVDDQSNS
REFOUT Source Current
Limit
REFOUT Sink Current Limit
VTOL_REFOUT
mV
UVLO/S3/S5
UVLO Threshold
S3/S5 Input
Voltage
VUVLO_VCNTL
Hysteresis
Logic-High VIN_H
Logic-Low
VIN_L
V
Thermal Shutdown
Thermal Shutdown
Threshold
TSD
°C
Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in
the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may
affect device reliability.
Note 2. θJA is measured at TA = 25°C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. θJC is
measured at the exposed pad of the package.
Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
Copyright © 2020 Richtek Technology Corporation. All rights reserved.
DS9089A-05 February 2020
is a registered trademark of Richtek Technology Corporation.
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5
RT9089A
Typical Application Circuit
VIN
2
C1
10µF x 2
1
VIN
RT9089A
10
VCNTL
C4
4.7µF
VDDQSNS
S5
6
REFOUT
C3
0.1µF
S3
7
REFOUT
S3
9
VOUT 3
SENSE 5
4
PGND
VCNTL
S5
VOUT
C5
10µF x 1
GND
8
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is a registered trademark of Richtek Technology Corporation.
DS9089A-05 February 2020
RT9089A
Typical Operating Characteristics
REFOUT Voltage vs. Temperature
1.0
0.9
0.9
Output Voltage (V)
Output Voltage (V)
Output Voltage vs. Temperature
1.0
0.8
0.7
0.6
0.8
0.7
0.6
VCNTL = 3.3V,
VIN = VDDQSNS = 1.5V, VOUT = 0.75V
VCNTL = 3.3V,
VIN = VDDQSNS = 1.5V, VOUT = 0.75V
0.5
0.5
-50
-25
0
25
50
75
100
125
-50
-25
0
Temperature (°C)
50
75
100
125
VCNTL Shutdown Current vs. Temperature
VCNTL Supply Current vs. Temperature
500
350
480
460
440
VCNTL = 5V
420
400
380
360
VCNTL = 3.3V
340
320
VIN = VDDQSNS = 1.5V, VOUT = 0.75V
VCNTL Shutdown Current (μA)1
VCNTL Supply Current (μA)1
25
Temperature (°C)
300
300
250
VCNTL = 5V
200
VCNTL = 3.3V
150
100
VIN = VDDQSNS = 1.5V, VOUT = 0.75V
50
-50
-25
0
25
50
75
100
125
-50
-25
0
Temperature (°C)
25
50
75
100
125
Temperature (°C)
UVLO vs. Temperature
Sourcing Current Limit vs. Temperature
3.0
4.0
2.9
3.5
2.8
Rising
Current Limit (A)
UVLO (V)
2.7
2.6
2.5
Falling
2.4
2.3
2.2
VIN = VDDQSNS = 1.5V,
S3 = 2V, VOUT = 0.75V
2.1
2.0
3.0
2.5
2.0
1.5
VCNTL = 3.3V,
VIN = VDDQSNS = 1.5V, VOUT = 0.75V
1.0
-50
-25
0
25
50
75
100
Temperature (°C)
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DS9089A-05 February 2020
125
-50
-25
0
25
50
75
100
125
Temperature (°C)
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RT9089A
Power On from S3
Sinking Current Limit vs. Temperature
4.0
Current Limit (A)
3.5
S3
(2V/Div)
3.0
VOUT
(0.5V/Div)
2.5
2.0
IOUT
(1A/Div)
1.5
VCNTL = 3.3V,
VIN = VDDQSNS = 1.5V, VOUT = 0.75V
VREFOUT
(1V/Div)
VCNTL = 3.3V, VIN = VDDQSNS = 1.5V,
VOUT = 0.75V, IOUT = 1.5A
1.0
-50
-25
0
25
50
75
100
Time (100μs/Div)
125
Temperature (°C)
0.75VOUT @ 1.5A Transient Response
Power Off from S3
S3
(2V/Div)
VOUT
(20mV/Div)
VOUT
(0.5V/Div)
IOUT
(1A/Div)
IOUT
(1A/Div)
VREFOUT
(1V/Div)
VCNTL = 3.3V, VIN = VDDQSNS = 1.5V,
VOUT = 0.75V, IOUT = 1.5A
Source, VIN = 1.5V
Time (500μs/Div)
Time (10μs/Div)
0.75VOUT @ 1.5A Transient Response
VOUT
(20mV/Div)
IOUT
(1A/Div)
Sink, VIN = 1.5V
Time (500μs/Div)
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is a registered trademark of Richtek Technology Corporation.
DS9089A-05 February 2020
RT9089A
Application Information
Capacitor Selection
Good bypassing is recommended from VIN to GND to help
improve AC performance. A 10μF or greater input capacitor
placed as close as possible to the IC is recommended.
The input capacitor must be located at a distance of less
than 0.5 inches from the VIN pin of the IC.
The 1μF ceramic capacitor added close to the VCNTL pin
should be kept away from any parasitic impedance from
the supply power. For stable operation, the total
capacitance of the ceramic capacitor at the VOUT output
terminal must be larger than 10μF. The RT9089A is
designed specifically to work with low ESR ceramic output
capacitor in space saving and performance consideration.
Larger output capacitance can reduce the noise and
improve load transient response, stability and PSRR. The
output capacitor should be located near the VOUT output
terminal pin as close as possible.
80°C/W on a standard JEDEC 51-7 four-layer thermal test
board. The maximum power dissipation at TA = 25°C can
be calculated by the following formula :
P D(MAX) = (125°C − 25°C) / (80°C/W) = 1.25W for
WDFN-10L 2x2 package
The maximum power dissipation depends on the operating
ambient temperature for fixed T J(MAX) and thermal
resistance, θJA. The derating curve in Figure 1 allows the
designer to see the effect of rising ambient temperature
on the maximum power dissipation.
2.0
Maximum Power Dissipation (W)1
The RT9089A is a 2A sink/source tracking termination
regulator. It is specifically designed for low-cost and lowexternal component count system such as notebook PC
applications. The RT9089A possesses a high speed
operating amplifier that provides fast load transient response
and only requires two 10μF ceramic input capacitor and a
10μF ceramic output capacitors.
Four-Layer PCB
1.5
1.0
0.5
0.0
0
25
50
75
100
125
Ambient Temperature (°C)
Figure 1. Derating Curve of Maximum Power Dissipation
Thermal Considerations
For continuous operation, do not exceed absolute
maximum junction temperature. The maximum power
dissipation depends on the thermal resistance of the IC
package, PCB layout, rate of surrounding airflow, and
difference between junction and ambient temperature. The
maximum power dissipation can be calculated by the
following formula :
PD(MAX) = (TJ(MAX) − TA) / θJA
where TJ(MAX) is the maximum junction temperature, TA is
the ambient temperature, and θJA is the junction to ambient
thermal resistance.
For recommended operating condition specifications, the
maximum junction temperature is 125°C. The junction to
ambient thermal resistance, θJA, is layout dependent. For
WDFN-10L 2x2 package, the thermal resistance, θJA, is
Copyright © 2020 Richtek Technology Corporation. All rights reserved.
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9
RT9089A
Outline Dimension
2
1
2
1
DETAIL A
Pin #1 ID and Tie Bar Mark Options
Note : The configuration of the Pin #1 identifier is optional,
but must be located within the zone indicated.
Symbol
Dimensions In Millimeters
Dimensions In Inches
Min
Max
Min
Max
A
0.700
0.800
0.028
0.031
A1
0.000
0.050
0.000
0.002
A3
0.175
0.250
0.007
0.010
b
0.150
0.250
0.006
0.010
D
1.900
2.100
0.075
0.083
D2
1.450
1.550
0.057
0.061
E
1.900
2.100
0.075
0.083
E2
0.850
0.950
0.033
0.037
e
L
0.400
0.250
0.016
0.350
0.010
0.014
W-Type 10L DFN 2x2 Package
Richtek Technology Corporation
14F, No. 8, Tai Yuen 1st Street, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: (8863)5526789
Richtek products are sold by description only. Customers should obtain the latest relevant information and data sheets before placing orders and should verify
that such information is current and complete. Richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek
product. Information furnished by Richtek is believed to be accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use;
nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent
or patent rights of Richtek or its subsidiaries.
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DS9089A-05 February 2020
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