RT9116GQW

® RT9116 10W Stereo Class-D Speaker Driver Amplifier General Description Features The RT9116 is a 10W per channel, high efficiency Class D stereo audio amplifier for driving bridge tied load (BTL) speakers. The RT9116 can drive stereo speakers with load as low as 4Ω. Its high efficiency eliminates the need for an extra heat sink when playing music. The gain of the amplifier can be controlled by gain select pins. The outputs are fully protected against shorts to GND, PVCC, and output to output with an auto recovery feature and monitored output.     The RT9116 is available in the WQFN-28L 4x5 package.  Ordering Information RT9116   Lead Plating System G : Green (Halogen Free and Pb Free)   Note : THD +N Ω Load, 16V Supply at 10%  15W / CH for an 8Ω THD +N  90% Efficiency Eliminates Need for Heat Sink DC Detect Protection Filter-Less Operation Over-Temperature Protection (OTP) with Auto Recovery Option Surface Mount 28-Lead WQFN Package Applications  Package Type QW : WQFN-28L 4x5 (W-Type) 8V to 17V Input Supply Range  10W / CH for an 8Ω Ω Load, 13V Supply at 10% LCD-TV Monitors Home Audio Amusement Equipment Electronic Music Equipment Richtek products are :  RoHS compliant and compatible with the current require- Pin Configuration ments of IPC/JEDEC J-STD-020. (TOP VIEW) Suitable for use in SnPb or Pb-free soldering processes. EN AVCC SR_CTRL PLIMIT GAIN BSTPL  Marking Information 0J= : Product Code 0J=YM DNN YMDNN : Date Code 28 27 26 25 24 23 INPL INNL INNR INPR GVDD AVSS NC NC 1 22 2 21 3 20 4 5 6 7 19 PVSS 18 17 29 8 16 15 VOUTPL PVDDL VOUTNL BSTNL BSTNR VOUTNR PVDDR VOUTPR AVSS AVSS NC NC GVDD2 BSTPR 9 10 11 12 13 14 WQFN-28L 4x5 Copyright © 2016 Richtek Technology Corporation. All rights reserved. DS9116-00 November 2016 is a registered trademark of Richtek Technology Corporation. www.richtek.com 1 RT9116 Typical Application Circuit PVCC RT9116 21 PVDDL 0.1µF 29 (Exposed Pad) 100µF BSTPL 0.22µF PVSS 0.1µF 100µF 23 VOUTPL Bead 22 16 PVDDR 5 GVDD 1µF 13 GVDD2 25 PLIMIT 2.2nF BSTNL 0.22µF Bead VOUTNL 20 0.1µF R/NC 19 BSTPR 2.2nF 14 0.22µF 26 SR_CTRL 0.1µF 150k Bead VOUTPR 15 2.2nF Audio Source 1µF 1 1µF 2 1µF 3 1µF 4 INPL INNL BSTNR 18 0.22µF VOUTNR 17 Bead 2.2nF INNR INPR PVCC 100k 28 Control System 100k EN AVCC 27 0.1µF 10 PVCC 1µF 24 GAIN AVSS 6, 9, 10 1k Note : When pin GAIN connect (a) 100kΩ to PVCC, SPK gain = 31dB; (b) 1kΩ to GND, SPK gain = 26dB Copyright © 2016 Richtek Technology Corporation. All rights reserved. www.richtek.com 2 is a registered trademark of Richtek Technology Corporation. DS9116-00 November 2016 RT9116 Functional Pin Description Pin No. Pin Name Pin Function 1 INPL Positive audio input for left channel. 2 INNL Negative audio input for left channel. 3 INNR Negative audio input for right channel. 4 INPR Positive audio input for right channel. 5 GVDD High-side FET gate drive supply. 6, 9, 10 AVSS Analog ground. NC No internal connection. 13 GVDD2 Reference voltage from GVDD. 14 BSTPR Bootstrap I/O for right channel, positive high-side MOSFET. 15 VOUTPR Class-D H-Bridge positive output for right channel. 16 PVDDR Power supply input for right channel H-Bridge. Right channel and left channel power supply inputs are connected internally. 17 VOUTNR Class-D H-Bridge negative output for right channel. 18 BSTNR Bootstrap I/O for right channel, negative high-side MOSFET. 19 BSTNL Bootstrap I/O for left channel, negative high-side MOSFET. 20 VOUTNL Class-D H-Bridge negative output for left channel. 21 PVDDL Power supply input for left channel H-Bridge. Right channel and left channel power supply inputs are connected internally. 22 VOUTPL Class-D H-Bridge positive output for left channel. 23 BSTPL Bootstrap I/O for left channel, positive high-side MOSFET. 24 GAIN Gain select least significant bit. 25 PLIMIT Power limit level adjustment. 26 SR_CTRL Control output stage driver slew rate 27 AVCC Analog supply input. 28 EN Chip enable (active high). 7, 8, 11, 12 29 PVSS (Exposed Pad) Power ground for power stage Copyright © 2016 Richtek Technology Corporation. All rights reserved. DS9116-00 November 2016 is a registered trademark of Richtek Technology Corporation. www.richtek.com 3 RT9116 Functional Block Diagram PVDDL BSTPL INPL OUTPL + PWM Generator - INNL OUTNL BSTNL PVDDR BSTNR OUTNR - INNR PWM Generator + BSTPR INPR OUTPR SR_CTRL PVSS GAIN PLIMIT AVCC UVP OCP OTP OVP AVSS EN GVDD2 GVDD Reference Voltage/Current Generator Control Logic Operation The RT9116 is a dual-channel 2 x 10W efficient, Class D audio power amplifier for driving bridge-tied stereo speakers. The RT9116 uses the three-level modulation (BD model) scheme that allows operation without external LC reconstruction when the amplifier is driving an inductive load. Moreover, the built-in spread spectrum modulation can efficiently reduce EMI and save the cost of the external inductor, replaced by ferrite beads. A closed-loop modulator, which enables negative error feedback, can improve THD+N and PSRR of output signals. The RT9116 offers two selectable power limit thresholds, 5W/10W under 8Ω for protecting load speakers. Though there is no requirement for power limit, the resistance connected from the PLIMIT pin to ground must be greater than 500kΩ. The RT9116 features over-current protection against output stage short-circuit conditions. When a short-circuit condition occurs, amplifier outputs will be switched to a Hi-Z state, and the short-circuit protection latch will be triggered. Once the short-circuit condition is removed, the RT9116 will be automatically recovered. The RT9116 can drive stereo speakers as low as 4Ω. The high efficiency of the RT9116, 90%, eliminates the need for an external heat sink when playing music. These two limit thresholds can be set easily by connecting two different resistors, 25kΩ/150kΩ, from the PLIMIT pin to ground. Copyright © 2016 Richtek Technology Corporation. All rights reserved. www.richtek.com 4 is a registered trademark of Richtek Technology Corporation. DS9116-00 November 2016 RT9116 Absolute Maximum Ratings            (Note 1) Supply Voltage, PVDDL, PVDDR, AVCC ----------------------------------------------------------------Input Voltage, EN, GAIN -------------------------------------------------------------------------------------Output Voltage, OUTPL,OUTPR,OUTNL,OUTNR ------------------------------------------------------Bootstrap Voltage, BSTPL,BSTPR,BSTNL,BSTNR ---------------------------------------------------Other Pins -------------------------------------------------------------------------------------------------------Power Dissipation, PD @ TA = 25°C −0.3V to 21V −0.3V to (PVDDx + 0.3V) −0.3V to (PVDDx + 0.3V) −0.3V to (PVDDx + 6V) −0.3V to (GVDD + 0.3V) WQFN-28L 4x5 ------------------------------------------------------------------------------------------------Package Thermal Resistance (Note 2) WQFN-28L 4x5, θJA -------------------------------------------------------------------------------------------WQFN-28L 4x5, θJC ------------------------------------------------------------------------------------------Lead Temperature (Soldering, 10 sec.) -------------------------------------------------------------------Junction Temperature -----------------------------------------------------------------------------------------Storage Temperature Range --------------------------------------------------------------------------------ESD Susceptibility (Note 3) HBM (Human Body Model) ----------------------------------------------------------------------------------- 3.64W Recommended Operating Conditions     27.4°C/W 2°C/W 260°C 150°C −65°C to 150°C 2kV (Note 4) Supply Input Voltage, PVDDL, PVDDR, AVCC ---------------------------------------------------------Min. SPK load in BTL mode, Rspk (BTL) ---------------------------------------------------------------Junction Temperature Range --------------------------------------------------------------------------------Ambient Temperature Range --------------------------------------------------------------------------------- 8V to 17V 4Ω −40°C to 125°C −40°C to 85°C Electrical Characteristics (PVDDx = 12V, RL = 8Ω, TA = 25°C, unless otherwise specified) Parameter Symbol Test Condition IGVDD = 2mA Min Typ Max Unit -- 5 5.5 V Gate Drive Supply Voltage VGVDD EN, Gain Input VIH : High-Level Voltage VIL : Low-Level VIH 3 -- -- V VIL -- -- 0.8 V EN, Gain Input VIH : High-Level Current VIL : Low-Level IIH EN, Gain, VI = 5V -- -- 50 A IIL EN, Gain, VI = 0.8V -- -- 10 A Output Offset Voltage Vos PVDDx = 12V, Gain = 31dB -- -- 20 mV Quiescent Current IQ PVDDx = 12V, GVDD2 = 5V, no filter and load -- 10 15 mA Shutdown Current ISD PVDDx = 12V, GVDD2 = 5V, EN = Low -- 1 1.5 mA Drain-Source On State Resistance RDS(ON) PVDDx = 12V, IO = 500mA High-side -- 250 -- Low-side -- 200 -- Gain Gain Gain = 0 25 26 27 Gain = 1 30 31 32 Copyright © 2016 Richtek Technology Corporation. All rights reserved. DS9116-00 November 2016 m dB is a registered trademark of Richtek Technology Corporation. www.richtek.com 5 RT9116 Parameter Output Integrated Noise Signal-to-Noise Ratio Output Power Total Harmonic Distortion Plus Noise Symbol Vn SNR Po THD+N Crosstalk Test Condition Min Typ Max PVDDx = 12V, Gain = 26dB, A-weighted -- 100 -- PVDDx = 12V, Gain = 31dB, A-weighted -- 200 -- PVCC = 12V, Gain = 26dB, A-weighted, THD+N = 1% -- 98 -- dB THD+N = 7%, PVCC = 11.3V, RL = 8 -- 8 -- W THD+N = 10%, PVCC = 16V, RL = 8 -- 15 -- W Po = 5W -- 0.2 -- Po = 1W -- 0.1 -- Vo = 1Vrms, Gain = 26dB, fin = 1kHz -- 70 -- dB 200mVPP ripple at 1kHz, Gain = 26dB, Inputs ac-coupled to AGND -- 70 -- dB PVDDx = 12V, fin = 1kHz Unit V % Power Supply Ripple Rejection PSRR Turn On Time tON -- 25 -- ms Turn Off Time tOFF -- 2 -- s Oscillator Frequency fOSC -- 330 -- kHz VIN 1Vrms, Plimit , 25k to GND 5 -- 6.5 VIN = 1Vrms, Plimit , 150kto GND 10 -- 13 Output Power Limit W Protection Circuitry Under-Voltage Protection Under-Voltage Protection Hysteresis Over-Voltage Protection VUVP -- 6.5 -- V VUVP -- 1 -- V VOVP -- 19 -- V Over-Voltage Protection Hysteresis VOVP -- 2 -- V Over-Temperature Protection TSD -- 170 -- C Over-Temperature Protection Hysteresis TSD -- 15 -- C SPK Over-Current Protection IOCP -- 3.5 -- A Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Note 2. θJA is measured under natural convection (still air) at TA = 25°C with the component mounted on a high effectivethermal-conductivity four-layer test board on a JEDEC 51-7 thermal measurement standard. θJC is measured at the exposed pad of the package. Note 3. Devices are ESD sensitive. Handling precaution is recommended. Note 4. The device is not guaranteed to function outside its operating conditions. Copyright © 2016 Richtek Technology Corporation. All rights reserved. www.richtek.com 6 is a registered trademark of Richtek Technology Corporation. DS9116-00 November 2016 RT9116 Typical Operating Characteristics THD+N vs. Output Power Efficiency vs. Output Power 100 20 90 10 5 RL = 8Ω RL= 6Ω RL = 4Ω 70 2 THD+N (%) Efficiency (%) 80 60 50 40 0.5 0.2 0.1 20 0.05 0 10 1 2 3 4 5 6 7 8 9 1kHz 20Hz 10kHz 0.02 PVCC = 12V, f = 1kHz, Gain = 26dB 0 0.01 10m 20m 50m 100m 200m 500m 1 10 THD+N vs. Frequency Crosstalk vs. Frequency 0 PVCC = 12V, RL = 8Ω, Gain = 26dB -10 2 -20 1 -30 0.5 0.2 0.1 0.05 0.02 0.006 20 PVCC = 12V, RL = 8Ω, Gain = 26dB, Po = 1W -40 -50 -60 -70 R to L L to R -90 -100 20 50 100 200 500 1k 2k 5k 20 10k 20k 50 100 200 500 1k 2k 5k 10k 20k Frequency (Hz) Frequency (Hz) Frequency Results Output Power vs. Supply Voltage 25.0 PVCC = 12V, RL = 8Ω, Gain = 26dB, Po = 1W RL = 8Ω, Gain = 26dB, Stereo Out 22.5 20.0 Output Power (W) dBV (dB) 10 -80 0.5W 2.5W 5W 0.01 17.5 15.0 12.5 10.0 THD+N = 10% THD+N = 1% 7.5 5.0 2.5 0.0 20 50 100 200 500 1k 2k 5k 10k 20k Frequency (Hz) Copyright © 2016 Richtek Technology Corporation. All rights reserved. DS9116-00 5 Output Power (W) 5 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 2 Output Power (W) Crosstalk (dB) THD+N (%) 1 30 10 PVCC = 12V, RL = 8Ω, Gain = 26dB November 2016 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Supply Voltage (V) is a registered trademark of Richtek Technology Corporation. www.richtek.com 7 RT9116 Application Information GVDD Supply Over-Current Protection (OCP) The GVDD is used to supply the Gate Drivers for the output full bridge transistors. Connect a 1μF capacitor from this pin to ground for good bypass. The typical GVDD output voltage is 5V. The RT9116 provides OCP function to prevent the device from damages during overload or short-circuit conditions. The current are detected by an internal sensing circuit. Once overload happens, the OCP function is designed to operate in auto-recovery mode. Amplifier Gain Setting The gain of the RT9116 amplifier can be set by one input terminals, GAIN shown as Table 1. The gain setting is realized by changing the taps on the input resistors and feedback resistors inside the amplifier. This causes the input impedance (ZI) to be dependent on the gain setting. The actual gain settings are controlled by the ratios of the resistors, so the gain variation from part-to-part is small. However, the input impedance from part-to-part at the same gain may shift by ±20% due to shifts in the actual resistance of the input resistors. Table 1. Gain Setting Amplifier GAIN (dB) Input Impedance (k) Typ Typ 0 26 20 1 31 10 GAIN EN Operation The RT9116 employs a shutdown mode operation designed to reduce supply current (ICC) to the absolute minimum level for power saving. The EN input terminal should be held high (see specification table for trip point) in normal operation. Pulling EN low causes the outputs to mute and the amplifier to enter a low current state. Leaving EN floating will cause the amplifier operation to be unpredictable. Never leave EN pin unconnected. For the best power-off pop performance, turn off the amplifier in the shutdown mode prior to removing the power supply voltage. DC Detect Protection RT9116 has circuitry which will protect the speakers from DC current which might occur due to defective capacitors on the input or shorts on the printed circuit board at the inputs. To clear the DC Detect it is necessary to cycle the PVCC supply. ADC Detect Fault is issued when the output differential duty-cycle of either channel exceeds 18% (for example, +59%, −41%) for more than 290 msec at the same polarity. This feature protects the speaker from large DC currents or AC currents less than 4Hz. To avoid nuisance faults due to the DC detect circuit, hold the SD pin low at powerup until the signals at the inputs are stable. Also, take care to match the impedance seen at the positive and negative inputs to avoid nuisance DC detect faults. Under-Voltage Protection (UVP) The RT9116 monitors the voltage on PVDD voltage threshold. When the voltage on PVDDL and PVDDR pin falls below the under voltage threshold, 7V (typ.), the UVP circuit turns off the output immediately and operates in cycle by cycle auto-recovery mode. Over-Voltage Protection (OVP) The RT9116 monitors the voltage on PVDD voltage threshold. When the voltage on PVDDL and PVDDR pin rise behind the over voltage threshold, 15V (typ.), the OVP circuit turns off the output immediately and operates in cycle by cycle auto-recovery mode. Over-Temperature Protection (OTP) The OTP prevents damage to the device when the internal die temperature exceeds 170°C. There is a ±15°C tolerance on this trip point from device to device. Once the die temperature exceeds the OTP threshold, the device enters Copyright © 2016 Richtek Technology Corporation. All rights reserved. www.richtek.com 8 is a registered trademark of Richtek Technology Corporation. DS9116-00 November 2016 RT9116 into the shutdown state and the outputs are disabled. This is not a latched fault. The thermal fault is cleared once the temperature of the die is reduced by 15°C. The device begins normal operation at this point with no external system interaction. Power-On/Off Sequence Use the following sequence to power on the device PVCC power supply ready.  Past EN = 1 (EN pin goes high) Thermal Considerations The junction temperature should never exceed the absolute maximum junction temperature TJ(MAX), listed under Absolute Maximum Ratings, to avoid permanent damage to the device. The maximum allowable power dissipation depends on the thermal resistance of the IC package, the PCB layout, the rate of surrounding airflow, and the difference between the junction and ambient temperatures. The maximum power dissipation can be calculated using the following formula : PD(MAX) = (TJ(MAX) − TA) / θJA where TJ(MAX) is the maximum junction temperature, TA is the ambient temperature, and θJA is the junction-to-ambient thermal resistance. PVCC EN Figure 1. Power On Sequence Use the following sequence to power off the device EN = 0 (EN pin goes Low) Past PVCC power supply shutdown  EN For continuous operation, the maximum operating junction temperature indicated under Recommended Operating Conditions is 125°C. The junction-to-ambient thermal resistance, θJA, is highly package dependent. For a WQFN-28L 4x5 package, the thermal resistance, θJA, is 27.4°C/W on a standard JEDEC 51-7 high effective-thermalconductivity four-layer test board. The maximum power dissipation at TA = 25°C can be calculated as below : PD(MAX) = (125°C − 25°C) / (27.4°C/W) = 3.64W for a WQFN-28L 4x5 package. PVCC Figure 2. Power Off Sequence The maximum power dissipation depends on the operating ambient temperature for the fixed TJ(MAX) and the thermal resistance, θJA. The derating curves in Figure 3 allows the designer to see the effect of rising ambient temperature on the maximum power dissipation. The voltage at the PLIMIT pin can used to limit the power to levels below that which is possible based on the supply rail. Add a resistor (Table 2) to ground set the voltage at the PLIMIT pin. Also add a 1μF capacitor from the PLIMIT pin to ground. The PLIMIT circuit sets a limit on the output Power. Table 2. Plimit Setting Resistor (k) Output Power (W) 25 5.75 150 11.5 Open MAX Maximum Power Dissipation (W)1 4.0 Power Limit Four-Layer PCB 3.6 3.2 2.8 2.4 2.0 1.6 1.2 0.8 0.4 0.0 0 25 50 75 100 125 Ambient Temperature (°C) Figure 3. Derating Curve of Maximum Power Dissipation Copyright © 2016 Richtek Technology Corporation. All rights reserved. DS9116-00 November 2016 is a registered trademark of Richtek Technology Corporation. www.richtek.com 9 RT9116 LINN, RINP & RINN) and (OUTPL & OUTNL, OUTPR & OUTNR) should be kept equal width and length respectively. The thermal pad must be soldered to the PCB for proper thermal performance and optimal reliability. The dimensions of the thermal pad and thermal land should be larger for application. The vias should connect to a solid copper plane, either on an internal layer or on the bottom layer of the PCB. Layout Considerations For the best performance of the RT9116, the below PCB layout guidelines must be strictly followed. Place the decoupling capacitors as close as possible to the AVCC, PVDDL, PVDDR and GND pins. For achieving a good quality, consider adding a small, good performance low ESR ceramic capacitor between 220pF and 1000pF and a larger mid-frequency capacitor between 0.1μF and 1μF to the PVDD pins of the chip. The traces of (LINP & PVDD PVDD SR_CTRL PLIMIT GAIN PLIMIT GAIN GND BSTPL EN AVCC GND EN The decoupling capacitor (Cs) must be placed as close to the IC as possible SR_CTRL The decoupling capacitor (Cs) must be placed as close to the IC as possible CB CIN INPL VOUTPL INNL PVDDL INNR VOUTNL FB CIN Audio Input CIN FB CB CIN BSTNL INPR PVSS (Thermal Pad) tied to GND GND BSTNR AVSS VOUTNR NC PVDDR NC VOUTPR CB Cg GND The gate driver output decoupling capacitor (Cg) must be placed as close to the IC as possible GVDD FB FB CB BSTPR GVDD2 NC NC AVSS AVSS PVDD GND GND The decoupling capacitor (Cs) must be placed as close to the IC as possible Figure 4. PCB Layout Guide Copyright © 2016 Richtek Technology Corporation. All rights reserved. www.richtek.com 10 is a registered trademark of Richtek Technology Corporation. DS9116-00 November 2016 RT9116 Outline Dimension 2 1 2 1 DETAIL A Pin #1 ID and Tie Bar Mark Options Note : The configuration of the Pin #1 identifier is optional, but must be located within the zone indicated. Symbol Dimensions In Millimeters Dimensions In Inches Min Max Min Max A 0.700 0.800 0.028 0.031 A1 0.000 0.050 0.000 0.002 A3 0.175 0.250 0.007 0.010 b 0.180 0.300 0.007 0.012 D 3.900 4.100 0.154 0.161 D2 2.600 2.700 0.102 0.106 E 4.900 5.100 0.193 0.201 E2 3.600 3.700 0.142 0.146 e L 0.500 0.350 0.020 0.450 0.014 0.018 W-Type 28L QFN 4x5 Package Richtek Technology Corporation 14F, No. 8, Tai Yuen 1st Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)5526789 Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries. DS9116-00 November 2016 www.richtek.com 11