RT9232

RT9232 Programmable Frequency Synchronous Buck PWM Controller General Description The RT9232 is a single-phase synchronous buck PWM DC-DC converter controller designed to drive two N-Channel MOSFET. It provides a highly accurate, programmable output voltage precisely regulated to low voltage requirement with an internal 0.8V ± 1% reference. The RT9232 uses an external compensated, single feedback loop voltage mode PWM control for fast transient response. An oscillator with Programmable frequency (50kHz to 800kHz) reduces the external inductor and capacitor component size for saving PCB board area. The RT9232 provides fast transient response to satisfy high current output applications (up to 25A) while minimizing external components. It is suitable for highperformance graphic processors, DDR and VTT power. The RT9232 integrates complete protect functions such as Soft Start, Output Enable, UVLO(under-voltage lockout) into a small 14-pin package. Features Single IC Supply Voltage: 12V Single phase DC/DC Buck Converter with High Output Current (up to 25A ) Low Output Voltage (down to 0.8V ) High Input Voltage (up to 12V ) Operate from 12V, 5V or 3.3V Input 0.8V ± 1% Internal Reference Adaptive Non-Overlapping Gate Drivers Integrated High-Current, HV Gate Drivers External Programmable Soft Start External Programmable Frequency (Range: 50kHz to 800kHz, 200kHz Free Run ) Integrated Output Short Circuit Protection On/Off Control by Enable Pin Drives Two N-Channel MOSFET Full 0 to 100% Duty Cycle Fast Transient Response Voltage Mode PWM Control with External Feedback Loop Compensation RoHS Compliant and 100% Lead (Pb)-Free Ordering Information RT9232 Package Type S : SOP-14 Operating Temperature Range P : Pb Free with Commercial Standard G : Green (Halogen Free with Commercial Standard) Note : RichTek Pb-free and Green products are : RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020. Suitable for use in SnPb or Pb-free soldering processes. 100%matte tin (Sn) plating. Applications System (Graphic, MB) with 12V Power. Graphic Cards (AGP 8X, 4X, PCI Express*16): High-Current for High-Performance Graphic Processors (GPU, VPU) Middle Current for High-Performance Graphic Memory Power (DDR, DDR II) Low Current with Sink Capacity for High-Performance Graphic Memory Power (DDR/VTT) 3.3V to 12V Input DC-DC Regulators Low Voltage Distributed Power Supplies Pin Configurations (TOP VIEW) RT SENSE SS COMP FB EN GND 2 3 4 5 6 7 14 13 12 11 10 9 8 VCC PVCC LGATE PGND BOOT UGATE PHASE SOP-14 DS9232-06 March 2007 www.richtek.com 1 RT9232 Typical Application Circuit VCC D1 1N4148 14 13 C2 0.22uF CSS 0.1uF 3 1 VCC R3 10k R2 51k VCC PVCC UGATE SS RT PHASE LGATE PGND FB 8 12 11 5 BOOT SENSE 10 2 9 C3 1nF R5 0 C4 0.1uF R6 0 IPD06N03LA R4 3.01k + VIN 3.3V - 12V L1 1uH CE0 + 470uF C1 0.22uF R1 2.2 + + C5 0.1uF Q1 IPD09N03LA L2 2.2uH C6 10uF CE1 1000uF CE2 1000uF VOUT C8 C9 C10 + + 6 EN 7 GND 4 COMP Q2 R7 2.2 C7 1nF CE3 CE4 2200uF 510uF 22uF R9 1k R11 1k 10uF 0.1uF RT9232 C11 33pF R8 15k C12 10nF R10 562 C13 10nF Functional Pin Description No 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Pin Name RT SENSE SS COMP FB EN GND PHASE UGATE BOOT PGND LGATE PVCC VCC Pin Function Oscillator Frequency Setting Sense VIN Power Condition Soft Start Time Interval Setting Feedback Compensation Voltage Feedback Chip Enable (Active High) IC Signal Reference Ground Return Path for Upper MOSFET Upper MOSFET Gate Drive Input Supply for Upper Gate Drive Power Ground Lower MOSFET Gate Drive Input Supply for Lower Gate Drive Internal IC Supply (12V Bias) www.richtek.com 2 DS9232-06 March 2007 RT9232 Function Block Diagram VCC EN VIN Power-On POR Reset (POR) 10uA SS 0.6V + - + - SENSE 1.5V POR Soft Start and Fault Logic INHIBIT BOOT UGATE PHASE PVCC LGATE PGND Oscillator GND UV FB 0.8V Reference COMP + - EA + + + - PWM Driver Logic RT Operation Startup RT9232 initializes automatically after receiving both VCC and VIN power. Special power-on sequence is not necessary. The Power-On Reset (POR) function continually monitors input supply voltages and enable voltage. POR function monitors IC power via VCC pin and external MOSFET power via SENSE pin. Voltage on SENSE pin is a fixed voltage drop less than VIN. When voltages on VCC, SENSE, and EN pins exceed their thresholds, POR function initializes softstart operation. POR inhibits driver operation while EN pin pulls low. Transitioning EN pin high after input supply voltages ready initializes soft-start operation. Soft-Start After POR function releases soft-start operation, an internal 10uA current source charges an external capacitor on SS pin (Css) to 5V. Soft-start function clamps both COMP & FB pins to SS pin voltage & a fixed voltage drop less than SS pin voltage respectively. Thus upper MOSFET turns on at a limited duty and output current overshoot can be reduced. This method provides a rapid and controlled output voltage rise. Under Voltage Protection The under voltage protection function protects the converter from an shorted output by detecting the voltage on FB pin to monitor the output voltage. The UVP function cycles soft-start function in a hiccup mode. When output voltage lower than 75% of designated voltage, UVP function initializes soft-start cycles. The soft-start function discharges Css with 10uA current sink and disable PWM operation. Then soft-start function recharges Css and PWM operation resumes. The soft-start hiccup restarts after SS voltage fully charges to 4V if the output short event still remains. The converter is shutdown permanently after 3 times hiccup and only restarting supply voltages can enable the converter. DS9232-06 March 2007 www.richtek.com 3 RT9232 Absolute Maximum Ratings (Note 1) Supply Input Voltage, VCC, PVCC --------------------------------------------------------------------------- 15V PHASE to GND DC ------------------------------------------------------------------------------------------------------------------- −5V to 15V < 200ns ------------------------------------------------------------------------------------------------------------ −10V to 30V BOOT to PHASE ------------------------------------------------------------------------------------------------ 15V BOOT to GND DC ------------------------------------------------------------------------------------------------------------------- −0.3V to VCC+15V < 200ns ------------------------------------------------------------------------------------------------------------ −0.3V to 42V SS, FB, COMP, RT --------------------------------------------------------------------------------------------- 6V Input, Output or I/O Voltage ----------------------------------------------------------------------------------- GND−0.3V to VCC+ 0.3V Package Thermal Resistance (Note 4) SOP-14, θJA ----------------------------------------------------------------------------------------------------- 100°C/W Lead Temperature (Soldering, 10 sec.) -------------------------------------------------------------------- 260°C Junction Temperature ------------------------------------------------------------------------------------------ 150°C Storage Temperature Range ---------------------------------------------------------------------------------- −65°C to 150°C ESD Susceptibility (Note 2) HBM (Human Body Mode) ----------------------------------------------------------------------------------- 2kV MM (Machine Mode) ------------------------------------------------------------------------------------------- 200V Recommended Operating Conditions (Note 3) Supply Input Voltage, VCC ------------------------------------------------------------------------------------ 12V ±10% Supply Voltage to Drain of Upper MOSFETs, VIN ------------------------------------------------------- 3.3V, 5V to 12V ±10% Ambient Temperature Range --------------------------------------------------------------------------------- 0°C to 70°C Junction Temperature Range --------------------------------------------------------------------------------- 0°C to 125°C Electrical Characteristics (VCC = 12V, TA = 25°C, Unless otherwise specified.) Parameter Symbol VCC Supply Current Nominal Supply Current Power-On Reset (POR) VCC Rising Threshold Power On Reset Hysteresis SENSE Rising Threshold for start up VSENSE_ON Enable Input Threshold (ON) Enable Input Threshold (OFF) Oscillator Free Running Frequency Ramp Amplitude Reference Error Amplifier Reference Voltage www.richtek.com 4 Test Conditions EN=VCC, UGATE, LGATE open VSENSE = 4.5V VSENSE = 4.5V Min Typ. Max Units ICC VCC_ON -8.4 0.4 --0.8 170 3 -0.7 1.5 --200 2 0.8 -10 -2 2 -230 20 -0.808 mA V V V V V kHz % VP-P V VEN_ON VEN,_OFF fOSC VSENSE = 4.5V VSENSE = 4.5V RT9232 Variation 6k < (RT to GND) < 200k Δ VOSC VREF -20 -0.792 To be continued DS9232-06 March 2007 RT9232 Parameter Error Amplifier DC gain Gain-Bandwidth product Slew Rate Soft Start External SS Source Current PWM Controller Gate Driver Upper Drive Source Upper Drive Sink Lower Drive Source Lower Drive Sink Driving Capability Upper Drive Source Upper Drive Sink Lower Drive Source Lower Drive Sink Protection Under-Voltage Protection Under-Voltage Protection Delay FB Falling 0.5 -0.6 30 0.7 -V μs IUG_SC IUG_SK ILG_SC ILG_SK VBOOT – UGATE = 12V VUGATE – PHASE = 12V VPVCC – LGATE = 12V VLGATE – PGND = 12V ----1 1 2.4 2 ----A A A A RUG_SC RUG_SK RLG_SC RLG_SK VBOOT – PHASE = 12V VBOOT – UGATE = 1V VBOOT – PHASE = 12V VUGATE – PHASE = 1V VPVCC – LGATE = 1V VLGATE – PGND = 1V ----9 5 2.5 2.5 12 8 4 4 Ω Ω Ω Ω ISS 7 10 -μA GBW SR COMP = 10pF ---88 15 6 ---dB MHz V/μs Symbol Test Conditions Min Typ Max Units Note 1. Stresses listed as the above "Absolute Maximum Ratings" may cause permanent damage to the device. These are for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. Note 2. Devices are ESD sensitive. Handling precaution recommended. Note 3. The device is not guaranteed to function outside its operating conditions. Note 4. θJA i s measured in the natural convection at T A = 25 °C on a low effective thermal conductivity test board of JEDEC 51-3 thermal measurement standard. DS9232-06 March 2007 www.richtek.com 5 RT9232 Typical Operating Characteristics Efficient vs. Output Current 100 1000 RRT v s. Oscillator Frequency Pull high to VCC 90 Efficient (%) 70 (k Ω RRT (k )) 10 80 VIN = 3.3V VIN = 5V VIN = 12V 100 60 Pull down to GND 50 0 5 10 15 20 25 30 1 0 100 200 300 400 500 600 700 800 Output Current (A) Frequency (kHz) Dead Time Loading = 0A UGATE PHASE Loading = 0A Dead Time UGATE PHASE VGS (5V/Div) LGATE (5V/Div) VGS LGATE Time (25ns/Div) Time (25ns/Div) UVP Bootstrap Wave Form VCC = EN (2V/Div) V OUT LGATE FB (500mV/Div) PHASE UGATE UGATE (10V/Div) (5V/Div) (5V/Div) (500mV/Div) (5V/Div) SS (5V/Div) Time (20ms/Div) Time (1us/Div) www.richtek.com 6 DS9232-06 March 2007 RT9232 Power On Power On EN (2V/Div) EN (2V/Div) VOUT (500mV/Div) V OUT (500mV/Div) SS (1V/Div) IOUT (1A/Div) SS (1V/Div) COMP (500mV/Div) Time (10ms/Div) Time (10ms/Div) Power On VOUT (500mV/Div) VCC = EN (2V/Div) VOUT (500mV/Div) SS (2V/Div) Power Off UGATE (10V/Div) LGATE (10V/Div) IOUT (10A/Div) IOUT (2A/Div) Time (10ms/Div) Time (10ms/Div) Power Off VOUT (500mV/Div) Load Transient Response LGATE (10V/Div) UGATE (20V/Div) UGATE (10V/Div) IL (10A/Div) V OUT ( 2V/ LGATE (10V/Div) IL (20A/Div) Time (20us/Div) Time (200us/Div) DS9232-06 March 2007 www.richtek.com 7 RT9232 Load Transient Response IL (10A/Div) @IOUT = 30A to 1A Load Transient Response @IOUT = 1A to 30A IL (10A/Div) VOUT (500mV/Div) VOUT (500mV/Div) UGATE (20V/Div) UGATE (20V/Div) LGATE (10V/Div) LGATE (10V/Div) Time (10us/Div) Time (4us/Div) www.richtek.com 8 DS9232-06 March 2007 RT9232 Application Information The RT9232 is a single-phase synchronous buck PWM DC-DC converter controller designed to drive two N-Channel MOSFETs. It provides a highly accurate, programmable output voltage precisely regulated to low voltage requirement with an internal 0.8V ±1% reference. Initialization The RT9232 automatically initiates its softstart cycle only after VCC and VIN power and chip enabling signals are ready. There is no special power-on sequence should be took care especially while implement the chip in. The internal Power-On Reset (POR) logic continually monitors the voltage level of input power and enabling pin; in which the IC supply power is monitored via VCC pin and input power VIN is via SENSE pin. An internal current source with driving capability of 200uA causes a fixed voltage drop across the resistor connecting VIN to SENSE pin. The RT9232 internal logic will deem the input voltage ready once the voltage of SENSE pin is high than 1.5V. The preferred VIN ready level could be set by selecting an appropriate resistor RSENSE as: whichever is smaller dominates the behavior of the devices. During T0~T1, since SS is smaller than the sawtooth valley, the PWM comparator outputs low no matter what the COMP voltage is. T1~T2 During T1~T2, EA keeps COMP voltage low that makes the PWM output low. T2~T3 SSE ramps up and dominates the behavior of EA during T2~T3. EA regulates COMP appropriately so that FB ramps up along the SSE curve. The output voltage ramps up accordingly. Thus upper MOSFET turns on at a limited duty and output current overshoot can be reduced. It is noted that lower MOSFET keeps off before the upper MOSFET starts switching. This method provides smooth start up when there is residual voltage on output capacitors. The output voltage delay time and ramp up time are calculated as Equation (1) and (2) respectively. T2 − T0 = 1.2V x CSS (s) 10uA 1.6V x CSS (s) 10uA (1) RSENSE < VIN_READY − 1.5V Ω 200 μA T3 − T2 = Once all voltages of VCC, SENSE, and EN pins ramp higher than the internal specific thresholds. The internal POR logic will initialize the softstart operation then. Moreover, the POR inhibits driver operation while pulling the EN pin low. Transitioning EN pin high after input supply voltages ready to initialize soft-start operation. Soft-Start The behavior of RT9232 Soft-Start can be simply described as shown as Figure.1 below; and the Soft-Start can be sliced to several time-frames with specific operation respectively. T0~T1 (2) SSE FB EA COMP SS PWM 0.8V 5V SS The RT9232 initiates the softstart cycle as shown in Figure 1 when POR function is OK. An internal 10uA current source charges an external capacitor on SS pin (Css) to 5V. The softstart function produces an SSE signal that is equal to (SS-1.2V)/2. Error Amplifier (EA) and PWM comparator are triple-input devices. The non-inverting input DS9232-06 March 2007 SSE COMP 1V 0.8V T0 T1T2 T3 FB Figure 1. Timing diagram of softstart www.richtek.com 9 RT9232 Switching Frequency Setting The default switching frequency is 200kHz when RT pin left open. A resistor connected (RRT) from RT pin to ground increases the switching frequency as Equation (3). circuit short as shown in Figure 2. The SCP will be triggered while the POR is triggered 3 times including the 1st POR of system power on. While the SCP been triggered, the fault is latched until the VCC power is removed. (2V/Div) fOSC = 200kHz + 2.9 x 10 6 kHz (3) (RRT to GND) RRT (Ω) Conversely, connecting a pull-up resistor (RRT) from RT pin reduces the switching frequency according to Equation (4) SS (20V/Div) fOSC = 200kHz − 33 x 10 kHz (4) (RRT to VCC = 12V) RRT (Ω) 6 UGATE (2V/Div) Under Voltage Protection The under voltage protection is enabled when the RT9232 is activated and SS voltage is higher than 4V. The UVP function is specified for protecting the converter from an instant output short circuit during normal operation. The RT9232 continuously monitors the output voltage by detecting the voltage on FB pin. The UVP function is triggered and initiates the hiccup cycles when output voltage lower than 75% of designated voltage with a 30us delay. Hiccup cycle turns off both upper and lower MOSFET first. An internal 10uA current sink discharges the softstart capacitor CSS. SS pin voltage ramps down linearly. When SS pin voltage touches 0V, hiccup cycle releases and normal softstart cycle takes over. When SS voltage is higher than 4V, the UVP function is enabled again. The hiccup cycle restarts if the output short event still remains. The converter is shutdown permanently after 3 times hiccup and only restarting supply voltages can enable the converter. Note that triggering the POR function or EN will reset the hiccup counter. Make sure that VCC, EN and SENSE pin voltages are higher than their respective trip level when output short circuit occurs or the UVP function may not latch up the converter causing permanent damage to the converter. Short Circuit Protection There is a protection implemented in RT9232 for short circuit protection, the protection can significantly protect the power stage from burn-out while the congenital output www.richtek.com 10 VIN VOUT POR1 POR2 (10V/Div) POR3 Figure 2 As shown as Figure 3. The POR of the chip could be triggered by three major signal including 5VBUS which is applied for internal logic use only, 12V, and EN. The POR will be issued if all of the 3 events are true. Per RT9232 implementation, the EN is one of signals will trigger SCP, and it's possible to mal-trigger SCP while a unclear EN signals being applied. The enabling circuitry should be took care specially while implementing the EN circuit. 5VBUS 5VBUS 12V > VCC_ON EN > VEN_ON POR Figure 3 Component Selection Components should be appropriately selected to ensure stable operation, fast transient response, high efficiency, minimum BOM cost and maximum reliability. Output Inductor Selection The selection of output inductor is based on the considerations of efficiency, output power and operating frequency. For a synchronous buck converter, the ripple current of inductor (ΔIL) can be calculated as follows: DS9232-06 March 2007 RT9232 ΔIL = (VIN − VOUT) x VOUT VIN x fOSC x L (5) PUPPER = PCOND _UPPER + PSW_UPPER = IOUT x RDS(ON) x D + (8) 1 IOUT x VIN x (TRISE + TFALL ) x fOSC 2 Generally, an inductor that limits the ripple current between 20% and 50% of output current is appropriate. Make sure that the output inductor could handle the maximum output current and would not saturate over the operation temperature range. Output Capacitor Selection The output capacitors determine the output ripple voltage (ΔVOUT) and the initial voltage drop after a high slew-rate load transient. The selection of output capacitor depends on the output ripple requirement. The output ripple voltage is described as Equation (6). ΔVOUT = ΔIL x ESR + VOUT 1 x2 (1 − D) 8 fOSC x L x C OUT where TRISE and TFALL are rising and falling time of VDS of upper MOSFET respectively. RDS(ON) and QG should be simultaneously considered to minimize power loss of upper MOSFET. The power loss of lower MOSFET consists of conduction loss, reverse recovery loss of body diode, and conduction loss of body diode and is express as: PLOWER = PCOND _LOWER + PRR + PDIODE = IOUT x RDS(ON) x (1 − D) + QRR x VIN x fOSC 1 x IOUT x VF x TDIODE x fOSC 2 where TDIODE is the conducting time of lower body diode. + (9) (6) For electrolytic capacitor application, typically 90~95% of the output voltage ripple is contributed by the ESR of output capacitors. Paralleling lower ESR ceramic capacitor with the bulk capacitors could dramatically reduce the equivalent ESR and consequently the ripple voltage. Input Capacitor Selection Use mixed types of input bypass capacitors to control the input voltage ripple and switching voltage spike across the MOSFETs. The buck converter draws pulsewise current from the input capacitor during the on time of upper MOSFET. The RMS value of ripple current flowing through the input capacitor is described as: IIN(RMS) = IOUT x D x (1 − D) Special control scheme is adopted to minimize body diode conducting time. As a result, the RDS(ON) loss dominates the power loss of lower MOSFET. Use MOSFET with adequate RDS(ON) to minimize power loss and satisfy thermal requirements. Feedback Compensation Figure 4 highlights the voltage-mode control loop for a synchronous buck converter. Figure 5 shows the corresponding Bode plot. The output voltage (VOUT) is regulated to the reference voltage. The error amplifier EA output (COMP) is compared with the oscillator (OSC) sawtooth wave to provide a pulse-width modulated (PWM) wave with an amplitude of VIN at the PHASE node. The PWM wave is smoothed by the output filter (L and COUT). The modulator transfer function is the small-signal transfer function of VOUT/COMP. This function is dominated by a DC gain and the output filter (L and COUT), with a double pole break frequency at FP_LC and a zero at FZ_ESR. The DC gain of the modulator is simply the input voltage (VIN) divided by the peak-to-peak oscillator voltage ΔVOSC. The break frequency FLC and FESR are expressed as Equation (10) and (11) respectively. 1 FP_LC = (10) 2π LC OUT FZ_ESR = 1 2π x ESR x C OUT (11) (7) The input bulk capacitor must be cable of handling this ripple current. Sometime, for higher efficiency the low ESR capacitor is necessarily. Appropriate high frequency ceramic capacitors physically near the MOSFETs effectively reduce the switching voltage spikes. MOSFET Selection The selection of MOSFETs is based upon the considerations of RDS(ON), gate driving requirements, and thermal management requirements. The power loss of upper MOSFET consists of conduction loss and switching loss and is expressed as: DS9232-06 March 2007 www.richtek.com 11 RT9232 The compensation network consists of the error amplifier EA and the impedance networks ZIN and ZFB. The goal of the compensation network is to provide a closed loop transfer function with the highest DC gain, the highest 0dB crossing frequency (FC) and adequate phase margin. Typically, FC in range 1/5~1/10 of switching frequency is adequate. The higher FC is, the faster dynamic response is. A phase margin in the range of 45°C~ 60°C is desirable. The equations below relate the compensation network’s poles, zeros and gain to the components (R1, R2, R3, C1, C2, and C3) in Figure 4. FZ1 = 1 2π x R2 x C1 100 80 60 Gain (dB) FZ1 FZ2 FP1 FP2 40 20 0 -20 -40 -60 10 100 1K FLC 10K FESR 100K Modulator Gain 20LOG (R1/R2) 20LOG (VIN/ΔVOSC) Open Loop Error AMP Gain Compensation Gain Closed Loop Gain 1M 10M Frequency (Hz) (12) (13) Figure 5 Feedback Loop Design Procedure Use these guidelines for locating the poles and zeros of the compensation network: 1. Pick Gain (R2/R1) for desired 0dB crossing frequency (FC). 2. Place 1ST zero FZ1 below modulator double pole FLC (~75% FLC). FZ2 = FP1 = 1 2π x (R1 + R3) x C3 1 2π x R2 x C1 x C2 C1 + C2 (14) (15) FP2 1 = 2π x R3 x C3 VIN OSC PWM Comparator ΔVOSC + Driver L Driver PHASE COUT ESR VE/A ZFB EA + 3. Place 2ND zero FZ2 at modulator double pole FLC. 4. Place 1ST pole FZ1 at the ESR zero FZ_ESR VOUT 5. Place 2ND pole FZ2 at half the switching frequency. 6. Check gain against error amplifier open-loop gain. 7. Pick RFB for desired output voltage. 8. Estimate phase margin and repeat if necessary. Layout Consideration ZIN REF C2 C1 COMP EA + ZFB R2 C3 ZIN R3 R1 VOUT FB REF Figure 4 Layout is very important in high frequency switching converter design. If designed improperly, the PCB could radiate excessive noise and contribute to the converter instability. First, place the PWM power stage components. Mount all the power components and connections in the top layer with wide copper areas. The MOSFETs of Buck, inductor, and output capacitor should be as close to each other as possible. This can reduce the radiation of EMI due to the high frequency current loop. If the output capacitors are placed in parallel to reduce the ESR of capacitor, equal sharing ripple current should be considered. Place the input capacitor directly to the drain DS9232-06 March 2007 www.richtek.com 12 RT9232 of high-side MOSFET. The MOSFETs of linear regulator should have wide pad to dissipate the heat. In multilayer PCB, use one layer as power ground and have a separate control signal ground as the reference of the all signal. To avoid the signal ground is effect by noise and have best load regulation, it should be connected to the ground terminal of output. Furthermore, follows below guidelines can get better performance of IC: (1). The IC needs a bypassing ceramic capacitor as a R-C filter to isolate the pulse current from power stage and supply to IC, so the ceramic capacitor should be placed adjacent to the IC. (2). Place the high frequency ceramic decoupling close to the power MOSFETs. (3). The feedback part should be placed as close to IC as possible and keep away from the inductor and all noise sources. (4). The components of bootstraps should be closed to each other and close to MOSFETs. (5).The PCB trace from Ug and Lg of controller to MOSFETs should be as short as possible and can carry 1A peak current. (6). Place all of the components as close to IC as possible. DS9232-06 March 2007 www.richtek.com 13 RT9232 Outline Dimension A H M J B F C I D Symbol A B C D F H I J M Dimensions In Millimeters Min 8.534 3.810 1.346 0.330 1.194 0.178 0.102 5.791 0.406 Max 8.738 3.988 1.753 0.508 1.346 0.254 0.254 6.198 1.270 Dimensions In Inches Min 0.336 0.150 0.053 0.013 0.047 0.007 0.004 0.228 0.016 Max 0.344 0.157 0.069 0.020 0.053 0.010 0.010 0.244 0.050 14– Lead SOP Plastic Package Richtek Technology Corporation Headquarter 5F, No. 20, Taiyuen Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)5526789 Fax: (8863)5526611 Richtek Technology Corporation Taipei Office (Marketing) 8F, No. 137, Lane 235, Paochiao Road, Hsintien City Taipei County, Taiwan, R.O.C. Tel: (8862)89191466 Fax: (8862)89191465 Email: marketing@richtek.com www.richtek.com 14 DS9232-06 March 2007