RT9243GS

RT9243 Multi-Phase PWM Controller for CPU Core Power Supply General Description The RT9243 is a multi-phase buck DC/DC controller integrated with all control functions for GHz CPU VRM. The RT9243 controls 2, 3 or 4 buck switching stages operating in interleaved phase set automatically. The multiphase architecture provides high output current while maintaining low power dissipation on power devices and low stress on input and output capacitors. The high equivalent operating frequency also reduces the component dimension and the output voltage ripple in load transient. RT9243 controls both voltage and current loops to achieve good regulation, response & power stage thermal balance. Precise current loop using RDS(ON) as sense component builds precise load line for strict VRM DC & transient specification and also ensures thermal balance of different power stages. The settings of current sense, droop tuning, VCORE i nitial offset and over current protection are independent to compensation circuit of voltage loop. The feature greatly facilitates the flexibility of CPU power supply design and tuning. The DAC output of RT9243 supports VRD10.x by 6-bit VID input, precise initial value & smooth VCORE transient at VIID jump. The IC monitors the VCORE voltage for PGOOD and over-voltage protection. Soft-start, over-current protection and programmable under-voltage lockout are also provided to assure the safety of microprocessor and power system. Features Multi-Phase Power Conversion with Automatic Phase Selection VRD10.x DAC Output with Active Droop Compensation for Fast Load Transient Smooth VCORE Transition at VID Jump Power Stage Thermal Balance by RDS(ON) Current Sense Hiccup Mode Over-Current Protection Programmable Switching Frequency (50kHz to 400kHz per Phase), Under-Voltage Lockout and Soft-Start High Ripple Frequency Times Channel Number RoHS Compliant and 100% Lead (Pb)-Free Applications Intel® Processors Voltage Regulator: VRD10.x Low Output Voltage, High Current DC-DC Converters Voltage Regulator Modules Pin Configurations (TOP VIEW) OVP PGOOD VID4 VID3 VID2 VID1 VID0 VID125 VOSS ADJ SS FB COMP VDIF ISN4 ISN3 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 RT DVD VCC PWM4 ISP4 ISP2 PWM2 PWM1 ISP1 ISP3 PWM3 GND SGND VSEN ISN1 ISN2 Ordering Information RT9243 Package Type S : SOP-32 Operating Temperature Range P : Pb Free with Commercial Standard G : Green (Halogen Free with Commercial Standard) Note : SOP-32 RichTek Pb-free and Green products are : RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020. Suitable for use in SnPb or Pb-free soldering processes. 100%matte tin (Sn) plating. DS9243-07 March 2007 www.richtek.com 1 +12V +12V C7 4.7uF 2 BOOT PVCC PHASE LGATE GND 4 IPD06N03LA C9 0.01uF 5 Q2 R14 4.7 VCC PWM 8 IPD09N03LA L1 1uH UGATE 7 C4 1uF +12V C5 1uF 3 RT DVD VCC PWM4 ISP4 ISP2 PWM2 PWM1 ISP1 ISP3 PWM3 GND SGND VSEN ISN1 ISN2 17 R12 2k +12V 18 R11 2k 19 +12V C16 1uF C17 4.7uF R17 10 2 7 6 C15 1uF 3 C18 2200uF 20 21 GND 4 22 C10 1uF 3 PWM LGATE 5 23 R10 2k 6 VCC 24 PHASE R9 2k PVCC 7 8 25 UGATE R15 10 2 BOOT IPD09N03LA Q4 IPD06N03LA 26 27 C12 4.7uF R8 2k 28 +12V C11 1uF C13 2200uF L2 1uH C25 to C28 2200uF x 4 C14 0.01uF 29 +12V R7 1k VCORE C20 to C24 2200uF x 5 30 R6 12k 31 32 R5 4.7k 6 C8 2200uF +5V R13 10 C6 1uF www.richtek.com 2 RT9600 1 Q1 RT9243 RT9243 OVP < 1 OVP PG_VCORE < 2 PGOOD VID4 > 3 VID4 Typical Application Circuit VID3 > 4 VID3 VID2 > 5 VID2 VID1 > 6 VID1 VID0 > 7 VID0 RT9600 1 Q3 VID125 > 8 R1 100k VID125 9 VOSS 10 ADJ R16 4.7 C1 0.1uF 11 SS 12 FB R2 15k C2 22nF 13 COMP C3 33pF 14 VIDF 15 ISN4 R3 2.4k 16 ISN3 R4 2k RT9600 BOOT PVCC VCC PWM LGATE GND 4 UGATE PHASE 1 8 Q5 IPD09N03LA Q6 5 1uH R18 4.7 IPD06N03LA C19 0.01uF DS9243-07 March 2007 RT9243 Functional Pin Description OVP (Pin 1) Over voltage trip output. PGOOD (Pin 2) Power good open-drain output. VID4 (Pin 3), VID3 (Pin 4), VID2 (Pin 5), VID1 (Pin 6), VID0 (Pin 7) & VID125 (Pin 8) DAC voltage identification inputs for VRD10.x. These pins are internally pulled to 3V if left open. VOSS (Pin 9) VCORE initial value offset. Connect this pin to GND with a resistor to set the offset value. ADJ (Pin 10) Current sense output for active droop adjust. Connect a resistor from this pin to GND to set the load droop. SS (Pin 11) Connect this SS pin to GND with a capacitor to set the soft-start time interval. Pulling this pin below 1V (ramp valley of sawtooth wave in pulse width modulator) would make all PWMs low, turn on low side MOSFETs and turn off high side MOSFETs. FB (Pin 12) Inverting input of the internal error amplifier. COMP (Pin 13) Output of the error amplifier and input of the PWM comparator. VDIF (Pin 14) VCORE differential sense output. VSEN (Pin 19) VCORE differential sense positive input. SGND (Pin 20) VCORE differential sense negative input. GND (Pin 21) Ground for the IC. DS9243-07 March 2007 www.richtek.com 3 PWM1 (Pin 25), PWM2 (Pin 26), PWM3 (Pin 22) & PWM4 (Pin 29) PWM outputs for each driven channel. Connect these pins to the PWM input of the MOSFET driver. For systems which use 3 channels, connect PWM4 high. Two channel systems connect PWM3 and PWM4 high. ISN1 (Pin 18), ISN2 (Pin 17), ISN3 (Pin 16) & ISN4 (Pin 15) RDS(ON) current sense inputs from each individual converter channel sense component's GND node. ISP1 (Pin 24), ISP2 (Pin 27), ISP3 (Pin 23) & ISP4 (Pin 28) RDS(ON) current sense inputs for each individual converter channel. Tie this pin to the component's sense node. VCC (Pin 30) IC power supply. Connect this pin to a 5V supply. DVD (Pin 31) Programmable power UVLO detection input. Trip threshold = 2V at VDVD rising. RT (Pin 32) Switching frequency setting. Connect this pin to GND with a resistor to set the frequency. 450 400 350 300 Frequency vs. RRT f OSC(kHz) 250 200 150 100 50 0 0 10 20 30 40 50 60 70 RRT (kΩ) Power On Reset ++ PWMCP INH Function Block Diagram ++ OVP Trip Point INH ++ - OCP Setting ++ + + DAC + Droop PG Trip Point Offset Currrent Source/Sink + + Current Correction VOSS Error Amplifier GAP Amplifier SS Control + + + + - SGND VSEN - Buffer Amplifier SUM/M VDIF SS FB COMP ADJ GND + + - - + + - - - + VID0 VID1 VID2 VID3 VID4 VID125 INH DAC PWM Logic & Driver Oscillator & Sawtooth + + - + - + www.richtek.com 4 OVP PGOOD VCC DVD RT INH RT9243 PWM Logic & Driver PWM1 PWM2 PWMCP PWM Logic & Driver PWM3 PWMCP INH PWM Logic & Driver PWMCP PWM4 ISN1 ISP1 ISN2 ISP2 ISN3 ISP3 ISN4 ISP4 DS9243-07 March 2007 RT9243 Table 1. Output Voltage Program Pin Name VID4 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 VID3 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 VID2 1 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 VID1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 0 0 1 1 1 1 VID0 1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 0 1 1 0 0 1 1 0 0 VID125 X 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Nominal Output Voltage DACOUT No CPU 0.8375V 0.850V 0.8625V 0.875V 0.8875V 0.900V 0.9125V 0.925V 0.9375V 0.950V 0.9625V 0.975V 0.9875V 1.000V 1.0125V 1.025V 1.0375V 1.050V 1.0625V 1.075V 1.0875V 1.100V 1.1125V 1.125V 1.1375V 1.150V 1.1625V 1.175V 1.1875V 1.200V 1.2125V To be continued DS9243-07 March 2007 www.richtek.com 5 RT9243 Table 1. Output Voltage Program Pin Name VID4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 VID3 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 VID2 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 VID1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 VID0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 VID125 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Nominal Output Voltage DACOUT 1.225V 1.2375V 1.250V 1.2625V 1.275V 1.2875V 1.300V 1.3125V 1.325V 1.3375V 1.350V 1.3625V 1.375V 1.3875V 1.400V 1.4125V 1.425V 1.4375V 1.450V 1.4625V 1.475V 1.4875V 1.500V 1.5125V 1.525V 1.5375V 1.550V 1.5625V 1.575V 1.5875V 1.600V Note: (1) 0 : Connected to GND (2) 1 : Open (3) X : Don't Care www.richtek.com 6 DS9243-07 March 2007 RT9243 Absolute Maximum Ratings (Note 1) Supply Voltage, VCC -------------------------------------------------------------------------------------------- 7V Input, Output or I/O Voltage ----------------------------------------------------------------------------------- GND-0.3V to VCC+0.3V Package Thermal Resistance SOP-32, θJA ------------------------------------------------------------------------------------------------------ 50°C/W Junction Temperature ------------------------------------------------------------------------------------------- 150°C Lead Temperature (Soldering, 10 sec.) --------------------------------------------------------------------- 260°C Storage Temperature Range ---------------------------------------------------------------------------------- −65°C to 150°C ESD Susceptibility (Note 2) HBM (Human Body Mode) ------------------------------------------------------------------------------------ 2kV MM (Machine Mode) -------------------------------------------------------------------------------------------- 200V Recommended Operating Conditions (Note 3) Supply Voltage, VCC -------------------------------------------------------------------------------------------- 5V ± 10% Ambient Temperature Range ---------------------------------------------------------------------------------- 0°C to 70°C Junction Temperature Range ---------------------------------------------------------------------------------- 0°C to 125°C Electrical Characteristics (VCC = 5V, TA = 25°C, unless otherwise specified) Parameter VCC Supply Current Nominal Supply Current Power-On Reset POR Threshold Hysteresis VDVD Threshold Oscillator Free Running Frequency Frequency Adjustable Range Ramp Amplitude Ramp Valley Maximum On-Time of Each Channel RT Pin Voltage Reference and DAC DACOUT Voltage Accuracy DAC (VID0-VID125) Input Low DAC (VID0-VID125) Input High Trip (Low to High) Hysteresis Symbol Test Conditions Min Typ Max Units ICC VCCRTH VCCHYS VDVDTP VDVDHYS fOSC fOSC_ADJ ΔVOSC VRV VRT PWM 1,2,3,4 Open -- 12 4.2 0.5 2.0 100 200 -1.9 1.0 66 0.60 ----- 16 4.5 -2.1 -230 400 --75 0.65 +1 +10 0.4 -- mA V V V mV kHz kHz V V % V % mV V V VCC Rising Enable 4.0 0.2 1.9 -- RRT = 12kΩ RRT = 12kΩ 170 50 -0.7 62 RRT = 12kΩ VDAC ≥ 1V VDAC < 1V 0.55 −1 −10 -0.8 ΔVDAC VILDAC VIHDAC To be continued DS9243-07 March 2007 www.richtek.com 7 RT9243 Parameter DAC (VID0-VID125) Bias Current VOSS Pin Voltage Error Amplifier DC Gain Gain-Bandwidth Product Slew Rate Differential Sense Amplifier Input Impedance Gain-Bandwidth Product Slew Rate Current Sense GM Amplifier ISP 1,2,3,4 Full Scale Source Current ISP 1,2,3,4 Current for OCP Protection SS Current Over-Voltage Trip (VSEN/DACOUT) OVP Voltage Power Good Lower Threshold (VSEN/DACOUT) Output Low Voltage VPGOOD− VPGOODL VSEN Rising IPGOOD = 4mA --92 --0.2 % V ISS ΔOVT VOVP IOVP = 4mA VSS = 1V 8 130 -13 140 -18 150 0.2 μA % V IISPFSS IISPOCP 60 --100 --μA μA ZIMP GBW SR ---16 10 3 ---kΩ MHz V/μs GBW SR COMP = 10pF ---85 10 3 ---dB MHz V/μs Symbol IBIAS_DAC VVOSS RVOSS = 100kΩ Test Conditions Min 60 0.95 Typ 120 1.0 Max 180 1.05 Units μA V Note 1. Stresses listed as the above "Absolute Maximum Ratings" may cause permanent damage to the device. These are for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. Note 2. Devices are ESD sensitive. Handling precaution recommended. Note 3. The device is not guaranteed to function outside its operating conditions. www.richtek.com 8 DS9243-07 March 2007 RT9243 Typical Operating Characteristics 200 180 160 140 GM Adjustable Frequency 500 450 400 350 V ADJ (mV) 120 100 80 60 40 20 0 0 10 20 F SW (kHz) GM1 GM2 GM3 GM4 30 40 50 60 70 80 90 100 300 250 200 150 100 50 0 0 10 20 30 40 50 60 70 VDS (mV) (k RRT (k Ω) Linearity of Each PWM 0.8 0.7 EA Falling Slew Rate (500mV/Div) 0.6 Duty (%) 0.5 0.4 0.3 0.2 0.1 0 1 1.25 1.5 1.75 2 2.25 2.5 2.75 3 Ramp1 Ramp2 Ramp3 Ramp4 (1V/Div) VCONTROL (V) Time (250ns/Div) EA Rising Slew Rate Differential Amp Rising Slew Rate (500mV/Div) (500mV/Div) (1V/Div) (500mV/Div) Time (250ns/Div) Time (50ns/Div) DS9243-07 March 2007 www.richtek.com 9 RT9243 Differential Amp Falling Slew Rate The Bandwidth of Differential Amplifier (200mV/Div) (500mV/Div) (200mV/Div) (500mV/Div) fBandwidth = 17MHz VPP-DIFF = 0.707VPP-IN Time (50ns/Div) Time (25ns/Div) Start-up Waveforms @IOUT = 60A Inductor Current VSS PWM UGATE LGATE (20V/Div) (2V/Div) (5V/Div) Current Sharing at IOUT = 80A (5A/Div) PWM (5V/Div) (10V/Div) Time (5ms/Div) Time (2.5μs/Div) Over Current Protection (5V/Div) PGOOD Waveform VSS PWM1 (5V/Div) (2V/Div) PGOOD PWM2 (5V/Div) (1V/Div) VOUT PWM3 (5V/Div) Time (25ms/Div) Time (5ms/Div) www.richtek.com 10 DS9243-07 March 2007 RT9243 Transient Response VOUT Phase1 Phase2 Phase3 DS9243-07 March 2007 www.richtek.com 11 RT9243 Application Information RT9243 is a multi-phase DC/DC controller that precisely regulates CPU core voltage and balances the current of different power channels. The converter consisting of RT9243 and its companion MOSFET driver provides high quality CPU power and all protection functions to meet the requirement of modern VRM. Voltage Control RT9243 senses the CPU VCORE by an precise instrumental amplifier to minimize the voltage drop on PCB trace at heavy load. VSEN & SGND are the differential inputs. VDIF is the output node of the differential voltage & the input for PGOOD & OVP sense. The internal high accuracy VID DAC provides the reference voltage for VRD10.x compliance. Control loop consists of error amplifier, multi-phase pulse width modulator, driver and power components. Like conventional voltage mode PWM controller, the output voltage is locked at the VREF of error amplifier and the error signal is used as the control signal VC of pulse width modulator. The PWM signals of different channels are generated by comparison of EA output and split-phase saw-tooth wave. Power stage transforms VIN to output by PWM signal on-time ratio. Current Balance RT9243 senses the current of low side MOSFET in each synchronous rectifier when it is conducting for channel current balance and droop tuning. The differential sensing GM amplifier converts the voltage on the sense component (can be a sense resistor or the RDS(ON) of the low side MOSFET) to current signal into internal balance circuit. The current balance circuit sums and averages the current signals and then produces the balancing signals injected to pulse width modulator. If the current of some power channel is greater than average, the balancing signal reduces the output pulse width to keep the balance. Load Droop The sensed power channel current signals regulate the reference of DAC to form a output voltage droop proportional to the load current. The droop or so-called “active voltage positioning” can reduce the output voltage ripple at load transient and the LC filter size. Fault Detection The chip detects VCORE for over voltage and power good detection. The “ hiccup mode” operation of over-current protection is adopted to reduce the short circuit current. The inrush current at the start up is suppressed by the soft start circuit through clamping the pulse width and output voltage. Phase Setting and Converter Start Up RT9243 interfaces with companion MOSFET drivers (like RT9600, RT9602 series) for correct converter initialization. The tri-state PWM output (high, low and high impedance) pins sense the interface voltage at IC POR period (both VCC and DVD trip). The channel is enabled if the pin voltage is 1.2V less than VCC. Please tie the PWM output to VCC and the current sense pins to GND or left floating if the channel is unused. For 3-Channel application, connect PWM4 high. Current Sensing Setting RT9243 senses the current of low side MOSFET in each synchronous rectifier when it is conducting for channel current balance and droop tuning. The differential sensing GM amplifier converts the voltage on the sense component (can be a sense resistor or the RDS(ON) of the low side MOSFET) to current signal into internal circuit (see Figure 1). IX IBP Sample & Hold Current Balance Droop Tune GM + IBN ISPx ISNx RSP1 RS RSN1 IL < < < Over-Current Detection Figure 1. Current Sense Circuit www.richtek.com 12 DS9243-07 March 2007 RT9243 I L × RS by local feedback. RSP RSP = RSN to cancel the voltage drop caused by GM amplifier input bias current. IX is sampled and held just before low side MOSFET turns off (See Figure 2). Therefore, IL(S/H) × R S V T I X(S/H) = , IL(S/H) = IL(AVG) − OUT × OFF , R SP L 2 The sensing circuit gets IX = ⎡ V − VOUT ⎤ TOFF = ⎢ IN ⎥ × 5 μs for fosc = 200kHz VIN ⎣ ⎦ I X(S/H) ⎡ ⎤ ⎡ V − VOUT ⎤ VOUT − ⎢ IN ⎢ ⎥ × 5 μs ⎥ R VIN ⎣ ⎦ ⎥× S = ⎢IL(AVG) − ⎢ ⎥ R SP 2L ⎢ ⎥ ⎣ ⎦ Falling Slope = Vo/L IL IL(AVG) Inductor Current Protection and SS Function For OVP, the RT9243 detects the VCORE by VDIF pin voltage of the differential amplifier output. Eliminate the delay due to compensation network (compared to sensing FB voltage) for fast and accurate detection. The trip point of OVP is 140% of normal output level. The PWM outputs are pulled low to turn on the low side MOSFET and turn off the high side MOSFET of the synchronous rectifier at OVP. The OVP latch can only be reset by VCC or DVD restart power on reset sequence. The PGOOD detection trip point of VCORE is 92% lower than the normal level. The PGOOD open drain output pulls low when VCORE is lower than the trip point. For VID jumping issue, only power fail conditions (VCC & DVD are lower than trip point or OVP) reset the output low. Soft-start circuit generates a ramp voltage by charging external capacitor with 13μA current after IC POR acts. The PWM pulse width and VCORE are clamped by the rising ramp to reduce the inrush current and protect the power devices. Over-current protection trip point is internally set at around 100μA for each channel. OCP is triggered if one channel S/H current signal IX > ⎜ IL(S/H) PWM Signal & High Side MOSFET Gate Signal Low Side MOSFET Gate Signal Figure 2. Inductor Current and PWM Signal DAC Offset Voltage & Droop Tuning The DAC offset voltage is set by compensation network ⎛ 1V ⎞ R f 1 & VOSS pin external resistors by ⎜ R VOSS ⎟ × 4 . ⎝ ⎠ The S/H current signals from power channels are injected to ADJ pin to create droop voltage. VADJ = RADJ× 2 IX ∑ PWM output latched at high impedance to turn off both high and low side MOSFETs in the power stage and initial the hiccup mode protection. The SS pin voltage is pulled low with a 13μA current after it is less than 90% VCC. The converter restarts after SS pin voltage < 0.2V. Three times of OCP disable the converter and only release the latch by POR acts (see Figure 4). COUNT= 1 COUNT= 2 COUNT==33 Count = 1 Count = 2 Count ⎛ 0 .6 V ⎞ ⎟ × 1 .5 . Controller forces ⎝ 9K ⎠ The DAC output voltage decreases by VADJ to form the VCORE load droop (see Figure 3). VDAC VADJ 2IX1 2IX2 2IX3 2IX4 + COMP Current Source IVOSS 1V = RVOSS + EA 1 IVOSS 4 FB RF1 ADJ RADJ S.S VCORE 0V ∑ Overload Applied > ILOAD 0A + - Figure 3. DAC Offset Voltage & Droop Tune Circuit DS9243-07 March 2007 > VOSS RVOSS VCORE T0,T1 T2 TIME T3,T4 > Figure 4. www.richtek.com 13 RT9243 3-Phase Converter and Components Function Grouping 12V VCC PVCC BOOT UGATE PHASE RT9600 PWM SGND VSEN VDIF PWM1 VID OVP PGOOD 12V ISP1 ISN1 VCC PVCC BOOT UGATE PHASE VCORE LGATE GND RT9243 Compensation & Offset COMP FB ADJ Droop Setting 12V DVD VOSS SS DAC Offset Voltage Setting RT Frequency Setting ISP3 ISN3 PWM3 GND ISP2 ISN2 PWM2 RT9600 PWM LGATE GND Driver Power UVLO 12V VCC PVCC BOOT UGATE PHASE RT9600 PWM LGATE GND Current Sense Components Design Procedure Suggestion Voltage Loop Setting a. Output filter pole and zero (Inductor, output capacitor value & ESR). b. Error amplifier compensation & sawtooth wave amplitude (compensation network). c. Kelvin sense for VCORE. Current Loop Setting a. GM amplifier S/H current (current sense component Ron, ISPx & ISNx pin external resistor value, keep ISPx current < 60μA at full load condition for better load line linearity). b. Over-current protection trip point (Internal setting, keep ISPx current < 100μA at OCP condition for precision issue). www.richtek.com 14 VRM Load Line Setting a. Droop amplitude (ADJ pin resistor). b. No load offset (additional resistor in compensation network). c. DAC offset voltage setting (VOSS pin & compensation network resistor). Power Sequence & SS DVD pin external resistor and SS pin capacitor. PCB Layout a. Kelvin sense for current sense GM amplifier input. b. Refer to layout guide for other item. DS9243-07 March 2007 RT9243 Design Example Given: Apply for three phase converter VIN = 12V ILOAD(MAX) = 60A VDROOP = 120mV at full load OCP trip point set at 33A for each channel (S/H) RDS(ON) = 6mΩ of low side MOSFET at 27°C L = 2μH COUT = 9,000μF with 2mΩ ESR. 1. Compensation Setting a. Modulator Gain, Pole and Zero: From the following formula: V IN 12V Modulator Gain = = = 4.2 (12.46dB) V RAMP 1.9V × 3 where VRAMP : ramp amplitude of sawtooth wave LC Filter Pole = 2π x LC = 1.2kHz and ESR Zero = 2π x ESR x COUT = 8.8kHz b. EA Compensation Network : Select R1 = 2.4kΩ, R2 = 24kΩ, C1 = 6.6nF, C2 = 33pF and use the type 2 compensation scheme shown in Figure 5. R2 Asymptotic Bode Plot of PWM Loop Gain 100 80 60 Uncompensated EA Gain Gain (dB) VCORE = 1.5V 40 20 0 -20 -40 -60 10 10 100 100 1K 1000 Compensated EA Gain PWM Loop Gain Modulator Gain 10K 10000 100K 100000 1M 10M 1000000 10000000 Frequency (Hz) Figure 6. 2. Droop & DAC Offset Setting For each channel the load current is 60A / 3 = 20A and the ripple current, ΔIL, is given as : 2 5us x 1 1 C1 R3 R1 C3 C2 COMP + DACOUT FB > VDIF R3,C3 are used in type 3 compensation scheme (left NC in type 2) ΔIL = 18.36 A . 2 Using the following formula to select the appropriate IX (MAX) for the S/H of GM amplifier : R DS(ON) × 18.36A I X (MAX) = R SP The suggested IX is in the order of 50 to 60μA, select RSP = RSN = 2kΩ, then IX (MAX) will be 55μA. VDROOP = 120mV = 55μA × 2 × 3 (phase no.) × RADJ, therefore RADJ will be 360Ω. The RDS(ON) of MOSFET varies with temperature rise. When the low side MOSFET working at 70°C and 5000ppm/°C temperature coefficient of RDS(ON), the RDS(ON) at 70°C is given as : 6mΩ × {1+ (70°C − 27°C) × 5000ppm/°C} = 7.3mΩ. RADJ at 70°C is given as : RADJ_27°C × (RDS(ON)_27°C / RDS(ON)_70°C) = 296Ω The load current, IL, at S/H is 20 A − 3. Over-Current Protection Setting OCP trip point is internally set at around 100μA of IX for each channel. As above-selected RSP = RSN = 2kΩ, the OCP trip point is found using : 1.5V ⎛ 1.5V ⎞ x ⎜1 − ⎟ = 3.28A 2uH ⎝ 12V ⎠ Figure 5. From the following formulas : 1 1 FZ = , FP = 2π x R 2 x C 1 ⎛ C1 × C 2 ⎞ 2π x R 2 x ⎜ ⎟ R2 ⎝ C1 + C 2 ⎠ Middle Band Gain = R1 By calculation, the FZ = 1kHz, FP = 200kHz and Middle Band Gain is 10 (i.e 20dB). The asymptotic bode plot of EA compensation and PWM loop gain is shown as Figure 6. DS9243-07 March 2007 IX (OCP) = R DS(ON) × IL (TRIP) 6m Ω × 33A = = 100 μ A R SP 2K Ω 4. Soft-Start Capacitor Selection CSS = 0.1μF is the suitable value for most application. www.richtek.com 15 RT9243 Layout Guide Place the high-power switching components first, and separate them from sensitive nodes. 1. Most critical path: the current sense circuit is the most sensitive part of the converter. The current sense resistors tied to ISP1,2,3,4 and ISN1,2,3,4 should be located not more than 0.5 inch from the IC and away from the noise switching nodes. The PCB trace of sense nodes should be parallel and as short as possible. Kelvin connection of the sense component (additional sense resistor or MOSFET RDS(ON)) ensures the accurate stable current sensing. Keep well Kelvin sense to ensure the stable operation! 2. Switching ripple current path: a. Input capacitor to high side MOSFET. b. Low side MOSFET to output capacitor. c. The return path of input and output capacitor. d. Separate the power and signal GND. e. The switching nodes (the connection node of high/low side MOSFET and inductor) is the most noisy points. Keep them away from sensitive small-signal node. f. Reduce parasitic R, L by minimum length, enough copper thickness and avoiding of via. 3. MOSFET driver should be closed to MOSFET. 4. The compensation, bypass and other function setting components should be near the IC and away from the noisy power path. SW1 L1 VIN RIN CIN VOUT COUT RL V SW2 L2 Figure 7. Power Stage Ripple Current Path www.richtek.com 16 DS9243-07 March 2007 RT9243 +12V CBP VCC PVCC PWM BOOT UGATE PHASE CIN Kelvin Sense Next to IC +12V or +5V PWM RT VOSS VCC CBP +5VIN CBOOT LO1 Next to IC COMP CC VCORE RT9600 LGATE GND COUT RSIP RT9243 ISPx ISNx ADJ FB RC Locate next to FB Pin RFB Locate near MOSFETs RSIN VSEN GND For Thermal Couple Figure 8. Layout Consideration DS9243-07 March 2007 www.richtek.com 17 RT9243 Outline Dimension A H M J B F C I D Dimensions In Millimeters Symbol Min A B C D F H I J M 0.229 0.102 10.008 0.381 20.320 7.391 2.362 0.330 1.27 0.330 0.305 10.643 1.270 Max 20.726 7.595 2.642 0.508 Dimensions In Inches Min 0.800 0.291 0.093 0.013 0.050 0.009 0.004 0.394 0.015 0.013 0.012 0.419 0.050 Max 0.816 0.299 0.104 0.020 32-Lead SOP Plastic Package Richtek Technology Corporation Headquarter 5F, No. 20, Taiyuen Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)5526789 Fax: (8863)5526611 Richtek Technology Corporation Taipei Office (Marketing) 8F, No. 137, Lane 235, Paochiao Road, Hsintien City Taipei County, Taiwan, R.O.C. Tel: (8862)89191466 Fax: (8862)89191465 Email: marketing@richtek.com www.richtek.com 18 DS9243-07 March 2007