RT9245BGC

RT9245B Multi-Phase PWM Controller for K8 CPU Core Power Supply General Description RT9245B is a multi-phase buck DC/DC controller integrated with all control functions for AMD K8 CPU. The RT9245B could be operated with 2, 3 or 4 buck switching stages operating in interleaved phase set automatically. The multiphase architecture provides high output current while maintaining low power dissipation on power devices and low stress on input and output capacitors. The high equivalent operating frequency also reduces the component dimension and the output voltage ripple in load transient. RT9245B implements both voltage and current loops to achieve good regulation, response and power stage thermal balance. RT9245B applies the DCR sensing technology newly. The RT9245B extracts the ESR of output inductor as sense component to deliver a precise load line regulation and good thermal balance for next generation processor application. Current sense setting, droop tuning, VCORE initial offset and ov er current protection are independent on compensation circuit of voltage loop. The feature greatly facilitates the flexibility of CPU power supply design and tuning. The DAC output of RT9245B supports AMD K8 6-bit VID, precise offset value & smooth VCORE transient at VID jump. The IC monitors the VCORE voltage for PGOOD and over-voltage protection. Soft-start, over-current protection and programmable under-voltage lockout are also provided to assure the safety of microprocessor and power system. The RT9245B comes to a small footprint package TSSOP-28. Features l l l l l l l l l Multi-Phase Power Conversion with Automatic Phase Selection 6-bit AMD K8 M2 DAC Output with Active Droop Compensation for Fast Load Transient Smooth VCORE Transition at VID Jump Power Stage Thermal Balance by DCR Current Sense Hiccup Mode Over-Current Protection Programmable Switching Frequency (50kHz to 400kHz per Phase), Under-Voltage Lockout and SoftStart High Ripple Frequency Times Channel Number 28-TSSOP Package RoHS Compliant and 100% Lead (Pb)-Free Applications l l l AMD K8 Processors Voltage Regulator Low Output Voltage, High Current DC-DC Converters Voltage Regulator Modules Pin Configurations (TOP VIEW) VID4 VID3 VID2 VID1 VID0 VID5 SGND FB COMP PGOOD DVD SS RT VOSS 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC PWM1 PWM2 PWM3 PWM4 CSP4 CSP2 CSP3 CSP1 GND ADJ IOUT CSN IMAX Ordering Information RT9245B Package Type C : TSSOP-28 Operating Temperature Range P : Pb Free with Commercial Standard G : Green (Halogen Free with Commercial Standard) Note : TSSOP-28 RichTek Pb-free and Green products are : }RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020. }Suitable for use in SnPb or Pb-free soldering processes. }100% matte tin (Sn) plating. DS9245B-02 March 2007 www.richtek.com 1 VIN ATX 12V 1uH + C11 1000uF C12 4.7uF C14 1000uF ATX 12V C10 1uF + + www.richtek.com 2 C13 R20 10 D1 1N4148 R21 0 Q1 L1 1uH IPD09N03LA Q2 IPD06N03LA C16 3.3nF RT9619 8 1 BOOT UGATE 4 VCC 7 PHASE 2 PWM NC PGND 6 LGATE 3 R9 10 R38 820 C4 1uF 5 R22 2.2 4.7uF C15 1000uF RT9245B VCC 5V C9 1uF RT9245B + ATX 12V C18 1uF C19 R24 0 IPD09N03LA Q4 Q3 4.7uF L2 1uH VIN C21 C20 1000uF 1000uF + Typical Application Circuit 6 VID5 PWM1 PWM2 4 25 C17 1uF R10 1k LGATE IPD06N03LA PGND 6 C5 1uF R11 1k R12 1k R13 1k C6 1uF C7 1uF 5 2 PWM 3 NC PHASE VCC 7 26 1 RT9619 8 BOOT UGATE 27 VCC R23 10 D2 1N4148 28 VOUT VID4 VID3 1 VID4 2 VID3 PWM3 PWM4 24 CSP4 CSP2 CSP3 CSP1 GND ADJ IOUT 1 4 C23 1uF 2 3 PWM NC 17 16 R16 470 R15 C8 1uF R27 10 D3 1N4148 18 R14 33 19 C24 1uF 20 21 22 23 VID2 3 C35 to C46 1000uF x 12 + R25 2.2 VID1 4 VID2 VID1 VID0 5 VID0 + C22 3.3nF NTC 10k C47 to C50 10uF x 4 R1 0 7 SGND C51 NC 8 FB ATX 12V C1 33pF 9 COMP R2 3k VIN R26 240 C27 C26 1000uF 1000uF + + C2 10nF R3 15k VCC 3.3V/FSBVTT 10 C25 R28 0 RT9619 8 BOOT UGATE VCC PHASE 7 Q5 IPD09N03LA Q6 5 LGATE PGND 6 IPD06N03LA R29 2.2 C28 3.3nF 4.7uF PGOOD ATX 12V R5 10k R4 10k 11 DVD CSN IMAX R18 6.8k 15 R17 100k D5 R19 BAT254 100 C3 68nF 12 SS L3 1uH R6 1.2k 13 RT R7 20k 14 VOSS R8 100k ATX 12V C30 1uF VIN C33 C32 1000uF 1000uF + + C31 R30 10 D4 1N4148 R31 0 1 4 C29 1uF 2 3 PWM NC RT9619 8 BOOT UGATE VCC PHASE 7 Q7 IPD09N03LA Q8 5 LGATE PGND 6 IPD06N03LA R32 2.2 C34 3.3nF 4.7uF L4 1uH DS9245B-02 March 2007 RT9245B Functional Pin Description VID4 (Pin 1), VID3 (Pin 2), VID2 (Pin 3), VID1 (Pin 4), VID0 (Pin 5), VID5 (Pin 6) DAC voltage identification inputs for K8. These pins are internally pulled to 1.2V if left open. SGND (Pin 7) VCORE differential sense negative input. FB (Pin 8) Inverting input of the internal error amplifier. COMP (Pin 9) Output of the error amplifier and input of the PWM comparator. PGOOD (Pin 10) Power good open-drain output. DVD (Pin 11) Programmable power UVLO detection input. Trip threshold = 1.0V at VDVD rising. SS (Pin 12) Connect this SS pin to GND with a capacitor to set the soft-start time interval. RT (Pin 13) Switching frequency setting. Connect this pin to GND with a resistor to set the frequency. VOSS (Pin 14) VCORE initial value offset. Connect this pin to GND with a resistor to set the negative offset value. Connect this pin to VCC to set positive offset value. IMAX (Pin 15) Programmable over currert setting. CSN (Pin 16) Current sense negative input of all channels. IOUT (Pin 17) Output Current Indication Pin. The current through IOUT pin is proportional to the output current. ADJ (Pin 18) Current sense output for active droop adjust. Connect a resistor from this pin to GND to set the load droop. GND (Pin 19) Ground for the IC. CSP1 (Pin 20), CSP2 (Pin 22), CSP3 (Pin 21) & CSP4 (Pin 23) Current sense positive inputs for individual converter channel current sense. PWM1 (Pin 27), PWM2 (Pin 26), PWM3 (Pin 25) & PWM4 (Pin 24) PWM outputs for each driven channel. Connect these pins to the PWM input of the MOSFET driver. For systems which use 3 channels, connect PWM4 high. Two channel systems connect PWM3 high. VCC (Pin 28) IC power supply. Connect this pin to a 5V supply. DS9245B-02 March 2007 www.richtek.com 3 OCP Setting Power On Reset + + PWMCP INH Function Block Diagram DAC ++ OVP Trip Point ++ + + + INH VID4 VID3 VID2 VID1 VID0 VID5 - Oscillator & Sawtooth PG Trip Point + + + Current Correction MUX + GAP Amplifier SS Control - SUM/M DS9245B-02 March 2007 FB COMP SS VOSS ADJ IOUT GND - + - - + Offset Currrent Source/Sink + - Error Amplifier MUX - + DAC + Droop + + + - - + www.richtek.com 4 IMAX PGOOD VCC DVD RT INH RT9245B PWM Logic & Driver PWM1 PWM Logic & Driver PWM2 PWMCP INH PWM Logic & Driver PWMCP INH PWM3 PWM Logic & Driver PWMCP Phase Control PWM4 CSP1 CSP2 CSP3 CSP4 CSA CSN RT9245B Table 1. Output Voltage Program Pin Name VID5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 VID4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 VID3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 VID2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 VID1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 VID0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1.5500 1.5250 1.5000 1.4750 1.4500 1.4250 1.4000 1.3750 1.3500 1.3250 1.3000 1.2750 1.2500 1.2250 1.2000 1.1750 1.1500 1.1250 1.1000 1.0750 1.0500 1.0250 1.0000 0.9750 0.9500 0.9250 0.9000 0.8750 0.8500 0.8250 0.8000 0.7750 0.7625 0.7500 Nominal Output Voltage DACOUT To be continued DS9245B-02 March 2007 www.richtek.com 5 RT9245B Table 1. Output Voltage Program Pin Name VID5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID3 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 VID2 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 VID1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 VID0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0.7375 0.7250 0.7125 0.7000 0.6875 0.6750 0.6625 0.6500 0.6375 0.6250 0.6125 0.6000 0.5875 0.5750 0.5625 0.5500 0.5375 0.5250 0.5125 0.5000 0.4875 0.4750 0.4625 0.4500 0.4375 0.4250 0.4125 0.4000 0.3875 0.3750 Nominal Output Voltage DACOUT Note: (1) 0 : Connected to GND (2) 1 : Open www.richtek.com 6 DS9245B-02 March 2007 RT9245B Absolute Maximum Ratings l l l (Note 1) l l l l l Supply Voltage, VCC ------------------------------------------------------------------------------------------ 7V Input, Output or I/O Voltage -------------------------------------------------------------------------------- GND − 0.3V to VCC + 0.3V Power Dissipation, PD @ TA = 25°C TSSOP-28 ------------------------------------------------------------------------------------------------------ 1W Package Thermal Resistance (Note 4) TSSOP-28, θJA ------------------------------------------------------------------------------------------------ 100°C/W Junction Temperature ---------------------------------------------------------------------------------------- 150°C Lead Temperature (Soldering, 10 sec.)------------------------------------------------------------------- 260°C Storage Temperature Range -------------------------------------------------------------------------------- −65°C to 150°C ESD Susceptibility (Note 2) HBM (Human Body Mode) ---------------------------------------------------------------------------------- 2kV MM (Machine Mode) ----------------------------------------------------------------------------------------- 200V (Note 3) Recommended Operating Conditions l l l Supply Voltage, VCC ----------------------------------------------------------------------------------------- 5V ± 10% Junction Temperature Range ------------------------------------------------------------------------------- −40°C to 125°C Ambient Temperature Range ------------------------------------------------------------------------------- −40°C to 85°C Electrical Characteristics (VCC = 5V, TA = 25°C, unless otherwise specified) Parameter VCC Supply Current Nominal Supply Current Power-On Reset POR Threshold Hysteresis VDVD Threshold Oscillator Free Running Frequency Frequency Adjustable Range Ramp Amplitude Ramp Valley Maximum Duty of Each Channel RT Pin Voltage Reference and DAC DACOUT Voltage Accuracy DAC (VID0-VID5) Input Low DAC (VID0-VID5) Input High ∆VDAC VILDAC VIHDAC VDAC ≥ 1V VDAC < 1V −1 −10 -1.2 ----+1 +10 0.8 -% mV V V VRT RRT = 20k Ω f OSC fOSC_ADJ ∆VOSC VRV RRT = 20k Ω RRT = 20k Ω 170 50 -0.7 58 0.9 200 -1.9 1.0 64 1.0 230 400 --70 1.1 kHz kHz V V % V Trip (Low to High) Hysteresis VCCRTH VCCHYS VDVDTP VDVDHYS Enable VCC R ising 4.0 0.2 0.94 -4.2 0.5 1.0 50 4.5 -1.06 -V V V mV ICC PWM 1,2,3,4 Open -12 16 mA Symbol Test Conditions Min Typ Max Units To be continued DS9245B-02 March 2007 www.richtek.com 7 RT9245B Parameter DAC (VID0-VID5) pull up resistor DAC Pull Up Voltage VOSS Pin Voltage Error Amplifier DC Gain Gain-Bandwidth Product Slew Rate Current Sense GM Amplifier CSN Full Scale Source Current CSN Current for OCP Protection Over-Voltage Trip (VFB − VDAC) IMAX Voltage Power Good Output Low Voltage VPGOODL IPGOOD = 4mA --0.2 V ∆OVT VIMAX RADJ = 0Ω RIMAX = 20kΩ 320 0.9 400 1.0 450 1.1 mV V IISPFSS 100 150 ----µA µA GBW SR COMP = 10pF ---60 10 6 ---dB MHz V/µs VVOSS RVOSS = 100kΩ Symbol Test Conditions Min 2.5 -0.9 Typ 3.5 2.1 1.0 Max 4.5 -1.1 Units kΩ V V Note 1. S tresses listed as the above “ Absolute Maximum Ratings” may cause permanent damage to the device. These are for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. Note 2. Devices are ESD sensitive. Handling precaution recommended. Note 3. The device is not guaranteed to function outside its operating conditions. Note 4. θJA is measured in the natural convection at TA = 2 5°C on a low effective single layer thermal conductivity test board of JEDEC 51-3 thermal measurement standard. www.richtek.com 8 DS9245B-02 March 2007 RT9245B Typical Operating Characteristics Adjustable Frequency 700 600 500 70 60 50 40 30 20 10 0 0 10 20 30 40 50 60 70 0.5 1 1.5 2 2.5 3 3.5 PWM vs. VCOMP RRT = 16kΩ 400 300 200 100 0 R RT (kΩ) (kW) Duty Ratio (%) F SW (k Hz) VCOMP (V) Relationship Between Inductor Current and VADJ CH1:(5V/Div) CH2:(5V/Div) Power-Off @ IOUT = 60A PWM PWM CH1:(5V/Div) CH2:(20V/Div) VSS VADJ UGATE CH3:(10V/Div) CH4:(1V/Div) LGATE IL CH3:(50mV/Div) CH4:(20A/Div) VCOMP Time (10 µs/Div) Time (25ms/Div) Power-On @ IOUT = 60A CH1:(5V/Div) CH2:(5V/Div) Ripple VSS PWM VCORE UGATE CH3:(20V/Div) CH4:(10V/Div) (5mV/Div) LGATE L = 0.3µ H, C = 5600µ F Time (10ms/Div) Time (2.5 µs/Div) DS9245B-02 March 2007 www.richtek.com 9 RT9245B DVID at Rising DVID at Falling VCORE (500mV/Div) (500mV/Div) VCORE VID5 (2V/Div) VID5 (2V/Div) Time (50 µs/Div) Time (50 µs/Div) Transient Response Transient Falling (20mV/Div) VCORE (20mV/Div) Time (5ms/Div) Time (500ns/Div) www.richtek.com 10 DS9245B-02 March 2007 RT9245B Application Information RT9245B is a multi-phase DC/DC controller that precisely regulates CPU core voltage and balances the current of different power channels. The converter consisting of RT9245B and its companion MOSFET driver RT9619 provides high quality CPUpower and all protection functions to meet the requirement of modern VRM. Voltage Control RT9245B senses the CPU VCORE by SGND pin to sense the return of CPU to minimize the voltage drop on PCB trace at heavy load. OVP is sensed at FB pin. The internal high accuracy VID DAC provides the reference voltage for K8 compliance. Control loop consists of error amplifier, multi-phase pulse width modulator, driver and power components. As conventional voltage mode PWM controller, the output voltage is locked at the VREF of error amplifier and the error signal is used as the control signal of pulse width modulator. The PWM signals of different channels are generated by comparison of EA output and split-phase sawtooth wave. Power stage transforms VIN to output by PWM signal on-time ratio. Current Balance RT9245B senses the inductor current via inductor's DCR for channel current balance and droop tuning. The differential sensing GM amplifier converts the voltage on the sense component (can be a sense resistor or the DCR of the inductor) to current signal into internal balance circuit. The current balance circuit sums and averages the current signals and then produces the balancing signals injected to pulse width modulator. If the current of some power channel is larger than average, the balancing signal reduces that channels pulse width to keep current balance. The use of single GM amplifier via time sharing technique to sense all inductor currents can reduce the offset errors and linearity variation between GMs. Thus it can greatly improve signal processing especially when dealing with such small signal as voltage drop across DCR. Droop & Load Line Setting RT9245B injects averaged current IX into the resistor RADJ connected to ADJ pin to generate a load-currentdependent voltage RADJ for droop setting: VADJ = 8 x IX x RADJ VADJ is then subtracted from VID_DAC output as the real reference voltage at non-inverting input of the error amplifier as shown if Figure 1. Consequently, load line slope is calculated as : Load Line = ΔVCORE 8 x RADJ x DCR = ΔICORE N x RCSN where N is the phase number of operation. IVOSS /4 VCORE RCSN EA + VADJ 8IX RADJ DAC Figure 1. Load Line and Offset Function Fault Detection The chip detects FB for over voltage and power good detection. The “ hiccup mode” operation of over current protection is adopted to reduce the short circuit current. The in-rush current at the start up is suppressed by the soft start circuit through clamping the pulse width and output voltage. Phase Setting and Converter Start Up RT9245B interfaces with companion MOSFET drivers (like RT9619, RT9607 series) for correct converter initialization. The tri-state PWM output (high, low and high impedance) senses its interface voltage when IC POR acts (both VCC and DVD trip). The channel is enabled if the pin voltage is 1.2V less than VCC. Tie the PWM to VCC and the corresponding current sense pins to GND or left float if the channel is unused. For example, for 3-Channel application, connect PWM4 high. Current Sensing Setting RT9245B senses the current flowing through inductor via its DCR for channel current balance and droop tuning. DS9245B-02 March 2007 + - www.richtek.com 11 RT9245B The differential sensing GM amplifier converts the voltage on the sense component (can be a sense resistor or the DCR of the inductor) to current signal into internal circuit (see Figure 2). L VC = R × C VC = DCR × IL I X = DCR R CSN L DCR +VCR + GMx Ix RCSN VCSP4 C Figure 5 shows the time sharing technique of GM amplifier. We apply test signal at phase 4 and observe the waveforms at both pins of GM amplifier. The waveforms show time sharing mechanism and the perfomance of GM to hold both input pins equal when the shared time is on. Time Sharing of GM CH1:(2V/Div) CH2:(50mV/Div) CH3:(50mV/Div) PWM3 Figure 2. Current Sense Circuit Figure 3 is the test circuit for GM. We apply test signal at GM inputs and observe its signal process output at ADJ pin. Figure 4 shows the variation of signal processing of all channels. We observe zero offsets and good linearity between phases. CSPX ADJ + VADJ - VCSP4 and VCSN V CSN Time (1 µs/Div) Figure 5 Over Current Protection RT9245B uses an external resistor R IMAX t o set a programmable over current trip point. OCP comparator compares each inductor current with this reference current. RT9245B uses hiccup mode to eliminate fault detection of OCP or reduce output current when output is shorted to ground. 1 VIMAX 1 IL x DCR x ⇔x 2 RIMAX 3 RCSN VC SUM/M MUX + GM - RADJ 1k RCSN 1k CSN Ix Figure 3. The Test Circuit of GM GM 300 250 200 OCP Comparator + 1/3 IX 1/2 IIMAX OCP Setting RIMX VADJ (m V) 150 100 50 0 0 25 50 75 100 125 150 VIMX Figure 6. Over Current Comparator VC (mV) Figure 4. The Linearity of GMx www.richtek.com 12 DS9245B-02 March 2007 RT9245B Over Current Protection CH1:(5V/Div) CH2:(5V/Div) PWM For some case with preferable current ratio instead of current balance, the corresponding technique is provided. Due to different physical environment of each channel, it is necessary to slightly adjust current loading between channels. Figure 9 shows the application circuit of GM for current ratio requirement. Applying KVL along L+DCR branch and R1+C//R2 branch : L dIL V dV + DCR × IL = R1( C + C C ) + VC dt R2 dt dVC R1 + R 2 = R1C + VC dt R2 R2 For VC = DCR × IL R1 + R 2 VSS Time (25ms/Div) Figure 7. The Over Current Protection in the soft start interval Look for its corresponding conditions : dIL dI + DCR × IL = (R1//R2)× C × DCR × L + DCR × IL dt dt L Let = (R1//R2)× C DCR L Over Current Protection CH1:(5V/Div) CH2:(5V/Div) Thus if PWM L = (R1//R2) × C DCR Then VC = R2 × DCR × IL R1+ R2 VSS Time (25ms/Div) With internal current balance function, this phase would share (R1+R2)/R2 t imes current than other phases. Figure 10 & 11 show different settings for the power stages. Figure 12 shows the performance of current ratio compared with conventional current balance function in Figure 13. IL 0.3uH 0.6m Figure 8. Over Current Protection at steady state Current Ratio Setting IL L DCR +VCR1 C R2 470 1uF 470 Figure 10. GM4 Setting for current ratio function IL 0.3uH 0.6m Figure 9. Application circuit for current ratio setting 470 1uF Figure 11. GM1~3 Setting for current ratio function DS9245B-02 March 2007 www.richtek.com 13 RT9245B Current Ratio Function 35 30 25 Load Line without dead zone at light loads 1.31 IL4 1.3 1.29 w/o Dead Zone Compensation RCSN open I L (A ) 20 15 10 5 0 0 15 30 45 60 75 IL3 IL2 IL1 V CORE (V) 1.28 1.27 1.26 1.25 1.24 1.23 RCSN = 82k w/i Dead Zone Compensation 90 0 5 10 15 20 25 I OUT (A) I OUT (A) Figure 12 ILX Figure 14 LX RLX CX +VX + IL1 IL2 GMx Ix VOUT Current Balance Function 30 RX IL3 IL4 25 20 IL (A) RCSN RCSN2 15 10 5 0 0 20 40 60 Figure 15. Application circuit of GM Referring to Figure 15, IX is expressed as : 80 100 IOUT (A) IX = VOUT ILX_50% x RLX ILX_50% x RLX + + RCSN2 RCSN2 RCSN (1) Figure 13 Dead Zone Elimination RT9245B samples and holds inductor current at 50% period by time-sharing sourcing a current IX to RCSN. At light load condition when inductor current is not balance, voltage VX across the sensing capacitor would be negative. It needs a negative IX to sense the voltage. However, RT9245B CANNOT provide a negative IX and consequently cannot sense negative inductor current. This results in dead zone of load line performance as shown in Figure 14. Therefore a technique as shown in Figure 15 is required to eliminate the dead zone of load line at light load condition. www.richtek.com 14 where ILX_50% is the of inductor current at 50% period. To make sure RT9245B could sense the inductor current, right hand side of Equation (1) should always be positive: VOUT ILX_50% x RLX ILX_50% x RLX + + ≥0 RCSN2 RCSN2 RCSN (2) Since RCSN2 >> RCSN in practical application, Equation (2) could be simplified as : VOUT ILX_50% x RLX ≥ RCSN2 RCSN Figure 14 shows that dead zone of load line at light load is eliminated by applying this technique. DS9245B-02 March 2007 RT9245B VID on the Fly With external pull up resistors tied to VID pins, RT9245B converters different VID codes from CPU into output voltage. Figure 16 and Figure 17 show the waveforms of VID on the fly function. Output Voltage Offset Function To meet AMD K8 requirement of initial offset of load line, RT9245B provides programmable initial offset function. External resistor RVOSS and voltage source at VOSS pin V generate offset current IVOSS = VOSS R VOSS , where VVOSS is 1V typical. One quarter of IVOSS f lows through RB1 as shown in Figure 18. Error amplifier would hold the inverting pin equal to VDAC - VADJ. Thus output voltage is subtracted from VDAC - VADJ for a constant offset voltage. RFB1 VCORE = VDAC - VADJ 4 × R VOSS A positive output voltage offset is possible by connecting RVOSS to VDD instead of to GND. Please note that when RVOSS is connected to VDD, VVOSS is VDD − 2V typically and half of IVOSS flows through RFB1. VCORE is rewritten as: VCORE = VDAC - VADJ + RFB1 RVOSS VID on the Fly (Falling) PWM VCORE VFB CH3:(500mV/Div) CH4:(1V/Div) CH1:(5V/Div) CH2:(500mV/Div) VID5 VDAC = 1.500, IOUT = 5A Time (25 µs/Div) Voltage Offset Function 1.284 1.282 Figure 16 VID on the Fly (Rising) V CORE (V) CH3:(500mV/Div) CH4:(1V/Div) CH1:(5V/Div) CH2:(500mV/Div) 1.28 1.278 1.276 1.274 1.272 1.27 1.268 50 60 70 80 90 100 110 PWM VCORE VFB VID5 VDAC = 1.500, IOUT = 5A ROSS (kΩ) (k Figure 19 Time (25 µs/Div) Figure 17 Load Line Setting and Thermal Compensation VADJ = 8 x AVG(IX) x RADJ 1/4 IVOSS RB1 EA + VDAC-VADJ VOUT = VDAC - VADJ AVG(IX) is a PTC current. By properly use an NTC resistor at ADJ. Load line can be thermally compensated. Figure 18. Offset Setting DS9245B-02 March 2007 www.richtek.com 15 RT9245B PGOOD Function During start-up, RT9245B will detect 5VCC and 12VIN (through DVD pin). In Figure 21, 5VCC or 12VIN is not ready during T1. V(SS) (in Figure 20) is pulled to GND by FAULT. V(EAP) is also equal to GND. V(FB) and VOUT will try to follow V(EAP) thus both V(FB) and VOUT are equal to GND during T1. During T2, both 5VCC and 12VIN are ready, FAULT = low, OPSS starts charging up CSS. In the design of RT9245B, ISS (the maximal current sink and source capability of OPSS) is limited and time-variant. During T2 (V1 = 0.4V > V(SS) > 0), ISS(T2) is equal to about 10uA. T2 = CSS x V1 ISS(T2) ≅ 4x10 4 x CSS FAULT SS CSS If the fault condition is OV, V(SS) and PGOOD will be pulled low immediately also. RT9245B will try to turn on low side MOSFET and turn off high side MOSFET. VOUT will fall quickly to protect CPU from high voltage. The typical waveform is shown in Figure 23. Z2 VOUT 5VCC VDAC + OPSS N1 EAP Z1 FB EA + COMP After V(SS) > V1, ISS changes to about 20uA. The rising speed of V(SS) becomes about 2 times faster than in T1. In Figure 20, MOSFET N1 will turn on only if V(SS) > VTH_N1 (threshold voltage of N1) ≅ 0.7V = V2. Before N1 turns on, V(EAP) is still 0V. T3 = CSS x (V2 - V1) ≅ 1.5x10 4 x CSS ISS(T3) Figure 20. Soft Start Circuit 5VCC_ready and DVD_ready PGOOD After V(SS) > V2, MOSFET N1 turns on, V(EAP) starts rising. ISS(T4) is still equal to about 20uA. V(SS,EAP) is equal to VTH_N1. Due to the body effect of MOSFET N1, VTH_N1 increases with higher V(EAP). For example, if VOUT target is 1.4V, V(SS,EAP) will be equal to about 0.7V at the beginning of T4 and equal to about 1.1V at the end of T4. T4 = CSS x (V4 - V2) ≅ 9x10 4 x CSS ISS(T4) V4 V(SS) V3 V2 V1 T1 T2 T3 T4 T5 T6 VOUT At the end of T4, VOUT is very close to the target (within the range of ±40mV). An internal 1ms timer starts. After about 1ms(T5), The open-drain output PGOOD releases. PGOOD Figure 21. Soft Start Waveform After PGOOD releases, ISS(T6) becomes about 320uA to accelerate OPSS. RT9245B enters normal operation mode and is capable to follow VID on the fly. When any of the fault conditions happens, V(SS) and PGOOD will be pulled low immediately. If the fault condition is one of 5VCC low, DVD low, OC or VID_OFF, RT9245B will try to turn off both high side MOSFET and low side MOSFET. VOUT will fall slowly to avoid negative VOUT. The typical waveform is shown in Figure 22. V(SS) VOUT 5VCC_Low + DVD_Low + OC + VID_OFF Figure 22. Waveform for 5VCC_Low, DVD_Low, OC or VID_OFF DS9245B-02 March 2007 www.richtek.com 16 RT9245B PGOOD EA Rising Slew Rate VFB V(SS) VOUT OV Figure 23. Waveform for OV Error Amplifier Characteristic For fast response of converter to meet stringent output current transient response, RT9245B provides large slew rate capability and high gain-bandwidth performance. VCOMP CH1:(500mV/Div) CH2:(2V/Div) Time (250ns/Div) Figure 25. EA Falling Transient with 10pF Loading; Slew Rate = 8V/us 4.7k EA Falling Slew Rate B 4.7k EA + VDAC A VFB Figure 26. Gain-Bandwidth Measurement by signal A divided by signal B VCOMP CH1:(500mV/Div) CH2:(2V/Div) Time (250ns/Div) Figure 24. EA Rising Transient with 10pF Loading; Slew Rate = 8V/us DS9245B-02 March 2007 www.richtek.com 17 RT9245B 0dB 180 ° Figure 27. EA Frequency Response with closed loop gain set at 0db to observe gain-bandwidth product; -3dB at 10.86MHz Design Procedure Suggestion a.Output filter pole and zero (Inductor, output capacitor value & ESR). b.Error amplifier compensation & sawtooth wave amplitude (compensation network). c.Kelvin sense for VCORE. Current Loop Setting a.GM amplifier S/H current (current sense component DCR, CSN pin external resistor value). b.Over-current protection trip point (RIMAX resistor). VRM Load Line Setting a.Droop amplitude (ADJ pin resistor). b.No load offset (RCSN2) c.DAC offset voltage setting (VOSS pin & compen- sation network resistor RB1). Power Sequence & SS DVD pin external resistor and SS pin capacitor. PCB Layout a.Kelvin sense for current sense GM amplifier input. b.Refer to layout guide for other items. Voltage Loop Setting Design Example Given: Apply for four phase converter VIN = 12V VCORE = 1.4V ILOAD = 30A to 125A VDROOP = 95mV with load (1mΩ Load Line) OCP trip point set at 40A for each channel (S/H) DCR = 0.6mΩ of inductor at 25°C L = 0.3µH COUT = 5600µF with 1mΩ equivalent ESR. www.richtek.com 18 DS9245B-02 March 2007 RT9245B 1. Compensation Setting a. Modulator Gain, Pole and Zero: From the following formula: Modulator Gain = VIN/VRAMP = 12/1.9 = 6.3 (i.e 16dB) where VRAMP : Ramp amplitude of saw-tooth wave LC Filter Pole = 3.88kHz and ESR Zero = 28kHz b. EA Compensation Network: Select RB1 = 1.5k, RB2 = 15k, C1 = 2.7nF, C2 = 5.6pF, C3 = 680pF and use the Type 3 compensation scheme shown in Figure 28. By calculation. 1 = 156kHz 2π x RB1 x C3 1 FZ2 = = 3.9kHz 2π x RB2 x C1 1 FP = = 5.8kHz 2π x RB2 x (C2//C1) Middle Band Gain = 10 (i.e. 20dB) FZ1 = 3. Over-Current Protection Setting Consider the temperature coef f icient of copper 3900ppm/°C, 1 VIMAX × 2 RIMAX 1 1.690V × 2 RIMAX ⇔ ⇔ 1 IL × DCR × 3 R COMMON 1 40A × 1.39mΩ × 3 330Ω Figure 28. Type 3 compensation network of EA The over all loop gain with load is shown in Figure 29 to Figure 31. C3 680pF RB1 1.5k C2 5.6pF RB2 C1 15k 2.7nF EA + Let RIMAX = 14kΩ 4. Soft-Start Capacitor Selection For most application cases, 0.1µF is a good engineering value. Figure 29. The Frequency Response with No Load DS9245B-02 March 2007 www.richtek.com 19 RT9245B Figure 30. The Frequency Response with Middle Load Figure 31. The Frequency Response with Heavy Load www.richtek.com 20 DS9245B-02 March 2007 RT9245B Layout Guide Place the high-power switching components first, and separate them from sensitive nodes. 1. Most critical path: the current sense circuit is the most sensitive part of the converter. The current sense resistors tied to CSP1,2,3,4 and CSN should be located not more than 0.5 inch from the IC and away from the noise switching nodes. The PCB trace of sense nodes should be parallel and as short as possible. 2. Switching ripple current path: a. Input capacitor to high side MOSFET. b. Low side MOSFET to output capacitor. c. The return path of input and output capacitor. d. Separate the power and signal GND. e. The switching nodes (the connection node of high/low side MOSFET and inductor) is the most noisy points. Keep them away from sensitive small-signal node. f. Reduce parasitic R, L by minimum length, enough copper thickness and avoiding of via. 3. MOSFET driver should be closed to MOSFET. 4. The compensation, bypass and other function setting components should be near the IC and away from the noisy power path. SW1 L1 VIN RIN CIN L2 SW2 VOUT COUT RL V Figure 32. Power Stage Ripple Current Path DS9245B-02 March 2007 www.richtek.com 21 RT9245B +12V 0.1uF VCC BOOT UGATE PWM PHASE CIN LGATE PGND CSPx ADJ GND CBOOT LO1 Next to IC +12V or +5V PWM RT VOSS SGND RCSN COMP CC VCC CBP Next to IC +5VIN VCORE COUT RT9619 RT9245B CSN FB RC Locate next to FB Pin R FB Locate near MOSFETs For Thermal Couple Figure 33. Layout Consideration Figure 34. Layout of power stage www.richtek.com 22 DS9245B-02 March 2007 RT9245B Outline Dimension D L E E1 e A A1 b A2 Symbol A A1 A2 b D e E E1 L Dimensions In Millimeters Min 0.850 0.050 0.800 0.178 9.601 0.650 6.300 4.293 0.450 6.500 4.496 0.762 Max 1.200 0.152 1.050 0.305 9.804 D imensions In Inches Min 0.033 0.002 0.031 0.007 0.378 0.026 0.248 0.169 0.018 0.256 0.177 0.030 Max 0.047 0.006 0.041 0.012 0.386 28-Lead TSSOP Plastic Package Richtek Technology Corporation Headquarter 5F, No. 20, Taiyuen Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)5526789 Fax: (8863)5526611 Richtek Technology Corporation Taipei Office (Marketing) 8F, No. 137, Lane 235, Paochiao Road, Hsintien City Taipei County, Taiwan, R.O.C. Tel: (8862)89191466 Fax: (8862)89191465 Email: marketing@richtek.com DS9245B-02 March 2007 www.richtek.com 23