®
RT9259A
12V Synchronous Buck PWM DC/DC and Linear Power
Controller
General Description
Features
The RT9259A is a dual-channel DC/DC controller
specifically designed to deliver high quality power where
12V power source is available. This part consists of a
synchronous buck controller and an LDO controller. The
synchronous buck controller integrates MOSFET drivers
that support 12V+12V bootstrapped voltage for high
efficiency power conversion. The bootstrap diode is builtin to simplify the circuit design and minimize external
part count. The LDO controller drives an external NMOSFET for lower power requirement.
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Other features include adjustable operation frequency,
internal soft start, under voltage protection, over current
protection and shut down function. With the above
functions, this part provides customers a compact, high
efficiency, well-protected and cost-effective solution. This
part comes to SOP-14 package.
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Ordering Information
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RT9259A
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Package Type
S : SOP-14
Lead Plating System
P : Pb Free
G : Green (Halogen Free and Pb Free)
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Applications
RoHS compliant and compatible with the current require-
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ments of IPC/JEDEC J-STD-020.
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Graphic Card GPU, Memory Core Power
Graphic Card Interface Power
Motherboard, Desktop and Servers Chipset and Memory
Core Power
IA Equipments
Telecomm Equipments
Suitable for use in SnPb or Pb-free soldering processes.
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High Power DC/DC Regulators
Note :
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Richtek products are :
`
`
Single 12V Bias Supply
Support Dual Channel Power Conversion
` One Synchronous Rectified Buck PWM Controller
` One Linear Controller
Both Controllers Drive Low Cost N-Channel
MOSFETs
Adjustable Frequency from 150kHz to 1MHz
and Free-Run Frequency at 230kHz
Small External Component Count
Output Voltage Regulation
` PWM Controller : ±1% Accuracy
` LDO Controller : ±2% Accuracy
Two Internal VREF Power Support Lower to 0.8V
Adjustable External Compensation
Linear Controller Drives N-MOSFET Pass
Transistor
Fully-Adjustable Outputs
Under Voltage Protection for Both Outputs
Adjustable Over Current Protection
RoHS Compliant and 100% Lead (Pb)-Free
Pin Configurations
(TOP VIEW)
BOOT
RT_DIS
COMP
FB
DRV
FBL
GND
2
3
4
5
6
7
14
13
12
11
10
9
8
UGATE
PHASE
PGND
LGATE
OCSET
VREF
VCC12
SOP-14
Copyright © 2012 Richtek Technology Corporation. All rights reserved.
DS9259A-04 March 2012
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
1
RT9259A
Marking Information
RT9259APS
RT9259APS : Product Number
RT9259A
PSYMDNN
YMDNN : Date Code
RT9259AGS
RT9259AGS : Product Number
RT9259A
GSYMDNN
YMDNN : Date Code
Typical Application Circuit
VCC
+12V
VIN1
+3.3V/+5V/+12V
CIN
RT9259A
VIN2
+5V to +12V
1
8
Q3
VOUT2
COUT2
5
6
2
7
BOOT
VCC12
UGATE
DRV
PHASE
FBL
LGATE
RT_DIS
PGND
GND
FB
9
VREF
10 OCSET
COMP
14
Q1
13
11
12
LOUT1
VOUT1
Q2
COUT
4
3
ROCSET
Copyright © 2012 Richtek Technology Corporation. All rights reserved.
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is a registered trademark of Richtek Technology Corporation.
DS9259A-04 March 2012
RT9259A
Functional Pin Description
BOOT (Pin 1)
VREF (Pin 9)
Bootstrap supply for the upper gate driver. Connect the
bootstrap capacitor between BOOT pin and the PHASE
pin. The bootstrap capacitor provides the charge to turn
on the upper MOSFET.
0.8V reference voltage output.
RT_DIS (Pin 2)
Connect a resistor from RT_DIS to GND to set frequency.
In addition, if this pin is pulled down towards GND, it will
disable both regulator outputs until released.
COMP (Pin 3)
Buck converter external compensation. This pin is used
to compensate the control loop of the buck converter.
FB (Pin 4)
Buck converter feedback voltage. This pin is the inverting
input of the PWM error amplifier. FB senses the switcher
output through an external resistor divider network.
DRV (Pin 5)
Connect this pin to the gate of an external MOSFET. This
pin provides the drive for the linear regulator’ s pass
MOSFET.
FBL (Pin 6)
Linear regulator feedback voltage. This pin is the inverting
input of the LDO error amplifier and protection monitor.
Connect this pin to an external resistor divider network of
the linear regulator.
GND (Pin 7)
Signal ground for the IC. All voltages levels are measured
with respect to this pin.
OCSET (Pin 10)
Connecting a resistor (ROCSET) from this pin to the source
of the upper MOSFET and the drain of the lower MOSFET
sets the over-current trip point. ROCSET, an internal 40μA
current source, and the lower MOSFET on resistance,
RDS(ON), set the converter over-current trip point (IOCSET)
according to the following Equation :
IOCSET =
40uA × ROCSET − 0.4V
RDS(ON) of the lower MOSFET
LGATE (Pin 11)
Lower gate driver output. Connect to the gate of the lowside power N-Channel MOSFET. This pin is monitored by
the adaptive shoot-through protection circuitry to
determine when the lower MOSFET has turn off.
PGND (Pin 12)
Power ground return for the lower gate driver.
PHASE (Pin 13)
Connect this pin to the source of the upper MOSFET and
the drain of the lower MOSFET. This pin is monitored by
the adaptive shoot-through protection circuitry to
determine when the upper MOSFET has turned off.
UGATE (Pin 14)
Upper gate driver output. Connect to gate of the high-side
power N-Channel MOSFET. This pin is monitored by the
adaptive shoot-through protection circuitry to determine
when the upper MOSFET has turned off.
VCC12 (Pin 8)
Connect this pin to a well-decoupled 12V bias supply. It
is also the positive supply for the lower gate driver, LGATE.
Copyright © 2012 Richtek Technology Corporation. All rights reserved.
DS9259A-04 March 2012
is a registered trademark of Richtek Technology Corporation.
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RT9259A
Function Block Diagram
VCC12
Voltage
Reference
VREF
REF_OUT
0.8V
VREF1
Inhibit
5VDD
POR
-
OC
+
VCC12
+
+
5V
Regulator
0.4V
FBL
DRV
Power
On Reset
Bias
-
0.4V
PH_M
-
SSE
40uA
OCSET
-
Soft-Start
&
Fault Logic
+
VREF2
+
1.5V
+
BOOT
UGATE
Shutdown
SSE
RT_DIS
Inhibit
+
+ EA
-
+
-
PHASE
Driver
Logic
PWM
LGATE
Oscillator
PGND
GND
FB
Copyright © 2012 Richtek Technology Corporation. All rights reserved.
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COMP
is a registered trademark of Richtek Technology Corporation.
DS9259A-04 March 2012
RT9259A
Absolute Maximum Ratings
(Note 1)
Supply Voltage, VCC -------------------------------------------------------------------------------- −0.3V to 15V
BOOT to PHASE ------------------------------------------------------------------------------------- −0.3V to 15V
z PHASE to GND
DC -------------------------------------------------------------------------------------------------------- −0.3V to 15V
< 20ns -------------------------------------------------------------------------------------------------- −5V to 30V
z LGATE to GND
DC -------------------------------------------------------------------------------------------------------- (GND − 0.3V) to (VCC + 0.3V)
< 20ns -------------------------------------------------------------------------------------------------- (GND − 5V) to (VCC + 5V)
z UGATE to GND
DC -------------------------------------------------------------------------------------------------------- (VPHASE − 0.3V) to (VBOOT + 0.3V)
< 20ns -------------------------------------------------------------------------------------------------- (VPHASE − 5V) to (VBOOT + 5V)
z PWM to GND ------------------------------------------------------------------------------------------ −0.3V to 7V
z Power Dissipation, PD @ TA = 25°C
SOP-14 ------------------------------------------------------------------------------------------------- 1.000W
z Package Thermal Resistance (Note 2)
SOP-14, θJA -------------------------------------------------------------------------------------------- 100°C/W
z Junction Temperature -------------------------------------------------------------------------------- 150°C
z Lead Temperature (Soldering, 10 sec.) ---------------------------------------------------------- 260°C
z Storage Temperature Range ----------------------------------------------------------------------- −40°C to 150°C
z ESD Susceptibility (Note 3)
HBM (Human Body Mode) ------------------------------------------------------------------------- 2kV
MM (Machine Mode) --------------------------------------------------------------------------------- 200V
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Recommended Operating Conditions
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(Note 4)
Supply Voltage, VCC -------------------------------------------------------------------------------- 12V ± 10%
Junction Temperature Range ----------------------------------------------------------------------- −40°C to 125°C
Ambient Temperature Range ----------------------------------------------------------------------- −40°C to 85°C
Electrical Characteristics
(VCC = 12V, TA = 25°C unless otherwise specified)
Parameter
Symbol
Test Conditions
Min
T yp
Max
Unit
--
12
15
V
8.8
9.6
10.4
V
0.4
0.78
1.2
V
--
3
--
mA
250
300
350
kHz
--
1.6
--
V
Supply Input
Power Supply Voltage
VCC
Power On Reset
V VCCRTH
Power On Reset Hysteresis
VV CCHYS
Power Supply Current
IVCC
V CC Rising
UGATE, LGATE Open
Oscillator
Free Running Frequency
fOSC
RRT = 110kΩ
Ramp Amplitude
Copyright © 2012 Richtek Technology Corporation. All rights reserved.
DS9259A-04 March 2012
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RT9259A
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
Reference Voltage
PWM Error Amplifier Reference
VREF1
0.792
0.8
0.808
V
Linear Driver Reference
VREF2
0.784
0.8
0.816
V
5
--
--
mA
70
88
--
dB
6
15
--
MHz
3
6
--
V/μs
VBOOT − VUGATE = 1V
--
4
8
Ω
V REF Buffer Source Current
Error Amplifier
DC Gain
Gain-Bandwidth Product
GBW
Slew Rate
SR
CLOAD = 5pF
Gate Driver
VBOOT − VPHASE = 12V,
Upper Drive Source
RUGATE
Upper Drive Sink
RUGATE
VUGATE = 1V
--
4
8
Ω
Lower Drive Source
RLGATE
VCC – VLGATE = 1V
--
4
6
Ω
Lower Drive Sink
RLGATE
VLGATE = 1V
--
2
4
Ω
0.36
0.4
0.45
V
2
3
4
ms
--
−400
--
mV
0.35
0.4
--
V
Protection
Under Voltage Protection
VUVP
Soft-Start Time Interval
TSS
ROCSET = 20kΩ
Over Current Threshold
RT_DIS Shutdown Threshold
Linear Regulator
Output High Voltage
VDRV
9.5
10.3
--
V
Output Low Voltage
VDRV
--
0.1
1
V
Source Current
IDRVSR
2
--
--
mA
Sink Current
IDRVSC
0.5
--
--
mA
Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in
the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may
affect device reliability.
Note 2. θJA is measured at TA = 25°C on a high effective thermal conductivity four-layer test board per JEDEC 51-7.
Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
Copyright © 2012 Richtek Technology Corporation. All rights reserved.
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is a registered trademark of Richtek Technology Corporation.
DS9259A-04 March 2012
RT9259A
Typical Operating Characteristics
Dead Time
Dead Time
No Load, Falling
No Load, Rising
UGATE
UGATE
VIN1
VIN1
PHASE
PHASE
(5V/Div)
LGATE
(5V/Div)
LGATE
Time (25ns/Div)
Time (25ns/Div)
OCP
Power Off
No Load
UGATE
V OUT1
(10V/Div)
(2V/Div)
V REF
IL
(10V/Div)
LGATE
(0.5A/Div)
(10A/Div)
IL
(200mV/Div)
Time (2.5ms/Div)
Time (5μs/Div)
Shut Down
Start Up
Full Load
No Load
VIN1
UGATE
(20V/Div)
(5V/Div)
LGATE
(10V/Div)
RT_Dis
(500mV/Div)
V OUT1
(500mV/Div)
PHASE
RT_Dis
(1V/Div)
V OUT1
(500mV/Div)
Time (5μs/Div)
Copyright © 2012 Richtek Technology Corporation. All rights reserved.
DS9259A-04 March 2012
(10V/Div)
Time (1ms/Div)
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RT9259A
Start Up
Start Up
No Load
ILoad = 20A
ILOAD
(2.5A/Div)
RT_Dis
(500mV/Div)
V OUT1
V OUT1
(500mV/Div)
(500mV/Div)
Time (1ms/Div)
Time (1ms/Div)
Transient Response
Transient Response
UGATE
V OUT
(20V/Div)
(100mV/Div)
(100mV/Div)
V OUT1
(20V/Div)
UGATE
IL
VIN1 = 12V, VOUT1 = 2V
ILOAD1 = 1A to 20A
(10A/Div)
LDO
(10A/Div)
VIN1 = 12V, VOUT1 = 2V
ILOAD1 = 20A to 1A
IL
Time (2.5μs/Div)
Time (10μs/Div)
Transient Response
Under Voltage Protection
LDO
VIN2 = 12V, VOUT2 = 2.5V
ILOAD = 1A to 100mA
VIN2 = 0V
LGATE
(2mV/Div)
(10V/Div)
UGATE
V OUT2
(20V/Div)
IL
COMP
(500mV/Div)
(0.5A/Div)
(1V/Div)
Time (100μs/Div)
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V OUT2
Time (10ms/Div)
is a registered trademark of Richtek Technology Corporation.
DS9259A-04 March 2012
RT9259A
Application Information
The RT9259A is a dual-channel DC/DC controller
specifically designed to deliver high quality power where
12V power source is available. This part consists of a
synchronous buck controller and an LDO controller. The
synchronous buck controller integrates internal MOSFET
drivers that support 12V+12V bootstrapped voltage for high
efficiency power conversion. The bootstrap diode is builtin to simplify the circuit design and minimize external
part count. The LDO controller drives an external NMOSFET for lower power requirement.
Internal 5VDD Regulator
It is highly recommended to power the RT9259A with welldecoupled 12V to VCC12 pin. VCC12 powers the RT9259A
control circuit, low side gate driver and bootstrap circuit
for high side gate driver. A bootstrap diode is embedded
to facilitates PCB design and reduce the total BOM cost.
No external Schottky diode is required. The RT9259A
integrates MOSFET gate drives that are powered from
the VCC12 pin and support 12V + 12V driving capability.
Converters that consist of RT9259A feature high efficiency
without special consideration on the selection of
MOSFETs.
An internal linear regulator regulates VCC12 input to a
5VDD voltage for internal control logic circuit. No external
bypass capacitor is required for filtering the 5VDD voltage.
This further facilitates PCB design and reduces the total
BOM cost.
Power On Reset
The RT9259A automatically initializes upon applying of
input power (at the VCC12) pin. The power on reset
function (POR) continually monitors the input bias supply
voltage at the VCC12 pin. The VCC12V POR level is
typically 9.6V at VCC12V rising.
Frequency Setting and Shut Down
Connecting a resistor RRT from the RT_DIS pin to GND
sets the operation frequency. The relation can be roughly
expressed in the equation.
fOSC ≅ 230kHz + 7700 (kHz)
RRT
Copyright © 2012 Richtek Technology Corporation. All rights reserved.
DS9259A-04 March 2012
When let open, the free running frequency is 230kHz
typically. Figure 1 shows the operation frequency vs. RRT
for quick reference.
1400
1200
1000
f SW (kHz)
Introduction
800
600
400
200
0
10
100
1000
RRT (kΩ)
(kohm)
Figure 1. RT vs. fsw at Low Frequency
Shorting the RT_DIS pin to GND with an external signallevel MOSFET shuts down the device. This allows flexible
power sequence control for specified application. The
RT_DIS pin threshold voltage is 0.4V typically.
VIN1 Detection
The RT9259A continuously generates a 10kHz pulse train
with 1μs pulse width to turn on the upper MOSFET for
detecting the existence of VIN1 after VCC12V POR and
RT_DIS enabled as shown in Figure 2. PHASE pin voltage
is monitored during the detection duration.
If the PHASE voltage crosses 1.5V four times, VIN1
existence is recognized and the RT9259A initiates its soft
start cycle as described in next section.
VIN1 POR_H
PHASE_M
PHASE
+
-
1.5V
UGATE
1st 2nd 3rd 4th PHASE
waveform
Internal Counter will count (VPHASE > 1.5V)
four times (rising & falling) to recognize
VIN1 is ready.
Figure 2
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RT9259A
Soft Start for Synchronous Buck Converter
A built-in soft-start is used to prevent surge current from
power supply input during power on (referring to the
Functional Block Diagram). The error amplifier EA is a
three-input device. SSE or VREF1 whichever is smaller
dominates the behavior non-inverting input. The internal
soft start voltage SSE linearly ramps up to about 4V after
VIN1 existence is recognized with about 2ms delay.
According, the output voltage ramps up smoothly to its
target level. The rise time of output voltage is about 2ms
as shown in Figure 3. VREF1 takes over the behavior EA
when SSE > VREF1.
SSE is also used for LDO soft start. LDO input voltage
VIN2 MUST be ready before SSE starts to ramp up.
Otherwise UVP function of LDO may be triggered and
shut down the RT9259A.
RT_DIS
(500mV/Div)
VIN1 = 12V to 0V
UGATE
(20V/Div)
FB
(500mV/Div)
VOUT
(20V/Div)
Time (10ms/Div)
Figure 4. UVP triggered by FB
VIN2 = 0V
LGATE
(10V/Div)
UGATE
(20V/Div)
COMP
(500mV/Div)
VOUT1
(1V/Div)
UGATE
(20V/Div)
VOUT1
(500mV/Div)
LGATE
(10V/Div)
Time (10ms/Div)
Figure 5. UVP hiccups triggered by FBL
Time (1ms/Div)
Over Current Protection
Figure 3 : Start up by RT_DIS
Under Voltage Protection
The voltages at FB and FBL pin are monitored for under
voltage protection (UVP) after the soft start is completed.
UVP is triggered if one of the feedback voltages is under
(50% x VREFX) with a 30us delay. As shown in Figure 4,
the RT9259A PWM controller is shut down when VFB drops
lower than the UVP threshold. In Figure 5, the RT9259A
shuts down after 4 time UVP hiccups triggered by FBL.
The RT9259A senses the current flowing through lower
MOSFET for over current protection (OCP) by sensing
the PHASE pin voltage as shown in the Functional Block
Diagram. A 40uA current source flows through the external
resistor ROCSET to PHASE pin causes 0.8V voltage drop
across the resistor. OCP is triggered if the voltage at
PHASE pin (drop of lower MOSFET VDS) is lower than −
0.4V when low side MOSFET conducting. Accordingly
inductor current threshold for OCP is a function of
conducting resistance of lower MOSFET RDS(ON) as :
IOCSET =
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10
40 μA × R OCSET - 0.4V
RDS(ON)
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DS9259A-04 March 2012
RT9259A
If MOSFET with RDS(ON) = 16mΩ is used, the OCP
threshold current is about 25A. Once OCP is triggered,
the RT9259A enters hiccup mode and re-soft starts again.
The RT9259A shuts down after 4 time OCP hiccups.
A well-designed compensator regulates the output voltage
to the reference voltage VREF with fast transient response
and good stability.
In order to achieve fast transient response and accurate
output regulation, an adequate compensator design is
necessary. The goal of the compensation network is to
provide adequate phase margin (greater than 45 degrees)
and the highest 0dB crossing frequency. It is also
recommended to manipulate loop frequency response that
its gain crosses over 0dB at a slope of −20dB/dec.
VIN
OSC
Driver
PWM
Comparator
Inductor Current
(20A/Div)
ΔVOSC
L
Driver
+
PHASE
COUT
Time (2.5ms/Div)
Figure 6. Shorted then Start Up
VOUT
ESR
ZFB
COMP
EA
+
IL
(20A/Div)
REF
ZFB
C2
C1
LGATE
(5V/Div)
UGATE
(5V/Div)
Time (5μs/Div)
ZIN
ZIN
C3
R2
VOUT
R3
R1
COMP
EA
+
FB
REF
Figure 8. Closed Loop
Figure 7. Shorted then Start Up (Extended Figure 3)
1) Modulator Frequency Equations
Feedback Compensation
The RT9259A is a voltage mode controller. The control
loop is a single voltage feedback path including a
compensator and modulator as shown Figure 8. The
modulator consists of the PWM comparator and power
stage. The PWM comparator compares error amplifier EA
output (COMP) with oscillator (OSC) sawtooth wave to
provide a pulse-width modulated (PWM) with an amplitude
of VIN at the PHASE node. The PWM wave is smoothed
by the output filter LOUT and COUT. The output voltage (VOUT)
is sensed and fed to the inverting input of the error amplifier.
Copyright © 2012 Richtek Technology Corporation. All rights reserved.
DS9259A-04 March 2012
The modulator transfer function is the small-signal transfer
function of VOUT/VCOMP (output voltage over the error
amplifier output. This transfer function is dominated by a
DC gain, a double pole, and a zero as shown in Figure 10.
The DC gain of the modulator is the input voltage (VIN)
divided by the peak to peak oscillator voltage VOSC. The
output LC filter introduces a double pole, 40dB/decade
gain slope above its corner resonant frequency, and a total
phase lag of 180 degrees. The resonant frequency of the
LC filter expressed as :
1
fLC =
2π L OUT × C OUT
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11
RT9259A
fESR =
1
2π × COUT × ESR
Loop Gain
60
40 40
Compensation
Gain
20
0
0
-20
Modulator
Gain
-40-40
2) Compensation Frequency Equations
The compensation network consists of the error amplifier
and the impedance networks ZC and ZF as shown in
Figure 9.
ZF
-60-60
10Hz
10vdb(vo)
100Hz
vdb(comp2)100
vdb(lo)
1.0KHz
10KHz
1k
10k
Frequency (Hz)
Frequency
100KHz
100k
1.0MHz
1M
Figure 10. Bode Plot
Thermal Considerations
C1
ZC
C2
R2
80 80
Gain (dB)
The ESR zero is contributed by the ESR associated with
the output capacitance. Note that this requires that the
output capacitor should have enough ESR to satisfy
stability requirements. The ESR zero of the output
capacitor expressed as follows :
EA
+
COMP
R1
VOUT
FB
VREF
RF
For continuous operation, do not exceed absolute
maximum operation junction temperature 125°C. The
maximum power dissipation depends on the thermal
resistance of IC package, PCB layout, the rate of
surroundings airflow and temperature difference between
junction to ambient. The maximum power dissipation can
be calculated by following formula :
PD(MAX) = ( TJ(MAX) − TA ) / θJA
Figure 9. Compensation Loop
fZ1 =
1
2π x R2 x C2
fP1 =
1
2π x R2 x C1 x C2
C1 + C2
Figure 10 shows the DC/DC converter's gain vs. frequency.
The compensation gain uses external impedance networks
ZC and ZF to provide a stable, high bandwidth loop. High
crossover frequency is desirable for fast transient
response, but often jeopardize the system stability. In
order to cancel one of the LC filter poles, place the zero
before the LC filter resonant frequency. In the experience,
place the zero at 75% LC filter resonant frequency.
Crossover frequency should be higher than the ESR zero
but less than 1/5 of the switching frequency. The second
pole is placed at half the switching frequency.
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12
Where T J(MAX) is the maximum operation junction
temperature 125°C, TA is the ambient temperature and the
θJA is the junction to ambient thermal resistance.
The junction to ambient thermal resistance θJA is layout
dependent. For SOP-14 package, the thermal resistance
θJA is 100°C/W on the standard JEDEC 51-7 four-layers
thermal test board.
The maximum power dissipation at TA = 25°C can be
calculated by following formula :
PD(MAX) = (125°C − 25°C) / 100°C/W = 1.000W for
SOP-14 package
The maximum power dissipation depends on operating
ambient temperature for fixed T J(MAX) and thermal
resistance θJA. The Figure 11 of derating curves allows
the designer to see the effect of rising ambient temperature
on the maximum power allowed.
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DS9259A-04 March 2012
RT9259A
Maximum Power Dissipation (W)
1.2
4-Layers PCB
1
0.8
SOP-14
0.6
0.4
0.2
0
0
25
50
75
100
125
Ambient Temperature (°C)
Figure 11. Derating Curve of Maximum Power
Dissipation
Layout Consideration
DS9259A-04 March 2012
IL
VOUT
5V/12V
Q1
+
Copyright © 2012 Richtek Technology Corporation. All rights reserved.
IQ1
+
There are two sets of critical components in a DC/DC
converter using the RT9259A. The switching power
components are most critical because they switch large
amounts of energy, and as such, they tend to generate
equally large amounts of noise. The critical small signal
components are those connected to sensitive nodes or
those supplying critical bypass current.
Use a dedicated grounding plane and use vias to ground
all critical components to this layer. Apply another solid
layer as a power plane and cut this plane into smaller
islands of common voltage levels. The power plane should
support the input power and output power nodes. Use
copper filled polygons on the top and bottom circuit layers
for the PHASE node, but it is not necessary to oversize
this particular island. Since the PHASE node is subjected
to very high dV/dt voltages, the stray capacitance formed
between these islands and the surrounding circuitry will
tend to couple switching noise. Use the remaining printed
circuit layers for small signal routing. The PCB traces
between the PWM controller and the gate of MOSFET
and also the traces connecting source of MOSFETs should
be sized to carry 2A peak currents.
+
MOSFETs switch very fast and efficiently. The speed with
which the current transitions from one device to another
causes voltage spikes across the interconnecting
impedances and parasitic circuit elements. The voltage
spikes can degrade efficiency and radiate noise, that results
in over-voltage stress on devices. Careful component
placement layout and printed circuit design can minimize
the voltage spikes induced in the converter. Consider, as
an example, the turn-off transition of the upper MOSFET
prior to turn-off, the upper MOSFET was carrying the full
load current. During turn-off, current stops flowing in the
upper MOSFET and is picked up by the low side MOSFET
or schottky diode. Any inductance in the switched current
path generates a large voltage spike during the switching
interval. Careful component selections, layout of the
critical components, and use shorter and wider PCB traces
help in minimizing the magnitude of voltage spikes.
The power components and the PWM controller should
be placed firstly. Place the input capacitors, especially
the high-frequency ceramic decoupling capacitors, close
to the power switches. Place the output inductor and
output capacitors between the MOSFETs and the load.
Also locate the PWM controller near by MOSFETs. A
multi-layer printed circuit board is recommended. Figure
12 shows the connections of the critical components in
the converter. Note that the capacitors CIN and COUT each
of them represents numerous physical capacitors.
LOAD
IQ2
Q2
GND
GND
LGATE VCC
RT9259A
FB
UGATE
Figure 12. The Connections of the Critical Components
in the Converter
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
13
RT9259A
Outline Dimension
H
A
M
J
B
F
C
I
D
Dimensions In Millimeters
Dimensions In Inches
Symbol
Min
Max
Min
Max
A
8.534
8.738
0.336
0.344
B
3.810
3.988
0.150
0.157
C
1.346
1.753
0.053
0.069
D
0.330
0.508
0.013
0.020
F
1.194
1.346
0.047
0.053
H
0.178
0.254
0.007
0.010
I
0.102
0.254
0.004
0.010
J
5.791
6.198
0.228
0.244
M
0.406
1.270
0.016
0.050
14–Lead SOP Plastic Package
Richtek Technology Corporation
5F, No. 20, Taiyuen Street, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: (8863)5526789
Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should
obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot
assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be
accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.
www.richtek.com
14
DS9259A-04 March 2012
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