RT9605AGQV

Preliminary RT9605A Triple-Channel Synchronous-Rectified Buck MOSFET Driver General Description The RT9605A is a high frequency, triple-channel synchronous-rectified buck MOSFET driver specifically designed to drive six power N-MOSFETs. The part is promoted to pair with RichTek's multiphase buck PWM controller family for high-density power supply implementation. The output drivers of RT9605A can efficiently switch power MOSFETs at frequency 300kHz typically. Operating in higher frequency should consider the thermal dissipation carefully. Each driver of RT9605A is capable to drive a 3nF load in 30/40ns rising/falling time with little propagation delay from input transition to the gate of the power MOSFET. The device implements bootstrapping on the upper gate with only an external capacitor and a diode required. This reduces circuit complexity and allows the use of higher performance, cost effective N-MOSFETs. All drivers incorporate adaptive shoot-through protection to prevent upper and lower MOSFETs from conducting simultaneously and shorting the input supply. The RT9605A also detects the fault condition during initial start-up prior to the multi-phase PWM controller takes control. As a result, the input supply will latch into the shutdown state. The RT9605A comes to a small footprint package with VQFN-24L 4x4 package. Features Drive Six N-MOSFETs for 3-Phase Buck PWM Control Adaptive Shoot-Through Protection Support High Switching Frequency Fast Output Rise/Fall Time Propagation Delay 40ns Tri-State Input for Bridge Shutdown Upper MOSFET Direct Short Protection Small 24-Lead VQFN Package RoHS Compliant and 100% Lead (Pb)-Free Applications CPU Core Voltage Supplies on Motherboard High Frequency Low Profile DC-DC Converters High Current Low Voltage DC-DC Converters Marking Information For marking information, contact our sales representative directly or through a Richtek distributor located in your area, otherwise visit our website for detail. Pin Configurations (TOP VIEW) Ordering Information PHASE1 RT9605A Package Type QV : VQFN-24L 4x4 (V-Type) Operating Temperature Range P : Pb Free with Commercial Standard G : Green (Halogen Free with Commercial Standard) UGATE1 BOOT1 NC PWM1 PWM2 GND 1 2 3 4 5 6 24 23 22 21 20 19 18 17 16 PHASE2 LGATE1 LGATE2 PVCC1 PVCC2 GND UGATE2 BOOT2 PVCC3 LGATE3 GND GND 15 14 25 13 Note : Richtek Pb-free and Green products are : RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020. Suitable for use in SnPb or Pb-free soldering processes. 100% matte tin (Sn) plating. 7 8 9 10 11 12 VDD BOOT3 PWM3 VQFN-24L 4x4 All brandname or trademark belong to their owner respectively DS9605A-05 August 2007 www.richtek.com 1 UGATE3 PHASE3 GND RT9605A Typical Application Circuit Preliminary PHASE2 L1 0.5uH 12V VIN 1uH C8 1000uF C1 33pF Optional C2 R2 5V C4 4.7uF C9 1uF C10 to C13 1500uF x 4 D1 C14 1uF R18 0 12V Q1 C15 1uF R20 0 C24 to C35 1000uF x 12 R19 2.2 C16 3.3uF Q3 Q2 17 UGATE2 R1 15k C3 10nF R3 3k 19 PHASE2 21 PVCC2 20 LGATE2 3 NC Q7 PHASE3 C23 3.3nF C21 1uF Q8 R27 2.2 R26 0 D3 C22 1uF 12V VIN L2 0.5uH VCORE Q9 16 7 15 14 10 11 Optional C5 1uF R17 R R17 R C7 1uF VCORE R R16 PHASE3 BOOT2 PWM3 PWM2 PWM1 BOOT1 UGATE1 PHASE1 R4 110k VID5 VID0 VID1 R7 VID2 VID3 VID4 R8 6.8k R9 3.3k R10 5.1k 13k R5 R6 56k 27k RT9605A LGATE3 PVCC3 R25 14 0 C36 to C39 10uF x 4 16 13 PWM1 5 COMP 3 FB VDD RDROOP 6 15 11 12V PI 2 DACQ R11 1.8k RT8800 GND PWM3 PWM2 ISP3 5 4 2 GND PHASE3 UGATE3 10 BOOT3 PVCC1 LGATE1 VDD 9 1 DACFB ICOMMON 9 PGOOD DVD 4 RT 7 R12 10k 3.3V ISP2 ISP1 12 R13 12V 27k R14 3k Optional C6 1uF Optional PHASE2 C17 1uF PHASE1 D2 1 24 R21 0 22 12V 23 C18 1uF 8 R23 10 R22 0 C19 1uF 8 5VSB PHASE1 L3 0.5uH R15 16k 430 Optional RICOMMON2 RICOMMON1 Q4 12V VIN R24 2.2 Q5 C20 3.3nF Q6 Functional Pin Description UGATE1 (Pin 1), UGATE2 (Pin 17), UGATE3 (Pin 10) Upper Gate Drive Output. Should be connected to the upper MOSFET gate. BOOT1 (Pin 2), BOOT2 (Pin 16), BOOT3 (Pin 9) Floating bootstrap supply pin for the upper gate drive. Connect the bootstrap capacitor between this pin and the PHASE pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET. NC (Pin 3) No connected. PWM1 (Pin 4), PWM2 (Pin 5), PWM3 (Pin 7) PWM input control signal. Connect this pin to the PWM output of the controller. If the PWM signal enters and remains within the shutdown window, are both UGATE and LGATE are drived low, disabling the output MOSFETs. LGATE1 (Pin 23), LGATE2 (Pin 20), LGATE3 (Pin 14) Lower Gate Drive Output. Should be connected to the lower MOSFET gate. PVCC1 (Pin 22), PVCC2 (Pin 21), PVCC3 (Pin 15) Supply Input. Connect to +12V supply. Place a bypass capacitor between this pin and PGND. All brandname or trademark belong to their owner respectively www.richtek.com 2 DS9605A-05 August 2007 GND [Pin 6, 12, 13, 18, Exposed Pad (25)] Chip power ground. The exposed pad must be soldered to a large PCB and connected to GND for maximum power dissipation. VDD (Pin 8) Supply Input. Connect to +5V stand-by power. Place a bypass capacitor between this pin and GND. PHASE1 (Pin 24), PHASE2 (Pin 19), PHASE3 (Pin 11) Upper driver return. Should be connected to the common node of upper and lower MOSFETs. The PHASE voltage is monitored for adaptive shoot-through protection. Preliminary Function Block Diagram BOOT1 RT9605A VDD UGATE1 Short-Through Protection PWM1 PHASE1 PVCC1 LGATE1 GND VDD BOOT2 UGATE2 PWM2 Control Logic Short-Through Protection PHASE2 PVCC2 LGATE2 GND VDD BOOT3 UGATE3 Short-Through Protection PWM3 PHASE3 PVCC3 LGATE3 GND Timing Diagram PWM TPDUGATE TRUGATE TFUGATE UGATE LGATE TFLGATE TRLGATE TPDLGATE All brandname or trademark belong to their owner respectively DS9605A-05 August 2007 www.richtek.com 3 RT9605A Absolute Maximum Ratings Preliminary (Note 1) 15V 7V Supply Voltage, PVCC ----------------------------------------------------------------------------------Supply Voltage, VDD ------------------------------------------------------------------------------------PHASE to GND DC -----------------------------------------------------------------------------------------------------------< 200ns ----------------------------------------------------------------------------------------------------BOOT to PHASE ----------------------------------------------------------------------------------------BOOT to GND DC -----------------------------------------------------------------------------------------------------------< 200ns ----------------------------------------------------------------------------------------------------PHASE to GND ------------------------------------------------------------------------------------------PWM Input Voltage -------------------------------------------------------------------------------------UGATE -----------------------------------------------------------------------------------------------------LGATE -----------------------------------------------------------------------------------------------------Package Thermal Resistance (Note 4) VQFN-24L 4x4, θJA -------------------------------------------------------------------------------------Lead Temperature (Soldering, 10 sec.) -------------------------------------------------------------Storage Temperature Range --------------------------------------------------------------------------ESD Susceptibility (Note 2) HBM (Human Body Mode) ----------------------------------------------------------------------------MM (Machine Mode) ------------------------------------------------------------------------------------- −5V to 15V −10V to 30V 15V −0.3V to VCC+15V −0.3V to 42V −4V to 15V GND - 0.3V to 7V VPHASE - 0.3V to VBOOT + 0.3V GND - 0.3V to VPVCC + 0.3V 67° C/W 260°C −40°C to 150°C 1kV 100V Recommended Operating Conditions (Note 3) Supply Voltage, VDD ------------------------------------------------------------------------------------- 12V ±10% Ambient Temperature Range --------------------------------------------------------------------------- 0°C to 70°C Junction Temperature Range --------------------------------------------------------------------------- 0°C to 125°C Electrical Characteristics Parameter VDD Supply Current Operation Current Power-On Reset POR Threshold Hysteresis PWM Input Input Current Floating Voltage PWM Threshold (Recommended Operating Conditions, TA = 25°C unless otherwise specified) Symbol IVDD PVCCRTH PVCCHYS IPWM VPWMFL VPWMRTH VPWMFTH Test Conditions Frequency = 250kHz Min -6 -- Typ -6.5 0.15 300 2.2 3.7 1.38 Max 10 7.5 -500 2.6 4.3 1.5 Units mA PVCC Rising V V μA V V V VPWM_IN = 0V or 5V PVCC = 12V PWM_IN Rising PWM_IN Falling 200 1.8 3.3 1.0 To be continued All brandname or trademark belong to their owner respectively www.richtek.com 4 DS9605A-05 August 2007 Preliminary Parameter Output UGATE Rise Time UGATE Fall Time LGATE Rise Time LGATE Fall Time UGATE Turn-Off Propagation Delay LGATE Turn-Off Propagation Delay Shutdown Window TRUGATE TFUGATE TRLGATE TFLGATE TPDUGATE TPDLGATE PVCC = 12V, 3nF load PVCC = 12V, 3nF load PVCC = 12V, 3nF load PVCC = 12V, 3nF load PVCC = 12V, 3nF load PVCC = 12V, 3nF load ------1.0 Symbol Test Conditions Min RT9605A Typ 30 40 30 30 40 35 -Max ------4.3 Units ns ns ns ns ns ns V Note 1. Stresses listed as the above “ Absolute Maximum Ratings” may cause permanent damage to the device. These are for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. Note 2. Devices are ESD sensitive. Handling precaution recommended. Note 3. The device is not guaranteed to function outside its operating conditions. Note 4. θJA i s measured in the natural convection at T A = 25 °C on a low effective thermal conductivity test board of JEDEC 51-3 thermal measurement standard. All brandname or trademark belong to their owner respectively DS9605A-05 August 2007 www.richtek.com 5 RT9605A Preliminary Typical Operating Characteristics Efficiency vs. Output Current 0.86 0.84 Dead Time Phase 1, Heavy Load VIN = 12V, IOUT = 30A VIN = 12V IR MOSFET Efficiency (%) 0.82 0.8 0.78 0.76 UGATE (5V/Div) PHASE (5V/Div) LGATE (5V/Div) 0.74 0 10 20 30 40 50 60 70 80 90 100 Time (50ns/Div) Output Current (A) Dead Time Phase 1, Heavy Load VIN = 12V, IOUT = 30A UGATE (5V/Div) Dead Time Phase 1, No Load VIN = 12V, IOUT = 30A UGATE (5V/Div) PHASE (5V/Div) PHASE (5V/Div) LGATE (5V/Div) LGATE (5V/Div) Time (50ns/Div) Time (50ns/Div) Dead Time Phase 1, No Load VIN = 12V, IOUT = 30A UGATE (5V/Div) Dead Time Phase 2, Heavy Load VIN = 12V, IOUT = 30A UGATE (5V/Div) PHASE (5V/Div) PHASE (5V/Div) LGATE (5V/Div) LGATE (5V/Div) Time (50ns/Div) Time (50ns/Div) All brandname or trademark belong to their owner respectively www.richtek.com 6 DS9605A-05 August 2007 Preliminary RT9605A Dead Time Phase 2, No Load VIN = 12V, IOUT = 30A UGATE (5V/Div) Dead Time Phase 2, Heavy Load VIN = 12V, IOUT = 30A UGATE (5V/Div) PHASE (5V/Div) PHASE (5V/Div) LGATE (5V/Div) LGATE (5V/Div) Time (50ns/Div) Time (50ns/Div) Dead Time Phase 2, No Load VIN = 12V, IOUT = 30A UGATE (5V/Div) Dead Time Phase 3, Heavy Load VIN = 12V, IOUT = 30A UGATE (5V/Div) PHASE (5V/Div) PHASE (5V/Div) LGATE (5V/Div) LGATE (5V/Div) Time (50ns/Div) Time (50ns/Div) Dead Time Phase 3, Heavy Load VIN = 12V, IOUT = 30A UGATE (5V/Div) Dead Time Phase 3, No Load VIN = 12V, IOUT = 30A UGATE (5V/Div) PHASE (5V/Div) PHASE (5V/Div) LGATE (5V/Div) LGATE (5V/Div) Time (50ns/Div) Time (50ns/Div) All brandname or trademark belong to their owner respectively DS9605A-05 August 2007 www.richtek.com 7 RT9605A Dead Time Preliminary Power On IOUT = 0A VIN (10V/Div) Phase 3, No Load VIN = 12V, IOUT = 30A UGATE (5V/Div) UGATE (20V/Div) PHASE (5V/Div) PHASE (10V/Div) LGATE (5V/Div) LGATE (10V/Div) Time (50ns/Div) Time (1ms/Div) Power Off IOUT = 0A Power Off IOUT = 0A VIN (10V/Div) UGATE (20V/Div) VIN (10V/Div) UGATE (20V/Div) PHASE (10V/Div) PWM (10V/Div) LGATE (10V/Div) LGATE (10V/Div) Time (50ms/Div) Time (50ms/Div) Power Off IOUT = 0A VOUT (2V/Div) VIN (10V/Div) UGATE (20V/Div) PHASE (10V/Div) Time (250ms/Div) All brandname or trademark belong to their owner respectively www.richtek.com 8 DS9605A-05 August 2007 Preliminary Application Information The RT9605A is designed to drive three sets of both high side and low side N-Channel MOSFET through externally input PWM control signal. It has power-on protection function which held UGATE and LGATE low before PVCC rising across the threshold voltage. After the initialization, the PWM signal takes the control. The rising PWM signal first forces the LGATE turns low then UGATE is allowed to go high just after a non-overlapping time to avoid shootthrough. The falling of PWM signal first forces UGATE to go low. When UGATE and PHASE reach a predetermined low level, LGATE is allowed to turn high. The nonoverlapping function is also presented between UGATE and LGATE signal transient. The PWM signal is acted as "High" if above the rising threshold and acted as "Low" if below the falling threshold. Any signal level remaining within the shutdown window is considered as "tri-state", the output drivers are disabled and both MOSFET gates are pulled and held low. If the PWM signal floating, the pin will be kept at 2.1V by the internal divider and provide the PWM controller with a recognizable level. The RT9605A typically operates at frequency of 200kHz to 300kHz. It shall be noted that to place a 1N4148 or schottky diode between the PVCC and BOOT pin as shown in the typical application circuit. Driving Power MOSFETs The DC input impedance of the power MOSFET is extremely high. When Vgs at 12V, the gate draws the current only few nano-amperes. Thus once the gate has been driven up to "ON" level, the current could be negligible. However, the capacitance at the gate to source terminal should be considered. It requires relatively large current to source and sink the gate rapidly. It also needs to switch drain current on and off with high speed. The required gate drive currents are calculated as follows. D1 d1 VIN Cgd1 Igs1 Ig2 Igd2 g1 g2 Igs2 Cgs1 s1 RT9605A L VOUT Cgd2 Igd1 Ig1 d2 D2 Cgs2 s2 GND Vg1 VPHASE +12V t Vg2 12V t Figure 1. Equivalent Circuit and Associated Waveforms In Figure 1, the current Ig1 and Ig2 are required to move the gate up to 12V. The operation consists of charging Cgd and Cgs. Cgs1 and Cgs2 are the capacitances from gate to source of the high side and the low side power MOSFETs, respectively. In general data sheets, the Cgs is referred as "Ciss" which is the input capacitance. Cgd1 and Cgd2 are the capacitances from gate to drain of the high side and the low side power MOSFETs, respectively and referred to the data sheets as " C rss " t he reverse transfer capacitance. For example, tr1 and tr2 are the rising time of the high side and the low side power MOSFETs respectively, the required current Igs1 and Igs2 are showed , below: Igs1 = C gs1 dVg1 dt dVg2 dt = C gs1 × 12 t r1 C gs2 × 12 t r2 (1) Igs2 = C gs2 = (2) All brandname or trademark belong to their owner respectively DS9605A-05 August 2007 www.richtek.com 9 RT9605A Preliminary Layout Consideration Figure 2 shows the schematic circuit of a two-phase synchronous buck converter to implement the either phase of RT9605A. The converter operates at VIN 12V. L1 D1 C2 1uF CB 1uF Q1 L2 VCORE + C3 1500uF 2uH Q2 PHB83N03LT PHB95N03LT + R1 C4 10 1uF BOOTX PVCCX UGATEX PHASEX PWMX RT9605A PWM 12V VIN 12V Before driving the gate of the high side MOSFET up to 12V (or 5V), the low side MOSFET has to be off; and the high side MOSFET is turned off before the low side is turned on. From Figure 1, the body diode "D2" had been turned on before high side MOSFETs turned on. dV 12V Igd1 = C g1 = C gd1 dt t r1 (3) 1.2uH C1 1000uF Before the low side MOSFET is turned on, the Cgd2 have been charged to VIN. Thus, as Cgd2 reverses its polarity and g2 is charged up to 12V, the required current is LGATEX GND Igd2 = C gd2 dV V + 12V = C gd2 IN dt t r2 (4) Figure 2. Sync. Buck Converter Circuit When layout the PC board, it should be very careful. The power-circuit section is the most critical one. If not configured properly, it will generate a large amount of EMI. The junction of Q1, Q2, L2 should be very close. Next, the trace from UGATE, and LGATE to the gates of MOSFET should also be short to decrease the noise of the driver output signals. The bypass capacitor C4 should be connected to GND directly. Furthermore, the bootstrap capacitors (CB) should always be placed as close to the pins of the IC as possible. The trace from PHASE to the common node of the two MOSFETs should be kept wide since it usually carries large current. Select the Bootstrap Capacitor It is helpful to calculate these currents in a typical case. Assume a synchronous rectified buck converter, input voltage VIN = 12V, Vg1 = Vg2 = 12V. The high side MOSFET is PHB83N03LT whose Ciss = 1660pF, Crss = 380pF, and t r = 1 4ns. The low side MOSFET is PHB95N03LT whose Ciss = 2200pF, Crss = 500pF and tr = 30ns, from the equation (1) and (2) we can obtain Igs1 = 1660 × 10 × 12 = 1.428 (A) 14 × 10 −9 −12 -12 Igs2 = 2200 × 10 × 12 = 0.88 (A) 30 × 10 −9 (5) (6) from equation. (3) and (4) −12 Igd1 = 380 × 10 × 12 = 0.326 (A) 14 × 10 −9 -12 Igd2 = 500 × 10 × 12 = 0.4 (A) 30 × 10 −9 (7) (8) Figure 3 shows part of the bootstrap circuit of RT9605A. The VCB (the voltage difference between BOOT and PHASE pins provides a voltage to the gate of the high side power MOSFET. This supply needs to be ensured that the MOSFET can be driven. For this, the capacitance CB has to be selected properly. It is determined by following constraints. 1N4148 VIN the total current required from the gate driving source is Ig1 = Igs1 + Igd1 = (1.428 + 0.326) = 1.745 (A) Ig2 = Igs2 + Igd2 = (0.88 + 0.4) = 1.28 (A) (9) (10) BOOT UGATE PHASE CB + VCB - By a similar calculation, we can also get the sink current required from the turned off MOSFET. LGATE GND Figure 3. Part of Bootstrap Circuit of RT9605A All brandname or trademark belong to their owner respectively www.richtek.com 10 DS9605A-05 August 2007 Preliminary In practice, a low value capacitor CB will lead the overcharging that could damage the IC. Therefore to minimize the risk of overcharging and reducing the ripple on VCB, the bootstrap capacitor should not be smaller than 0.1μF, and the larger the better. In general design, using 1μF can provide better performance. At least one low-ESR capacitor should be used to provide good local de-coupling. Here, to adopt either a ceramic or tantalum capacitor is suitable. Power Dissipation For not exceeding the maximum allowable power dissipation to drive the IC beyond the maximum recommended operating junction temperature of 125°C, it is necessary to calculate power dissipation appropriately. This dissipation is a function of switching frequency and total gate charge of the selected MOSFET. Figure 4 shows the power dissipation test circuit. CL and C U a re the UGATE and LGATE load capacitors, respectively. The bootstrap capacitor value is 1μF. RT9605A The method to improve the thermal transfer is to increase the PC board copper area around the RT9605A firstly. Then, adding a ground pad under IC to transfer the heat to the peripheral of the board. Power Dissipation vs. Frequency 1000 900 CU=CL=3nF Power Dissipation (mW) 800 700 600 500 400 300 200 100 0 0 200 400 600 800 1000 CU=CL=2nF CU=CL=1nF Frequency (kHz) Figure 5. Power Dissipation vs. Frequency Over-Voltage Protection Function at Power-On 10 +12V 1N4148 1uF CBOOTx +12V BOOTX VDD 1uF UGATEX 2N7002 CU 3nF 2N7002 PWM PWMX LGATEX GND 20 CL 3nF RT9605A PHASEX An unique feature of the RT9605A is the addition of overvoltage protection in the event of upper MOSFET direct shorted before power-on. The RT9605A detects the fault condition during initial start-up, the internal power-on OVP sense circuitry will rapidly drive the low side MOSFET on before the multi-phase PWM controller takes control. Figure 6 shows the measured waveforms with the high side MOSFET directly shorted to 12V. Figure 4. Test Circuit (One Phase is Shown) Figure 5 shows the power dissipation of the RT9605A as a function of frequency and load capacitance. The value of the CU and CL are the same and the frequency is varied from 100kHz to 1MHz. The operating junction temperature can be calculated from the power dissipation curves (Figure 5). Assume VDD = 12V, operating frequency is 200kHz and the CU=CL=1nF which emulate the input capacitances of the high side and low side power MOSFETs. From Figure 5, the power dissipation is 100mW. For RT9605A, the package thermal resistance θJA is 67°C/W, the operating junction temperature is calculated as : TJ = (67°C/W x 100mW) + 25°C = 31.7°C where the ambient temperature is 25°C. DS9605A-05 August 2007 +12V PHASEX LGATEX VCORE Figure 6. Waveforms at High Side MOSFET Shorted Please note that the +12V trigger point to RT9605A is at 3V, and the clamped level on PHASE pin is at about 2.4V. Obviously since the PHASE pin voltage increases during initial start-up, the VCORE increases correspondingly, but it would quickly drop-off following the voltage in LGATE and +12V. www.richtek.com 11 (11) All brandname or trademark belong to their owner respectively RT9605A Outline Dimension Preliminary D D2 SEE DETAIL A L 1 E E2 1 2 1 2 e A A3 A1 b DETAIL A Pin #1 ID and Tie Bar Mark Options Note : The configuration of the Pin #1 identifier is optional, but must be located within the zone indicated. Symbol A A1 A3 b D D2 E E2 e L Dimensions In Millimeters Min 0.800 0.000 0.175 0.180 3.950 2.300 3.950 2.300 0.500 0.350 0.450 Max 1.000 0.050 0.250 0.300 4.050 2.750 4.050 2.750 Dimensions In Inches Min 0.031 0.000 0.007 0.007 0.156 0.091 0.156 0.091 0.020 0.014 0.018 Max 0.039 0.002 0.010 0.012 0.159 0.108 0.159 0.108 V-Type 24L QFN 4x4 Package Richtek Technology Corporation Headquarter 5F, No. 20, Taiyuen Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)5526789 Fax: (8863)5526611 Richtek Technology Corporation Taipei Office (Marketing) 8F, No. 137, Lane 235, Paochiao Road, Hsintien City Taipei County, Taiwan, R.O.C. Tel: (8862)89191466 Fax: (8862)89191465 Email: marketing@richtek.com www.richtek.com 12 DS9605A-05 August 2007