RT9619GS

RT9619/A Synchronous-Rectified Buck MOSFET Drivers General Description The RT9619/A is a high frequency, dual MOSFET driver specifically designed to drive two power N-Channel MOSFETs in a synchronous-rectified buck converter topology. This driver combined with Richtek's series of Multi-Phase Buck PWM controller form a complete corevoltage regulator solution for advanced micro-processors. The RT9619/A drives both the lower/upper gate in a synchronous-rectifier bridge with 12V. This drive-voltage flexibility provides the advantage of optimizing applications involving trade-offs between switching losses and conduction losses. RT9619A has longer UGATE/LGATE deadtime which can drive the MOSFETs with large gate RC value, avoiding the shoot-through phenomenon. RT9619 is targeted to drive low gate RC MOSFETs and performs better efficiency. The output drivers in the RT9619/A can efficiently switch power MOSFETs at frequency up to 500kHz. Switching frequency above 500kHz has to take into account the thermal dissipation of SOP-8 package. RT9619/A is capable to drive a 3nF load with a 30ns rise time. RT9619/A implements bootstrapping on the upper gate with an external capacitor and an embedded diode. This reduces implementation complexity and allows the use of higher performance, cost effective N-Channel MOSFETs. Adaptive shoot-through protection is integrated to prevent both MOSFETs from conducting simultaneously. Features Drives Two N-Channel MOSFETs Adaptive Shoot-Through Protection Embedded Boot Strapped Diode Supports High Switching Frequency Fast Output Rise Time Small SOP-8 Package Tri-State Input for Bridge Shutdown Supply Under Voltage Protection Upper MOSFET Direct Shorted Protection RoHS Compliant and 100% Lead (Pb)-Free Applications Core Voltage Supplies for Desktop, Motherboard CPU High Frequency Low Profile DC-DC Converters High Current Low Voltage DC-DC Converters Ordering Information RT9619/A Package Type S : SOP-8 Operating Temperature Range P : Pb Free with Commercial Standard G : Green (Halogen Free with Commercial Standard) Long Dead Time Short Dead Time Note : RichTek Pb-free and Green products are : RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020. Suitable for use in SnPb or Pb-free soldering processes. 100% matte tin (Sn) plating. Pin Configurations (TOP VIEW) BOOT PWM NC VCC 2 3 4 8 7 6 5 UGATE PHASE PGND LGATE SOP-8 DS9619/A-04 March 2007 www.richtek.com 1 www.richtek.com 2 L1 2.2uH VIN C9 10uF C2 1uF C10 1000uF C11 1000uF C12 1000uF C13 10uF C14 10uF D1 RT9619/A Typical Application Circuit ATX_12V C8 10uF R2 1 1 BOOT R3 2.2 Q1 L2 1uH + ATX_12V UGATE C1 1uF RT9619/A 3 NC PWM LGATE PGND 6 5 R4 0 PWM 2 Q2 PHASE 7 R5 2.2 C3 3.3nF R1 10 4 VCC 8 VCORE + + + C4 2200uF C5 2200uF C6 10uF C7 10uF DS9619/A-04 March 2007 RT9619/A Functional Pin Description Pin No. 1 2 3 4 5 6 7 8 Pin Name BOOT PWM NC VCC LGATE PGND PHASE UGATE Pin Function Floating bootstrap supply pin for upper gate drive. Input PWM signal for controlling the driver. No Connection Pin. +12V Supply Voltage. Lower Gate Drive Output. Connected to gate of low-side power N-Channel MOSFET. Common Ground. Connected this pin to the source of the high-side MOSFET and the drain of the low-side MOSFET. Upper Gate Drive Output. Connected to gate of high-side power N-Channel MOSFET. Function Block Diagram VCC Internal 5V POR R PWM R Turn off Detect VCC Shoot-Through Protection LGATE PGND PHASE Tri-State Detect Shoot-Through Protection BOOT UGATE Timing Diagram PWM LGATE tpdlLGATE 90% 2V tpdlUGATE 2V 90% 2V UGATE tpdhUGATE tpdhLGATE 2V DS9619/A-04 March 2007 www.richtek.com 3 RT9619/A Absolute Maximum Ratings (Note 1) −0.3V to 15V −0.3V to 15V −0.3V to VCC + 15V −0.3V to 42V −5V to 15V −10V to 30V GND − 0.3V to VCC + 0.3V −2V to VCC + 0.3V VPHASE − 0.3V to VBOOT + 0.3V VPHASE − 2V to VBOOT + 0.3V GND − 0.3V to 7V 0.625W 160°C/W 260°C −40°C to 150°C 2kV 200V Supply Voltage, VCC ------------------------------------------------------------------------------------BOOT to PHASE ----------------------------------------------------------------------------------------BOOT to GND DC -----------------------------------------------------------------------------------------------------------< 200ns ----------------------------------------------------------------------------------------------------PHASE to GND DC -----------------------------------------------------------------------------------------------------------< 200ns ----------------------------------------------------------------------------------------------------LGATE DC -----------------------------------------------------------------------------------------------------------< 200ns ----------------------------------------------------------------------------------------------------UGATE -----------------------------------------------------------------------------------------------------< 200ns ----------------------------------------------------------------------------------------------------PWM Input Voltage -------------------------------------------------------------------------------------Power Dissipation, PD @ TA = 25°C SOP-8 ------------------------------------------------------------------------------------------------------Package Thermal Resistance (Note 4) SOP-8, θJA ------------------------------------------------------------------------------------------------Lead Temperature (Soldering, 10 sec.) -------------------------------------------------------------Storage Temperature Range --------------------------------------------------------------------------ESD Susceptibility (Note 2) HBM (Human Body Mode) ----------------------------------------------------------------------------MM (Machine Mode) ------------------------------------------------------------------------------------- Recommended Operating Conditions (Note 3) Supply Voltage, VCC ------------------------------------------------------------------------------------- 12V ±10% Junction Temperature Range --------------------------------------------------------------------------- 0°C to 125°C Ambient Temperature Range --------------------------------------------------------------------------- 0°C to 70°C Electrical Characteristics (Recommended Operating Conditions, TA = 25°C unless otherwise specified) Parameter VCC Supply Voltage Power Supply Voltage VCC Supply Current Power Supply Current Power-On Reset POR Threshold Hysteresis Symbol Test Conditions Min Typ Max Units VCC IVCC VBOOT = 12V, PWM = 0V 7.3 -- 13.5 V -- 1 2.5 mA VVCCrth VVCChys VCC Rising 5.5 -- 6.4 2.2 7.3 -- V V To be continued www.richtek.com 4 DS9619/A-04 March 2007 RT9619/A Parameter PWM Input Maximum Input Current PWM Floating Voltage PWM Rising Threshold PWM Falling Threshold Timing UGATE Rise Time UGATE Fall Time LGATE Rise Time LGATE Fall Time RT9619 RT9619A Propagation Delay RT9619/A tpdlUGATE tpdhLGATE tpdlLGATE Shutdown Window Output UGATE Drive Source UGATE Drive Sink LGATE Drive Source LGATE Drive Sink RUGATEsr RUGATEsk RLGATEsr RLGATEsk VBOOT – VPHASE = 12V VBOOT – VPHASE = 12V VCC = 12V VCC = 12V ----1.9 1.4 1.9 1.1 3 3 3 2.2 Ω Ω Ω Ω See Timing Diagram trUGATE tfUGATE trLGATE tfLGATE tpdhUGATE VCC = 12V, 3nF load VCC = 12V, 3nF load VCC = 12V, 3nF load VCC = 12V, 3nF load VBOOT − VPHASE = 12V See Timing Diagram ---------1.5 27 32 35 27 20 90 15 20 8 -35 45 45 38 -----3.2 V ns ns ns ns ns IPWM VPWMfl VPWMrth VPWMfth PWM = 0V or 5V VCC = 12V --3.2 1.1 300 2.4 3.6 1.3 --3.9 1.5 μA V V V Symbol Test Conditions Min Typ Max Units Note 1. Stresses listed as the above “ Absolute Maximum Ratings” may cause permanent damage to the device. These are for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. Note 2. Devices are ESD sensitive. Handling precaution recommended. Note 3. The device is not guaranteed to function outside its operating conditions. Note 4. θJA i s measured in the natural convection at T A = 25 °C on a low effective thermal conductivity test board of JEDEC 51-3 thermal measurement standard. DS9619/A-04 March 2007 www.richtek.com 5 RT9619/A Typical Operating Characteristics PWM to Drive Waveform PWM (5V/Div) UGATE (20V/Div) LGATE (10V/Div) PHASE (10V/Div) Time (25ns/Div) PWM to Drive Waveform PWM (5V/Div) UGATE (20V/Div) LGATE (10V/Div) PHASE (10V/Div) No Load No Load Time (25ns/Div) Dead Time Full Load Full Load Dead Time UGATE UGATE PHASE PHASE (5V/Div) LGATE (5V/Div) LGATE Time (20ns/Div) Time (20ns/Div) Dead Time No Load No Load Dead Time UGATE UGATE PHASE PHASE (5V/Div) LGATE (5V/Div) LGATE Time (20ns/Div) Time (20ns/Div) www.richtek.com 6 DS9619/A-04 March 2007 RT9619/A Short Pulse IOUT = 119A to 24A 0.06 0.05 Internal Diode I-V Curve UGATE LGATE PHASE Current (A) 0.04 0.03 0.02 0.01 0.00 (5V/Div) Time (20ns/Div) 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 Voltage (V) DS9619/A-04 March 2007 www.richtek.com 7 RT9619/A Application Information The RT9619/A is designed to drive both high side and low side N-Channel MOSFET through externally input PWM control signal. It has power-on protection function which held UGATE and LGATE low before VCC up across the rising threshold voltage. After the initialization, the PWM signal takes the control. The rising PWM signal first forces the LGATE signal turns low then UGATE signal is allowed to go high just after a non-overlapping time to avoid shootthrough current. The falling of PWM signal first forces UGATE to go low. When UGATE and PHASE signal reach a predetermined low level, LGATE signal is allowed to turn high. The PWM signal is acted as "High" if above the rising threshold and acted as "Low" if below the falling threshold. Any signal level enters and remains within the shutdown window is considered as "tri-state", the output drivers are disabled and both MOSFET gates are pulled and held low. If left the PWM signal floating, the pin will be kept around 2.4V by the internal divider and provide the PWM controller with a recognizable level. The RT9619/A typically operates at frequency of 200kHz to 500kHz. It shall be noted that to place a 1N4148 or schottky diode between the VCC and BOOT pin as shown in the typical application circuit for ligher efficiency. Non-overlap Control To prevent the overlap of the gate drives during the UGATE turn low and the LGATE turn high, the non-overlap circuit monitors the voltages at the PHASE node and high side gate drive (UGATE-PHASE). When the PWM input signal goes low, UGATE begins to turn low (after propagation delay). Before LGATE can turn high, the non-overlap protection circuit ensures that the monitored voltages have gone below 1.2V. Once the monitored voltages fall below 1.2V, LGATE begins to turn high. For short pulse condtion, if the PHASE pin had not gone high after LGATE turns low, the LGATE has to wait for 200ns before turn high. By waiting for the voltages of the PHASE pin and high side gate drive to fall below 1.2V, the non-overlap protection circuit ensures that UGATE is low before LGATE turns high. Vg1 VPHASE +12V Also to prevent the overlap of the gate drives during LGATE turn low and UGATE turn high, the non-overlap circuit monitors the LGATE voltage. When LGATE go below 1.2V, UGATE is allowed to go high. Driving Power MOSFETs The DC input impedance of the power MOSFET is extremely high. When Vgs at 12V (or 5V), the gate draws the current only few nano-amperes. Thus once the gate has been driven up to "ON" level, the current could be negligible. However, the capacitance at the gate to source terminal should be considered. It requires relatively large currents to drive the gate up and down 12V (or 5V) rapidly. It also required to switch drain current on and off with the required speed. The required gate drive currents are calculated as follows. D1 d1 VIN Cgd1 Igs1 g1 Ig2 Igd2 g2 Igs2 Cgs2 s2 GND D2 Cgs1 Cgd2 d2 s1 L VOUT Igd1 Ig1 t Vg2 12V t Figure 1. Equivalent Circuit and Associated Waveforms In Figure 1, the current Ig1 and Ig2 are required to move the gate up to 12V. The operation consists of charging Cgd and Cgs. Cgs1 and Cgs2 are the capacitances from gate to source of the high side and the low side power MOSFETs, respectively. In general data sheets, the Cgs is referred as "Ciss" which is the input capacitance. Cgd1 and Cgd2 are the capacitances from gate to drain of the high side and the www.richtek.com 8 DS9619/A-04 March 2007 RT9619/A low side power MOSFETs, respectively and referred to the data sheets as "Crss" the reverse transfer capacitance. For example, tr1 and tr2 are the rising time of the high side and the low side power MOSFETs respectively, the required current Igs1 and Igs2 are showed below : , the total current required from the gate driving source is Ig1 = Igs1 + Igd1 = (1.428 + 0.326) = 1.754 (A) Ig2 = Igs2 + Igd2 = (0.88 + 0.4) = 1.28 (A) (9) (10) Igs1 = C gs1 Igs2 = C gs1 dVg1 C gs1 × 12 = dt t r1 dVg2 C gs1 × 12 = dt t r2 (1) (2) By a similar calculation, we can also get the sink current required from the turned off MOSFET. Select the Bootstrap Capacitor Figure 2 shows part of the bootstrap circuit of RT9619/A. The VCB (the voltage difference between BOOT and PHASE on RT9619/A) provides a voltage to the gate of the high side power MOSFET. This supply needs to be ensured that the MOSFET can be driven. For this, the capacitance CB has to be selected properly. It is determined by following constraints. VIN Before driving the gate of the high side MOSFET up to 12V (or 5V), the low side MOSFET has to be off; and the high side MOSFET is turned off before the low side is turned on. From Figure 1, the body diode "D2" had been turned on before high side MOSFETs turned on. Igd1 = C gd1 dV = C gd1 12V dt t r1 (3) 1N4148 Before the low side MOSFET is turned on, the Cgd2 have been charged to VIN. Thus, as Cgd2 reverses its polarity and g2 is charged up to 12V, the required current is VCC BOOT UGATE CB + VCB - Igd2 = Cgd2 dV = Cgd2 Vi + 12V dt t r2 (4) VCC PHASE It is helpful to calculate these currents in a typical case. Assume a synchronous rectified buck converter, input voltage VIN = 12V, Vg1 = Vg2 = 12V. The high side MOSFET is PHB83N03LT whose Ciss = 1660pF, Crss = 380pF, and tr = 14ns. The low side MOSFET is PHB95N03LT whose Ciss = 2200pF, Crss = 500pF and tr = 30ns, from the equation (1) and (2) we can obtain Igs1 = 1660 × 10 × 12 = 1.428 (A) 14 × 10 -9 -12 -12 Igs2 = 2200 × 10 × 12 = 0.88 30 × 10 -9 LGATE PGND Figure 2. Part of Bootstrap Circuit of RT9619/A In practice, a low value capacitor CB will lead the overcharging that could damage the IC. Therefore to minimize the risk of overcharging and reducing the ripple on VCB, the bootstrap capacitor should not be smaller than 0.1μF, and the larger the better. In general design, using 1μF can provide better performance. At least one low-ESR capacitor should be used to provide good local de-coupling. Here, to adopt either a ceramic or tantalum capacitor is suitable. Power Dissipation (5) (6) (A) from equation. (3) and (4) Igd1 = 380 × 10 -9× 12 = 0.326 (A) 14 × 10 Igd2 = 500 × 10 -12 -12 (7) × (12 + 12) -9 30 × 10 = 0.4 (A) (8) For not exceeding the maximum allowable power dissipation to drive the IC beyond the maximum recommended operating junction temperature of 125°C, it is necessary to calculate power dissipation appro-priately. DS9619/A-04 March 2007 www.richtek.com 9 RT9619/A This dissipation is a function of switching frequency and total gate charge of the selected MOSFET. Figure 3 shows the power dissipation test circuit. CL and CU are the UGATE and LGATE load capacitors, respectively. The bootstrap capacitor value is 1μF. 10 +12V BOOT VCC 1uF RT9619/A PHASE 2N7002 PWM VIN LGATE PGND 20 CL 3nF UGATE 2N7002 CU 3nF 1N4148 TJ = (160°C/W x 100mW) + 25°C = 41°C where the ambient temperature is 25°C. (11) CBOOT 1uF +12V The method to improve the thermal transfer is to increase the PCB copper area around the RT9619/A first. Then, adding a ground pad under IC to transfer the heat to the peripheral of the board. Over-Voltage Protection Function at Power-On An unique feature of the RT9619/A driver is the addition of over-voltage protection in the event of upper MOSFET direct shorted before power-on. The RT9619/Adetects the fault condition during initial start-up, the internal power-on OVP sense circuitry will rapidly drive the output lower MOSFET on before the multi-phase PWM controller takes control. Figure 5 shows the measured waveforms with the high side MOSFET directly shorted to 12V. Figure 3. Test Circuit Figure 4 shows the power dissipation of the RT9619/A as a function of frequency and load capacitance. The value of the CU and CL are the same and the frequency is varied from 100kHz to 1MHz. (2V/Div) VCC (2V/Div) Power Dissipation vs. Frequency 1000 900 PHASE CU=CL=3nF (2V/Div) Power Dissipation (mW) 800 700 600 500 400 300 200 100 0 0 200 400 600 800 1000 LGATE (2V/Div) V CORE CU=CL=2nF Time (50ms/Div) CU=CL=1nF Figure 5. Waveforms at High Side MOSFET Shorted Please note that the VCC trigger point to RT9619/A is at 3V, and the clamped level on PHASE pin is at about 2.4V. Obviously since the PHASE pin voltage increases during initial start-up, the VCORE increases correspondingly, but it would quickly drop-off followed by LGATE and VCC decreased. Layout Consideration Figure 6 shows the schematic circuit of a two-phase synchronous buck converter to implement the RT9619/A. The converter operates from 5V to 12V of VIN. Frequency (kHz) Figure 4. Power Dissipation vs. Frequency The operating junction temperature can be calculated from the power dissipation curves ( Figure 4). Assume VCC=12V, operating frequency is 200kHz and the CU=CL=1nF which emulate the input capacitances of the high side and low side power MOSFETs. From Figure 4, the power dissipation is 100mW. For RT9619/A, the package thermal resistance θJA is 160°C/W, the operating junction temperature is calculated as : www.richtek.com 10 DS9619/A-04 March 2007 RT9619/A L1 VIN 12V 1.2uH C1 1000uF Q1 L2 VCORE + + D1 C2 1uF CB 1uF 8 7 2uH Q2 PHB83N03LT R1 4 VCC C4 10 1uF 12V 1 BOOT UGATE PHASE C3 1500uF PHB95N03LT 5 RT9619/A VIN 2 PWM LGATE PGND 6 Figure 6. Two-Phase Synchronous Buck Converter Circuit When layout the PCB, it should be very careful. The powercircuit section is the most critical one. If not configured properly, it will generate a large amount of EMI. The junction of Q1, Q2, L2 should be very close. Next, the trace from UGATE, and LGATE should also be short to decrease the noise of the driver output signals. PHASE signals from the junction of the power MOSFET, carrying the large gate drive current pulses, should be as heavy as the gate drive trace. The bypass capacitor C4 should be connected to PGND directly. Furthermore, the bootstrap capacitors (CB) should always be placed as close to the pins of the IC as possible. DS9619/A-04 March 2007 www.richtek.com 11 RT9619/A Outline Dimension A H M J B F C I D Dimensions In Millimeters Symbol Min A B C D F H I J M 4.801 3.810 1.346 0.330 1.194 0.170 0.050 5.791 0.400 Max 5.004 3.988 1.753 0.508 1.346 0.254 0.254 6.200 1.270 Dimensions In Inches Min 0.189 0.150 0.053 0.013 0.047 0.007 0.002 0.228 0.016 Max 0.197 0.157 0.069 0.020 0.053 0.010 0.010 0.244 0.050 8-Lead SOP Plastic Package Richtek Technology Corporation Headquarter 5F, No. 20, Taiyuen Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)5526789 Fax: (8863)5526611 Richtek Technology Corporation Taipei Office (Marketing) 8F, No. 137, Lane 235, Paochiao Road, Hsintien City Taipei County, Taiwan, R.O.C. Tel: (8862)89191466 Fax: (8862)89191465 Email: marketing@richtek.com www.richtek.com 12 DS9619/A-04 March 2007