RT9643
5 Channel ACPI Regulator with Step-Down DC/DC Controller
General Description
The RT9643 is a combo regulator which is compliant to
ACPI specification for desktop/motherboard power
management and system application. The part features
one switch regulator for DDR memory VDDQ power; three
Features
Integrated 5 Channels Power Regulator
DC/DC Buck PWM Regulator for VDDQ (2.5V or 1.8V)
Linear Regulator Supports 1.5Amp Peak Sinking/
Sourcing Capability for VTT
capability regulator for DDR VTT, a 1.2V ultra-low-dropout
1.2V Ultra-Low-Dropout Linear Controller for
GMCH VTT Power
linear controller for chipset miscellaneous power, a 3.3VSB
power with 1.25Amp peak current capability; and 2 dual
3.3VSB Linear Regulator Supports 1.25A Capability
5VDL Switch Control
power control including 5VDL, and 3.3VDL control for S3
and S5 system power. The part totally feature 5 sets power
3VDL Switch Control
linear regulators including 1.5Amp peak sourcing/sinking
which are compliant to ACPI specification into a single
small footprint package VQFN-24L 5x5.
The part is generally operated to conform to ACPI
specification, in S3 state, there are only VDDQ and
3.3VSB regulators remain on while the VTT and ULDO
regulators are off. In the transition from S3 to S0, an
external SS capacitor is attached for linear regulators to
control its slew rates respectively to avoid inrush current
induced. Moreover, the PGOOD signal raises high in S0
stage while all 3 regulators go stable. In the stage of S5
(EN = 0), there only 3.3VSB LDO remain on, while the
other regulators are powered down. The VDDQ PWM
regulator is a voltage mode implementation with external
compensation to provide high load transient response. The
VTT is regulated to follow 1/2 of VDDQ and is capable of
sourcing or sinking 1.5A peak currents.
Ordering Information
Conform to ACPI Specification
Support Power Management at S0, S3, and S5
State
300kHz Fixed Frequency Switching
RDS(ON) Current Sensing or Optional Current
Sense Resistor for Precision Over-Current Detect
Embedded Synchronous Boot-Strapped Diode
Power Good Signal Indication for All Voltages
Thermal Shutdown
24-Lead VQFN Package
RoHS Compliant and 100% Lead (Pb)-Free
Applications
DDR VDDQ and VTT Voltage Generator with ACPI
Support
Desktop System Power
Servers System Power
Pin Configurations
(TOP VIEW)
RT9643
Package Type
QV : VQFN-24L 5x5 (V-Type)
Operating Temperature Range
P : Pb Free with Commercial Standard
G : Green (Halogen Free with Commercial Standard)
24
23
22
21
20
19
1.2V_DRV
1
18
1.2V_FB
2
17
S3#I
5VSB_DRV
3
16
VCC_EN
Note :
5V_MAIN
4
15
3VSB_OUT
Richtek Pb-free and Green products are :
VTT_SNS
5
14
VCC
VTT_OUT
6
13
PGOOD
RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020.
GND
25
7
8
9
10
11
EN
12
Suitable for use in SnPb or Pb-free soldering processes.
100% matte tin (Sn) plating.
VQFN-24L 5x5
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1
RT9643
Typical Application Circuit
5V_MAIN
12V
L2
R4
RT9643
Q3
5V DUAL
Q4
5VSB
3.3 MAIN
3 5VSB_DRV
C13
>
Q5
C12
17 S3#I
15
3V DUAL R8
C17
VDDQ
5VSB
UGATE
2
ISNS
LGATE
3VSB_OUT
Q6
1
BOOT
1.2V_FB
FB
1.2V_DRV
COMP
C4
C3
R5
Chip Enable
14 VCC
21
SS
20
ILIM
13
PGOOD
18 EN
9
C1
Q1
PHASE 10
GND
R7
1.2 OUT
C2
4
16 VCC_EN
5V_MAIN
11
R3
12
Q2
R2
19,
Exposed Pad (25)
8
C5
R1
23
22
C9
R6
VDDQ_IN 7
VTT_SNS 5
REF_IN
VTT_OUT
C6
C11
R9
C10
R10
24
6
C8
C7
Operation
The RT9643 provides 5 functions:
1. A general purpose PWM regulator, used to generate VDDQ power for DDR memory.
2. A source-sink linear VTT regulator capable of sinking and sourcing 1.5A peak(minimum).
3. An adjustable Low Drop Out controller which, in conjunction with an external N-Channel power MOSFET, provides a
programmable low voltage output. It normally provides 1.2V for GTL FSB termination voltage.
4. Generating a 5V DUAL voltage using an external N-channel to supply power from 5V MAIN in S0, and an external
P-Channel to provide power from 5V Standby (5VSB) in S3.
5.An internal LDO which regulates “3V DUAL” in S3 mode from VCC(VSB). In S3, this regulator is capable of 1.25A
peak currents with current limit protection (2A typ.).
100k pull up resistor to VOUT to obtain an output voltage. When the output voltage arrive 90% of normal value the power
good will output voltage with 3ms delay time.
When the output voltage falling arrive 75% of normal value the power good will turn off with less than 1ms delay time.
But, there are two exceptions. One is the enable pull low the power good will turn off quickly. The second is the V CC
falling arrive POR value (4V typ.) the power good also will turn off quickly.
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RT9643
Table 1. While S5àS0àS3
Start up Sequencing
The VCC pin provides power to all logic and analog control functions of the regulator including : After VCC is above
UVLO, the start-up sequence begins as shown in Figure 1.
Figure 1
T0 to T3 : After initial power-up, the IC will ignore all logic inputs for a time period (T3-T0) of about :
T3 - T0
6.5 x CSS
5
The 3V Dual LDO is in regulation. The 3.3V LDO’ s slew rate is limited by the discharge slope of CSS. If 3V MAIN has
come up prior to this time, the 3V DUAL node will already be pre-charged through the body diode of Q5 (see Figure 1).
T3 to T4 : The IC waits about 100s before initiating soft-start on VDDQ to allow CSS time to fully discharged. The IC is
in “SLEEP” or S5 state when EN is low. In S5 only the 3.3V LDO is on. If the IC is in S5 at T4, C SS will be held to 0V.
T4 to T5 : While First time to enter S0, The IC will start VDDQ only if 5V_MAIN is above its UVLO threshold (5V_MAIN
o.k.) and S3#I is high.
T5 to T7 : After VDDQ is stabilized (when CSS is above about 1.5V) which will allow the 1.2V LDO and the VTT LDO to
soft start. To ensure that the VDDQ output is not subjected to large transient currents during transition, the VTT and 1.2V
LDO slew rates are limited by the slew rate of the C SS until the LDO is in regulation. In addition, the VTT regulator is
current limited.
T8 (S0 to S3) : Dropping the S3#I signal. When this occurs, VCC_EN goes low, and the 3.3V LDO turns on. The 1.2V
LDO and the VTT LDO are turned off, and CSS is discharged to 2V. 5VSB_DRV pulls low to turn on the P-Channel 5V
DUAL switch.
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RT9643
S3 to S0 : The system signals this transition by raising the S3#I signal. S0 mode is not entered until 5V_MAIN o.k..
Then the following occurs :
VCC_EN releases and pull high by external resistor.
5VSB_DRV pulls high to turn off the P-Channel switch.
The 3.3V LDO turns off.
The 1.2V LDO and the VTT LDO are turned on and C SS is allowed to charge up
In most systems, the ATX power supply is enabled when S3#I goes to high. At that point, 5V_MAIN and 3.3 MAIN will
start to rise. The RT9643 waits until 5V_MAIN is above 4.5V to turn on Q3 and Q5. This can cause about a 10% “bump”
in both 5V DUAL and 3.3V DUAL when Q3 and Q5 turn on, since at that point, 5V_MAIN and 3.3 MAIN are at 90% of their
regulation value.
Figure 2. S3 to S0 Transition (5V DUAL)
To eliminate the “bump” add delay to the 5V_MAIN pin as shown below. The 5V_MAIN pin on the RT9643 does not
supply power to the IC, it is only used to monitor the voltage level of the 5V_MAIN supply.
5V_MAIN
to RT9643
5V_MAIN
from ATX
Figure 3. Adding Delay to 5V_MAIN
Another method to eliminate the potential for this “bump” is to use the PWR_OK to drive the 5V_MAIN pin. Some
systems cannot tolerate the long delay for PWR_OK (>100ms) to assert, hence the solution in figure C may be
preferable.
S5 to S3 : During S5 to S3 transition, the IC will pull 5VSB_DRV low with 500nA current sink to limit inrush in Q4 if 5V
MAIN is below its UVLO threshold. At that time, 5V Dual is charged. The limited gate drive controls the inrush current
through Q4 as it charges C1 (Capacitance on 5V Dual). Depending on the CGD of Q4, the current available from 5VSB,
and the size of C1, C13 may be omitted.
IQ4(INRUSH)
C1 x 5 x 10 7
C13 C GD(Q4)
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RT9643
Table 3. B.O.M of the Application Circuit
Component Description
Qty
Ref
See notes below
Cout
See notes below
C1,C12,C17
Vendor
Capacitor 1uF, 10%, 16VDC, X7R, 0603
2
C2,C4
TDK
Capacitor 10nF, 10%, 50VDC, X7R, 0603
1
C3
TDK
Capacitor 10nF, 10%, 16V, X7R, 0603
1
C6
WALSIN
Capacitor 220pF, 10%, 50VDC, NPO, 0603
1
C9
WALSIN
Capacitor 10nF, 10%, 50VDC, X7R, 0603
2
C10, C11
TDK
Capacitor 220nF,10%, 10VDC, X7R, 0603
1
C5
WALSIN
Capacitor 100nF, 10%, 25VDC, X7R, 0603
1
C8
WALSIN
Inductor 1.8uH, 3.24m?
, 16 Amps
1
L1
Inter-Technical
Inductor 0.39uH, 2.8m, 15 Amps
1
L2
Inter-Technical
MOSFET N-CH, 8.8m, 30V, 50A, D-PAK, FSID: FDD6296
1
Q1
Fairchild
MOSFET N-CH, 6m, 30V, 75A, D-PAK, FSID: FDD6606
1
Q2
Fairchild
MOSFET N-CH, 32m, 20V, 21A, D-PAK, FSID: FDD6530A
3
Q3,Q5,Q6
Fairchild
MOSFET P-CH, 35m, -20V, -5.5A, SSOT-6, FSID : DC602P
1
Q4
Fairchild
Resistor 1.82k, 1%, 0805
4
R1,R2,R9,R10
Yageo
Resistor 56k, 1%, 0805
1
R5
Any
Resistor 11.8k, 1%, 0805
1
R6
Any
Resistor 3.01k, 1%, 0603
1
R7
Any
Resistor 9.09k, 1%, 0603
1
R8
Any
Resistor 10k, 1%, 0805
1
R4
Any
Resistor 1k, 1%, 0805
1
R3
Any
RT9643
1
U1
RichTek
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RT9643
Function Block Diagram
S3#I
VCC_EN
5VSB_DRV
UVL
VTT_SNS
FB
PGOOD
VCC
5V_MAIN
EN
BOOT
UV
VR
Gate
Control
FB1.2
Soft-Start
and
Control
Circuit
PGOOD
+
1.2V_DRV
UGATE
PHASE
VDD
LGATE
GND
ISNS
COMP
OC
+
+
+
+
1.2V_FB
RA
FB
VDDQ_IN
VCC
+
+
Oscillator
+
VTT_OT
3VSB_OUT
SS
ILIM
REF_IN
VTT_SNS
Functional Pin Description
1.2V_DRV (Pin1)
VTT_SNS (Pin5)
Gate drive for 1.2V linear controller. The pin will be turned
off (low) in S3 and S5 state.
Remote sense for VTT. The pin is applied to remote sense
the output voltage of VTT.
1.2V_FB (Pin2)
VTT_OUT (Pin6)
Feedback for the 1.2V linear controller. The pin is applied
Output of VTT. Regulator power VTT output.
for 1.2V LDO output regulation sense. The voltage can be
disabled by pulling the pin higher than 0.9V.
VDDQ_IN (Pin7)
Input of external VDDQ. Input power of VTT, the VTT is
5VSB_DRV (Pin3)
5VSB Control Switch. The pin is applied to drive an external
P-Channel MOSFET to switch 5VDL power to 5VSB in
S3 stage. The pin goes high in S0 and S5.
implemented to tracking 1/2 VDDQ.
BOOT (Pin8)
PWM Boot. The pin is applied for VDDQ PWM bootstrapped power for the embedded driver power.
5V_Main (Pin4)
5V main power. When this pin is below 4.5V, transition
UGATE (Pin9)
from S3 to S0 is inhibited.
High-Side Drive. High-side MOSFET driver output of VDDQ
PWM. Connect to gate of high-side MOSFET.
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RT9643
PHASE (Pin10)
EN (Pin18)
Phase node of VDDQ PWM. The pin is applied to sense
Chip ENABLE. Typically tied to S5#. When this pin is
phase node of VDDQ PWM for gates switch control.
low, the IC is operated in standby mode, all regulators are
ISNS (Pin11)
off and VCC_EN is low.
Current Sense input. Monitors the voltage drop across
the low-side MOSFET or external sense resistor for over
GND [Pin19, Exposed Pad (25)]
current control.
exposed pad must be soldered to a large PCB and
LGATE (Pin12)
IC GROUND. The ground power for whole chip. The
connected to GND for maximum power dissipation.
Low-Side Drive. The low-side MOSFET driver output.
ILIM (Pin20)
Connect to gate of low-side MOSFET.
Current Limit setting pin. A external resistor is attached
PGOOD (Pin13)
to set the current limit value.
Power Good Indication Signal. An open-drain output signal
that will pull LOW if FB is outside of a 10% range of the
SS (Pin21)
0.9V reference and the LDO outputs are > 80% or < 110%
of its reference. PGOOD goes low when S3 is high. The
slew rate of the converter during initialization as well as
sets the initial slew rate of the LDO controllers when
power good signal from the PWM regulator enables the
transitioning from S3 to S0. This pin is charged/discharged
VTT regulator and the LDO controller.
with a internal 5uA current source during initialization,
and charged with 50uA during PWM soft-start.
VCC (Pin14)
Soft Start. A external capacitor is attached to control the
IC VCC. 5VSB is generally applied for bias power for IC
logics and gate driver control. The IC stays at standby
COMP (Pin22)
until this pin is higher than 4.35V.
error amplifier. Connect compensation network between
this pin and FB.
3VSB_OUT (Pin15)
Compensation pin of VDDQ PWM. Output of the PWM
3.3VSB LDO Output. Internal linear regulator and is
FB (Pin23)
capable to drive up to 1.25Amp peak current. The power
is Turned off in S0 state, and on in S5 or S3 stage.
VDDQ PWM Feedback. The output feedback of VDDQ
PWM. The pin is applied for voltage regulation, PGOOD,
VCC_EN (Pin16)
under-voltage, and over-voltage protection and monitoring.
VCC enable signal for dual power. The pin is applied to
REF_IN (Pin24)
control VCC power on for 3.3VDL and 5VDL, the signal is
an open drain output which pulls the gate of an two N-
VTT voltage setting. The VTT regulator tracks the voltage
set the pin, typically, it should be 1/2VDDQ
Channel blocking MOSFETs low in S5 and S3. This pin
goes high (open) in S0.
S3#I (Pin17)
S3 Input. When LOW, the VTT and 1.2V LDO regulators
are turned off and 3.3VSB regulator is turned on the.
PGOOD is set to low when S3#I is LOW.
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RT9643
Absolute Maximum Ratings
(Note 1)
Supply Input Voltage, VCC ------------------------------------------------------------------------------- 6.5V
PHASE Voltage -------------------------------------------------------------------------------------------- GND n 5V to 24V
UGATE Voltage -------------------------------------------------------------------------------------------- VPHASE n 0.3V to VBOOT 0.3V
LGATE Voltage --------------------------------------------------------------------------------------------- GND n 0.3V to VCC 0.3V
BOOT to GND ---------------------------------------------------------------------------------------------- 24V
VCC_EN to GND ------------------------------------------------------------------------------------------- 24V
BOOT to PHASE ------------------------------------------------------------------------------------------ 6.5V
BOOT to UGATE ------------------------------------------------------------------------------------------ 6.5V
UGATE to PHASE ---------------------------------------------------------------------------------------- 6.5V
Input, Output or I/O Voltage ----------------------------------------------------------------------------- GND n 0.3V to VCC + 0.3V
Storage Temperature Range ---------------------------------------------------------------------------- n65C to 150C
Lead Temperature (Soldering, 10 sec.) --------------------------------------------------------------- 260C
Junction Temperature Range ---------------------------------------------------------------------------- n20C to 125C
Power Dissipation, PD @ TA = 25C
VQFN-24L 5x5 --------------------------------------------------------------------------------------------- 1.923W
Package Thermal Resistance (Note 4)
VQFN-24L 5x5, JA ---------------------------------------------------------------------------------------- 52C/W
ESD Susceptibility (Note 2)
HBM (Human Body Mode) ------------------------------------------------------------------------------ 2kV
MM (Machine Mode) -------------------------------------------------------------------------------------- 200V
Recommended Operating Conditions
(Note 3)
Supply Voltage, VCC -------------------------------------------------------------------------------------- 5V 10%
Ambient Temperature Range ---------------------------------------------------------------------------- n10C to 85C
Electrical Characteristics
(Rocommended Operating Conditions, unless otherwise specification)
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
LGATE, UGATE open, FB > 0.9,
I(VTT) = 0, EN = 1, S3#I = 1
--
6
24
mA
EN = 1, S3#I=LOW, I(3.3)< 10mA
--
6
24
mA
EN = 0, I(3.3) = 0
--
2
4
mA
Rising VCC
4.0
4.2
4.4
V
Falling
3.9
4.05
4.2
V
--
150
--
mV
Rising
4.3
4.4
4.6
V
Falling
3.9
4.1
4.2
V
--
300
--
mV
Converter & POR
VCC Current
VCC UVLO Threshold
IVCC
Hysteresis
5V_MainUVLO Threshold
Hysteresis
To be continued
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RT9643
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
Oscillator
Frequency
250
300
350
kHz
Ramp Amplitude pk-pk
FOSC
--
1.8
--
V
Ramp offset
--
0.5
--
V
0.891
0.900
0.909
V
Initial ramp after power-up
--
5
--
A
During PWM/LOD soft start
--
48
--
A
EN = 0
--
280
--
IOUT from 0 to 16A
-2
--
+2
%
0.75
1
1.25
A
Reference and Soft Start
Internal Reference voltage
Soft Start Current
SS discharge on resistance
PWM Converter
Load Regulation
FB Bias Current
Under Voltage shutdown
2us noise filter
65
75
80
%
Isns over-current threshold
RILIM
145
170
195
A
110
115
120
%
Sourcing
--
1.8
3
Sinking
--
1.8
3
Sourcing
-
1.8
3
Sinking
--
1.2
2
Over voltage threshold
PWM Output Driver
UGATE Output Resistance
LGATE Output Resistance
PGOOD (Power good Output) and control pins, VDDQ output
Lower threshold
2us noise filter
86
--
92
%
Upper threshold
2us noise filter
108
--
115
%
PGOOD Output Low
IPGOOD
--
--
0.5
V
Leakage Current
Pull up to 5V
--
--
1
A
VDDQ IN Current
S0 mode, IVTT = 0
--
35
70
mA
VREF IN to VTT
Differential Output Voltage
IVTT = 0, TA = 25 C
-20
--
20
mV
IVTT = ±1.25A (pulsed)
-40
--
40
mV
Internal Divider Gain
EN=0
0.493
0.498
0.503
V/V
VTT Current Limit
Pulse(300ms MAX), TA = 25 C
±1.5
±3
±4
A
VTT Leakage Current
S3#I = Low
20
--
20
A
VTT SNS input resistance
VTT = 0.9V
--
110
--
VTT PGOOD
Measured at VTT SNS
80
--
110
%
Drop-Out Voltage
ITT = ±1.5A
-0.8
--
0.8
V
VTT Regulator
k
To be continued
DS9643-03 August 2007
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RT9643
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
1.17
1.2
1.23
V
--
--
0.3
V
--
--
4.5
V
Gate Drive Source Current
--
1.2
--
mA
Gate Drive Sink Current
--
1.2
--
mA
FB 1.2V PGOOD Threshold
--
--
0.8
V
3.2
3.3
3.4
V
--
--
1.5
V
S3#I, EN input threshold
1
1.25
1.55
V
S3#I, EN input Current
-1
--
1
A
--
150
--
C
--
25
--
C
--
170
300
VVCC_EN = 12V
--
4
10
5V_MAIN OK
--
125
200
5V_MAIN < UVLO
--
500
--
--
820
1200
1.2V LDO
Regulation
I(1.2) from 0 to 5A
Drop-Out Voltage
I(1.2
External Gate Drive
VCC = 4.75V
5A, RDS(ON) < 50m
3.3V LDO
Regulation
I(3.3) from 0 to 1.25A, VCC > 4.75V
Drop-Out Voltage
I(3.3)
1.25A
Control Function
Over-Temperature
Shutdown
Over-Temperature
Hysteresis
VCC_EN Output Low
RDS(ON)
VCC_EN Output High
Leakage
5VSB_DRV Output Low
resistance
5VSB_DRV Sink Current
5VSB_DRVOutput High
A
nA
Note 1. Stresses listed as the above "Absolute Maximum Ratings" may cause permanent damage to the device. These are for
stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may remain possibility to affect device reliability.
Note 2. Devices are ESD sensitive. Handling precaution is highly recommended.
Note 3. The operating conditions beyond the recommended range is not guaranteed.
Note 4.
JA
is measured in the natural convection at TA = 25C on a low effective thermal conductivity test board (single-layer,
1S) of JEDEC 51-3 thermal measurement standard.
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RT9643
Application Information
PWM Regulator
source. The output voltage starts to go up when VCSS is
The RT9643 combines a single-phase synchronous buck
PWM controller designed to drive two N-Channel
larger than 0.4V. To prevent large duty cycles and high
currents during the beginning of the PWM soft-start, Once
MOSFETs. It provides a highly accurate, programmable
CSS has charged to 1.3V, the output voltage will be in
output voltage precisely regulated to low voltage
regulation.
requirement with an internal 0.9V reference.
The time it takes SS to reach 1.3V is : T1.3
Setting the output voltage
where T1.3 is in ms if CSS is in nF.
The output voltage of the PWM regulator can be set in the
The PWM regulator’ s latched faults are enabled until CSS
range of 0.9V to 90% of its power input by an external
resistor divider.
charges up to 1.5V. When CSS reaches 2.5V, the VTT
and 1.2V LDO will begin their soft-start ramps. After the
The internal reference is 0.9V. The output is divided down
VTT and 1.2V LDO regulators are in regulation, PGOOD
by an external voltage divider to the FB pin (for example,
R1 and R2 in Typical Application Circuit). There is also a
discharge SS and reset the IC.
1A precision (5%) current sourced out of FB to ensure
that if the pin is open, VDDQ will remain low. The output
voltage therefore is :
0.9V
R2
VOUT 0.9V
R1
1.3 x CSS
50
is then allowed to go HIGH (open). UVLO on V CC will
Current Sensing Section
1 A
+
-
To minimize noise pickup on this node, keep the resistor
to GND (R2) below 2k. We selected R2 at 1.82k and solved
for R1.
R1
R2 x (VOUT 0.9)
0.9 1 A x R2
1.816k
Figure 4. Current Sense & Limit
1.82k
The synchronous buck converter is optimized for 5V
The following discussion refers to Figure 4.
The current through RSENSE resistor (ISNS) is sensed
operation.
shortly after low side MOSFET is turned on.
Oscillator
The internal oscillator frequency is 300kHz. The internal
Setting the Current Limit
PWM ramp is reset on the rising clock edge.
An ISNS is compared to the current established when a
0.9 V internal reference drives the ILIM pin. RILIM, the
PWM Soft Start
RDS(ON) of Q2, and RSENSE determine the current limit :
When the PWM regulator is enabled the circuit will wait
until the VDDQ_IN pin is below 100mV to ensure that the
RILIM
soft-start cycle does not begin with a large residual voltage
on the PWM regulator output.
When the PWM regulator is disabled, 50
Where I LIMIT is the peak inductor current. Since the
is turned on
from VDDQ_IN to PGND to discharge the output.
The voltage at the positive input of the error amplifier is
limited to VCSS which is charged with a 50A current
DS9643-03 August 2007
10 x 0.9 RSENSE
x
ILIMIT
RDS(ON)
tolerance on the current limit is largely dependent on the
ratio of the external resistors it is fairly accurate if the
voltage drop on the Switching Node side of RSENSE is an
accurate representation of the load current.
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RT9643
When using the MOSFET as the sensing element, the
Frequency Loop Compensation
variation of RDS(ON) causes proportional variation in the
ISNS. This value not only varies from device to device,
The loop is compensated using a feedback network around
but also has a typical junction temperature coefficient of
Figure 5 shows a complete type3 compensation network.
about 0.4%/C (consult the MOSFET datasheet for actual
A type2 compensation configuration eliminates R3 and
values), so the actual current limit set point will decrease
C3 and is shown in typical application circuit. Type2
compensation can be used for most applications. For
proportional to increasing MOSFET die temperature. A
factor of 1.6 in the current limit set point should compensate
for all MOSFET R DS(ON) variations, assuming the
MOSFET’ s heat sinking will keep its operating die
the error amplifier, which is a voltage output OP Amp.
critical applications that require wide loop-bandwidth, and
use very low ESR output capacitors, type3 compensation
may be required.
temperature below 125C.
Current limit (ILIMIT) should be set sufficiently high as to
allow inductor current to rise in response to an output
C1
will need to multiply ILOAD(MAX) by the inductor ripple current
ZFB
C2
load transient. Typically, a factor of 1.3 is sufficient. In
addition, since ILIMIT is a peak current cut-off value, we
R2
C3
R3
ZIN
VOUT
R1
COMP
EA
+
(20% is chosen).
FB
ILIMIT > ILOAD(MAX) x 1.6 x 1.3 x 1.2
REF
Gate Driver Section
Figure 5. Compensation Network
The adaptive gate control logic translates the internal PWM
control signal into the MOSFET gate drive signals providing
PGOOD Signal
necessary amplification, level shifting and shoot-through
protection. Also, it has functions that help optimize the IC
PGOOD monitors the status of the PWM output as well
as the VTT and 1.2V LDO regulators. PGOOD remains
performance over a wide range of operating conditions.
Since MOSFET switching time can vary dramatically from
type to type and with the input voltage, the gate control
logic provides adaptive dead time by monitoring the gate
low unless all of the conditions below are met :
1. S3#I is HIGH
2. SS is above 4V
to source voltages of both upper and lower MOSFETs.
3. Fault latch is cleared
The lower MOSFET drive is not turned on until the PHASE
has decreased to less than approximately one VT
4. FB is between 90% and 110% of VREF
(~0.6volt). Similarly, the upper MOSFET is not turned on
until the gate-to-source voltage of the lower MOSFET has
decreased to less than approximately one VT (~0.6 volt).
This allows a wide variety of upper and lower MOSFETs
5. VTT and 1.2V LDO regulators are in regulation
Protection
The converter output is monitored and protected against
or shoot-through.
extreme overload, short circuit, over-voltage and undervoltage conditions.
There must be a low-resistance, low-inductance path
An internal “Fault Latch” is set for any fault intended to
to be used without a concern for simultaneous conduction,
between the driver pin and the MOSFET gate for the
adaptive dead-time circuit to work properly. Any delay along
that path will subtract from the delay generated by the
adaptive dead-time circuit and shoot-through may occur.
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12
shut down the IC. When the “Fault Latch” is set, the IC
will discharge VDDQ_IN by driving L GATE high until
VDDQ_IN < 0.5V. LGATE will then go low until VDDQ_IN >
0.8V. This behavior will discharge the output without
causing undershoot (negative output voltage).
DS9643-03 August 2007
RT9643
To discharge the output capacitors, a 50
load resistor is
switched in from VDDQ_IN to PGND whenever the IC is in
fault condition, or when EN is low. After a latched fault,
operation can be restored by recycling power or by toggling
the EN pin.
1. VDDQ_IN (PWM output voltage) > 1V and
2. FB < 100mV
Any of these 3 faults will set the fault latch. These 3 faults
can set the fault latch during the SS time (SS < 1.5V).
To ensure that FB pin open will not cause a destructive
Under-Voltage Shutdown
If FB stays below the under-voltage threshold for 2s, the
condition, a 1A current source ensures that the FB pin
will be high if open. This will cause the regulator to keep
“Fault latch” is set. This fault is prevented from setting
the fault latch during PWM soft-start (SS < 1.5V).
the output low, and eventually result in an Under-voltage
fault shutdown (after PWM SS complete).
Over-Current Sensing
Over-Temperature Protection
If the circuit’ s current limit signal (“ILIM det” as shown in
RT9643 incorporates an internal over temperature circuit
Figure 4) is high at the beginning of a clock cycle, a pulse
designed to protect the device during overload conditions.
skipping circuit is activated and UGATE is inhibited. The
circuit continues to pulse skip in this manner for the next
If the junction temperature reaches a nominal temperature
of 150C, the over temperature circuit will shut the chip.
8 clock cycles. If at any time from the 9th to the 16 th
Normal operation is restored at when the die temperature
falls below 125C with internal Power On Reset asserted,
clock cycle, the “ILIM det” is again reached, the fault latch
is set. If “ILIM det” does not occur between cycle 9 and
16, normal operation is restored and the over-current circuit
resets itself. This fault is prevented from setting the fault
resulting in a full soft-start cycle. To accomplish this, the
over temperature comparator should discharge the SS
pin.
latch during soft-start (SS < 1.5V).
VTT Regulator
The VTT regulator is a simple and high-speed linear
PGOOD (5V/Div)
IL (10A/Div)
UGATE (10V/Div)
LGATE (5V/Div)
Time (10s/Div)
Figure 6. Over Current Protection Waveform
OVP / HS Fault / FB short to GND detection:
A HS Fault is detected when there is more than 0.5V
from PHASE to PGND 350ns after LGATE reaches 4V (same
time as the current sampling time).
OVP Fault Detection occurs if FB > 115% VREF for 16
regulator designed to generate termination voltage in
double data rate (DDR) memory system. The regulator is
capable of actively sinking or sourcing up to 1.25A while
regulating an output voltage to within 40mV. The output
termination voltage can be tightly regulated to track
1/2VDDQ_IN by two internal voltage divider resistors (50k
for each resistor) or two external voltage divider resistors
from the output of the PWM regulator.
The VTT regulator also incorporates a high-speed
differential amplifier to provide ultra-fast response in line/
load transient. Other features include extremely low initial
offset voltage, excellent load regulation, current limiting
in bi-directions.
The VTT regulator is enabled when S3#I is HIGH and the
PWM regulator's internal PGOOD signal is true. The VTT
regulator also includes its own PGOOD signal which is
high when VTT_SNS > 90% of REF_IN.
clock cycles. During soft-start, the output voltage could
potentially “run away” if either the FB pin is shorted to
LDO Controller
GND or R1 is open. This fault will be detected if the following
The LDO controller combined with an external N-Channel
condition persists for more than 14s during soft-start.
MOSFET pass element is used to provide 1.2V for the
DS9643-03 August 2007
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13
RT9643
Front-side bus GTL termination. The driving voltage on
current from the input capacitor during the on time of upper
the gate drive pin can be pull up to within 0.5V of VCC.
Use low Vth MOSFET to assure RDS(ON) is small enough
MOSFET. The RMS value of ripple current flowing through
the input capacitor is described as :
for full load operation. The soft start for the LDO is
IIN(RMS)
accomplished by clamping the input voltage to a smooth
up-going ramp. The final input reference voltage after soft
start is 0.9V.
Components should be appropriately selected to ensure
stable operation, fast transient response, high efficiency,
minimum BOM cost and maximum reliability.
Output Inductor Selection
The selection of output inductor is based on the
considerations of efficiency, output power and operating
frequency. For a synchronous buck converter, the ripple
current of inductor ( IL) can be calculated as follows :
(VIN VOUT) x
The input bulk capacitor must be cable of handling this
ripple current. Sometime, for higher efficiency the low ESR
capacitor is necessarily. Appropriate high frequency
Component Selection
IL
IOUT x D x (1 D)
VOUT
VIN x fOSC x L
Generally, an inductor that limits the ripple current between
20% and 50% of output current is appropriate. Make sure
ceramic capacitors physically near the MOSFETs
effectively reduce the switching voltage spikes.
MOSFET Selection
The selection of MOSFETs is based upon the
considerations of RDS(ON), gate driving requirements, and
thermal management requirements. The power loss of
upper MOSFET consists of conduction loss and switching
loss and is expressed as :
PUPPER
PCOND _UPPER
IOUT x R DS(ON) x D
PSW_UPPER
1
IOUT x VIN x (TRISE
2
TFALL ) x fOSC
where TRISE and TFALL are rising and falling time of VDS of
upper MOSFET respectively. RDS(ON) and QG should be
that the output inductor could handle the maximum output
current and would not saturate over the operation
simultaneously considered to minimize power loss of upper
temperature range.
The power loss of lower MOSFET consists of conduction
Output Capacitor Selection
The output capacitors determine the output ripple voltage
( VOUT) and the initial voltage drop after a high slew-rate
load transient. The selection of output capacitor depends
on the output ripple requirement. The output ripple voltage
is described as follows :
VOUT
1
x 2
VOUT
IL x ESR
(1 D)
8 fOSC
x L x C OUT
For electrolytic capacitor application, typically 90~95%
of the output voltage ripple is contributed by the ESR of
output capacitors. Paralleling lower ESR ceramic capacitor
with the bulk capacitors could dramatically reduce the
equivalent ESR and consequently the ripple voltage.
Input Capacitor Selection
Use mixed types of input bypass capacitors to control
the input voltage ripple and switching voltage spike across
the MOSFETs. The buck converter draws pulsewise
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14
MOSFET.
loss, reverse recovery loss of body diode, and conduction
loss of body diode and is express as :
PLOWER
PCOND _LOWER
PRR
PDIODE
IOUT x R DS(ON) x (1 D) QRR x VIN x fOSC
1
x IOUT x VF x TDIODE x fOSC
2
where TDIODE is the conducting time of lower body diode.
Special control scheme is adopted to minimize body diode
conducting time. As a result, the R DS(ON) loss dominates
the power loss of lower MOSFET. Use MOSFET with
adequate RDS(ON) to minimize power loss and satisfy
thermal requirements.
Bypass Capacitor Notes
Input capacitor C1 is typically chosen based on the ripple
current requirements. COUT is typically selected based
on both current ripple rating and ESR requirement. C17
DS9643-03 August 2007
RT9643
and C12 selection will be largely determined by ESR and
copper filled polygons on the top and bottom circuit layers
load transient response requirements.
for the PHASE node, but it is not necessary to oversize
this particular island. Since the PHASE node is subjected
PWM Layout Considerations
to very high dV/dt voltages, the stray capacitance formed
between these island and the surrounding circuitry will
MOSFETs switch very fast and efficiently. The speed with
which the current transitions from one device to another
tend to couple switching noise. Use the remaining printed
causes voltage spikes across the interconnecting
impedances and parasitic circuit elements. The voltage
circuit layers for small signal routing. The PCB traces
spikes can degrade efficiency and radiate noise, that results
and also the traces connecting source of MOSFETs should
be sized to carry 2A peak currents.
in over-voltage stress on devices. Careful component
placement layout and printed circuit design can minimize
the voltage spikes induced in the converter. Consider, as
an example, the turn-off transition of the upper MOSFET
between the PWM controller and the gate of MOSFET
Below PCB gerber files are our test board for your
reference :
prior to turn-off, the upper MOSFET was carrying the full
load current. During turn-off, current stops flowing in the
upper MOSFET and is picked up by the low side MOSFET
or schottky diode. Any inductance in the switched current
path generates a large voltage spike during the switching
interval. Careful component selections, layout of the
critical components, and use shorter and wider PCB traces
help in minimizing the magnitude of voltage spikes.
There are two sets of critical components in a DC-DC
converter using the RT9643. The switching power
components are most critical because they switch large
amounts of energy, and as such, they tend to generate
equally large amounts of noise. The critical small signal
components are those connected to sensitive nodes or
those supplying critical bypass current.
Figure 7. Component Side
The power components and the PWM controller should
be placed firstly. Place the input capacitors, especially
the high-frequency ceramic decoupling capacitors, close
to the power switches. Place the output inductor and
output capacitors between the MOSFETs and the load.
Also locate the PWM controller near by MOSFETs.
A multi-layer printed circuit board is recommended.
Figure 9 shows the connections of the critical components
in the converter. Note that the capacitors C IN and COUT
each of them represents numerous physical capacitors.
Use a dedicated grounding plane and use vias to ground
all critical components to this layer. Apply another solid
layer as a power plane and cut this plane into smaller
islands of common voltage levels. The power plane should
Figure 8. GND
support the input power and output power nodes. Use
DS9643-03 August 2007
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15
RT9643
Figure 9. Power
Figure 10. Bottom
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DS9643-03 August 2007
RT9643
Outline Dimension
D2
D
SEE DETAIL A
L
1
E
E2
e
b
A
A3
A1
1
1
2
2
DETAIL A
Pin #1 ID and Tie Bar Mark Options
Note : The configuration of the Pin #1 identifier is optional,
but must be located within the zone indicated.
Symbol
Dimensions In Millimeters
Dimensions In Inches
Min
Max
Min
Max
A
0.800
1.000
0.031
0.039
A1
0.000
0.050
0.000
0.002
A3
0.175
0.250
0.007
0.010
b
0.250
0.350
0.010
0.014
D
4.950
5.050
0.195
0.199
D2
3.100
3.400
0.122
0.134
E
4.950
5.050
0.195
0.199
E2
3.100
3.400
0.122
0.134
e
L
0.650
0.350
0.026
0.450
0.014
0.018
V-Type 24L QFN 5x5 Package
Richtek Technology Corporation
Richtek Technology Corporation
Headquarter
Taipei Office (Marketing)
5F, No. 20, Taiyuen Street, Chupei City
Hsinchu, Taiwan, R.O.C.
8F, No. 137, Lane 235, Paochiao Road, Hsintien City
Taipei County, Taiwan, R.O.C.
Tel: (8863)5526789 Fax: (8863)5526611
Tel: (8862)89191466 Fax: (8862)89191465
Email: marketing@richtek.com
DS9643-03 August 2007
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