®
RT9731A/B
Dual Channel Precision Adjustable Current Limited Power
Switch
General Description
Features
The RT9731A/B is a dual channel power distribution switch
intended for applications where precision current limiting
is required or heavy capacitive loads and short circuits
are encountered. This device offers a programmable current
limit threshold between 560mA and 2.8A (typ.) per channel
via an external resistor. The power-switch's rising and falling
times are controlled to minimize current surges during
on/off transitions.
Each channel of the RT9731A/B limits the output current
to a safe level by switching into constant-current mode
whenever the output load exceeds the current limit
threshold. The FLAG logic output of each channel
independently asserts low during over current.
Built-in Soft-Start
Thin 10-Lead WDFN Package
UL Approved−E219878
Applications
RT9731A/B
(2)
Pin 1 Orientation***
(2) : Quadrant 2, Follow EIA-481-D
Package Type
QW : WDFN-10L 3x3 (W-Type)
Lead Plating System
Z : ECO (Ecological Element with
Halogen Free and Pb free)
EN Function
A : Active Low
B : Active High
Note :
***Empty means Pin1 orientation is Quadrant 1
Richtek products are :
RoHS compliant and compatible with the current require-
Suitable for use in SnPb or Pb-free soldering processes.
ments of IPC/JEDEC J-STD-020.
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
DS9731A/B-02 May 2015
USB Ports/Hubs
Digital TV
Set-Top Boxes
VOIP Phones
Pin Configurations
(TOP VIEW)
GND
VIN
VIN
EN1
EN2
1
2
3
4
5
GND
Ordering Information
Nemko Approved-NO65969
RoHS Compliant and Halogen Free
11
10
9
8
7
6
FLAG1
VOUT1
VOUT2
ISET
FLAG2
WDFN-10L 3x3
RT9731A
GND
VIN
VIN
EN1
EN2
1
2
3
4
5
GND
The RT9731A/B is available in a thin WDFN-10L 3x3
package.
2.5V to 5.5V Input Voltage Range
Two Separate Current Limiting Channels
Meets USB Current Limiting Requirements
Adjustable Current Limit from 560mA to 2.8A
±7.5% Current Limit Accuracy at 2.8A
Two 44mΩ
Ω High Side MOSFETs
2μ
μA Maximum Standby Supply Current
11
10
9
8
7
6
FLAG1
VOUT1
VOUT2
ISET
FLAG2
WDFN-10L 3x3
RT9731B
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1
RT9731A/B
Marking Information
RT9731AZQW
RT9731BZQW
14 : Product Code
20 : Product Code
YMDNN : Date Code
14 YM
DNN
YMDNN : Date Code
20 YM
DNN
Typical Application Circuit
RT9731A/B
Supply Voltage
2.5V to 5.5V
2, 3
R1
10µF
R2
0.1µF
VIN
RT9731A
Chip Enable
9
VOUT2 8
6 FLAG2
10 FLAG1
RT9731B
Chip Enable
VOUT1
4 EN1/EN1
5 EN2/EN2
ISET
GND
VOUT1
COUT2
150µF
COUT1
150µF
VOUT2
7
1, 11 (Exposed Pad)
RISET
Note : R1, R2 ; Pull-Up Resistance (10k to 100k)
Functional Pin Description
Pin No.
Pin Name
1, 11 (Exposed Pad)
GND
2, 3
VIN
4
5
Pin Function
Ground. The exposed pad must be soldered to a large PCB and
connected to GND for maximum power dissipation.
Input Voltage.
EN1
(RT9731A)
EN1
(RT9731B)
Chip Enable (Active Low). Turns on power switch for channel 1.
EN2
(RT9731A)
EN2
(RT9731B)
Chip Enable (Active Low). Turns on power switch for channel 2.
6
FLAG2
7
ISET
8
VOUT2
9
VOUT1
10
FLAG1
Chip Enable (Active High). Turns on power switch for channel 1.
Chip Enable (Active High). Turns on power switch for channel 2.
Channel 2 Fault Indicator (Active Low). This open-drain output asserts
low during over current and over temperature conditions.
Current Limit Set Pin. Connect to an external resistor to set the current
limit threshold.
Channel 2 Power Switch Output.
Channel 1 Power Switch Output.
Channel 1 Fault Indicator (Active Low). This open-drain output asserts
low during over current and over temperature conditions.
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DS9731A/B-02 May 2015
RT9731A/B
Function Block Diagram
Bias
EN1/EN1
Current
Limiting
Oscillator
Charge
Pump
Gate
Control
Output Voltage
Detection
Thermal
Protection
VOUT1
FLAG1
Delay
ISET
VIN
Bias
EN2/EN2
Oscillator
UVLO
Charge
Pump
Current
Limiting
Gate
Control
Output Voltage
Detection
GND
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DS9731A/B-02 May 2015
VOUT2
FLAG2
Delay
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RT9731A/B
Absolute Maximum Ratings
(Note 1)
Supply Input Voltage, VIN -------------------------------------------------------------------------------------------------- 6V
EN1, EN2, EN1, EN2 ------------------------------------------------------------------------------------------------------ −0.3V to 6V
FLAG1, FLAG2 -------------------------------------------------------------------------------------------------------------- 6V
Power Dissipation, PD @ TA = 25°C
WDFN-10L 3x3 --------------------------------------------------------------------------------------------------------------- 1.429W
Package Thermal Resistance (Note 2)
WDFN-10L 3x3, θJA --------------------------------------------------------------------------------------------------------- 70°C/W
WDFN-10L 3x3, θJC --------------------------------------------------------------------------------------------------------- 8.2°C/W
Junction Temperature ------------------------------------------------------------------------------------------------------- 150°C
Lead Temperature (Soldering, 10 sec.) --------------------------------------------------------------------------------- 260°C
Storage Temperature Range ---------------------------------------------------------------------------------------------- −65°C to 150°C
ESD Susceptibility (Note 3)
HBM (Human Body Mode) ------------------------------------------------------------------------------------------------ 2kV
MM (Machine Mode) -------------------------------------------------------------------------------------------------------- 200V
Recommended Operating Conditions
(Note 4)
Supply Voltage, VIN --------------------------------------------------------------------------------------------------------- 2.5V to 5.5V
Chip Enable Voltage, EN -------------------------------------------------------------------------------------------------- 0V to 5.5V
Junction Temperature Range ---------------------------------------------------------------------------------------------- −40°C to 100°C
Ambient Temperature Range ---------------------------------------------------------------------------------------------- −40°C to 85°C
Electrical Characteristics
(VIN = 5V, TA = 25°C, unless otherwise specified)
Parameter
Resistor Limit Range
Switch On-Resistance
Symbol
Test Conditions
Min
Typ
Max
Unit
RISET
20
--
100
k
RDS(ON)
--
44
50
m
2
3
4
1
2
3
--
0.8
--
--
0.6
--
VIN = 5.5V
COUT = 1F,
ROUT = 100
ms
Rising Time
tR
Falling Time
tF
ENx/ENx Input
Logic-High
Threshold Voltage Logic-Low
VIH
VIN = 2.5V to 5.5V, Power On
1.1
--
--
VIL
VIN = 2.5V to 5.5V, Shutdown
--
--
0.66
--
55
--
mV
A
VIN = 2.5V
VIN = 5.5V
VIN = 2.5V
COUT = 1F,
ROUT = 100
ENx/ENx Threshold Hysteresis
ENx/ENx Input Current
IENx/IENx
VENx/VENx = 0V to 5.5V
RISET = 20k
Current Limit
Supply Current
Reverse Leakage Current
--
0.5
2800
3005
ILIM
RISET = 61.9k
RISET = 100k
---
900
560
---
ISW_OFF
Switch Off, VOUT = Open
--
0.1
2
ISW_ON
Switch On,
VOUT = Open
RISET = 20k
--
130
200
RISET = 100k
--
100
150
IREV
VOUTx = 5.5V, VIN = 0V
--
0.01
1
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4
0.5
2590
ms
V
mA
A
A
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DS9731A/B-02 May 2015
RT9731A/B
Parameter
Under Voltage Lockout Threshold
Symbol
V UVLO
Test Conditions
VIN Rising
Under Voltage Lockout Hysteresis VUVLO
Min
Typ
Max
Unit
--
2.35
2.45
V
--
35
--
mV
--
--
180
mV
--
--
1
A
FLAGx Output Low Voltage
V FLAGx
FLAGx Off Current
IFLAGx_OFF VFLAGx = 5.5V
FLAG Delay Time
tD
From fault condition to
FLAGx assertion
5
12
20
ms
Thermal Shutdown Protection
T SD
VOUTx > 1V
--
120
--
C
T SD_SHT
VOUTx < 1V
--
100
--
C
--
20
--
C
Thermal Shutdown Threshold in
Short
Thermal Shutdown Hysteresis
ISINK = 1mA
T SD
Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in
the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may
affect device reliability.
Note 2. θJA is measured at TA = 25°C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. θJC is
measured at the exposed pad of the package.
Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
DS9731A/B-02 May 2015
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RT9731A/B
Typical Operating Characteristics
Quiescent Current vs. Input Voltage
175
Quiescent Current vs. Temperature
175
RISET = 20kΩ, No Load
VIN = 5V, RISET = 20kΩ, No Load
170
Quiescent Current (µA)
Quiescent Current (µA) 1
170
165
160
155
150
145
140
165
160
155
150
145
140
135
135
2.5
3
3.5
4
4.5
5
5.5
-50
-25
0
Input Voltage (V)
RISET = 20kΩ, No Load
Shutdown Current (µA)1
Shutdown Current (µA)1
75
100
125
Shutdown Current vs. Temperature
1.8
0.8
0.6
0.4
0.2
0.0
VIN = 5V, RISET = 20kΩ, No Load
1.5
1.2
0.9
0.6
0.3
0.0
2.5
3
3.5
4
4.5
5
-50
5.5
-25
0
Input Voltage (V)
25
50
75
100
125
Temperature (°C)
On Resistance vs. Input Voltage
48
On Resistance vs. Temperature
55
RISET = 20kΩ, IOUT = 1A
46
On Resistance (m Ω)
On Resistance (m Ω)
50
Temperature (°C)
Shutdown Current vs. Input Voltage
1.0
25
44
42
40
38
VIN = 5V, RISET = 20kΩ, IOUT = 1A
50
45
40
35
30
2.5
3
3.5
4
4.5
5
Input Voltage (V)
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5.5
-50
-25
0
25
50
75
100
125
Temperature (°C)
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RT9731A/B
Output Voltage vs. Output Current
Current Limit vs. RISET
5.5
3.5
VIN = 5V
5.0
3.0
4.0
Current Limit (A)
Output Voltage (V)
4.5
3.5
3.0
VIN = 2.5V
2.5
2.0
1.5
1.0
2.5
2.0
1.5
1.0
0.5
0.5
RISET = 20kΩ
VIN = 5V
0.0
0.0
0
0.5
1
1.5
2
2.5
3
3.5
4
20
30
40
50
Output Current (A)
Current Limit vs. Input Voltage
3.3
3.4
3.2
3.2
3.0
2.8
2.6
80
90
100
3.1
3.0
2.9
2.8
2.7
RISET = 20kΩ
VIN = 5V, RISET = 20kΩ
2.4
2.6
2.5
3
3.5
4
4.5
5
5.5
-50
-25
0
Input Voltage (V)
25
50
75
100
125
Temperature (°C)
Short Current vs. Input Voltage
Short Current vs. Temperature
1.80
2.0
1.70
1.9
Short Current (A)
Short Current (A)
70
Current Limit vs. Temperature
3.6
Current Limit (A)
Current Limit (A)
60
RISET (k Ω)
1.60
1.50
1.40
1.30
1.8
1.7
1.6
1.5
1.4
RISET = 20kΩ
1.20
VIN = 5V, RISET = 20kΩ
1.3
2.5
3
3.5
4
4.5
5
Input Voltage (V)
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DS9731A/B-02 May 2015
5.5
-50
-25
0
25
50
75
100
125
Temperature (°C)
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RT9731A/B
FLG Delay Time vs. Temperature
18
17
17
FLG Delay Time (ms)
FLG Delay Time (ms)
FLG Delay Time vs. Input Voltage
19
15
13
11
9
7
5
16
15
14
13
12
11
RISET = 20kΩ
3
VIN = 5V, RISET = 20kΩ
10
2.5
3
3.5
4
4.5
5
5.5
-50
25
50
75
Temperature (°C)
Power On from VIN
Power Off from VIN
VIN
(2V/Div)
VOUT
(2V/Div)
VOUT
(2V/Div)
VIN = 5V, RLOAD = 5kΩ
100
125
VIN = 5V, RLOAD = 5kΩ
Time (2ms/Div)
Time (2ms/Div)
Power On from EN
FLG Response
VOUT
(2V/Div)
VOUT
(2V/Div)
EN
(5V/Div)
EN
(5V/Div)
VIN = 5V, RLOAD = 5kΩ
Time (2ms/Div)
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0
Input Voltage (V)
VIN
(2V/Div)
IOUT
(1A/Div)
-25
FLAGx
(5V/Div)
IOUT
(2A/Div)
VIN = 5V, RLOAD = 0kΩ
Time (4ms/Div)
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RT9731A/B
Applications Information
The RT9731A/B are dual N-MOSFET high side power
switch with enable input, optimized for self-powered and
bus-powered Universal Serial Bus (USB) applications. The
RT9731A/B are equipped with a charge pump circuitry to
drive the internal N-MOSFET switch; the switch's low
RDS(ON), 44mΩ, meets USB voltage drop requirements;
and a flag output is available to indicate fault conditions
to the local USB controller.
Input and Output
VIN (input) is the power source connection to the internal
circuitry and the drain of the MOSFET. VOUT (output) is
the source of the MOSFET. In a typical application, current
flows through the switch from VIN to VOUT toward the load.
If VOUT is greater than VIN, current will flow from VOUT to
VIN since the MOSFET is bidirectional when on.
Unlike a normal MOSFET, there is no parasitic body diode
between drain and source of the MOSFET, the RT9731A/
B prevents reverse current flow if VOUT is externally forced
to a higher voltage than VIN when the chip is disabled
(VENx < 0.66V or VENx > 1.1V).
D
S
S
D
G
G
Normal MOSFET
RT9731A/B
Chip Enable Input
The switch will be disabled when the ENx/ENx pin is in a
logic low/high condition. During this condition, the internal
circuitry and MOSFET will be turned off, reducing the
supply current to 0.1μA typical. Floating the ENx/ENx
may cause unpredictable operation. ENx/ENx should not
be allowed to go negative with respect to GND. The ENx/
ENx pin may be directly tied to VIN (GND) to keep the
part on.
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DS9731A/B-02 May 2015
Soft-Start for Hot Plug-In Applications
In order to eliminate the upstream voltage droop caused
by the large inrush current during hot-plug events, the
“soft-start” feature effectively isolates the power source
from extremely large capacitive loads, satisfying the USB
voltage droop requirements.
Fault Flag
The RT9731A/B series provides a FLAGx signal pin which
is an N-Channel open drain MOSFET output. This open
drain output goes low when current limit or the die
temperature exceeds 120°C approximately. The FLAGx
output is capable of sinking a 10mA load to typically 200mV
above ground. The FLAGx pin requires a pull-up resistor,
this resistor should be large in value to reduce energy
drain. A 100kΩ pull-up resistor works well for most
applications. In the case of an over-current condition,
FLAGx will be asserted only after the flag response delay
time, tD, has elapsed. This ensures that FLAGx is asserted
only upon valid over current conditions and that erroneous
error reporting is eliminated.
For example, false over-current conditions may occur
during hot-plug events when extremely large capacitive
loads are connected and causes a high transient inrush
current that exceeds the current limit threshold. The
FLAGx response delay time tD is typically 12ms.
Under Voltage Lockout
Under Voltage Lockout (UVLO) prevents the MOSFET
switch from turning on until the input voltage exceeds
approximately 2.35V. If input voltage drops below
approximately 1.3V, UVLO turns off the MOSFET switch.
Under voltage detection functions only when the switch is
enabled.
Current Limit Setting and Short-Circuit Protection
The RT9731A/B provides an adjustable current limit
threshold, between 560mA and 2.8A (typ.) via an external
resistor, RISET, between 20kΩ and 100kΩ. The following
equations calculates the resulting over current threshold
for a given external resistor value (RISET). The traces routing
the RISET resistor to the RT9731A/B should be as short as
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RT9731A/B
possible to reduce parasitic effects on the current limit
accuracy. When a heavy load or short circuit is applied to
an enabled switch, a large transient current may flow until
the current limit circuitry responds. Once this current limit
threshold is exceeded the device enters constant current
mode until the thermal shutdown occurs or the fault is
removed. Figure 1 shows the typical current limit value
under various setting resistance, RISET.
A Bus-Powered Hub draws all of the power to any internal
functions and downstream ports from the USB connector
power pins. The hub may draw up to 500mA from the
upstream device. External ports in a Bus-Powered Hub
can supply up to 100mA per port, with a maximum of four
external ports.
ISET(typ.) (mA) = 56000V
RISET k
the USB interface may draw up to 100mA from its
upstream connect to allow the interface to function when
the remainder of the hub is powered down. The hub must
be able to supply up to 500mA on all of its external
downstream ports. Please refer to “Universal Serial Bus
Specification Revision 2.0” for more details on designing
compliant USB hub and host systems.
Current Limit Threshold (mA)
3000
2700
2400
2100
1800
1500
Self-Powered Hub power for the internal functions and
downstream ports does not come from the USB, although
Over current protection devices such as fuses and PTC
1200
resistors (also called polyfuse or polyswitch) have slow
trip times, high on-resistance, and lack the necessary
circuitry for USB-required fault reporting.
900
600
300
0
20
40
60
80
100
RISET (kΩ)
Figure 1. Current Limit Threshold vs. RISET
Universal Serial Bus (USB) & Power Distribution
The goal of USB is to enable device from different vendors
to interoperate in an open architecture. USB features
include ease of use for the end user, a wide range of
workloads and applications, robustness, synergy with the
PC industry, and low-cost implementation. Benefits
include self-identifying peripherals, dynamically attachable
and reconfigurable peripherals, multiple connections
(support for concurrent operation of many devices), support
for as many as 127 physical devices, and compatibility
with PC Plug-and-Play architecture.
The Universal Serial Bus connects USB devices with a
USB host: each USB system has one USB host. USB
devices are classified either as hubs, which provide
additional attachment points to the USB, or as functions,
which provide capabilities to the system (for example, a
digital joystick). Hub devices are then classified as either
Bus-Power Hubs or Self-Powered Hubs.
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The faster trip time of the RT9731A/B power distribution
allow designers to design hubs that can operate through
faults. The RT9731A/B provide low on-resistance and
internal fault-reporting circuitry to meet voltage regulation
and fault notification requirements.
Because the devices are also power switches, the designer
of self-powered hubs has the flexibility to turn off power to
output ports. Unlike a normal MOSFET, the devices have
controlled rising and falling times to provide the needed
inrush current limiting required for the bus-powered hub
power switch.
Supply Filter/Bypass Capacitor
A 0.1μF or greater low-ESR ceramic capacitor from VIN to
GND, located at the device is strongly recommended to
prevent the input voltage drooping during hot-plug events.
However, higher capacitor values will further reduce the
voltage droop on the input. Furthermore, without the
bypass capacitor, an output short may cause sufficient
ringing on the input (from source lead inductance) to
destroy the internal control circuitry. The input transient
must not exceed 6V of the absolute maximum supply
voltage even for a short duration.
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RT9731A/B
Output Filter Capacitor
A low-ESR 150μF capacitor between VOUT and GND is
strongly recommended to meet the 330mV maximum
droop requirement in the hub VBUS (Per USB 2.0, output
ports must have a minimum 120μF of low-ESR bulk
capacitance per hub). Standard bypass methods should
be used to minimize inductance and resistance between
the bypass capacitor and the downstream connector to
reduce EMI and decouple voltage droop caused when
downstream cables are hot-insertion transients. Ferrite
beads in series with VBUS, the ground line and the 0.1μF
bypass capacitors at the power connector pins are
recommended for EMI and ESD protection. The bypass
capacitor itself should have a low dissipation factor to allow
decoupling at higher frequencies.
Voltage Drop
The USB specification states a minimum port-output
voltage in two locations on the bus, 4.75V out of a SelfPowered Hub port and 4.4V out of a Bus-Powered Hub
port. As with the Self-Powered Hub, all resistive voltage
drops for the Bus-Powered Hub must be accounted for to
guarantee voltage regulation (see Figure 7-47 of “Universal
Serial Bus Specification Revision 2.0”).
The following calculation determines VOUT (MIN) for multiple ports (NPORTS) ganged together through one switch (if
using one switch per port, NPORTS is equal to 1) :
The USB specification defines the maximum resistance
per contact (RCONN) of the USB connector to be 30mΩ
and the drop across the PCB and switch to be 100mV.
This basically leaves two variables in the equation : the
resistance of the switch and the resistance of the cable.
If the hub consumes the maximum current (II) of 500mA,
the maximum resistance of the cable is 90mΩ.
The resistance of the switch can be defined as follows :
RSWITCH = { 4.75V − 4.4V − [ 0.5A x ( 4 x 30mΩ + 2 x
90mΩ) ] − VPCB } ( 0.1A x NPORTS )
= (200mV − VPCB ) ( 0.1A x NPORTS )
If the voltage drop across the PCB is limited to 100mV,
the maximum resistance for the switch is 250mΩ for four
ports ganged together. The RT9731A/B, with its maximum
50mΩ on-resistance over temperature can fit the demand
of this requirement.
Thermal Shutdown
Thermal protection limits power dissipation in the
RT9731A/B. When the operation junction temperature
exceeds 120°C (typ.), the OTP circuit starts the thermal
shutdown function and turns the pass element off. The
pass element turns on again after the junction temperature
cools to 80°C. The IC lowers its OTP trip level from 120°C
to 100°C when output short circuit occurs (VOUT < 1V) as
shown in Figure 2.
VOUT (MIN) = 4.75V − [ II x ( 4 x RCONN + 2 x RCABLE ) ] −
VOUT Short to GND
(0.1A x NPORTS x RSWITCH ) − VPCB
Where
1V
RCONN = Resistance of connector contacts
(two contacts per connector)
VOUT
IOUT
RCABLE = Resistance of upstream cable wires
(one 5V and one GND)
RSWITCH = Resistance of power switch
(44mΩ typical for RT9731A/B)
Thermal
Shutdown
120 C 100 C
OTP Trip Point
100 C
VPCB = PCB voltage drop
IC Temperature
80 C
Figure 2. Short Circuit Thermal Folded Back Protection
when Output Short Circuit Occurs (Patent)
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RT9731A/B
Thermal Considerations
Layout Consideration
For continuous operation, do not exceed absolute
maximum operation junction temperature. The maximum
power dissipation depends on the thermal resistance of
IC package, PCB layout, the rate of surroundings airflow
and temperature difference between junction to ambient.
The maximum power dissipation can be calculated by
following formula :
For best performance of the RT9731A/B series, the
following guidelines must be strictly followed.
where T J(MAX) is the maximum operation junction
temperature, TA is the ambient temperature and the θJA is
the junction to ambient thermal resistance.
For recommended operating conditions specification. The
maximum junction temperature is 125°C. The junction to
ambient thermal resistance θJA is layout dependent. For
WDFN-10L 3x3 package, the thermal resistance θJA is
70°C/W on a standard JEDEC 51-7 four-layer thermal test
board. The maximum power dissipation at TA = 25°C can
be calculated by the following formula :
PD(MAX) = (125°C − 25°C) / (70°C/W) = 1.429W for
WDFN-10L 3x3 packages
The maximum power dissipation depends on operating
ambient temperature for fixed T J(MAX) and thermal
resistance θJA. The Figure 3 of derating curves allows the
designer to see the effect of rising ambient temperature
on the maximum power dissipation.
Maximum Power Dissipation (W)
1.6
Input and output capacitors should be placed close to
the IC and connected to ground plane to reduce noise
coupling.
The GND should be connected to a strong ground plane
for heat sink.
Keep the main current traces as possible as short and
wide.
The RISET resistor should be placed as close to the IC
as possible.
The input and output capacitors should
be placed as close as possible to the IC.
GND
CIN
GND
VIN
VIN
1
2
3
4
5
GND
PD(MAX) = (TJ(MAX) − TA) / θJA
11
10
9
8
7
6
COUT1
VOUT1
VOUT2
ISET
RISET
COUT2
GND
The main current trace
should be as possible
as short and wide.
The RISET resistor should
be placed as close to the
IC as possible.
Figure 4. PCB Layout Guide
Four-Layer PCB
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
0
25
50
75
100
125
Ambient Temperature (°C)
Figure 3. Derating Curve of Maximum Power Dissipation
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
www.richtek.com
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is a registered trademark of Richtek Technology Corporation.
DS9731A/B-02 May 2015
RT9731A/B
Outline Dimension
D2
D
L
E
E2
1
e
SEE DETAIL A
b
2
1
2
1
A
A1
A3
DETAIL A
Pin #1 ID and Tie Bar Mark Options
Note : The configuration of the Pin #1 identifier is optional,
but must be located within the zone indicated.
Dimensions In Millimeters
Dimensions In Inches
Symbol
Min
Max
Min
Max
A
0.700
0.800
0.028
0.031
A1
0.000
0.050
0.000
0.002
A3
0.175
0.250
0.007
0.010
b
0.180
0.300
0.007
0.012
D
2.950
3.050
0.116
0.120
D2
2.300
2.650
0.091
0.104
E
2.950
3.050
0.116
0.120
E2
1.500
1.750
0.059
0.069
e
L
0.500
0.350
0.020
0.450
0.014
0.018
W-Type 10L DFN 3x3 Package
Richtek Technology Corporation
14F, No. 8, Tai Yuen 1st Street, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: (8863)5526789
Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should
obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot
assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be
accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.
DS9731A/B-02 May 2015
www.richtek.com
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