®
RT9750
6-A Smart Load Switch Battery Charger
General Description
Features
The RT9750 is a 6-A smart load switch battery charger,
which integrates an internal load switch with charge pump
control and 4-path constant current/constant voltage
regulation, a 5-way hardware protection, and a 8-Channel
12-bit analog-to-digital converter. The RT9750 provides the
accurate analog-to-digital converter for voltage/current
measurement by I2C serial interface to report the battery
charging parameters and 3-way software protection and
flags.
Dual
Ordering Information
RT9750
Note :
Package Type
WSC : WL-CSP-42B 2.75x3.05 (BSC)
Richtek products are :
RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020.
Suitable for use in SnPb or Pb-free soldering processes.
Marking Information
0T : Product Code
0T YM
DNN
Internal Load Switch with Charge Pump Control
YMDNN : Date Code
NFETs in a Back to Back Configuration
Internal Charge Pump Control
4-Path CC/CV Regulation
Input Current Regulation (ICR)
Output Voltage Regulation (OVR)
Battery Voltage Regulation (BVR)
Battery Current Regulation (BCR)
5-Way Hardware Protection
VBUS Over-Voltage Protection (VBUS_OVP)
Drop-Out Over-Voltage Protection (VDR_OVP)
Reverse Over-Current Protection (RE_OCP)
Junction Over-Temperature Protection (TJ_OTP)
Input Over-Current Protection (IOC_OCP)
8-Channel 12-bit ADC
High Accuracy of 12-bit Resolution
8-Channel for Voltage/Current Measurement
High Speed Data Rate for 8/16 Times Average
per Channel
3-Way Software Protection
Drop-Out Over-Voltage Protection Alarm
(VDR_ALM)
TS of the VBUS Over-Temperature Protection
(TBUS_OTP)
TS of the BAT Over-Temperature Protection
(TBAT_OTP)
Applications
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Handheld Products
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RT9750
Pin Configuration
(TOP VIEW)
A1
A2
A3
A4
A5
A6
NC
NC
VOUT
VOUT
PMID
VBUS
B1
B2
B3
SCL TSVBUS VOUT
C1
C2
C3
SDA
INT
VOUT
B4
B5
B6
VOUT
PMID
VBUS
C4
C5
VOUT PMID
C6
VBUS
D1
D2
D3
D4
D5
D6
TSBAT
EN
VOUT
VOUT
PMID
VBUS
E3
E4
E1
E2
GND
GND
F1
F2
GND
GND
G1
VOUT VOUT
F3
E6
VBUS
F4
VOUT VOUT
G2
BATN
E5
PMID
G3
G4
BATP VOUT VOUT
F5
F6
PMID
VBUS
G5
G6
PMID
VBUS
WL-CSP-42B 2.75x3.05 (BSC)
Typical Application Circuit
RT9750
Adapter
A6, B6, C6,
VBUS
D6, E6, F6, G6
VOUT
A5
B5
C5
PMID D5
E5
F5
G5
Pull up
Pull up
B2
C1
B1
Host
C2
D2
A3, B3, C3, D3, E3, F3, G3,
A4, B4, C4, D4, E4, F4, G4
TSVBUS
TSBAT
BATP
SDA
SCL
Pull up
D1
Battery
Pack
G2
1k ±1%
BATN G1
1k ±1%
INT
EN
GND
F2, E1, E2, F1
Below are recommended capacitor and inductor information
Pin
Description
Part Number
Package
Manufacturer
VBUS
1F/25V
GRM185R61E105KA12
0603
muRata
VOUT
10F/25V
GRM188R61E106MA73
0603
muRata
SRP / SRN
10m
1%
WMCS0805R010FSTA
0805
Wellcomp
BATP
BATN
1k
1%
WR04X1001FTL
0402
WAISIN
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RT9750
Functional Pin Description
Pin No.
A1, A2
Pin Name
NC
I/O
Pin Function
NC
No internal connection.
A6, B6, C6, D6, E6,
VBUS
F6, G6
P
DC input power supply.
A5, B5, C5, D5, E5,
PMID
F5, G5
NC
A3, B3, C3, D3, E3,
F3, G3, A4, B4, C4, VOUT
D4, E4, F4, G4
P
Battery connection point to positive terminal of the battery pack.
E1, E2, F1, F2
GND
P
Ground.
G1
BATN
AI
Negative input for battery current sensing by 1k. Connect to negative
terminal of battery pack.
G2
BATP
AI
Positive input for battery voltage sensing by 1k. Connect to positive
terminal of battery pack.
B2
TSVBUS
AI
VBUS temperature qualification voltage input. Require an external
resistor divider and a voltage reference.
D1
TSBAT
AI
Battery temperature qualification voltage input. Require an external
resistor divider and a voltage reference.
C1
SDA
DI
I2C interface data. Connect to pull-up voltage via 10k pull-up resistor.
B1
SCL
DIO
I2C interface clock. Connect to pull-up voltage via 10k pull-up resistor.
D2
EN
DI
Device enable control pin. Pull low to disable device. I2C not available
when disabled.
C2
INT
DO
Open drain interrupt output. connect to pull-up voltage via 10k pull-up
resistor. Normally high, the INT pin sends an active low.
Connect these pin together and do not connect to power input or
ground.
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RT9750
Functional Block Diagram
Power
Select
-
VREF
-
VREF
+
+
VDDA
VBUS
VOUT
IBUS
Fast
Discharge
VOUT
Internal Charge Pump
with CC and CV
Regulation
(ICR, OVR, BVR,
BCR)
+
-
BATP
BATN
VBUS_OVP
VDR_OVP
RE_OCP
EN
Hardware
Protection
TJ_OTP
Digital Core
IOC_OCP
SDA
VDR_ALM
SCL
TBUS_OTP
INT
Software
Protection
TBAT_OTP
10 Channel 12-bit ADC
VOUT
VBUS
VBUS_ADC
VOUT_ADC
BATP
VBUS
VDR_ADC
BAT_ADC
VOUT
BATN
IBUS
TSVBUS
IBUS_ADC
TSVBUS_ADC
TDIE_ADC
TSBAT_ADC
TDIE
TSBAT
GND
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is a registered trademark of Richtek Technology Corporation.
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RT9750
Absolute Maximum Ratings
(Note 1)
Supply Pin Voltage, VBUS -------------------------------------------------------------------------------------------Supply Pin Voltage, VOUT ------------------------------------------------------------------------------------------- Other Pin Voltage ------------------------------------------------------------------------------------------------------- Power Dissipation, PD @ TA = 25°C
WL-CSP-42B 2.75x3.05 (BSC) -------------------------------------------------------------------------------------- Package Thermal Resistance (Note 2)
WL-CSP-42B 2.75x3.05 (BSC), θJA -------------------------------------------------------------------------------- Junction Temperature -------------------------------------------------------------------------------------------------- Lead Temperature (Soldering, 10 sec.) ---------------------------------------------------------------------------- Storage Temperature Range ------------------------------------------------------------------------------------------ ESD Susceptibility (Note 3)
HBM (Human Body Model) -------------------------------------------------------------------------------------------
Recommended Operating Conditions
−0.3V to 22V
−0.3V to 22V
0.3V to 6V
3.54W
28.2°C/W
150°C
260°C
−65°C to 150°C
2kV
(Note 4)
Supply Input Voltage Range, VBUS --------------------------------------------------------------------------------Supply Input Voltage Range, VOUT --------------------------------------------------------------------------------Analog Sense Voltage Range, BATP, BATN ----------------------------------------------------------------------Temperature Sense Voltage Range, TSVBUS, TSBAT ---------------------------------------------------------Output Sink Current, INT ----------------------------------------------------------------------------------------------Junction Temperature Range -----------------------------------------------------------------------------------------Ambient Temperature Range ------------------------------------------------------------------------------------------
3.0V to 6V
3.0V to 6V
0V to 5V
0V to 3V
1mA
−40°C to 125°C
−40°C to 85°C
Electrical Characteristics
(TA = 25°C, unless otherwise specified)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
2.7
2.8
2.9
V
50
150
250
mV
Input Power Source
VDDA_VBUS_UVLO
VDDA rising, VBUS > VOUT,
VDDA = VBUS
VDDA_VOUT_UVLO
VDDA rising, VBUS < VOUT,
VDDA = VOUT
VDDA_VBUS_HYS
VDDA falling, VBUS > VOUT,
VDDA = VBUS
VDDA_VOUT_HYS
VDDA falling, VBUS < VOUT,
VDDA = VOUT
VBUS Quiescent
Current
IQ_VBUS
VBUS = 4.2V > VOUT, charge mode,
LDSW enable
3
4
6
mA
VOUT Quiescent
Current
IQ_VOUT
VOUT = 4.2V > VBUS, battery mode,
ADC enable
2
3
5
mA
VOUT Leakage Current
ILEAK_VOUT
VOUT = 4.2V > VBUS, EN disable
0.5
1
1.5
A
VBAT Insert
VBAT_INSERT
VBAT = BATP-BATN
1.9
2
2.1
V
VDDA UVLO Threshold
VDDA UVLO Hysteresis
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RT9750
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
--
8
10
m
I2C programmable
0.4
--
6.35
A
7-bit DAC
25
50
75
mA
I2C programmable
4.2
--
5
V
5
10
15
mV
4.2
--
5
V
5
10
15
mV
I2C programmable
4.2
--
6.5
V
7-bit DAC
12.5
25
37.5
mV
I2C programmable
0
--
1000
mV
7-bit DAC
5
10
15
mV
Default, load switch RON = 10m
0.5
1.5
2.5
A
1-value
115
125
140
°C
0
--
6.5
A
250
500
750
mA
I2C programmable
0
--
1000
mV
Drop-Out ALM Step
7-bit DAC
5
10
15
mV
TSVBUS OTP
Threshold
I2C programmable
0
--
2.4
V
7-bit DAC
10
20
30
mV
I2C programmable
0
--
2.4
V
7-bit DAC
10
20
30
mV
Load Switch On-Resistance and Regulation
Load Switch
On-Resistance
IBUS REG Threshold
Range
IBUS REG Threshold
Step
VOUT REG Threshold
Range
VOUT REG Threshold
Step
VBAT REG Threshold
Range
VBAT REG Threshold
Step
RON_LDSW
IBUS_REG
VOUT_REG
7-bit DAC
I2C programmable
VBAT_REG
7-bit DAC
Hardware Protection
VBUS OVP Threshold
Range
VBUS_OVP
VBUS OVP Threshold
Step
Drop-Out OVP
Threshold
VDROP_OVP
Drop-Out OVP Step
Reverse OCP
Threshold
IRE_OCP
Junction OTP Threshold TJC_OTP
Input OCP Threshold
IOC_OCP
Input OCP Step
2
I C programmable
4-bit DAC
Software Protection
Drop-Out ALM
Threshold
VDROP_ALM
VTSVBUS_OTP
TSVBUS OTP Step
TSBAT OTP Threshold
TSBAT OTP Step
VTSBAT_OTP
ADC Specification
ADC Sample Rate
f SAMPLE_ADC
(Note 5)
--
2.25
--
MHz
ADC Data Rate
f DATA_ADC
(Note 5), 16 averages
--
10
--
kHz
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RT9750
Parameter
Symbol
VBUS ADC Range
VBUS_ADC_RAN
VBUS ADC Accuracy
VBUS_ADC_ACC
IBUS ADC Range
IBUS_ADC_RAN
IBUS ADC Accuracy
IBUS_ADC_ACC
VOUT ADC Range
VOUT_ADC_RAN
VOUT ADC Accuracy
VOUT_ADC_ACC
VDROP ADC Range
VDROP_ADC_RAN
VDROP ADC Accuracy
VDROP_ADC_ACC
VBAT ADC Range
VBAT_ADC_RAN
VBAT ADC Accuracy
VBAT_ADC_ACC
TSVBUS ADC Range
VTSVBUS_ADC_RAN
TSVBUS ADC Accuracy VTSVBUS_ADC_ACC
TSBAT ADC Range
VTSBAT_ADC_RAN
TSBAT ADC Accuracy
VTSBAT_ADC_ACC
Junction Thermal ADC
Range
TJC_ADC_RAN
Junction Thermal ADC
Accuracy
TJC_ADC_ACC
Test Conditions
VDDA > 3V, 16 averages
VDDA > 3V, 16 averages
VDDA > 3V, 16 averages
VDDA > 3V, 16 averages
VDDA > 3V, 16 averages
VDDA > 3V, 16 averages
VDDA > 3V, 16 averages
Min
Typ
Max
Unit
1.5
--
6.5
V
15
--
15
mV
0
--
7
A
200
--
200
mA
1.5
--
6.5
V
15
--
15
mV
0
--
1000
mV
15
--
15
mV
2.5
--
5
V
15
--
15
mV
0
--
2.4
V
15
--
15
mV
0
--
2.4
V
15
--
15
mV
0
--
125
°C
3
--
3
°C
VDDA > 3V, 16 averages
I2C Interface
Serial-Clock Frequency
f SCL_I2C
(Note 5)
10
--
1000
kHz
I2C Input Logic
Threshold
VIH_I2C
Logic high
1.5
--
--
V
VIL_I2C
Logic low
--
--
0.4
V
EN Input Logic
Threshold
VIH_EN
Logic high
1
--
--
V
VIL_EN
Logic low
--
--
0.4
V
EN Pull Down Resistor
RPD_EN
On chip
--
500
--
k
--
--
500
s
EN Input
Device turn-on delay
time after EN pull-high
Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may affect
device reliability.
Note 2. θJA is measured under natural convection (still air) at TA = 25°C with the component mounted on a high effectivethermal-conductivity four-layer test board on a JEDEC 51-7 thermal measurement standard.
Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
Note 5. Specification is guaranteed by design and/or correlation with statistical process control.
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RT9750
Typical Operating Characteristics
4.44
4.43
4.43
4.42
4.42
VBAT ADC (V)
VBAT ADC (V)
VOUT ADC vs. Temperature
VBAT ADC vs. Temperature
4.44
4.41
4.40
4.39
4.41
4.40
4.39
4.38
4.38
4.37
4.37
VBAT = 4.4V
4.36
VOUT = 4.4V
4.36
-20
-5
10
25
40
55
-20
70
-5
10
Temperature (°C)
55
70
VOUT REG vs. Temperature
4.55
4.0
4.50
3.5
VOUT REG Set (V)
Battery Quiescent ( μ A)
Battery Quiescent vs. Temperature
3.0
2.5
2.0
1.5
1.0
4.5V
4.45
4.40
4.35V
4.35
4.30
4.25
4.2V
4.20
VBAT = 4.2V
0.0
4.15
-40 -25 -10
5
20
35
50
65
80
95 110 125
-40
-25
Temperature (°C)
-10
5
20
35
50
65
80
Temperature (°C)
VBAT REG vs. Temperature
IBUS vs. Temperature
4.55
2.08
4.5V
4.50
4.45
2.06
4.40
IBUS (A)
VBAT REG Set (V)
40
Temperature (°C)
4.5
0.5
25
4.35V
4.35
4.30
4.25
2.04
2.02
4.2V
4.20
VBUS = 5V, IBUS_REG = 2A
4.15
2.00
-40
-25
-10
5
20
35
50
65
Temperature (°C)
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8
80
-40
-20
0
20
40
60
80
Temperature (°C)
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RT9750
IBUS vs. Temperature
4.16
IBUS (A)
4.14
4.12
4.10
4.08
VBUS = 5V, IBUS_REG = 4A
4.06
-40
-20
0
20
40
60
80
Temperature (°C)
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RT9750
Application Information
Device Power On
The internal bias circuit (VDDA) are powered from higher
of two voltages between VBUS and VOUT. The device will
powered on when the VDDA is higher than VDDA UVLO
threshold and EN pin is higher than VIH_EN. In VBUS >
VDDA UVLO & EN pin from low logic to high logic
condition, the device need maximum 500μs turn on delay
time after EN pin set to high logic.
Smart Load Switch
The RT9750 is a 8mΩ RON and loading can up to 6-A
smart load switch battery charger. The load switch can
be controlled by the host via I2C. The load switch can be
turn on by set CHG_EN bit to “1” (0x06 bit4) if no
protection event happened (Please check 0X03 & 0X04).
The load switch can be turn off by set CHG_EN bit to “0”
or pull EN pin to low. If the protection event happen the
load switch will be turn off automatically and set CHG_EN
bit to “0” The smart load switch also implement soft-on
& soft off to function minimize the inrush current and
voltage spike.
8-Channel 12-bit Analog to Digital Converter
The device integrate 8-Cannel 12 bit ADC function, user
can monitor voltage of VBUS, VOUT, VDROP (voltage
different between VBUS and VOUT), and VBAT. The user
also can monitor the internal junction temperature, battery
temperature (by external resistor divider and NTC
thermistor), and VBUS temperature (by external resistor
divider and NTC thermistor). The ADC function also provide
IBUS information for user to monitor.
User can set ADC_EN (0x07 bit3) bit to enable or disable
ADC conversion. User also can enable or disable ADC
channels respective by using register 0x07 and 0x08. The
ADC has two conversion rate 1- shot mode and continuous
mode. User can select the mode by ADC_RATE bit (0X07
bit2).
1. 1-shot mode
In this mode, user need to set ADC_EN bit to 1 to start
ADC conversion. The ADC_EN bit will change to 0
automatically after ADC start conversion. After the ADC
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conversion complete, the ADC_DONE bit (0x04 bit6) will
change to 1 and INT pin will pull low if the
ADC_DONE_MASK bit is no mask. The typical conversion
time of one channel is 100μs (16 averages).
2. Continuous mode
In continuous mode, ADC conversion continuously if user
set ADC_EN bit to 1 and ADC stop conversion if user set
ADC_EN bit to 0.
User can set the ADC_AVG_EN bit to enable or disable
ADC measurement averaging function in both 1-shot mode
and continuous mode. If ADC_AVG_EN = 0 the ADC is
instantaneous measurement. If ADC_AVG_EN = 1 the ADC
is averaging measurement and user can set the number
of samples by ADC_SAMPLES bit.
Linear Regulation Mode (LDO)
The load switch implement LDO mode to regulate VOUT
voltage, battery voltage and input current. If an event that
VOUT_REG, VBAT_REG or IBUS_REG threshold is
exceeded, the load switch act as LDO and will regulate
VOUT, VBAT, IBUS (depending upon which threshold is
exceeded). These regulations threshold can be selected
by I2C.
Protection Features
The load switch implement 5 way hardware protection
and 2 temperature protection as below. All these protection
functions have IRQ and active with INT pin to inform host
to monitor which protection is active.
1. VBUS Over-Voltage Protection (VBUS_OVP)
When VBUS_OVP event is happened the device will turn
off load switch and the CHG_EN bit will be set to 0. User
can enable or disable this protection function by I2C 0x06
bit 7. The protection threshold and deglitch time also can
be selected by I2C (Protection threshold is 0x0A, deglitch
time is 0x09 bit0).
2. VBUS Over-Temperature Protection (TSVBUS_OTP)
As below picture, user need to place an external NTC
voltage dived circuit at TSBUS pin. When the voltage of
TSBUS pin is over the threshold, the device will turn off
load switch and set CHG_EN bit to 0. User can enable or
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RT9750
disable this protection function by I2C (0x05 bit2). Use
also can set the threshold by I2C (0x11).
Due to the VDROP_ALM is an alarm signal, user should
set VDROP_OVP threshold higher than VDROP_ALM.
6. Junction Thermal Shutdown (TSHUT_FLT)
Pull Up
TVBUS
The device will turn off load switch and set CHG_EN bit to
“0” if the threshold of junction temperature shutdown is
triggered. If the junction thermal shutdown is triggered
device asserted INT low to alert the host (no mask for
TSHUT_FLT) and also set the TSHUT_FLT bit to “1”.
7. IBUS Over-Current protection (IOC_FLT)
3. VBAT Over-Temperature Protection
(TSBAT_OTP)
As below picture, user need to place an external NTC
voltage dived circuit at TSBAT pin. When the voltage of
TSBAT pin is over the threshold, the device will turn off
load switch and set CHG_EN bit to 0. User can enable or
disable this protection function by I2C (0x05 bit1). Use
also can set the threshold by I2C (0x12).
Pull Up
TSBAT
4. IBUS Reverse Current Protection (IBUS_ IREV)
The device implement a reverse current protection function
to turn off load switch when the reverse current is detected
(current flow from VOUT to VBUS). The device set CHG_EN
to “0” when this event is detected. The user can set the
protection level and deglitch time by I2C (0x26 set level,
0x27 set deglitch).
The device monitor the current flow from VBUS to VOUT.
If the current over the threshold the device has two
protection option for user to select by I2C. If user set
OCP_RES bit “0” (blanking mode), the device will turn
off load switch and set CHG_EN to “0” when IBUS current
over IOC threshold. If user set OCP_RES bit “1” (hiccup
mode), load switch is disabled instantaneously, and the
device will attempt to turn on the load switch wait 250μs
to check OCP and turn off every 100ms, up to 7 times
before latching off.
I2C Interface Timing Diagram
The RT9750 acts as an I2C- bus slave. The I2C-bus master
configures the settings for charge mode by sending
command bytes to the RT9750 via the 2-wire7 I2C-bus.
After the START condition the I2C master sends a chip
address. This address is seven bits long followed by an
eighth bit which is a data direction bit(R/W). The second
byte selects the register to which the data will be written.
The third byte contains data to the selected register.
5. Dropout Voltage Protection (VDROP_OVP)
VDROP is the voltage different between VBUS and VOUT.
The device implement two VDROP threshold for user to
set by I2C. One is VDROP_LAM and the other on is
VDROP_OVP. User can use these thresholds to monitor
the health of load switch. When the VDROP_ALM
threshold be triggered the device assert INT pin low to
alert the host. If VDROP_OVP threshold is be triggered
the device will turn off the load switch and set CHG_EN
bit to “0”.
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RT9750
Start
The 1st Byte
(Slave Address, R/W)
The 2nd Byte
(Data Address, Data)
The 3rd Byte (Data)
1 1 0 1 0 0 1 R/W
B7B6B5B4B3B2B1B0
C7C6C5C4C3C2C1C0
Stop
S
P
SCL
SDA
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
0 A6 A5 A4 A3 A2 A1 A0 W ACK B7 B6 B5 B4 B3 B2 B1 B0 ACK C7 C6 C5 C4 C3 C2 C1 C0 ACK
Thermal Considerations
under Absolute Maximum Ratings, to avoid permanent
damage to the device. The maximum allowable power
dissipation depends on the thermal resistance of the IC
package, the PCB layout, the rate of surrounding airflow,
and the difference between the junction and ambient
temperatures. The maximum power dissipation can be
calculated using the following formula :
PD(MAX) = (TJ(MAX) − TA) / θJA
where TJ(MAX) is the maximum junction temperature, TA is
the ambient temperature, and θJA is the junction-to-ambient
thermal resistance.
Maximum Power Dissipation (W)1
The junction temperature should never exceed the
absolute maximum junction temperature TJ(MAX), listed
4.0
Four-Layer PCB
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
0
25
50
75
100
125
Ambient Temperature (°C)
Figure 1. Derating Curve of Maximum Power Dissipation
For continuous operation, the maximum operating junction
temperature indicated under Recommended Operating
Conditions is 125°C. The junction-to-ambient thermal
resistance, θJA, is highly package dependent. For a WLCSP-42B 2.75x3.05 (BSC) package, the thermal
resistance, θJA, is 28.2°C/W on a standard JEDEC 51-7
high effective-thermal-conductivity four-layer test board.
The maximum power dissipation at TA = 25°C can be
calculated as below :
PD(MAX) = (125°C − 25°C) / (28.2°C/W) = 3.54W for a WLCSP-42B 2.75x3.05 (BSC) package.
The maximum power dissipation depends on the operating
ambient temperature for the fixed TJ(MAX) and the thermal
resistance, θJA. The derating curves in Figure 1 allows
the designer to see the effect of rising ambient temperature
on the maximum power dissipation.
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RT9750
Register Descriptions
I2C Slave Address is 1100111 (67H)
Name
Function
Addr
Reset
DEVICE_INFO
DEVICE_INFO
0x00
0x00
Description
Bit
Mode
Name
Reset Value
[5:3]
R
DEVICE_RE
000
Device revision
[2:0]
R
DEVICE_ID
000
Device ID
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13
RT9750
Name
Function
Addr
Reset
EVENT_1_MASK
MASK
0x01
0x00
Name
Reset Value
Description
Bit
7
6
Mode
R/W
R/W
VBUS_OVP_MASK
IBUS_REG_MASK
0
VBUS over-voltage fault mask.
0 – no mask. INT will toggle when VBUS_OVP_FLT bit
is set. (default)
1 – VBUS_OVP_FLT is masked. INT will not toggle
when VBUS_OVP_FLT bit is set.
0
IBUS over-current fault mask.
0 – no mask. INT will toggle when IBUS_REG_FLT bit is
set. (default)
1 – IBUS_REG_FLT is masked. INT will not toggle
when IBUS_REG_FLT bit is set.
5
R/W
VBAT_REG_MASK
0
VBAT over-voltage fault mask.
0 – no mask. INT will toggle when VBAT_REG_LDO bit
is set. (default)
1 – VBAT_REG_LDO is masked. INT will not toggle
when VBAT_REG_LDO bit is set.
4
R/W
Reserved
0
Reserved
0
VOUT over-voltage fault mask.
0 – no mask. INT will toggle when VOUT_REG_LDO bit
is set. (default)
1 – VOUT_REG_LDO is masked. INT will not toggle
when VOUT_REG_LDO bit is set.
0
VBUS over-temperature fault mask.
0 – no mask. INT will toggle when TBUS_OTP_FLT bit
is set. (default)
1 – TBUS_OTP_FLT is masked. INT will not toggle
when TBUS_OTP_FLT bit is set.
0
BAT over-temperature fault mask.
0 – no mask. INT will toggle when TBAT_OTP_FLT bit
is set. (default)
1 – TBAT_OTP_FLT is masked. INT will not toggle
when TBAT_OTP_FLT bit is set.
0
IBUS reverse current fault mask.
0 – no mask. INT will toggle when IBUS_REV_FLT bit is
set. (default)
1 – IBUS_REV_FLT is masked. INT will not toggle when
IBUS_REV_FLT bit is set.
3
2
1
0
R/W
R/W
R/W
R/W
VOUT_REG_MASK
TBUS_OTP_MASK
TBAT_OTP_MASK
IBUS_IREV_MASK
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RT9750
Name
Function
Addr
Reset
EVENT_2_MASK
MASK
0x02
0x00
Name
Reset Value
Description
Bit
7
6
5
4
3
2
1
0
Mode
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LOWCHG_ALM_MASK
ADC_DONE_MASK
VDROP_ALM_MASK
VDROP_OVP_MASK
VBUS_INSERT_MASK
BAT_INSERT_MASK
TSHUT_FLT_MASK
R/W
IOC_FLT_MASK
0
LOWCHG_ALM event mask.
0 – no mask. INT will toggle when LOWCHG_ALM
bit is set. (default)
1 – LOWCHG_ALM is masked. INT will not toggle
when LOWCHG_ALM bit is set.
0
ADC_DONE event mask.
After all required CHs complete, set ADC_DONE
0 – no mask. INT will toggle no mask when
ADC_DONE bit is set. (default).
1 – ADC_DONE bit is masked. INT will not toggle
when ADC_DONE bit is set.
0
VDROP_ALM_FLT mask.
0 – no mask. INT will toggle when
VDROP_ALM_FLT bit is set. (default)
1 – VDROP_ALM_FLT is masked. INT will not
toggle when VDROP_ALM_FLT bit is set.
0
VDROP_OVP_FLT mask.
0 – no mask. INT will toggle when
VDROP_OVP_FLT bit is set. (default)
1 – VDROP_OVP_FLT is masked. INT will not
toggle when VDROP_OVP_FLT bit is set.
0
VBUS_INSERT mask.
0 – no mask. INT will toggle when VBUS_INSERT
bit is set. (default)
1 – VBUS_INSERT is masked. INT will not toggle
when VBUS_INSERT bit is set.
0
BAT_INSERT mask.
0 – no mask. INT will toggle when BAT_INSERT bit
is set. (default)
1 – VBUS_INSERT is masked. INT will not toggle
when BAT_INSERT bit is set.
0
TSHUT_FLT mask.
0 – no mask. INT will toggle when TSHUT_FLT bit is
set. (default)
1 – TSHUT_FLT is masked. INT will not toggle
when TSHUT_FLT bit is set.
0
IOC_FLT mask.
0 – no mask. INT will toggle when IOC_FLT bit is
set. (default)
1 – IOC_FLT is masked. INT will not toggle when
IOC_FLT bit is set.
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15
RT9750
Name
Function
Addr
Reset
EVENT_1
EVENT
0x03
0x00
Name
Reset Value
Description
Bit
7
6
Mode
R/C
R/C
VBUS_OVP_FLT
IBUS_REG_LDO
0
VBUS over-voltage fault. This bit is set when the VBUS
voltage exceeds the limit set in VBUS_OVP register.
0 – no fault (default)
1 – VBUS OVP fault
0
Indicates if in LDO mode due to IBUS regulation
threshold.
0 – no fault (default)
1 – IBUS in regulation
5
R/C
VBAT_REG_LDO
0
Indicates if in LDO mode due to VBAT regulation
threshold.
0 – no in regulation (default)
1 – VBAT in regulation
4
R/C
Reserved
0
Reserved
0
Indicates if in LDO mode due to VOUT regulation
threshold.
0 – not in regulation (default)
1 – VOUT in regulation
0
VBUS over-temperature fault. This bit is set when the
TS_BUS voltage exceeds the limit set in TBUS_OTP
register.
0 – no fault (default)
1 – VBUS over-temperature fault
0
BAT over-temperature fault. This bit is set when the
TS_BAT voltage exceeds the limit set in TBAT_OTP
register.
0 – no fault (default)
1 – BAT over-temperature fault
0
IBUS reverse current fault. This bit is set when current
from BAT to VBUS is detected. The battery switch will be
disabled when reverse current is detected.
0 – no fault (default)
1 – IBUS reverse current fault
3
2
1
0
R/C
R/C
R/C
R/C
VOUT_REG_LDO
TBUS_OTP_FLT
TBAT_OTP_FLT
IBUS_IREV_FLT
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RT9750
Name
Function
Addr
Reset
EVENT_2
EVENT
0x04
0x00
Name
Reset Value
Description
Bit
7
Mode
R/C
LOWCHG_ALM_FLT
0
Indicates if LOWCHG_ALM threshold is reached.
0 – no LOWCHG_ALM (default)
1 – LOWCHG_ALM when CHG_EN and IBUS <
threshold
6
R/C
ADC_DONE
0
Indicates if the ADC conversion is complete for the
requested parameters in 1-shot mode only (set from
0x07).
0 – Conversion not complete (default)
1 – Conversion complete
5
R/C
VDROP_ALM_FLT
0
Indicates if VDROP_ALM threshold is reached.
0 – no fault (default)
1 – VDROP_ALM fault
4
R/C
VDROP_OVP_FLT
0
Indicates if VDROP_OVP threshold is reached.
0 – no fault (default)
1 – VDROP_OVP fault
3
R/C
VBUS_INSERT
0
Indicates if VBUS is detected
0 – no VBUS (default)
1 – VBUS inserted (VBUS > 2.8V)
2
R/C
BAT_INSERT
0
Indicates if battery is detected (sensed between BATP
and BATN).
0 – no BAT (default)
1 – BAT inserted (VBAT > 2.0V)
1
R/C
TSHUT_FLT
0
IC thermal shutdown fault indicator. (TDIE > 125℃)
0 – Normal operation (default)
1 – Thermal shutdown
0
Indicates if high current from VBUS to VOUT has hit the
internal threshold.
0 – no fault (default)
1 – High current fault
0
R/C
IOC_FLT
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17
RT9750
Name
Function
Addr
Reset
EVENT_1_EN
EVENT_EN
0x05
0xFE
Description
Bit
Mode
Name
Reset Value
7
R/W
VBUS_OVP_EN
1
Enables VBUS_OVP protection
0 – Disable VBUS OVP protection
1 – Enable VBUS OVP protection (default)
6
R/W
IBUS_REG_EN
1
Enables IBUS regulation for LDO mode
0 – Disable IBUS OCP protection
1 – Enable IBUS OCP protection (default)
5
R/W
VBAT_REG_EN
1
Enables VBAT regulation for LDO mode
0 – Disable VBAT regulation
1 – Enable VBAT regulation (default)
4
R/W
Reserved
1
Reserved
3
R/W
VOUT_REG_EN
1
Enables VOUT regulation in LDO mode
0 – Disable VOUT regulation
1 – Enable VOUT regulation (default)
2
R/W
TBUS_OTP_EN
1
Enables TS_VBUS pin protection
0 – Disable TBUS_OTP
1 – Enable TBUS_OTP (default)
1
R/W
TBAT_OTP_EN
1
Enables TS_BAT pin protection
0 – Disable TBAT_OTP
1 – Enable TBAT_OTP (default)
0
R/W
VBUS_PD_EN
0
Enables the VBUS pull-down resistor
0 – Disable RVBUS_PD (default)
1 – Enable RVBUS_PD
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RT9750
Name
Function
Addr
Reset
CONTROL
CONTROL
0x06
0x2A
Description
Bit
Mode
Name
Reset Value
7
R/W
VDROP_OVP_EN
0
Enables VDROP_OVP protection
0 – Disable VDROP_OVP (default)
1 – Enable VDROP_OVP
6
R/W
VDROP_ALM_EN
0
Enables VDROP_ALM alarm
0 – Disable VDROP_ALM (default)
1 – Enable VDROP_ALM
5
R/W
Reserved
1
Reserved
4
R/W
CHG_EN
0
[3:2]
R/W
WATCHDOG
10
1
R/W
IREV_EN
1
0
R/W
REG_RST
0
Software bit for charge enable. This enables the Load
Switch. This bit will be set to ‘0’ if reset or any action of
FET turned off (STATUS register).
0 – Charge disabled (default)
1 – Charge enabled
Watchdog timer setting. R/W any register will clear the
watchdog timer. FET must turn off after watchdog timer
out.
00 – Disable watchdog timer
01 – 0.5sec
10 – 1.0sec (default)
11 – 2.0sec
Reverse current protection (RCP) comparator control.
0 – RCP disable
1 – RCP enable (default)
Register reset
0 – no reset (default)
1 – Reset all registers to their default values
Name
Function
Addr
Reset
ADC_CTRL
ADC_CTRL
0x07
0x8F
Description
Bit
Mode
Name
Reset Value
7
R/W
TDIE_ADC_EN
1
Enable/disable TDIE_ADC sampling
0 – Disable sampling
1 – Enable sampling (default)
3
R/W
ADC_EN
1
Enable/disable ADC
0 – Disable ADC
1 – Enable ADC (default)
2
R/W
ADC_RATE
1
Sets ADC conversion rate
0 – 1-shot conversion
1 – Continuous conversion (default)
1
R/W
ADC_AVG_EN
1
Enable/disable ADC measurement averaging
0 – Disable averaging (instantaneous measurement)
1 – Enable averaging (default)
1
Sets the number of samples to be taken for an ADC
conversion
0 – 8 samples taken for averaging
1 – 16 samples taken for averaging (default)
0
R/W
ADC_SAMPLES
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19
RT9750
Name
Function
Addr
Reset
SAMPLE_EN
SAMPLE_EN
0x08
0xFF
Description
Bit
Mode
Name
Reset Value
7
R/W
VBUS_ADC_EN
1
Enable/disable VBUS_ADC sampling
0 – Disable sampling
1 – Enable sampling (default)
6
R/W
IBUS_ADC_EN
1
Enable/disable IBUS_ADC sampling
0 – Disable sampling
1 – Enable sampling (default)
5
R/W
VOUT_ADC_EN
1
Enable/disable VOUT_ADC sampling
0 – Disable sampling
1 – Enable sampling (default)
4
R/W
VDROP_ADC_EN
1
Enable/disable VDROP_ADC sampling
0 – Disable sampling
1 – Enable sampling (default)
3
R/W
VBAT_ADC_EN
1
Enable/disable VBAT_ADC sampling
0 – Disable sampling
1 – Enable sampling (default)
2
R/W
Reserved
1
Reserved
1
R/W
TBUS_ADC_EN
1
Enable/disable TBUS_ADC sampling
0 – Disable sampling
1 – Enable sampling (default)
0
R/W
TBAT_ADC_EN
1
Enable/disable TBAT_ADC sampling
0 – Disable sampling
1 – Enable sampling (default)
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RT9750
Name
Function
Addr
Reset
PROT_DLY&OCP
PROT_DLY&OCP
0x09
0xA0
Bit
Mode
Name
Reset Value
[7:4]
R/W
IOC_OCP
1010
3
R/W
LOWCHG_ALM_EN
0
2
R/W
LOWCHG_ALM
Description
IOC_OCP (Input Over-Current Protection)
Offset : 0A
LSB : 4A, 2A, 1A, 0.5A
Range Min : 0A (0b0000)
Range Max : 6.5A (0b1101)
Default : 5A (0b1010)
Enables LOWCHG_ALM in CHG mode
0 – Disable LOWCHG_ALM (default)
1 – Enable LOWCHG_ALM
0
LOWCHG_ALM
0 – 50mA (default)
(0x15 = 00000, 0x16 = 00110010)
1 – 100mA
(0x15 = 00000, 0x16 = 01100100)
1
R/W
OCP_RES
0
Controls the response of the OCP event for IBUS.
0 – Blanking mode; the device will wait 50µs before the
battery switch is disabled and latched off (default)
1 – Hiccup mode; battery switch is disabled
instantaneously, and the device will attempt to turn on
the battery switch wait 250µs to check OCP and turn
off every 100ms, up to 7 times before latching off.
0
R/W
VBUS_OVP_DLY
0
Sets VBUS fault deglitch time
0 – 4s deglitch time (default)
1 – 20s deglitch time
Name
Function
Addr
Reset
VBUS_OVP
VBUS_OVP
0x0A
0x34
Name
Reset Value
Description
Bit
[6:0]
Mode
R/W
VBUS_OVP
0110100
VBUS_OVP
Offset : 4.2V
LSB : 1600mV, 800mV, 400mV, 200mV,
100mV, 50mV, 25mV
Range Min : 4.2V (0b0000000)
Range Max : 6.5V (0b1011100)
Default : 5.5V (0b0110100)
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21
RT9750
Name
Function
Addr
Reset
VOUT_REG
VOUT_REG
0x0B
0x14
Name
Reset Value
Description
VOUT_REG
0010100
VOUT_Regulation (BAT – GND)
Offset : 4.2V
LSB : 640mV, 320mV, 160mV, 80mV, 40mV,
20mV, 10mV
Range Min : 4.2V (0b0000000)
Range Max : 5.0V (0b1010000)
Default : 4.4V (0b0010100)
Name
Function
Addr
Reset
VDROP_OVP
VDROP_OVP
0x0C
0x1E
Name
Reset Value
Description
VDROP_OVP
0011110
VDROP_OVP
Offset : 0V
LSB : 640mV, 320mV, 160mV, 80mV, 40mV,
20mV, 10mV
Range Min : 0mV (0b0000000)
Range Max : 1000mV (0b1100100)
Default : 300mV (0b0011110)
Name
Function
Addr
Reset
VDROP_ALM
VDROP_ALM
0x0D
0x0A
Name
Reset Value
Description
VDROP_ALM
0001010
VDROP_ALM
Offset : 0V
LSB : 640mV, 320mV, 160mV, 80mV, 40mV,
20mV, 10mV
Range Min : 0mV (0b0000000)
Range Max : 1000mV (0b1100100)
Default : 100mV (0b0001010)
Name
Function
Addr
Reset
VBAT_REG
VBAT_REG
0x0E
0x0A
Name
Reset Value
Description
0001010
VBAT_Regulation (BATP – BATN)
Offset : 4.2V
LSB : 640mV, 320mV, 160mV, 80mV, 40mV,
20mV, 10mV
Range Min : 4.2V (0b0000000)
Range Max : 5.0V (0b1010000)
Default : 4.3V (0b0001010)
Bit
[6:0]
Mode
R/W
Bit
[6:0]
Mode
R/W
Bit
[6:0]
Mode
R/W
Bit
[6:0]
Mode
R/W
VBAT_REG
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RT9750
Name
Function
Addr
Reset
IBUS_OCP
IBUS_OCP
0x10
0x64
Name
Reset Value
Description
Bit
Mode
[6:0]
R/W
IBUS_OCP (Input Current Regulation)
Offset : 0A
LSB : 3200mA, 1600mA, 800mA, 400mA,
200mA, 100mA, 50mA
Range Min : 0.40A (0b0001000)
Range Max : 6.35A (0b1111111)
Default : 5A (0b1100100)
IBUS_OCP
1100100
Name
Function
Addr
Reset
TBUS_OTP
TBUS_OTP
0x11
0x1E
Name
Reset Value
Description
Bit
Mode
[6:0]
R/W
TBUS_OTP
Offset : 0V
LSB : 1280mV, 640mV, 320mV, 160mV,
80mV, 40mV, 20mV
Range Min : 0V (0b0000000)
Range Max : 2.4V (0b1111000)
Default:0.6V (0b0011110)
External VREF = 1.8V, 10K/10K Divide
TBUS_OTP
0011110
Name
Function
Addr
Reset
TBAT_OTP
TBAT_OTP
0x12
0x23
Name
Reset Value
Description
Bit
[6:0]
Mode
R/W
TBAT_OTP
0100011
TBAT_OTP
Offset : 0V
LSB : 1280mV, 640mV, 320mV, 160mV,
80mV, 40mV, 20mV
Range Min : 0V (0b0000000)
Range Max : 2.4V (0b1111000)
Default : 0.7V (0b0100011)
External VREF = 1.8V, 10K/10K Divide
Name
Function
Addr
Reset
VBUS_ADC2
VBUS_ADC2
0x13
0x00
Description
Bit
Mode
Name
Reset Value
7
R
VBUS_POL
0
[4:0]
R
VBUS_ADC2
00000
Indicates polarity of VBUS
0 - Positive voltage
1 - Negative voltage
VBUS_ADC2
LSB : 1mV
LSB : 4096, 2048, 1024, 512, 256
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23
RT9750
Name
Function
Addr
Reset
VBUS_ADC1
VBUS_ADC1
0x14
0x00
Description
Bit
Mode
Name
Reset Value
[7:0]
R
VBUS_ADC1
00000000
Name
Function
Addr
Reset
IBUS_ADC2
IBUS_ADC2
0x15
0x00
Description
VBUS_ADC1
LSB : 1mV
LSB : 128, 64, 32, 16, 8, 4, 2, 1
Bit
Mode
Name
Reset Value
7
R
IBUS_POL
0
[4:0]
R
IBUS_ADC2
00000
Name
Function
Addr
Reset
IBUS_ADC1
IBUS_ADC1
0x16
0x00
Description
Indicates polarity of IBUS
0 - Positive current
1 - Negative current
IBUS_ADC2
LSB : 1mA
LSB : 4096, 2048, 1024, 512, 256
Bit
Mode
Name
Reset Value
[7:0]
R
IBUS_ADC1
00000000
Name
Function
Addr
Reset
VOUT_ADC2
VOUT_ADC2
0x17
0x00
Description
IBUS_ADC1
LSB : 1mA
LSB : 128, 64, 32, 16, 8, 4, 2, 1
Bit
Mode
Name
Reset Value
7
R
VOUT_POL
0
[4:0]
R
VOUT_ADC2
00000
Indicates polarity of VOUT
0 - Positive voltage
1 - Negative voltage
VOUT_ADC2
LSB : 1mV
LSB : 4096, 2048, 1024, 512, 256
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RT9750
Name
Function
Addr
Reset
VOUT_ADC1
VOUT_ADC1
0x18
0x00
Description
Bit
Mode
Name
Reset Value
[7:0]
R
VOUT_ADC1
00000000
Name
Function
Addr
Reset
VDROP_ADC2
VDROP_ADC2
0x19
0x00
Description
VOUT_ADC1
LSB : 1mV
LSB : 128, 64, 32, 16, 8, 4, 2, 1
Bit
Mode
Name
Reset Value
7
R
VDROP_POL
0
Indicates polarity of VDROP
0 - Positive voltage
1 - Negative voltage
[1:0]
R
VDROP_ADC2
00
VDROP_ADC2
LSB : 1mV
LSB : 512, 256
Name
Function
Addr
Reset
VDROP_ADC1
VDROP_ADC1
0x1A
0x00
Description
Bit
Mode
Name
Reset Value
[7:0]
R
VDROP_ADC1
00000000
Name
Function
Addr
Reset
VBAT_ADC2
VBAT_ADC2
0x1B
0x00
Description
VDROP_ADC1
LSB : 1mV
LSB : 128, 64, 32, 16, 8, 4, 2, 1
Bit
Mode
Name
Reset Value
7
R
VBAT_POL
0
[4:0]
R
VBAT_ADC2
00000
Name
Function
Addr
Reset
VBAT_ADC1
VBAT_ADC1
0x1C
0x00
Description
Indicates polarity of VBAT
0 - Positive voltage
1 - Negative voltage
VBAT_ADC2
LSB : 1mV
LSB : 4096, 2048, 1024, 512, 256
Bit
Mode
Name
Reset Value
[7:0]
R
VBAT_ADC1
00000000
VBAT_ADC1
LSB : 1mV
LSB : 128, 64, 32, 16, 8, 4, 2, 1
Copyright © 2017 Richtek Technology Corporation. All rights reserved.
DS9750-00 March 2017
is a registered trademark of Richtek Technology Corporation.
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25
RT9750
Name
Function
Addr
Reset
TBUS_ADC2
TBUS_ADC2
0x1F
0x03
Description
Bit
Mode
Name
Reset Value
7
R
TBUS_POL
0
[3:0]
R
TBUS_ADC2
0011
Name
Function
Addr
Reset
TBUS_ADC1
TBUS_ADC1
0x20
0x84
Description
Indicates polarity of TBUS
0 - Positive voltage
1 - Negative voltage
TBUS_ADC2
LSB : 1mV
LSB : 2048, 1024, 512, 256
Bit
Mode
Name
Reset Value
[7:0]
R
TBUS_ADC1
10000100
Name
Function
Addr
Reset
TBAT_ADC2
TBAT_ADC2
0x21
0x03
Description
TBUS_ADC1
LSB : 1mV
LSB : 128, 64, 32, 16, 8, 4, 2, 1
Bit
Mode
Name
Reset Value
7
R
TBAT_POL
0
[3:0]
R
TBAT_ADC2
0011
Name
Function
Addr
Reset
TBAT_ADC1
TBAT_ADC1
0x22
0x84
Description
Indicates polarity of TBAT
0 - Positive voltage
1 - Negative voltage
TBAT_ADC2
LSB : 1mV
LSB : 2048, 1024, 512, 256
Bit
Mode
Name
Reset Value
[7:0]
R
TBAT_ADC1
10000100
TBAT_ADC1
LSB : 1mV
LSB : 128, 64, 32, 16, 8, 4, 2, 1
Copyright © 2017 Richtek Technology Corporation. All rights reserved.
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26
is a registered trademark of Richtek Technology Corporation.
DS9750-00 March 2017
RT9750
Name
Function
Addr
Reset
TDIE_ADC1
TDIE_ADC1
0x23
0x00
Description
Bit
Mode
Name
Reset Value
[7:0]
R
TDIE_ADC1
00000000
Name
Function
Addr
Reset
EVENT_STATUS_1
STATUS_1
0x24
0x00
TDIE_ADC1
LSB : 1°C
LSB : 128, 64, 32, 16, 8, 4, 2, 1
Bit
Mode
Name
Reset Value
7
R
VBUS_OVP_STATUS
0
6
R
IBUS_REG_STATUS
0
Description
VBUS over-voltage fault. This bit is set
when the VBUS voltage exceeds the limit
set in VBUS_OVP register.
0 – no fault (default)
1 – VBUS OVP fault
Indicates if in LDO mode due to IBUS
regulation threshold.
0 – no fault (default)
1 – IBUS in regulation
5
R
VBAT_REG_STATUS
0
Indicates if in LDO mode due to VBAT
regulation threshold.
0 – no in regulation (default)
1 – VBAT in regulation
4
R
Reserved
0
Reserved
0
Indicates if in LDO mode due to VOUT
regulation threshold.
0 – not in regulation (default)
1 – VOUT in regulation
0
"VBUS over-temperature fault. This bit is
set when the TS_BUS voltage exceeds the
limit set in TBUS_OTP register.
0 – no fault (default)
1 – VBUS over-temperature fault"
0
"BAT over-temperature fault. This bit is set
when the TS_BAT voltage exceeds the
limit set in TBAT_OTP register.
0 – no fault (default)
1 – BAT over-temperature fault"
0
"IBUS reverse current fault. This bit is set
when current from BAT to VBUS is
detected. The battery switch will be
disabled when reverse current is detected.
0 – no fault (default)
1 – IBUS reverse current fault"
3
2
1
0
R
R
R
R
VOUT_REG_STATUS
TBUS_OTP_STATUS
TBAT_OTP_STATUS
IBUS_IREV_STATUS
Copyright © 2017 Richtek Technology Corporation. All rights reserved.
DS9750-00 March 2017
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
27
RT9750
Name
Function
Addr
Reset
EVENT_STATUS_2
STATUS_2
0x25
0x00
Description
Indicates if LOWCHG_ALM threshold is
reached.
0 – no LOWCHG_ALM (default)
1 – LOWCHG_ALM when CHG_EN and
IBUS < threshold
Indicates if the ADC conversion is
complete for the requested parameters in
1-shot mode only (set from 0x07).
0 – Conversion not complete (default)
1 – Conversion complete
Bit
Mode
Name
Reset Value
7
R
LOWCHG_ALM_STATUS
0
6
R
ADC_DONE_STATUS
0
5
R
VDROP_ALM_STATUS
0
Indicates if VDROP_ALM threshold is
reached.
0 – no fault (default)
1 – VDROP_ALM fault
4
R
VDROP_OVP_STATUS
0
Indicates if VDROP_OVP threshold is
reached.
0 – no fault (default)
1 – VDROP_OVP fault
3
R
VBUS_INSERT_STATUS
0
Indicates if VBUS is detected
0 – no VBUS (default)
1 – VBUS inserted (VBUS > 2.8V)
0
Indicates if battery is detected (sensed
between BATP and BATN).
0 – no BAT (default)
1 – BAT inserted (VBAT > 2.0V)
0
IC thermal shutdown fault indicator. (TDIE
> 125°C)
0 – Normal operation (default)
1 – Thermal shutdown
IOC_STATUS
0
Indicates if high current from VBUS to
VOUT has hit the internal threshold.
0 – no fault (default)
1 – High current fault
Name
Function
Addr
Reset
Control
Control
0x26
0x01
Name
Reset Value
Description
2
R
1
R
0
R
Bit
[3:0]
Mode
R/W
BAT_INSERT_STATUS
TSHUT_STATUS
IREV_OCP
Copyright © 2017 Richtek Technology Corporation. All rights reserved.
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28
0001
IREV_OCP (Ron = 10m)
Offset : 0A
LSB : 4A (40mV), 2A (20mV), 1A
(10mV), 0.5A (5mV)
Range Min : 0A (0b0000)
Range Max : 4A (0b1000)
Default : 500Ma (0b0001)
is a registered trademark of Richtek Technology Corporation.
DS9750-00 March 2017
RT9750
Outline Dimension
Dimensions In Millimeters
Symbol
Dimensions In Inches
Min
Max
Min
Max
A
0.500
0.600
0.020
0.024
A1
0.170
0.230
0.007
0.009
b
0.240
0.300
0.009
0.012
D
3.010
3.090
0.119
0.122
D1
E
2.400
2.710
0.094
2.790
0.107
0.110
E1
2.000
0.079
e
0.400
0.016
42B WL-CSP 2.75x3.05 Package (BSC)
Copyright © 2017 Richtek Technology Corporation. All rights reserved.
DS9750-00 March 2017
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
29
RT9750
Footprint Information
Package
Number of
Pin
WL-CSP2.75*3.05-42(BSC)
42
Type
NSMD
SMD
Footprint Dimension (mm)
e
0.400
Tolerance
A
B
0.240
0.340
0.270
0.240
±0.025
Richtek Technology Corporation
14F, No. 8, Tai Yuen 1st Street, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: (8863)5526789
Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should
obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot
assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be
accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.
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DS9750-00 March 2017
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