®
RTQ2531W
500mA, 5.5V, Low Noise Low Dropout Regulator
General Description
Features
The RTQ2531W is a low-noise, high accuracy, low-dropout
linear regulator (LDO), and is capable of sourcing 500mA.
The device supports single input supply voltage as low to
1.7V, which makes it easy to use.
Input Voltage Range : 1.7V to 5.5V
Output Voltage Range : 0.6V to 5.3V
Accurate Voltage Reference
0.6V ±
±1.5%, Over − 40°°C to 125°°C
Ultra High PSRR : 48dB at 500kHz
Excellent Noise Immunity : 25μ
μVRMS
Ultra Low Dropout Voltage : 150mV at 500mA
Enable Control
Short-Circuit Protection
Output-to-Input Reverse Current Protection
Support Power-OK Output Indicator Function
RoHS Compliant and Halogen Free
The RTQ2531W is designed with high PSRR and low
noise, which can meet the requirements of noise-sensitive
applications such as RF, PLL, Clocking and analog
circuits. The regulator control circuitry includes a
programmable soft-start circuit and short circuit, reverse
current, and over-temperature protection. Other features
include an enable input and a power-OK output. The
device is fully specified over the temperature range of TJ =
−40°C to 125°C and is offered in a WDFN-8SL 2x2 package.
Applications
Ordering Information
RTQ2531W
Package Type
QW : WDFN-8SL 2x2 (W-Type)
(Exposed Pad-Option1)
Lead Plating System
G : Green (Halogen Free and Pb Free)
Note :
Portable Electronic Device
Optical Modules
Camera Modules
PLL/Synthesizer, Clocking
Sensors
Medium-Current, Noise Sensitive Applications
Pin Configuration
Richtek products are :
(TOP VIEW)
RoHS compliant and compatible with the current require-
Suitable for use in SnPb or Pb-free soldering processes.
VIN
1
GND
2
EN
3
GS
4
GND
ments of IPC/JEDEC J-STD-020.
9
8
VOUT
7
BYP
6
FB
5
POK
WDFN-8SL 2x2
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RTQ2531W
Marking Information
5C : Product Code
W : Date Code
5CW
Functional
Pin Description
aPin No.
Pin Name
Pin Function
1
VIN
Supply input. A 10F or larger ceramic capacitor is recommended for good
noise bypass and should be placed as close as possible to this pin.
2,
9 (Exposed Pad)
GND
Ground. The exposed pad must be soldered to a large PCB and connected to
GND for maximum power dissipation.
3
EN
Enable control input. Connecting this pin to logic high enables the regulator,
and driving this pin low puts it into shutdown mode. The device can have VIN
and VEN sequenced in any order without causing damage to the device.
4
GS
Internally Used. Connect GS to GND.
5
POK
Power-OK Output. Open-drain output that goes low when the output is above
91% of the nominal regulation voltage. POK is high impedance in shutdown
or when the output is below the regulation voltage.
6
FB
Feedback voltage input. This pin is used to set the desired output voltage via
an external resistive divider. The feedback reference voltage is 0.6V typically.
7
BYP
Bypass Input. Connecting a 0.01F to this output further reduces output noise.
Slew rate = (5V / ms) x (0.01F / CBYP).
VOUT
LDO output pin. A 4.7F or larger ceramic capacitor (above 2F effective
capacitance) ensures the stability requirement. Place the output capacitor as
close as possible to the device and minimize the impedance between the VOUT
pin and the load.
8
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RTQ2531W
Functional Block Diagram
BYP
Reverse
Current
protection
VOUT
VIN
Thermal
Protection
Current
Limit
AB
FB
EA
POK
+
UVLO
Charge
Pump
EN
-
Bandgap
Control
Logic
+
0.54V
GND
Operation
The RTQ2531W operates with single supply input ranging
from 1.7V to 5.5V and is capable of delivering up to 500mA
current to the output. The high PSRR and low noise
features provides a clean supply to the application.
A low-noise reference and error amplifier are included to
reduce device noise. The BYP capacitor filters the noise
from the reference, and the feed-forward capacitor filters
the noise from the error amplifier. The high power-supply
rejection ratio (PSRR) of the RTQ2531W minimizes the
coupling of input supply noise to the output.
Enable
The RTQ2531W provides an EN pin, as an external chip
enable control, to enable or disable the device. Pull the
EN pin low to turn-off the regulator and enters the shutdown
mode, while pull the EN pin high to turn-on the regulator.
When the regulator is shutdown, the ground current is
reduced to a maximum of 1μA. The enable circuitry has
hysteresis (typically 100mV) for use with relatively slowly
ramping analog signals.
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DSQ2531W-01 August 2022
If not used, connect the EN pin as close as possible to
the largest capacitance on the input to prevent voltage
droops on the VIN line from triggering the enable circuit.
Bypass (BYP)
The capacitor connected from VOUT to BYP filters the
reference noise above the 100Hz range and provides a
high-speed feedback path for improved transient response.
The slew rate of the output voltage during startup is
determined by the BYP capacitor. A 0.01μF capacitor sets
the slew rate to 5V / ms. This startup rate results in a
50mA slew current drawn from the input at startup to
charge the output capacitance.
The BYP capacitor value can be adjusted from 4.7nF to
0.1μF to change the startup slew rate according to the
following formula :
Startup slew rate = (5V / ms) x (0.01μF / CBYP)
Note that this slew rate applies only at startup, and that
recovery from a short circuit occurs with a slew rate
approximately 100 times slower.
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RTQ2531W
Also note that, being a low-frequency filter node, BYP is
sensitive to leakage.
into thermal shutdown or above a junction temperature of
125°C reduces long-term reliability.
Power OK
Output Active Discharge
The RTQ2531W monitors the feedback pin voltage and
indicates the status of the output voltage on the opendrain POK pin. The POK pin requires an external pull-up
resistor to an external supply, and any downstream device
can receive POK as a logic signal that can be used for
sequencing. A pull-up resistor from 10kΩ to 100kΩ is
recommended. Make sure that the external pull-up supply
voltage results in a valid logic signal for the receiving device
or devices.
When EN and UVLO are lower than the respective
threshold voltage during over-temperature protection, the
RTQ2531W discharges the LDO output (via VOUT pins)
through an internal current sink to ground. Do not rely on
the active discharge circuit for discharging a large amount
of output capacitance after the input supply collapses
because reverse current can possibly flow from the output
to the input. External current protection should be added
if the device work at reverse voltage state.
During startup, POK stays high until the output voltage
rises to 91% (typical) of its regulation level. If an overload
occurs at the output or the output is shutdown, POK goes
high.
Internal Current Limit (ILIM)
The RTQ2531W continuously monitors the output current
to protect the pass transistor against abnormal operations.
When an overload or short circuit is encountered, the
current limit circuitry limits the output current to 0.7A
(typical).
Reverse Current Protection
The reverse current protection circuit stops the reverse
current from VOUT pin to VIN pin when the output voltage
is higher than the input.
When VIN drops 10mV below VOUT, the RTQ2531W will
shut off the regulator and open the PMOS body diode
connection, preventing any reverse current.
Thermal shutdown can be activated during a current limit
event because of the high power dissipation typically found
in these conditions. To ensure proper operation of the
current limit, minimize the inductances at the input and
load. Continuous operation in current limit is not
recommended.
Because of the build-in body diode, the pass transistor
conducts current when the output voltage exceeds the
input voltage. Since the current is not limited, external
current protection should be added if the device may work
at reverse voltage state.
Over-Temperature Protection (OTP)
The RTQ2531W implements thermal shutdown protection.
The device is disabled when the junction temperature (TJ)
exceeds 160°C (typical). The LDO automatically turns
on again when the temperature falls below 140°C (typical).
For reliable operation, limit the junction temperature to a
maximum of 125°C. Continuously running the RTQ2531W
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RTQ2531W
Absolute Maximum Ratings
All Pins --------------------------------------------------------------------------------------------------------------- −0.3V to 7V
Lead Temperature (Soldering, 10 sec.) -----------------------------------------------------------------------260°C
Junction Temperature ---------------------------------------------------------------------------------------------150°C
Storage Temperature Range ------------------------------------------------------------------------------------- −65°C to 150°C
ESD Ratings
(Note 1)
(Note 2)
ESD Susceptibility
HBM (Human Body Model) -------------------------------------------------------------------------------------- 2kV
Recommended Operating Conditions
(Note 3)
Supply Input Voltage, VIN ----------------------------------------------------------------------------------------1.7V to 5.5V
Junction Temperature Range ------------------------------------------------------------------------------------ −40°C to 125°C
Thermal Information
(Note 4 and Note 5)
Thermal Parameter
WDFN-8SL 2x2
Unit
JA
Junction-to-ambient thermal resistance (JEDEC standard)
52.2
C/W
JC(Top)
Junction-to-case (top) thermal resistance
160.1
C/W
JC(Bottom)
Junction-to-case (bottom) thermal resistance
23.1
C/W
JA(EVB)
Junction-to-ambient thermal resistance (specific EVB)
61.6
C/W
JC(Top)
Junction-to-top characterization parameter
5.61
C/W
JB
Junction-to-board characterization parameter
36.5
C/W
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RTQ2531W
Electrical Characteristics
Over operating temperature range (TJ = −40°C to 125°C), (1.7V ≤ VIN < 5.5V and VIN ≥ VOUT(TARGET) + 0.5V, VOUT(TARGET) = 0.6V,
VEN = VIN= 5V, CIN = 10μF, COUT = 10μF, CBYP = 0.01μF, unless otherwise noted. (Note 6)
Parameter
Symbol
Input Voltage
Range
VIN
Input Under
Voltage Lockout
VINUVLO
Output Voltage
Range
Output Voltage
Accuracy
VOUT
Test Conditions
Min
Typ
Max
Unit
1.7
--
5.5
V
VIN rising, 100mV typical hysteresis
1.45
1.6
1.7
V
VIN VOUT + 0.1V
0.6
--
5.3
V
1.7V VIN 5.5V for VOUT 1.4 V,
VOUT + 0.3V VIN 5.5V for VOUT > 1.4V,
0.1mA IOUT 500mA
1.5
--
1.5
%
--
0.02
--
%/A
--
0.04
--
%/V
VIN 3.6V, TA 85C
--
50
100
VIN 3.6V, TA 125C
--
--
120
VIN = 1.7V
--
150
--
600
700
800
mA
--
25
--
VRMS
f = 1kHz
--
60
--
f = 10kHz
--
55
--
f = 100kHz
--
63
--
f = 500kHz
--
48
--
0.591
0.6
0.609
TA = 25C
0.1
0.02
0.1
TA = 40C
--
0.03
--
4.7
--
100
nF
--
50
--
A
TA = 85C
--
130
200
TA = 125C
--
160
--
TA = 25C
--
0.001
+1
TA = 85C
--
0.01
--
Load Regulation
VOUT/IOUT 0.1mA IOUT 500 mA
Line Regulation
VOUT/VIN
Dropout Voltage
VDO
1.7V VIN 5.5V for VOUT 1.4V,
VOUT + 0.3V VIN 5.5V for VOUT 1.4V,
IOUT = 200mA
IOUT = 500mA
Output Current
Limit
ILIM
VOUT = 95% of regulation, VIN = VOUT +
0.5V
Output Noise
VN
IOUT = 100mA, f = 10Hz to 100kHz,
VOUT = 0.6V, CBYP = 0.01F
Power Supply
Rejection Ratio
PSRR
IOUT = 10mA
1.7V VIN 5.5V for 0.1mA IOUT
500mA
Threshold
Accuracy
VFB
Input Bias current
VFB = 0.6V
CBYP
BYP Startup
Current
CBYPASS
BYPASS
GND Supply
Current
From BYP to GND during startup
IOUT = 0mA
GND
GND Shutdown
Current
VIN = 5.5V,
EN = 0 V
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mV
dB
V
A
A
A
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DSQ2531W-01 August 2022
RTQ2531W
Parameter
Symbol
Test Conditions
Min
Typ
Max
--
0.8
1.2
EN falling, TA 85C
0.4
0.7
--
EN falling, TA 125C
0.38
0.7
--
EN falling, TA = 25C
1
0.001
1
EN falling, TA=85C
--
0.01
--
VOUT rising
86
91
95
%
VOUT falling
--
88
--
%
--
10
100
mV
TA = 25C
1
0.001
1
TA = 85C
--
0.01
--
TJ rising
--
165
--
TJ falling
--
150
--
IOUT = 50mA to 500mA to 50mA,
tRISE = tFALL = 1s
--
50
--
mV/PP
VIN = 5V to 5.5V to 5V, tRISE = tFALL = 5s,
IOUT = 500mA
--
3
--
mV/PP
VIN falling below VOUT
--
10
--
mV
EN rising
Enable Input
Threshold
1.7V VIN 5.5V
Enable
Enable Input Bias
Current
1.7V VEN 5.5V
POK Threshold
VOUT when
POK switches
POK Voltage Low POK
IPOK = 1mA
POK Leakage
Current
POK = 5.5V,
VEN = 0V
Thermal
Shutdown
Threshold
Thermal
Shutdown
Load Transient
Line Transient
IN-to-OUT
Reverse Voltage
Turnoff Threshold
Output
Transient
Unit
V
A
A
C
Note 1. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation of the device at these or any other conditions beyond those
indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating
conditions may affect device reliability.
Note 2. Devices are ESD sensitive. Handling precautions are recommended.
Note 3. The device is not guaranteed to function outside its operating conditions.
Note 4. θJA and θJC are measured or simulated at TA = 25°C based on the JEDEC 51-7 standard.
Note 5. θJA(EVB), ψJC(Top) and ψJB are measured on a high effective-thermal-conductivity four-layer test board which is in size of
70mm x 50mm; furthermore, all layers with 1 oz. Cu. Thermal resistance/parameter values may vary depending on the
PCB material, layout, and test environmental conditions.
Note 6. All devices are production tested at TA = 25°C. Specifications over the operating temperature range are guaranteed by
design and characterization.
Note 7. External resistor tolerance is not taken into account.
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RTQ2531W
Typical Application Circuit
VIN
1
CIN
10µF
RTQ2531W
VIN
VOUT
BYP
POK
Logic Supply
Enable
R3 100k
5
3
POK
FB
EN
GS
8
7
CBYP
0.01µF
R1
267k
COUT
10µF
VOUT
3.3V / 500mA
6
4
R2
59k
GND
2 (Exposed Pad)
VOUT = VREF 1 + R1 = 0.6V 1 + 267k = 3.3V
R2
59k
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RTQ2531W
Typical Operating Characteristics
Load Regulation
Quiescent Current
250
2.510
Output Voltage (V)
Input Current (μA)
200
150
100
50
2.506
2.502
2.498
2.494
EN = HIGH, No Load
0
VIN = 3.6V
2.490
1.5
2.5
3.5
4.5
5.5
0
200
300
400
Input Voltage (V)
Output Current (mA)
Line Regulation
Load Transient Response
2.510
VOUT
(50mV/Div)
offset 2.5V
2.506
Output Voltage (V)
100
500
VIN = 3.6V, VOUT = 2.5V, IOUT = 50mA to 500mA
COUT = 10μF, CBYP = 10nF, tRISE = tFALL = 1μs
2.502
2.498
IOUT
(200mA/Div)
2.494
IOUT = 200mA
2.490
2.5
3
3.5
4
4.5
5
Time (50μs/Div)
5.5
Input Voltage (V)
Power Up Response
Line Transient Response
VIN = 3.6V, VOUT = 2.5V, IOUT = 500mA
COUT = 10μF, CBYP = 10nF
VIN
(500mV/Div)
offset 4V
VEN
(2V/Div)
VOUT
(10mV/Div)
offset 2.5V
VOUT
(1V/Div)
VIN = 4V to 5V, VOUT = 2.5V, IOUT = 500mA
COUT = 10μF, CBYP = 10nF
Time (500μs/Div)
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IOUT
(200mA/Div)
Time (500μs/Div)
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RTQ2531W
Dropout Voltage vs. Output Current
Dropout Voltage vs. Input Voltage
160
125°C
85°C
25°C
0°C
−40°C
140
120
100
80
60
40
20
IOUT = 500mA
VIN-VOUT Dropout Voltage (mV)
VIN-VOUT Dropout Voltage (mV)
160
140
120
125°C
85°C
25°C
0°C
−40°C
100
80
60
40
20
VIN = 1.7V
0
0
1.5
2.5
3.5
4.5
0.0
5.5
0.1
125°C
85°C
25°C
0°C
−40°C
50
40
30
20
10
VIN = 5.5V
0
0.0
0.1
0.2
0.3
0.4
0.5
0.5
100
80
60
40
20
VIN = 3.6V, VOUT = 2.5V, IOUT = 10mA
COUT = 10μF, CBYP = 10nF
0
10
100
1K
10K
100K
1M
Frequency (Hz)
Output Current (A)
Output Spectral Noise Density (μV/ Hz)
Power-Supply Rejection Ratio (dB)
VIN-VOUT Dropout Voltage (mV)
90
60
0.4
PSRR vs. Frequency
Dropout Voltage vs. Output Current
100
70
0.3
Output Current (A)
Input Voltage (V)
80
0.2
Output Noise vs. Frequency
10
1
0.1
0.01
VIN = 1.7V, VOUT = 0.6V, IOUT = 100mA
COUT = 10μF, CBYP = 10nF
0.001
10
100
1K
10K
100K
1M
Frequency (Hz)
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RTQ2531W
Application Information
The RTQ2531W is a low-noise, high accuracy, low-dropout
linear regulator which is capable of sourcing with maximum
dropout of 150mV. The input voltage operating range is
from 1.7V to 5.5V and the adjustable output voltage is
from 0.6V to (VIN − VDROP) according to the external
resistor setting.
Output Voltage Setting
The output voltage of the RTQ2531W can be set by external
resistors.
By using external resistors, the output voltage is
determined by the values of R1 and R2 as shown in Figure
1. The values of R1 and R2 can be calculated for any
voltage value using the following formula :
VOUT = 0.6 R1 + R2
R2
RTQ2531W
VIN
VIN
CIN
CBYP
BYP
EN
VOUT
VOUT
R1
COUT
FB
EN
GND
R2
Figure 1. Output Voltage Set by External Resistors
Set the lower feedback resistor (R2) to 60kΩ or less to
minimize FB input bias current error.
Dropout Voltage
The dropout voltage refers to the voltage difference between
the VIN and VOUT pins while operating at a specific output
current. The dropout voltage VDROP also can be expressed
as the voltage drop on the pass-FET at a specific output
current (IRATED) while the pass-FET is fully operating in
the ohmic region and the pass-FET can be characterized
as a resistance RDS(ON). Thus, the dropout voltage can be
defined as (VDROP = VIN − VOUT = RDS(ON) x IRATED). For
normal operation, the suggested LDO operating range is
(VIN > VOUT + VDROP) for good transient response and
PSRR performance. However, operation in the ohmic
region will degrade the performance severely.
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CIN and COUT Selection
The RTQ2531W is designed to support low-seriesresistance (ESR) ceramic capacitors. X7R, X5R, and COGrated ceramic capacitors are recommended due to its good
capacitive stability across different temperatures, whereas
the use of Y5V-rated capacitors is not recommended
because of large capacitance variations.
However, ceramic capacitance varies with operating voltage
and temperature, and the design engineer must be aware
of these characteristics. Input capacitance is selected to
minimize transient input drop during load current steps.
For general applications, an input capacitor of 10μF is
highly recommended for minimal input impedance. If the
trace inductance between the RTQ2531W input pin and
power supply is high, a fast load transient can cause VIN
voltage level ringing above the absolute maximum voltage
rating which damages the device. Adding more input
capacitors is available to restrict the ringing and keep it
below the device absolute maximum ratings.
A 4.7μF or larger ceramic capacitor (above 2μF effective
capacitance) ensures the stability requirement at output
terminal. Generally, a 10μF 0805-sized ceramic capacitor
ensures the minimum effective capacitance at temperature
and DC bias requirement. Place these capacitors as close
as possible to the pins for performance and stability.
Input Inrush Current
During start-up, the input Inrush current into the VIN pin
consists of the sum of load current and the charging
current of the output capacitor. The inrush current is difficult
to measure because the input capacitor must be removed,
which is not recommended. Generally, the soft-start inrush
current can be estimated by Equation b1, where VOUT(t)
is the instantaneous output voltage of the power-on ramp,
dVOUT(t) / dt is the slope of the VOUT ramp and RLOAD is
the resistive load impedance.
IOUT t =
COUT dVOUT t
dt
VOUT t
+
RLOAD
b1
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RTQ2531W
Thermal protection limits power dissipation in the
RTQ2531W. When power dissipation on the pass
element (PDIS = (VIN − VOUT) x IOUT) is too high and raises
the junction operation temperature over 160°C, the OTP
circuit starts the thermal shutdown function and turns the
pass element off. The pass element turns on again after
the junction temperature cools down by 20°C.
The output is shorted to ground when there as short circuit
at the output. This procedure can reduce the chip
temperature and provides maximum safety to end users
when output short circuit occurs.
The junction temperature should never exceed the
absolute maximum junction temperature TJ(MAX), listed
under Absolute Maximum Ratings, to avoid permanent
damage to the device. The maximum allowable power
dissipation depends on the thermal resistance of the IC
package, the PCB layout, the rate of surrounding airflow,
and the difference between the junction and ambient
temperatures. The maximum power dissipation can be
calculated using the following formula :
PD(MAX) = (TJ(MAX) − TA) / θJA
where TJ(MAX) is the maximum junction temperature, TA is
the ambient temperature, and θJA is the junction-to-ambient
thermal resistance.
For continuous operation, the maximum operating junction
temperature indicated under Recommended Operating
2.0
Maximum Power Dissipation (W)1
Thermal Considerations
Four-Layer EVB
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
0
25
50
75
100
125
Ambient Temperature (°C)
Figure 2. Derating Curve of Maximum Power Dissipation
Layout Considerations
For best performance of the RTQ2531W, the PCB layout
suggestions below are highly recommended. All circuit
components should be placed on the same side and as
close to the respective LDO pin as possible. Place the
ground return path connection to the input and output
capacitor. Connect the ground plane with a wide copper
surface for good thermal dissipation. Using vias and long
power traces for the input and output capacitors
connections is not recommended and has negative effects
on performance. Figure 3 shows a layout example that
reduces conduction trace loops, helping to minimize
inductive parasitics and load transient effects while
improving the circuit stability.
Conditions is 125°C. The junction-to-ambient thermal
resistance, θJA(EVB), is highly package dependent. For a
WDFN-8SL 2x2 package, the thermal resistance, θJA(EVB),
is 61.6°C/W on a standard high effective-thermalconductivity four-layer test board. The maximum power
dissipation at TA = 25°C can be calculated as below :
PD(MAX) = (125°C − 25°C) / (61.6°C/W) = 1.62W for a
WDFN-8SL 2x2 package.
The maximum power dissipation depends on the operating
ambient temperature for the fixed TJ(MAX) and the thermal
resistance, θJA. The derating curves in Figure 2 allow the
designer to see the effect of rising ambient temperature
on the maximum power dissipation.
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DSQ2531W-01 August 2022
RTQ2531W
Place capacitors as close as possible to the connected pins for minimizing
power loop area and low impedance connection to GND plate.
GND
Output Power Plane
Input Power Plane
COUT
CIN
VIN
1
8
OUT
GND
EN
To EN GS
2
7
BYP
FB
POK
3
4
EP
6
5
R1
To Logic supply
To POK Output
R3
CBYP
R2
Thermal vias can help to reduce power
trace and improve thermal dissipation.
Figure 3. PCB Layout Guide
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DSQ2531W-01 August 2022
is a registered trademark of Richtek Technology Corporation.
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13
RTQ2531W
Outline Dimension
2
1
2
1
DETAIL A
Pin #1 ID and Tie Bar Mark Options
Note : The configuration of the Pin #1 identifier is optional,
but must be located within the zone indicated.
Dimensions In Millimeters
Symbol
D2
E2
Dimensions In Inches
Min
Max
Min
Max
A
0.700
0.800
0.028
0.031
A1
0.000
0.050
0.000
0.002
A3
0.175
0.250
0.007
0.010
b
0.200
0.300
0.008
0.012
D
1.900
2.100
0.075
0.083
Option1
1.150
1.250
0.045
0.049
Option2
1.550
1.650
0.061
0.065
E
1.900
2.100
0.075
0.083
Option1
0.750
0.850
0.030
0.033
Option2
0.850
0.950
0.033
0.037
e
L
0.500
0.250
0.020
0.350
0.010
0.014
W-Type 8SL DFN 2x2 Package
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is a registered trademark of Richtek Technology Corporation.
DSQ2531W-01 August 2022
RTQ2531W
Footprint Information
Package
V/W/U/XDFN2*2-8S
Option1
Option2
Footprint Dimension (mm)
Number of
Pin
P
A
B
C
D
8
0.50
2.80
1.30
0.75
0.30
Sx
Sy
1.30
0.90
1.60
0.90
M
1.80
Tolerance
±0.05
Richtek Technology Corporation
14F, No. 8, Tai Yuen 1st Street, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: (8863)5526789
Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should
obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot
assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be
accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.
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