R2061K

R2061 SERIES 3 wire interface Real-Time Clock ICs with Battery Backup switch-over Function NO.EA-112-070427 OUTLINE The R2061 is a CMOS real-time clock IC connected to the CPU by three signal lines, CE, SCLK, and SIO, and configured to perform serial transmission of time and calendar data to the CPU. Further, battery backup switchover circuit and a voltage detector. The periodic interrupt circuit is configured to generate interrupt signals with six selectable interrupts ranging from 0.5 seconds to 1 month. The 2 alarm interrupt circuits generate interrupt signals at preset times. As the oscillation circuit is driven under constant voltage, fluctuation of the oscillator frequency due to supply voltage is small, and the time keeping current is small (TYP. 0.4µA at 3V). The oscillation halt sensing circuit can be used to judge the validity of internal data in such events as power-on; The supply voltage monitoring circuit is configured to record a drop in supply voltage below two selectable supply voltage monitoring threshold settings. The oscillation adjustment circuit is intended to adjust time counts with high precision by correcting deviations in the oscillation frequency of the quartz crystal unit. Battery backup switchover function is the automatic switchover circuit between a main power supply and a backup battery of primary or secondary battery. Switchover is executed by monitoring the voltage of a main power supply, therefore the voltage of a backup battery voltage is not relevant. Since the package for these ICs is SSOP16 (5.0x6.4x1.25: R2061Sxx) and FFP12 (2.0x2.0x1.0: R2061Kxx), high density mounting of ICs on boards is possible. FEATURES • Minimum Timekeeping supply voltage Typ. 0.75V (Max. 1.00V); VDD pin • Low power consumption Typ. 0.4µA (Max. 1.0µA) at VDD=3V • Built-in Backup switchover circuit (can be used for a primary battery, a secondary battery, or an electric double layer capacitor) • Three signal lines (CE, SCLK, and SIO) required for connection to the CPU. ····· • (Maximum clock frequency of 1MHz (with VCC = 3V) ) • Time counters (counting hours, minutes, and seconds) and calendar counters (counting years, months, days, and weeks) (in BCD format) • Interrupt circuit configured to generate interrupt signals (with interrupts ranging from 0.5 seconds to 1 month) to the CPU and provided with an interrupt flag and an interrupt halt • 2 alarm interrupt circuits (Alarm_W for week, hour, and minute alarm settings and Alarm_D for hour and minute alarm settings) • Built-in voltage detector with delay • With Power-on flag to prove that the power supply starts from 0V • Supply voltage monitoring circuit with two supply voltage monitoring threshold settings • Automatic identification of leap years up to the year 2099 • Selectable 12-hour and 24-hour mode settings • Built-in oscillation stabilization capacitors (CG and CD) • High precision oscillation adjustment circuit • CMOS process • Package SSOP16 (5.0mm x 6.4mm x 1.25mm : R2061Sxx), FFP12 (2.0mm x 2.0mm x 1.0mm : R2061Kxx 1 R2061 series PIN CONFIGURATION R2061Sxx(SSOP16) NC VSB 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 R2061Kxx(FFP12) OSCOUT OSCIN INTR VCC VDD NC OSCIN OSCOUT NC INTR CIN CIN VSS CE VDCC SCLK SIO NC CE VSS 8 2 10 11 12 1 3 SIO TOP VIEW TOP VIEW BLOCK DIAGRAM C2 SW2 VSB R1 BATTERY VOLTAGE MONITOR VOLTAGE DETECTOR VDCC VDCC SCLK 9 7 6 5 4 VDD VCC VSB VDD SW1 VCC CPU power supply C3 DELAY OSCIN REAL TIME CLOCK CE SCLK SIO INTR LEVEL SHIFTER CPU OSCOUT CIN C1 VSS VOLTAGE REFERENCE 2 R2061 series SELECTION GUIDE In the R2061xxx Series, output voltage and options can be designated. Part Number is designated as follows: R2061K01-E2 ←Part Number ↑↑ ↑ R2061abb-cc Code Designation of the package. a bb cc K: FFP12 S: SSOP16 Serial number of Voltage detector setting etc. Designation of the taping type. Only E2 is available. Description Part Number R2061K01-E2 R2061K03-E2 R2061S02-E2 Package FFP12 FFP12 SSOP16 -VDET1 (switch-over threshold) 1.70(Typ.) 2.80(Typ.) 2.40(Typ.) P. 6 P. 8 P. 7 DC Electrical Characteristics 3 R2061 series PIN DESCRIPTION Symbol CE Item Chip enable Input Description The CE pin is used for interfacing with the CPU. Should be held high to allow access to the CPU. Incorporates a pull-down resistor. Should be held low or open when the CPU is powered off. Allows a maximum input voltage of 5.5 volts regardless of supply voltage. The SCLK pin is used to input clock pulses synchronizing the input and output of data to and from the SIO pin. Allows a maximum input voltage of 5.5 volts regardless of supply voltage. The SIO pin is used to input or output data intended for writing or reading in synchronization with the SCLK pin. The INTR pin is used to output alarm interrupt (Alarm_W) and alarm interrupt (Alarm_D) and output periodic interrupt signals to the CPU signals. Disabled at power-on from 0V. Nch. open drain output. Supply power to the IC. Connect a primary battery for backup. Normally, power is supplied from VCC to the IC. If VCC level is equal or less than –VDET1, power is supplied from this pin. The OSCIN and OSCOUT pins are used to connect the 32.768-kHz quartz crystal unit (with all other oscillation circuit components built into the R2061 series). The VDD pin is connected to the power supply. Connect a capacitor as much as 0.1µF between VDD and VSS. In the case of using a secondary battery, connecting the secondary battery to this pin is possible. While monitoring VCC Power supply, if the voltage is equal or lower than –VDET1, this output level is “L”. When VDCC becomes “L”, SW1 turns off and SW2 turns on. As a result, power is supplied from VSB pin to the internal real time clock. When VCC is equal to +VDET1 or more, SW1 turns on and SW2 turns off. After t DELAY passed, VDCC output becomes off, or “H”. Nch Open-drain output. To stabilize the internal reference, connect a capacitor as much as 0.1uF between this pin and VSS. The VSS pin is grounded. SCLK Serial Clock Input Serial Input / Output Interrupt Output Main Battery input Power Supply Input for Backup Battery Oscillation Circuit Input / Output Positive Power Supply Input SIO INTR VCC VSB OSCIN OSCOUT VDD VDCC VCC Power Supply Monitoring Result Output CIN VSS Noise Bypass Pin Negative Power Sup Supply Input 4 R2061 series ABSOLUTE MAXIMUM RATINGS (VSS=0V) Symbol Item VCC Supply Voltage 1 VDD Supply Voltage 2 VSB Supply Voltage 3 VI Input Voltage 1 Input Voltage 2 Input Voltage 3 VO Output Voltage 1 Output Voltage 2 IOUT Maximum Output Current PD Power Dissipation Topt Operating Temperature Tstg Storage Temperature Pin Name VCC VDD VSB CE, SCLK SIO CIN INTR , VDCC SIO VDD Topt = 25°C Description -0.3 to +6.5 -0.3 to +6.5 -0.3 to +6.5 -0.3 to +6.5 -0.3 to VCC+0.3 -0.3 to VDD+0.3 -0.3 to +6.5 -0.3 to VCC+0.3 10 300 -40 to +85 -55 to +125 Unit V V V V V V V V mA mW °C °C RECOMMENDED OPERATING CONDITIONS Symbol Vaccess Item Supply Voltage Pin Name VCC power supply voltage for interfacing with CPU (VSS=0V, Topt=-40 to +85°C) Min, Typ. Max. Unit -VDET1 5.5 V VCLK 32.768 kHz 5.5 V INTR , VDCC *1) -VDET1 in Vaccess specification is guaranteed by design. *2) CGout is connected between OSCIN and VSS, CDout is connected between OSCOUT and VSS. R2061 series incorporates the capacitors between OSCIN and VSS, between OSCOUT and VSS. Then normally, CGout and CDout are not necessary. *3) Quartz crystal unit: CL=6-8pF, R1=30KΩ fXT VPUP Minimum Timekeeping Voltage CGout,CDout=0pF *2), *3) Oscillation Frequency Pull-up Voltage 0.75 1.00 V 5 R2061 series DC ELECTRICAL CHARACTERISTICS • R2061K01 (Unless otherwise specified: VSS=0V, VSB=3.0V, VCC=2.0V, 0.1uF between VDD and VSS, CIN and VSS, Topt=-40 to +85°C) Symbol Item Pin Name Conditions Min. Typ. Max. VIH1 “H” Input Voltage 1 CE, SCLK 0.8xVCC 5.5 VIH2 “H” Input Voltage 2 SIO 0.8xVCC VCC+0.3 VIL “L” Input Voltage CE, SIO -0.3 0.2xVCC SCLK IOH “H” Output SIO VOH=VCC-0.5V -0.5 Current IOL1 “L” Output Current 1 SIO 0.5 VOL=0.4V IOL2 “L” Output Current 2 2.0 INTR VDD,VSB,VCC=1.4V IOL3 “L” Output Current 3 0.2 INTR VOL=0.4V IIL Input Leakage SCLK VI=5.5V or VSS -1.0 1.0 Current RDNCE Pull-down Input CE 40 120 400 register IOZ1 Output Off-state SIO VO=5.5V or VSS -1.0 1.0 Current 1 IOZ2 Output Off-state -1.0 1.0 VO=5.5V or VSS INTR , Current 2 VDCC ISB Time Keeping Current VSB VCC=0V, VSB=3.0V, 0.4 1.0 at Backup mode VDD, Output=OPEN ISBL Leakage Current of VSB VCC=3.0V, -1.0 1.0 Backup pin at VSB=5.5V or 0V, VCC_on VDD, Output=OPEN VDETH Supply Voltage VSB 1.90 2.10 2.30 Topt=25°C Monitoring Voltage “H” VDETL Supply Voltage VDD 1.20 1.35 1.50 Topt=25°C Monitoring Voltage “L” -VDET1 Detector Threshold VCC 1.657 1.700 1.743 Topt=25°C Voltage (falling edge of VCC) +VDET1 Detector Released VCC 1.731 1.785 1.839 Topt=25°C Voltage (rising edge of VCC) Detector Threshold VCC, VSB ±100 ∆VDET Topt=-40 to 85°C and Released Voltage *1) ∆Topt Temperature coefficient VDDOUT1 VDDOUT2 VDD Output Voltage 1 VDD VDD OSCIN OSCOUT Topt=25°C, VCC=2.0V, Iout=0.5mA Topt=25°C, VCC=1.4V, VSB=3.0V, Iout=0.1mA VCC0.12 VSB0.08 VCC0.04 VSB0.02 10 10 Unit V mA mA µA kΩ µA µA µA µA V V V V ppm /°C V V pF VDD Output Voltage 2 CG Internal Oscillation Capacitance 1 CD Internal Oscillation Capacitance 2 *1) Guaranteed by design. 6 R2061 series • R2061S02 (Unless otherwise specified: VSS=0V,VSB=VCC=3.0V, 0.1uF between VDD and VSS, CIN and VSS, Topt=-40 to +85°C) Symbol Item Pin Name Conditions Min. Typ. Max. VIH1 “H” Input Voltage 1 CE, SCLK 0.8xVCC 5.5 VIH2 “H” Input Voltage 2 SIO 0.8xVCC VCC+0.3 VIL “L” Input Voltage CE, SCLK -0.3 0.2xVCC SIO IOH “H” Output SIO VOH=VCC-0.5V -0.5 Current IOL1 “L” Output Current 1 SIO 0.5 VOL=0.4V IOL2 “L” Output Current 2 2.0 INTR VDD,VSB,VCC=2.0V IOL3 “L” Output Current 3 0.5 VDCC VOL=0.4V IIL Input Leakage SCLK VI=5.5V or VSS -1.0 1.0 Current RDNCE Pull-down Input CE 40 120 400 register IOZ1 Output Off-state SIO VO=5.5V or VSS -1.0 1.0 Current 1 VO=5.5V or VSS IOZ2 Output Off-state -1.0 1.0 INTR , Current 2 VDCC ISB Time Keeping Current VSB VCC=0V, VSB=3.0V, 0.4 1.0 at Backup mode VDD, Output=OPEN ISBL Leakage Current of VSB VCC=3.0V, -1.0 1.0 Backup pin at VSB=5.5V or 0V, VCC_on VDD, Output=OPEN VDETH Supply Voltage VSB 1.90 2.10 2.30 Topt=25°C Monitoring Voltage “H” VDETL Supply Voltage VDD 1.20 1.35 1.50 Topt=25°C Monitoring Voltage “L” -VDET1 Detector Threshold VCC 2.34 2.40 2.46 Topt=25°C Voltage (falling edge of VCC) +VDET1 Detector Released VCC 2.44 2.52 2.60 Topt=25°C Voltage (rising edge of VCC) Detector Threshold VCC, VSB ±100 ∆VDET Topt=-40 to 85°C and Released Voltage *1) ∆Topt Temperature coefficient VDDOUT1 VDDOUT2 CG CD VDD Output Voltage 1 VDD Output Voltage 2 Internal Oscillation Capacitance 1 Internal Oscillation Capacitance 2 *1) Guaranteed by design. Unit V mA mA µA kΩ µA µA µA µA V V V V ppm /°C V V pF VDD VDD OSCIN OSCOUT Topt=25°C, VCC=3.0V, Iout=1.0mA Topt=25°C, VCC=2.0V, VSB=3.0V, Iout=0.1mA VCC0.12 VSB0.08 VCC0.04 VSB0.02 10 10 7 R2061 series • R2061K03 (Unless otherwise specified: VSS=0V, VSB=3.0V, VCC=3.3V, 0.1uF between VDD and VSS, CIN and VSS, Topt=-40 to +85°C) Symbol Item Pin Name Conditions Min. Typ. Max. VIH1 “H” Input Voltage 1 CE, SCLK 0.8x 5.5 VCC VIH2 “H” Input Voltage 2 SIO 0.8x VCC+0.3 VCC VIL “L” Input Voltage CE, SCLK -0.3 0.2xVCC SIO IOH “H” Output SIO VOH=VCC-0.5V -0.5 Current VOL=0.4V IOL1 “L” Output Current 1 SIO 0.5 2.0 IOL2 “L” Output Current 2 INTR VDD,VSB,VCC=2.0V IOL3 “L” Output Current 3 0.5 VDCC VOL=0.4V IIL Input Leakage SCLK VI=5.5V or VSS -1.0 1.0 Current RDNCE Pull-down Input CE 40 120 400 register IOZ1 Output Off-state SIO VO=5.5V or VSS -1.0 1.0 Current 1 VO=5.5V or VSS IOZ2 Output Off-state -1.0 1.0 INTR , Current 2 VDCC ISB Time Keeping Current VSB VCC=0V, VSB=3.0V, 0.4 1.0 at Backup mode VDD, Output=OPEN ISBL Leakage Current of VSB VCC=3.3V, -1.0 1.0 Backup pin at VSB=5.5V or 0V, VCC_on VDD, Output=OPEN VDETH Supply Voltage VSB 1.90 2.10 2.30 Topt=25°C Monitoring Voltage “H” VDETL Supply Voltage VDD 1.20 1.35 1.50 Topt=25°C Monitoring Voltage “L” -VDET1 Detector Threshold VCC 2.73 2.80 2.87 Topt=25°C Voltage (falling edge of VCC) +VDET1 Detector Released VCC 2.85 2.94 3.03 Topt=25°C Voltage (rising edge of VCC) Detector Threshold VCC, ±100 ∆VDET Topt=-40 to 85°C and Released Voltage VSB *1) ∆Topt Temperature coefficient VCCVDDOUT1 VDD Output VDD VCCTopt=25°C, VCC=3.3V, Voltage 1 0.12 0.04 Iout=1.0mA VSBVDDOUT2 VDD Output VDD VSB-0. Topt=25°C, VCC=2.0V, Voltage 2 0.08 02 VSB=3.0V, Iout=0.1mA CG Internal Oscillation OSCIN 10 Capacitance 1 CD Internal Oscillation OSCOUT 10 Capacitance 2 *1) Guaranteed by design. Unit V mA mA µA kΩ µA µA µA µA V V V V ppm /°C V V pF 8 R2061 series AC ELECTRICAL CHARACTERISTICS Unless otherwise specified: VSS=0V,Topt=-40 to +85°C Input and Output Conditions: VIH=0.8×VCC,VIL=0.2×VCC,VOH=0.8×VCC,VOL=0.2×VCC,CL=50pF Sym Item CondiUnit VDD≥1.7V *1) -bol Tions Min. Typ. Max. tCES CE Set-up Time 400 ns tCEH CE Hold Time 400 ns tCR CE Recovery Time 62 µs fSCLK SCLK Clock Frequency 1.0 MHz tCKH SCLK Clock ”H” Time 400 ns tCKL SCLK Clock ”L” Time 400 ns tCKS SCLK Set-up Time 200 ns tRD Data Output Delay Time 300 ns tRZ Data Output Floating Time 300 ns tCEZ Data Output Delay Time After 300 ns Falling of CE tDS Input Data Set-up Time 200 ns tDH Input Data Hold Time 200 ns Time tDELAY Output Delay Time of Voltage 100 105 110 ms Keeping Detector *1) VCC voltage interfacing with CPU is defined by Vaccess (P.5 RECOMMENDED OPERATING CONDITIONS) *) For reading/writing timing, see “P.30 Interfacing with the CPU •Considerations in Reading and Writing Time Data under special condition”. tCKH CE tCKS SCLK tCES tCKL tCEH tCR tDS SIO(write cycle) SIO(read cycle) tRD tDH tCEZ tRD tRZ VCC +VDET1 tDELAY VDCC 9 R2061 series PACKAGE DIMENSIONS • R2061Kxx 9 10 7 6 1PIN INDEX 0.05 12 1 4 3 2PIN INDEX 0.35 0.35 0.25 1.0Max 0.103 0.3±0.15 0.5 0.2±0.15 0.5 (BOTTOM VIEW) 0.17±0.1 0.27±0.15 2.0±0.1 unit: mm 10 2.0±0.1 R2061 series • R2061Sxx 5.0±0.3 16 9 0 to 10° 4.4±0.2 6.4±0.3 1 0.65 0.225typ 8 0.15 1.15±0.1 +0.1 -0.05 0.10 +0.1 0.22 -0.05 0.15 M 0.1±0.1 0.5±0.3 unit: mm TAPING SPECIFICATION The R2061 Series have one designated taping direction. The product designation for the taping components is "R2061S/Kxx-E2". 11 R2061 series GENERAL DESCRIPTION • Battery Backup Switchover Function The R2061 Series have two power supply input, or VCC and VSB. With monitoring VCC pin input voltage, which voltage between the two is supplied to the internal power supply is decided. Refer to the next table to see the state of the backup battery and internal power supply’s state of the IC by each condition. VCC≥VDET1 VCC Generally, quartz crystal units have basic characteristics including an equivalent series resistance (R1) indicating the ease of their oscillation and a load capacitance (CL) indicating the degree of their center frequency. Particularly, quartz crystal units intended for use in the R2061 are recommended to have a typical R1 value of 30kΩ and a typical CL value of 6 to 8pF. To confirm these recommended values, contact the manufacturers of quartz crystal units intended for use in these particular models. < Considerations in Installing Components around the Oscillation Circuit > 1) Install the quartz crystal unit in the closest possible vicinity to the real-time clock ICs. 2) Avoid laying any signal lines or power lines in the vicinity of the oscillation circuit (particularly in the area marked "A" in the above figure). 3) Apply the highest possible insulation resistance between the OSCIN and OSCOUT pins and the printed circuit board. 4) Avoid using any long parallel lines to wire the OSCIN and OSCOUT pins. 5) Take extreme care not to cause condensation, which leads to various problems such as oscillation halt. < Other Relevant Considerations > 1) We cannot recommend connecting the external input of 32.768-kHz clock pulses to the OSCIN pin. 2) To maintain stable characteristics of the quartz crystal unit, avoid driving any other IC through 32.768-kHz clock pulses output from the OSCOUT pin. 32 R2061 series • Measurement of Oscillation Frequency VCC OSCIN OSCOUT IN T R 32768Hz Frequency Counter VDD VSS * 1) The R2061 is configured to generate 1Hz clock pulses for output from the INTR pin by setting (00XX0011) at address Eh. * 2) A frequency counter with 6 (more preferably 7) or more digits on the order of 1ppm is recommended for use in the measurement of the oscillation frequency of the oscillation circuit. • Adjustment of Oscillation frequency The oscillation frequency of the oscillation circuit can be adjusted by varying procedures depending on the usage of Model R2061 in the system into which they are to be built and on the allowable degree of time count errors. Course (A) When the time count precision of each RTC is not to be adjusted, the quartz crystal unit intended for use in that RTC may have any CL value requiring no presetting. The quartz crystal unit may be subject to frequency variations which are selectable within the allowable range of time count precision. Several quartz crystal units and RTCs should be used to find the center frequency of the quartz crystal units by the method described in "P33 • Measurement of Oscillation Frequency" and then calculate an appropriate oscillation adjustment value by the method described in "P35 • Oscillation Adjustment Circuit" for writing this value to the R2061. Course (B) When the time count precision of each RTC is to be adjusted within the oscillation frequency variations of the quartz crystal unit plus the frequency variations of the real-time clock ICs, it becomes necessary to correct deviations in the time count of each RTC by the method described in " P35 • Oscillation Adjustment Circuit". Such oscillation adjustment provides quartz crystal units with a wider range of allowable settings of their oscillation frequency variations and their CL values. The real-time clock IC and the quartz crystal unit intended for use in that real-time clock IC should be used to find the center frequency of the quartz crystal unit by the method described in " P33 • Measurement of Oscillation Frequency" and then confirm the center frequency thus found to fall within the range adjustable by the oscillation adjustment circuit before adjusting the oscillation frequency of the oscillation circuit. At normal temperature, the oscillation frequency of the oscillator circuit can be adjusted by up to approximately ±0.5ppm. * 1) Generally, quartz crystal units for commercial use are classified in terms of their center frequency 33 R2061 series depending on their load capacitance (CL) and further divided into ranks on the order of ±10, ±20, and ±50ppm depending on the degree of their oscillation frequency variations. * 2) Basically, Model R2061 is configured to cause frequency variations on the order of ±5 to ±10ppm at 25°C. * 3) Time count precision as referred to in the above flow chart is applicable to normal temperature and actually affected by the temperature characteristics and other properties of quartz crystal units. The R2061, which incorporate the CG and the CD, require adjusting the oscillation frequency of the quartz crystal unit through its CL value. Generally, the relationship between the CL value and the CG and CD values can be represented by the following equation: CL = (CG × CD)/(CG + CD) + CS where "CS" represents the floating capacity of the printed circuit board. The quartz crystal unit intended for use in the R2061 is recommended to have the CL value on the order of 6 to 8pF. Its oscillation frequency should be measured by the method described in " P33 • Measurement of Oscillation Frequency". Any quartz crystal unit found to have an excessively high or low oscillation frequency (causing a time count gain or loss, respectively) should be replaced with another one having a smaller and greater CL value, respectively until another one having an optimum CL value is selected. In this case, the bit settings disabling the oscillation adjustment circuit (see " P35 • Oscillation Adjustment Circuit ") should be written to the oscillation adjustment register. Incidentally, the high oscillation frequency of the quartz crystal unit can also be adjusted by adding an external oscillation stabilization capacitor CGOUT as illustrated in the diagram below. *1) The CGOUT should have a capacitance ranging from 0 to 15 pF. 32kHz OSCOUT CD CGOUT *1) OSCIN Oscillator Circuit CG RD 34 R2061 series • Oscillation Adjustment Circuit The oscillation adjustment circuit can be used to correct a time count gain or loss with high precision by varying the number of 1-second clock pulses once per 20 seconds or 60 seconds. When DEV bit in the Oscillation Adjustment Register is set to 0, R2061 varies number of 1-second clock pulses once per 20 seconds. When DEV bit is set to 1, R2061 varies number of 1-second clock pulses once per 60 seconds. The oscillation adjustment circuit can be disabled by writing the settings of "*, 0, 0, 0, 0, 0, *" ("*" representing "0" or "1") to the F6, F5, F4, F3, F2, F1, and F0 bits in the oscillation adjustment circuit. Conversely, when such oscillation adjustment is to be made, an appropriate oscillation adjustment value can be calculated by the equation below for writing to the oscillation adjustment circuit. (1) When Oscillation Frequency (* 1) Is Higher Than Target Frequency (* 2) (Causing Time Count Gain) When DEV=0: Oscillation adjustment value (*3) = (Oscillation frequency - Target Frequency + 0.1) Oscillation frequency × 3.051 × 10-6 ≈ (Oscillation Frequency – Target Frequency) × 10 + 1 When DEV=1: Oscillation adjustment value (*3) = (Oscillation frequency - Target Frequency + 0.0333) Oscillation frequency × 1.017 × 10-6 ≈ (Oscillation Frequency – Target Frequency) × 30 + 1 * 1) Oscillation frequency: 32768 times the frequency of 1Hz clock pulse output from the INTR pin at normal temperature in the manner described in " P33 • Measurement of Oscillation Frequency". * 2) Target frequency: Desired frequency to be set. Generally, a 32.768-kHz quartz crystal unit has such temperature characteristics as to have the highest oscillation frequency at normal temperature. Consequently, the quartz crystal unit is recommended to have target frequency settings on the order of 32.768 to 32.76810 kHz (+3.05ppm relative to 32.768 kHz). Note that the target frequency differs depending on the environment or location where the equipment incorporating the RTC is expected to be operated. * 3) Oscillation adjustment value: Value that is to be finally written to the F0 to F6 bits in the Oscillation Adjustment Register and is represented in 7-bit coded decimal notation. (2) When Oscillation Frequency Is Equal To Target Frequency (Causing Time Count neither Gain nor Loss) Oscillation adjustment value = 0, +1, -64, or –63 35 R2061 series (3) When Oscillation Frequency Is Lower Than Target Frequency (Causing Time Count Loss) When DEV=0: Oscillation adjustment value = (Oscillation frequency - Target Frequency) Oscillation frequency × 3.051 × 10-6 ≈ (Oscillation Frequency – Target Frequency) × 10 When DEV=1: Oscillation adjustment value = (Oscillation frequency - Target Frequency) Oscillation frequency × 1.017 × 10-6 ≈ (Oscillation Frequency – Target Frequency) × 30 Oscillation adjustment value calculations are exemplified below (A) For an oscillation frequency = 32768.85Hz and a target frequency = 32768.05Hz When setting DEV bit to 0: Oscillation adjustment value = (32768.85 - 32768.05 + 0.1) / (32768.85 × 3.051 × 10-6) ≈ (32768.85 - 32768.05) × 10 + 1 = 9.001 ≈ 9 In this instance, write the settings (DEV,F6,F5,F4,F3,F2,F1,F0)=(0,0,0,0,1,0,0,1) in the oscillation adjustment register. Thus, an appropriate oscillation adjustment value in the presence of any time count gain represents a distance from 01h. When setting DEV bit to 1: Oscillation adjustment value = (32768.85 - 32768.05 + 0.0333) / (32768.85 × 1.017 × 10-6) ≈ (32768.85 - 32768.05) × 30 + 1 = 25.00 ≈ 25 In this instance, write the settings (DEV,F6,F5,F4,F3,F2,F1,F0)=(1,0,0,1,1,0,0,1) in the oscillation adjustment register. (B) For an oscillation frequency = 32762.22Hz and a target frequency = 32768.05Hz When setting DEV bit to 0: Oscillation adjustment value = (32762.22 - 32768.05) / (32762.22 × 3.051 × 10-6) ≈ (32762.22 - 32768.05) × 10 = -58.325 ≈ -58 To represent an oscillation adjustment value of - 58 in 7-bit coded decimal notation, subtract 58 (3Ah) from 128 (80h) to obtain 46h. In this instance, write the settings of (DEV,F6,F5,F4,F3,F2,F1,F0) = (0,1,0,0,0,1,1,0) in the oscillation adjustment register. Thus, an appropriate oscillation adjustment value in the presence of any time count loss represents a distance from 80h. When setting DEV bit to 1: Oscillation adjustment value = (32762.22 - 32768.05) / (32762.22 × 1.017 × 10-6) ≈ (32762.22 - 32768.05) × 30 = -174.97 ≈ -175 Oscillation adjustment value can be set from -62 to 63. Then, in this case, Oscillation adjustment value is out of range. 36 R2061 series (4) Difference between DEV=0 and DEV=1 Difference between DEV=0 and DEV=1 is following, DEV=0 -189.2ppm to 189.2ppm 3ppm DEV=1 -62ppm to 63ppm 1ppm Maximum value range Minimum resolution Notes: If following 3 conditions are completed, actual clock adjustment value could be different from target adjustment value that set by oscillator adjustment function. 1. Using oscillator adjustment function 2. Access to R2061 at random, or synchronized with external clock that has no relation to R2061, or synchronized with periodic interrupt in pulse mode. 3. Access to R2061 more than 2 times per each second on average. For more details, please contact to Ricoh. • How to evaluate the clock gain or loss The oscillator adjustment circuit is configured to change time counts of 1 second on the basis of the settings of the oscillation adjustment register once in 20 seconds or 60 seconds. The way to measure the clock error as follows: (1) Output a 1Hz clock pulse of Pulse Mode with interrupt pin Set (0,0,x,x,0,0,1,1) to Control Register 1 at address Eh. (2) After setting the oscillation adjustment register, 1Hz clock period changes every 20seconds ( or every 60 seconds) like next page figure. 1Hz clock pulse T0 T0 19 times T0 T1 1 time Measure the interval of T0 and T1 with frequency counter. A frequency counter with 7 or more digits is recommended for the measurement. (3) Calculate the typical period from T0 and T1 T = (19×T0+1×T1)/20 Calculate the time error from T. 37 R2061 series Power-on Reset, Oscillation Halt Sensing, and Supply Voltage Monitoring • PON, XST , and VDET The power-on reset circuit is configured to reset control register1, 2, and clock adjustment register when VDD power up from 0v. The oscillation halt sensing circuit is configured to record a halt on oscillation by 32.768-kHz clock pulses. The supply voltage monitoring circuit is configured to record a drop in supply voltage below a threshold voltage of 2.1 or 1.35v. Each function has a monitor bit. I.e. the PON bit is for the power-on reset circuit, and XST bit is for the oscillation halt sensing circuit, and VDET is for the supply voltage monitoring circuit. PON and VDET bits are activated to “H”. However, XST bit is activated to “L”. The PON and VDET accept only the writing of 0, but XST accepts the writing of 0 and 1. The PON bit is set to 1, when VDD power-up from 0V, but VDET is set to 0, and XST is indefinite. The functions of these three monitor bits are shown in the table below. PON Monitoring for the power-on reset function D4 in Address Fh High 1 0 only XST Monitoring for the oscillation halt sensing function D5 in Address Fh Low indefinite Function Address Activated When VDD power up from 0v accept the writing VDET a drop in supply voltage below a threshold voltage of 2.1 or 1.35v D6 in Address Fh High 0 0 only Both 0 and 1 The relationship between the PON, XST , and VDET is shown in the table below. PON 0 XST VDET 0 0 0 0 1 0 1 0 0 1 1 1 * * Conditions of supply voltage and oscillation Halt on oscillation, but no drop in VDD supply voltage below threshold voltage Halt on oscillation and drop in VDD supply voltage below threshold voltage, but no drop to 0V No drop in VDD supply voltage below threshold voltage and no halt in oscillation Drop in VDD supply voltage below threshold voltage and no halt on oscillation Drop in supply voltage to 0v Condition of oscillator, and back-up status Halt on oscillation cause of condensation etc. Halt on oscillation cause of drop in back-up battery voltage Normal condition No halt on oscillation, but drop in back-up battery voltage Power-up from 0v, 38 R2061 series Threshold voltage (2.1V or 1.35V) VDD 32768Hz Oscillation Power-on reset flag (PON) Oscillation halt sensing flag ( XST ) VDD supply voltage monitor flag (VDET) VDET←0 XST ←1 PON←0 VDET←0 XST ←1 PON←1 VDET←0 XST ←1 PON←0 Internal initialization period (1 to 2 sec.) Internal initialization period (1 to 2 sec.) When the PON bit is set to 1 in the control register 2, the DEV, F6 to F0, WALE, DALE, 12 /24, SCRATCH2, TEST, CT2, CT1, CT0, VDSL, VDET, SCRATCH1, CTFG, WAFG, and DAFG bits are reset to 0 in the oscillation adjustment register, the control register 1, and the control register 2. The PON bit is also set to 1 at power-on from 0 volts. < Considerations in Using Oscillation Halt Sensing Circuit > Be sure to prevent the oscillation halt sensing circuit from malfunctioning by preventing the following: 1) Instantaneous power-down on the VDD 2) Condensation on the quartz crystal unit 3) On-board noise to the quartz crystal unit 4) Applying to individual pins voltage exceeding their respective maximum ratings In particular, note that the XST bit may fail to be set to 0 in the presence of any applied supply voltage as illustrated below in such events as backup battery installation. Further, give special considerations to prevent excessive chattering in the oscillation halt sensing circuit. VDD 39 R2061 series • Voltage Monitoring Circuit R2061 incorporates two kinds of voltage monitoring function. These are shown in the table below. VCC Voltage Monitoring VCC Voltage Monitoring Circuit Circuit (VDET) Purpose CPU reset output Back-up battery checker Monitoring supply voltage VCC pin VDD pin (supply voltage for the internal RTC circuit) Output for result Store in the Control Register 2 VDCC pin (D6 in Address Fh) Function After falling VCC, VDCC outputs “L”. tDEALY after rising VCC, VDCC outputs “H” (OFF) Below the threshold voltage, SW1 turns off and SW2 turns on. Over the threshold voltage, SW1 turns on and SW2 turns off. Detector Threshold (falling -VDET1 Selecting from VDETH or VDETL by edge of power supply voltage) writing to the register (D7 in Address Fh) Detector Released +VDET1 Same as falling edge Voltage (rising edge of power ( No hysteresis) supply voltage) The way to monitor Always One time every second The VDD supply voltage monitoring circuit is configured to conduct a sampling operation during an interval of 7.8ms per second to check for a drop in supply voltage below a threshold voltage of 2.1 or 1.35v for the VDSL bit setting of 0 (the default setting) or 1, respectively, in the Control Register 2, thus minimizing supply current requirements as illustrated in the timing chart below. This circuit suspends a sampling operation once the VDET bit is set to 1 in the Control Register 2. The VDD supply voltage monitor is useful for back-up battery checking. VDD 2.1v or 1.35v PON Internal initialization period (1 to 2sec.) 7.8ms 1s Sampling timing for VDD supply voltage monitor VDET (D6 in Address Fh) PON←0 VDET←0 VDET←0 40 R2061 series The VCC supply voltage monitor circuit operates always. When VCC rising over +VDET1, SW1 turns on, and SW2 turns off. And tDELAY after rising VCC, VDCC outputs OFF(H). But when oscillation is halt, VCC outputs OFF(H) tDELAY after oscillation starting. When VCC falling beyond -VDET1, SW1 turns off, and SW2 turns on. And VDCC outputs “L”. Oscillation starting -VDET1 +VDET1 Same voltage level as VSB VCC VDD 32768Hz Oscillation VDCC tDELAY SW1 SW2 tDELAY tDELAY ON ON ON ON ON Battery Switch Over Circuit R2061 incorporates three power supply pins, VDD, VCC, and VSB. VDD pin is the power supply pin for internal real time clock circuit. When VCC voltage is lower than ±VDET1, VSB supplies the power to VDD, and when higher than ±VDET1, VCC supplies the power to VDD. The timing chart for VCC, VDD, and VSB is shown following. +VDET1 -VDET1 VCC VSB VDD (1 ) (2 ) (3 ) (2 ) (3 ) (1) When VSB is 0v and VCC is rising from 0v, VDD follows half of VCC voltage level. After VCC rising over +VDET1, VDD follows VCC voltage level. (2) When VCC is higher than +VDET1, VDD level is equal to VCC. (3) After VCC falling beyond –VDET1, VDD level is equal to VSB. 41 R2061 series Alarm and Periodic Interrupt The R2061 incorporates the alarm interrupt circuit and the periodic interrupt circuit that are configured to generate alarm signals and periodic interrupt signals for output from the INTR pin as described below. (1) Alarm Interrupt Circuit The alarm interrupt circuit is configured to generate alarm signals for output from the INTR , which is driven low (enabled) upon the occurrence of a match between current time read by the time counters (the day-of-week, hour, and minute counters) and alarm time preset by the alarm registers (the Alarm_W registers intended for the day-of-week, hour, and minute digit settings and the Alarm_D registers intended for the hour and minute digit settings). (2) Periodic Interrupt Circuit The periodic interrupt circuit is configured to generate either clock pulses in the pulse mode or interrupt signals in the level mode for output from the INTR pin depending on the CT2, CT1, and CT0 bit settings in the control register 1. The above two types of interrupt signals are monitored by the flag bits (i.e. the WAFG, DAFG, and CTFG bits in the Control Register 2) and enabled or disabled by the enable bits (i.e. the WALE, DALE, CT2, CT1, and CT0 bits in the Control Register 1) as listed in the table below. Flag bits WAFG (D1 at Address Fh) DAFG (D0 at Address Fh) CTFG (D2 at Address Fh) Enable bits WALE (D7 at Address Eh) DALE (D6 at Address Eh) CT2=CT1=CT0=0 (These bit setting of “0” disable the Periodic Interrupt) (D2 to D0 at Address Eh) Alarm_W Alarm_D Peridic interrupt * At power-on, when the WALE, DALE, CT2, CT1, and CT0 bits are set to 0 in the Control Register 1, the INTR pin is driven high (disabled). * When two types of interrupt signals are output simultaneously from the INTR pin, the output from the INTR pin becomes an OR waveform of their negative logic. Example: Combined Output to INTR Pin Under Control of Alarm_D and Periodic Interrupt Alarm_D Periodic Interrupt IN T R In this event, which type of interrupt signal is output from the INTR pin can be confirmed by reading the DAFG, and CTFG bit settings in the Control Register 2. 42 R2061 series • Alarm Interrupt The alarm interrupt circuit is controlled by the enable bits (i.e. the WALE and DALE bits in the Control Register 1) and the flag bits (i.e. the WAFG and DAFG bits in the Control Register 2). The enable bits can be used to enable this circuit when set to 1 and to disable it when set to 0. When intended for reading, the flag bits can be used to monitor alarm interrupt signals. When intended for writing, the flag bits will cause no event when set to 1 and will drive high (disable) the alarm interrupt circuit when set to 0. The enable bits will not be affected even when the flag bits are set to 0. In this event, therefore, the alarm interrupt circuit will continue to function until it is driven low (enabled) upon the next occurrence of a match between current time and preset alarm time. The alarm function can be set by presetting desired alarm time in the alarm registers (the Alarm_W Registers for the day-of-week digit settings and both the Alarm_W Registers and the Alarm_D Registers for the hour and minute digit settings) with the WALE and DALE bits once set to 0 and then to 1 in the Control Register 1. Note that the WALE and DALE bits should be once set to 0 in order to disable the alarm interrupt circuit upon the coincidental occurrence of a match between current time and preset alarm time in the process of setting the alarm function. Interval (1min.) during which a match between current time and preset alarm time occurs IN T R WALE←1 current time = WALE←0 preset alarm time (DALE) (DALE) WALE←1 (DALE) current time = preset alarm time IN T R WALE←1 current time = preset alarm time (DALE) WAFG←0 (DAFG) current time = preset alarm time After setting WALE(DALW) to 0, Alarm registers is set to current time, and WALE(DALE) is set to 1, INTR will be not driven to “L” immediately, INTR will be driven to “L” at next alarm setting time. 43 R2061 series • Periodic Interrupt Setting of the periodic selection bits (CT2 to CT0) enables periodic interrupt to the CPU. There are two waveform modes: pulse mode and level mode. In the pulse mode, the output has a waveform duty cycle of around 50%. In the level mode, the output is cyclically driven low and, when the CTFG bit is set to 0, the output is return to High (OFF). CT2 CT1 CT0 Wave form mode 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Pulse Mode *1) Pulse Mode *1) Level Mode *2) Level Mode *2) Level Mode *2) Level Mode *2) Description Interrupt Cycle and Falling Timing OFF(H) Fixed at “L” 2Hz(Duty50%) 1Hz(Duty50%) Once per 1 second (Synchronized with Second counter increment) Once per 1 minute (at 00 seconds of every Minute) Once per hour (at 00 minutes and 00 Seconds of every hour) Once per month (at 00 hours, 00 minutes, and 00 seconds of first day of every month) (Default) *1) Pulse Mode: 2-Hz and 1-Hz clock pulses are output in synchronization with the increment of the second counter as illustrated in the timing chart below. CTFG Bit I N TR Pin Approx. 92µs (Increment of second counter) Rewriting of the second counter In the pulse mode, the increment of the second counter is delayed by approximately 92 µs from the falling edge of clock pulses. Consequently, time readings immediately after the falling edge of clock pulses may appear to lag behind the time counts of the real-time clocks by approximately 1 second. Rewriting the second counter will reset the other time counters of less than 1 second, driving the INTR pin low. *2) Level Mode: Periodic interrupt signals are output with selectable interrupt cycle settings of 1 second, 1 minute, 1 hour, and 1 month. The increment of the second counter is synchronized with the falling edge of periodic interrupt signals. For example, periodic interrupt signals with an interrupt cycle setting of 1 second are output in synchronization with the increment of the second counter as illustrated in the timing chart below. 44 R2061 series CTFG Bit I N TR Pin Setting CTFG bit to 0 (Increment of second counter) (Increment of second counter) Setting CTFG bit to 0 (Increment of second counter) *1), *2) When the oscillation adjustment circuit is used, the interrupt cycle will fluctuate once per 20sec. as follows: Pulse Mode: The “L” period of output pulses will increment or decrement by a maximum of ±3.784ms. For example, 1-Hz clock pulses will have a duty cycle of 50 ±0.3784%. Level Mode: A periodic interrupt cycle of 1 second will increment or decrement by a maximum of ±3.784ms. 45 R2061 series Typical Applications • Typical Power Circuit Configurations The case of back-up by primary battery The case of back-up by capacitor or secondary battery (Charging voltage is equal to CPU power supply voltage) The case of back-up by capacitor or secondary battery (Charging voltage is not equal to CPU power supply voltage) VCC VSB VDD CPU Power Supply VCC VSB VDD CPU power supply VCC VSB VDD CPU power supply (3V) 5V 0.1µF 0.1µF 0.1 µF D ouble layer capacitor etc. VSS CR2025 etc. VSS VSS ML614 etc. VDD pin cannot be connected to any additional heavy load components such as SRAM. And VDD pin must be connected C2, and C2 should be over 0.1µF. CPU power supply R2061 Series R1 C2 Vbat SW2 VSB VOLTAGE DETECTOR -VDET1 VDD SW1 VCC C3 CPU Rcpu When secondary battery or double layer capacitor connects to VDD pin, after CPU power supply turning off, secondary battery discharges through the root above figure. If R1 is much smaller than CPU impedance (Rcpu), VCC voltage keeps higher than -VDET1, and SW1 keeps on. Therefore R1 must be specified by following formula. R1 > Rcpu x (Vbat - (-VDET1)) / (-VDET1) R1 is specified by back-up battery or double layer capacitor, too. Please check the data sheet for back-up devices. 46 R2061 series • Connection of CIN pin Please connect capacitor over 0.1µF between CIN and VSS pin. • Connection of INTR and VDCC Pin The INTR and VDCC pins follow the N-channel open drain output logic and contains no protective diode on the power supply side. As such, it can be connected to a pull-up resistor of up to 5.5 volts regardless of supply voltage. CPU power supply INTR or VDCC A *1) B Backup power supply 32768Hz OSCIN OSCOUT VSB VSS *1) Depending on whether the INTR and VDCC pins are to be used during battery backup, it should be connected to a pull-up resistor at the following different positions: (1) Position A in the left diagram when it is not to be used during battery backup. (2) Position B in the left diagram when it is to be used during battery backup. 47 R2061 series Typical Characteristics • Time keeping current (ISB) vs. Supply voltage (VSB) (Topt=25°C) 0.5 Time keeping current (uA) Test Circuit VCC INTR OSCIN OSCOUT VSB VDD 0.1µF CIN VSS 0.1µF 0.4 0.3 0.2 VDCC CE A 0.1 SCLK 0 0 1 2 3 VSB(v) 4 5 6 SIO • Stand-by current (ICC) vs. Supply voltage (VCC) Test circuit VCC OSCIN OSCOUT VSB VDD 0.1µF SCLK 0 0 1 2 3 VCC(v) 4 5 6 (Topt=25°C) 2 Stand-by Current (uA) 1.5 A INTR 1 VDCC CE 0.5 CIN VSS 0.1µF SIO • Time keeping current (ISB) vs. Operating Temperature (Topt) Test circuit VCC INTR (VSB=3V) 0.7 Time keeping current (uA) 0.6 OSCIN OSCOUT VSB VDD 0.1µF CIN VSS 0.1µF 0.5 0.4 0.3 0.2 0.1 0 -50 VDCC CE SCLK -25 0 25 50 75 Operating Temperature (Celsius) 100 A SIO 48 R2061 series • Stand-by current (ICC) vs. Operating Temperature (Topt) Test circuit 2 Stand-by current(uA) VCC OSCIN OSCOUT VSB VDD 0.1µF CIN VSS 0.1µF (VCC=3V) 1.5 A 1 INTR VDCC 0.5 CE 0 -50 -25 0 25 50 75 100 Operating temperature (Celsius) SCLK SIO • CPU access current vs. SCLK clock frequency (kHz) 80 CPU access current (uA) (Topt=25°C) 60 VCC=5v 40 VCC=3v 20 0 0 200 400 600 800 1000 SCL clock frequency (KHz) • Oscillation frequency deviation (∆f/f0) vs. Operating temperature (Topt) Test circuit VCC INTR (VCC=3V Topt=25°C as standard) 20 0 -20 -40 -60 -80 -100 -120 -140 -160 -50 -25 0 25 50 75 100 Oscillation frequency deviation df/f0(ppm) OSCIN OSCOUT VSB VDD 0.1µF CIN VSS 0.1µF Frequency counter VDCC CE SCLK SIO Operating temperature Topt(Celsius) 49 R2061 series • Frequency deviation (∆f/f0) vs. Supply voltage (VSB/VCC) Test circuit VCC INTR Frequency deviation df/f0(ppm) (Topt=25°C) VCC/VSB=3V as standard 2 1 0 -1 -2 -3 -4 0 1 2 3 4 5 6 VCC/VSB(v) OSCIN OSCOUT VSB VDD 0.1µF CIN VSS 0.1µF Frequency counter VDCC CE SCLK SIO • Frequency deviation (∆f/f0) vs. CGOUT Test circuit VCC INTR (Topt=25°C, VCC=3V)CGOUT=0pF as standard Frequency deviation df/f0(ppm) 10 0 -10 -20 -30 -40 0 5 10 CGOUT(pF) 15 20 OSCIN OSCOUT VSB VDD 0.1µF CIN VSS 0.1µF Frequency counter VDCC CE SCLK SIO • Detector threshold voltage (+VDET1/-VDET1) vs. Operating temperature (Topt) (R2061K01) Test circuit VCC 1.8 OSCIN OSCOUT VSB VDD 0.1µF -50 -25 0 25 50 75 100 SCLK SIO CIN VSS 0.1µF 1.9 Detector threshold voltage ±VDET1(V) (VSB=3V) +VDET1 -VDET1 INTR 1.7 VDCC CE 1.6 Operating Temperature Topt(Celsius) 50 R2061 series • VCC-VDD(VDDOUT1) vs. Output load current (IOUT1) Test circuit VCC OSCIN OSCOUT VSB VDD 0.1µF SCLK 0 2 4 6 8 10 Output load current IOUT1(mA) (Topt=25°C) 0 -0.1 VCC-VDD(V) -0.2 -0.3 -0.4 VCC=5V INTR VCC=3V VCC=2.5V VDCC CE A 0.1µF VCC=2.0V -0.5 CIN VSS SIO • VSB-VDD(VDDOUT2) vs. Output load current (IOUT2) Test circuit VCC OSCIN OSCOUT VSB VDD 0.1µF SCLK 0 0.5 1 1.5 2 2.5 3 Output load current IOUT2(mA) 0 -0.1 VSB-VDD(V) -0.2 -0.3 -0.4 -0.5 -0.6 -0.7 -0.8 (Topt=25°C) VSB=3V VSB=1V VSB=2V INTR VDCC CE A 0.1µF CIN VSS SIO • VOL vs. IOL ( VDCC pin) • VOL vs. IOL ( INTR pin) (Topt=25°C) 0.4 0.3 VOL(v) (Topt=25°C, VSB=VCC=1.5v) 0.4 0.3 VOL(V) 0.2 0.1 0 0 1 2 3 4 5 IOL(mA) VCC=3V 0.2 VCC=5V 0.1 0 0 2 4 6 8 10 IOL(mA) 51 R2061 series Typical Software-based Operations • Initialization at Power-on Start *1) Power-on *2) PON=1? No *3) VDET=0? Yes *4) Yes Set Oscillation Adjustment Register and Control Register 1 and 2, etc. No Warning Back-up Battery Run-down *1) After power-on from 0 volt, the process of internal initialization require a time span on 1sec, so that access should be done after VDCC turning to OFF(H). *2) The PON bit setting of 0 in the Control Register 1 indicates power-on from backup battery and not from 0v. For further details, see "P.38 Power-on Reset, Oscillation Halt Sensing, and Supply Voltage Monitoring •PON, XST , and VDET ". *3) This step is not required when the supply voltage monitoring circuit is not used. *4) This step involves ordinary initialization including the Oscillation Adjustment Register and interrupt cycle settings, etc. • Writing of Time and Calendar Data *1) When writing to clock and calendar counters, do not insert CE=L until all times from second to year have been written to prevent error in writing time. (Detailed in "P.24 •Considerations in Reading and Writing Time Data under special condition". *2) Any writing to the second counter will reset divider units lower than the second digits. The R2061 may also be initialized not at power-on but in the process of writing time and calendar data. CE←H *1) W rite to Time Counter and Calendar Counter *2) CE←L *3) 52 R2061 series • Reading Time and Calendar Data (1) Ordinary Process of Reading Time and Calendar Data *1) When reading to clock and calendar counters, do not insert CE=L until all times from second to year have been read to prevent error in reading time. (Detailed in "P.24 •Considerations in Reading and Writing Time Data under special condition". CE←H *1) Read from Time Counter and Calendar Counter CE←L *1) (2) Basic Process of Reading Time and Calendar Data with Periodic Interrupt Function Set Periodic Interrupt Cycle Selection Bits *1) *1) This step is intended to select the level mode as a waveform mode for the periodic interrupt function. *2) This step must be completed within 0.5 second. *3) This step is intended to set the CTFG bit to 0 in the Control Register 2 to cancel an interrupt to the CPU. Generate Interrupt in CPU CTFG=1? No *2) Yes Read from Time Counter and Calendar Counter Other Interrupt Processes *3) Control Register 2 ←(X1X1X011) 53 R2061 series (3) Applied Process of Reading Time and Calendar Data with Periodic Interrupt Function Time data need not be read from all the time counters when used for such ordinary purposes as time count indication. This applied process can be used to read time and calendar data with substantial reductions in the load involved in such reading. For Time Indication in "Day-of-Month, Day-of-week, Hour, Minute, and Second" Format: Control Register 1← (XXXX0100) Control Register 2← (X1X1X011) *1) *1) This step is intended to select the level mode as a waveform mode for the periodic interrupt function. *2) This step must be completed within 0.5 sec. *3) This step is intended to read time data from all the time counters only in the first session of reading time data after writing time data. *4) This step is intended to set the CTFG bit to 0 in the Control Register 2 to cancel an interrupt to the CPU. Generate interrupt to CPU Other interrupts Processes CTFG=1? No *2) Yes Sec.=00? No *3) Use Previous Min.,Hr., Day,and Day-of-week data Yes Read Min.,Hr.,Day, and Day-of-week Control Register 2← (X1X1X011) *4) 54 R2061 series • Interrupt Process Set Periodic Interrupt Cycle Selection Bits (1) Periodic Interrupt *1) Generate Interrupt to CPU CTFG=1? Yes Conduct Periodic Interrupt No *1) This step is intended to select the level mode as a waveform mode for the periodic interrupt function. *2) This step is intended to set the CTFG bit to 0 in the Control Register 2 to cancel an Other Interrupt interrupt to the CPU. Processes *2) Control Register 2← (X1X1X011) 55 R2061 series (2) Alarm Interrupt WALE or DALE←0 *1) Set Alarm Min., Hr., and Day-of-week Registers WALE or DALE←1 *2) Generate Interrupt to CPU WAFG or DAFG=1? No Other Interrupt Processes Yes C onduct Alarm Interrupt *1) This step is intended to once disable the alarm interrupt circuit by setting the WALE or DALE bits to 0 in anticipation of the coincidental occurrence of a match between current time and preset alarm time in the process of setting the alarm interrupt function. *2) This step is intended to enable the alarm interrupt function after completion of all alarm interrupt settings. *3) This step is intended to once cancel the alarm interrupt function by writing the settings of "X,1,X, 1,X,1,0,1" and "X,1,X,1,X,1,1,0" to the Alarm_W Registers and the Alarm_D Registers, respectively. *3) C ontrol Register 2 ← (X1X1X101) 56