R3118x Series
Low Voltage Detector with Individual SENSE Pin and Delay Function
No. EA-242-211026
OUTLINE
The R3118x is a voltage detector IC with individual sense pin, high detector threshold accuracy and delay time,
and ultra-low supply current, which can be operated at an extremely low voltage and is used for system reset
as an example. Each of the IC consists of a voltage reference unit, a hysteresis comparator, resistors net for
detector threshold setting, an output driver transistor, and a delay circuit.
VDD supply pin for the IC and voltage supervisory sense pin are individual, therefore the output pin can keep
"L" level even if the sense pin voltage is going down to 0 V, or there is no indefinite range for the sense pin.
Since a delay circuit is built-in, by connecting an external capacitor, any output delay time can be set. In the
R3118x, detector released delay time can be set, and detector delay time is not influenced by the external
capacitor for the delay time.
The detector threshold is fixed with high accuracy internally and does not require any adjustment. The
tolerance of the detector threshold is ±22.5 mV (−VDET_S < 1.6 V) or ±1.5% (−VDET_S ≥ 1.6 V).
Minimum detector threshold voltage is 0.6 V, ultra-low voltage detector threshold can be set. Output delay time
for the detector release can be set with high accuracy. The tolerance of the IC side is ±30%. Two output types,
Nch. open drain type and CMOS type are available. If the sense pin voltage becomes to equal or lower than
the detector threshold voltage, the output voltage becomes "L", and if the sense pin voltage becomes to
released voltage, the output voltage becomes "H" after the set delay time.
Three types of packages, SOT-23-5, SC-88A, and DFN(PLP)1212-6 are available.
FEATURES (1)
•
•
•
•
•
•
•
•
•
•
Operating Voltage Range (Maximum Rating) .............. 1.0 V to 6.0 V (7.0 V)
Supply Current(2) .......................................................... Typ. 0.4 µA (VSENSE ≥ +VDET, VDD = 6 V)
Operating Temperature Range .................................... −40°C to 85°C
Detector Threshold Range ........................................... 0.6 V to 5.0 V (0.1 V step)
Accuracy Detector Threshold ...................................... ±1.5% (-VDET_S ≥ 1.6 V), ±22.5 mV (-VDET_S < 1.6 V)
Temperature-Drift Coefficient of Detector Threshold ·· Typ. ±30 ppm/°C
Accuracy Detector Released ...................................... ±30%
Temperature-Drift Coefficient of Detector Released··· Typ. ±0.16 ppm/°C
Output Types ................................................................ Nch Open Drain and CMOS
Packages ..................................................................... DFN(PLP)1212-6, SC-88A , SOT-23-5
APPLICATIONS
•
•
•
•
•
(1)
(2)
CPU and Logic Circuit Reset
Battery Checker
Window Comparator/Level Discrimination
Battery Back-up Circuit
Power Failure Detector
Ta = 25°C, unless otherwise specified.
Consumption current through SENSE pin is not included.
1
R3118x
No. EA-242-211026
SELECTION GUIDE
The detector threshold, the output type and the package type for the IC can be selected at the users’ request.
Selection Guide
Product Name
Package
Quantity per Reel
Pb Free
Halogen Free
R3118Kxx1∗-TR
DFN(PLP)1212-6
5,000 pcs
Yes
Yes
R3118Qxx2∗-TR-FE
SC-88A
3,000 pcs
Yes
Yes
R3118Nxx1∗-TR-FE
SOT-23-5
3,000 pcs
Yes
Yes
xx : The detector threshold can be designated in the range from 0.6 V (06) to 5.0 V (50) in 0.1 V step.
∗ : Designation of Output Type
(A) Nch Open Drain
(C) CMOS
BLOCK DIAGRAMS
SENSE
SENSE
VDD
DOUT
VDD
Delay
Circuit
Delay
Circuit
DOUT
VREF
Vref
GND
GND
CD
CD
R3118xxxxA (Nch. Open Drain Output)
Block Diagram
R3118xxxxC (CMOS Output)
Block Diagram
2
R3118x
No. EA-242-211026
PIN DESCRIPTIONS
Top View
6
5
Bottom View
4
4
5
5
5
4
6
(mark side)
1
2
3
3
2
1
DFN(PLP)1212-6 Pin Configuration
1
SENSE
2
GND
3
CD
4
VDD
5
NC
6
DOUT
2
(mark side)
3
SC-88A Pin Configuration
DFN(PLP)1212-6 Pin Description
Pin No.
Symbol
1
4
1
2
3
SOT-23-5 Pin Configuration
Description
Voltage Detector Voltage Sense Pin
Ground Pin
Pin for External Capacitor (for setting output delay)
Input Pin
No Connection
Output Pin ("L" at detection)
SC-88A Pin Description
Pin No.
Symbol
Description
1
DOUT
Output Pin ("L" at detection)
2
GND
Ground Pin
3
VDD
Input Pin
4
CD
5
SENSE
Pin for External Capacitor (for setting output delay)
Voltage Detector Voltage Sense Pin
SOT-23-5 Pin Description
Pin No.
Symbol
Description
1
DOUT
Output Pin ("L" at detection)
2
VDD
Input Pin
3
GND
Ground Pin
4
CD
5
SENSE
Pin for External Capacitor (for setting output delay)
Voltage Detector Voltage Sense Pin
3
R3118x
No. EA-242-211026
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings
Symbol
VDD
VSENSE
VDOUT
IDOUT
PD
Item
Rating
Unit
Supply Voltage
-0.3 to 7.0
V
SENSE Pin Voltage
-0.3 to 7.0
V
Output Voltage (R3118xxxxA)
-0.3 to 7.0
Output Voltage (R3118xxxxC)
-0.3 to VDD + 0.3
Output Current Nch Driver (Sink Current)
20
Output Current Pch Driver (Source Current)
-5
Power
Dissipation(1)
DFN(PLP)1212-6
JEDEC STD.51-7
Test Land Pattern
450
SC-88A
Standard Test Land Pattern
380
SOT-23-5
JEDEC STD.51-7
Test Land Pattern
660
V
mA
mW
Tj
Junction Temperature Range
-40 to 125
°C
Tstg
Storage Temperature Range
-55 to 125
°C
ABSOLUTE MAXIMUM RATINGS
Electronic and mechanical stress momentarily exceeded absolute maximum ratings may cause permanent damage
and may degrade the lifetime and safety for both device and system using the device in the field. The functional
operation at or over these absolute maximum ratings is not assured.
RECOMMENDED OPERATING CONDITIONS
Recommended Operating Conditions
Symbol
Item
Rating
Unit
VDD
Supply Voltage
1.0 to 6.0
V
Ta
Operating Temperature Range
−40 to 85
°C
RECOMMENDED OPERATING CONDITIONS
All of electronic equipment should be designed that the mounted semiconductor devices operate within the
recommended operating conditions. The semiconductor devices cannot operate normally over the recommended
operating conditions, even if they are used over such conditions by momentary electronic noise or surge. And the
semiconductor devices may receive serious damage when they continue to operate over the recommended operating
conditions.
(1)
Refer to POWER DISSIPATION for detailed information.
4
R3118x
No. EA-242-211026
ELECTRICAL CHARACTERISTICS
VDD = 1 V to 6 V, unless otherwise specified.
The specifications surrounded by
are guaranteed by design engineering at −40°C ≤ Ta ≤ 85°C.
R3118xxxxA/C Electrical Characteristics
Symbol
Item
Conditions
Detector
Threshold
−VDET_S
−VDET_S
−VDET_S
−0.0225
+0.0225
−40°C ≤ Ta ≤ 85°C
−VDET_S
−VDET_S
−0.0375
−VDET_S
+0.0375
Ta = 25°C
−VDET_S
−VDET_S
× 0.985
−VDET_S
× 1.015
−VDET_S
−VDET_S
× 0.975
−VDET_S
−VDET_S
×
× 0.040
0.055
−VDET_S
−VDET_S
×
× 0.035
0.055
0.480
−VDET_S
× 1.025
-VDET_S ≥ 1.6 V
−40°C ≤ Ta ≤ 85°C
VHYS
ISS
RSENSE
IDOUT
Detector
threshold
Hysteresis
Ta = 25°C
−40°C ≤ Ta ≤ 85°C
Supply
Current(2)
VSENSE = 0 V, VDD = 6 V
Sense Resistor
VSENSE = 6 V, VDD = 6 V
VSENSE = 6 V, VDD = 6 V
0.150
VDD = 3 V, VDOUT = 0.1 V
0.550
VDD = 5 V, VDOUT = 0.1 V
0.850
VDD = 1 V, VDOUT = 0.4 V
0.400
VDD = 3 V, VDOUT = 0.4 V
2.100
VDD = 5 V, VDOUT = 0.4 V
3.300
VDD = 1 V, VDOUT = 0.9 V
6
VDD = 3 V, VDOUT = 2.9 V
30
VDD = 5 V, VDOUT = 4.9 V
Nch Driver
Leakage Current VSENSE = 6 V, VDD = 6 V, VDOUT = 6 V
(R3118xxxxA)
VSENSE = 6 V, VDD = 1 V, VCD = 0.4 V
CD pin
45
Output Current
(Driver Output
Pin)
Pch
VSENSE = 6 V
(R3118xxxxC)
ILEAK
RDIS
(1)
(2)
9
VDD = 1 V, VDOUT = 0.1 V
Nch.
VSENSE = 0 V
Discharge Tr.
On Resistance
Typ.
Ta = 25°C
-VDET_S(1) < 1.6 V
-VDET
Min.
(Ta = 25°C)
Max.
Unit
−VDET_S
× 0.070
−VDET_S
× 0.075
1.450
0.400
1.200
34
58
V
V
µA
MΩ
mA
µA
80
2.200
6.200
VSENSE = 6 V, VDD = 3 V, VCD = 0.4 V
0.400
1.250
VSENSE = 6 V, VDD = 5 V, VCD = 0.4 V
0.250
0.800
nA
kΩ
-VDET_S : Set Detector Threshold
Consumption current through SENSE pin is not included.
5
R3118x
No. EA-242-211026
ELECTRICAL CHARACTERISTICS (continued)
VDD = 1 V to 6 V, unless otherwise specified.
The specifications surrounded by
are guaranteed by design engineering at −40°C ≤ Ta ≤ 85°C.
R3118xxxxA/C Electrical Characteristics
Symbol
Item
Conditions
Detect Output
tRESET
Ta = 25°C
Delay Time( 1)
Ta = 25°C
Release Output
tDELAY
Delay Time( 2)
−40°C ≤ Ta ≤ 85°C
Min.
Typ.
(Ta = 25°C)
Max.
Unit
80
µs
70
100
130
65
100
145
ms
All of unit are tested and specified under load conditions such that Tj ≈ Ta = 25°C except for Detector Output Delay Time
and Release Output Delay Time.
(1)
(2)
R3118xxxxC: In the case that a 0.022 µF capacitor is connected to the CD pin, the time interval from forcing pulsive
voltage between -VDET_S ×1.155 V and -VDET_S ×0.9 V to SENSE pin, to when the output voltage of the DOUT pin will
reach from "H" to VDD/2.
R3118xxxxA: In the case that a 0.022 µF capacitor is connected to the CD pin and the DOUT pin is pulled up to 5 V
with 470 kΩ, the time interval from forcing pulsive voltage between –VDET_S×1.155 V and -VDET_S×0.9 V to SENSE pin,
to when the output voltage reaches from "H" to 2.5V.
R3118xxxxC: In the case that a 0.022 µF capacitor is connected to the CD pin, the time interval from forcing pulsive
voltage between -VDET_S×0.9 V and -VDET_S×1.155 V to SENSE pin, to when the output voltage of the DOUT pin will
reach from "L" to VDD/2.
R3118xxxxA: In the case that a 0.022 μF capacitor is connected to the CD pin and the DOUT pin is pulled up to 5 V
with 470 kΩ, the time interval from forcing pulsive voltage between -VDET_S ×0.9 V and -VDET_S x1.155 V to SENSE pin,
to when the output voltage reaches from "L" to 2.5 V.
6
R3118x
No. EA-242-211026
ELECTRICAL CHARACTERISTICS (continued)
The specifications surrounded by
are guaranteed by design engineering at −40°C ≤ Ta ≤ 85°C.
R3118xxxxA/C
Product
Name
R3118x06xx
R3118x07xx
R3118x08xx
R3118x09xx
R3118x10xx
R3118x11xx
R3118x12xx
R3118x13xx
R3118x14xx
R3118x15xx
R3118x16xx
R3118x17xx
R3118x18xx
R3118x19xx
R3118x20xx
R3118x21xx
R3118x22xx
R3118x23xx
R3118x24xx
R3118x25xx
R3118x26xx
R3118x271x
R3118x28xx
R3118x29xx
R3118x30xx
R3118x31xx
R3118x32xx
R3118x33xx
R3118x34xx
R3118x35xx
R3118x36xx
R3118x37xx
R3118x38xx
R3118x39xx
R3118x40xx
R3118x41xx
R3118x42xx
R3118x43xx
R3118x44xx
R3118x45xx
R3118x46xx
R3118x47xx
R3118x48xx
R3118x49xx
R3118x50xx
-VDET [V]
Ta = 25°C
-40°C ≤ Ta ≤ 85°C
Min.
Typ.
Max.
Min.
Typ.
Max.
0.5775
0.6775
0.7775
0.8775
0.9775
1.0775
1.1775
1.2775
1.3775
1.4775
1.5760
1.6745
1.7730
1.8715
1.9700
2.0685
2.1670
2.2655
2.3640
2.4625
2.5610
2.6595
2.7580
2.8565
2.9550
3.0535
3.1520
3.2505
3.3490
3.4475
3.5460
3.6445
3.7430
3.8415
3.9400
4.0385
4.1370
4.2355
4.3340
4.4325
4.5310
4.6295
4.7280
4.8265
4.9250
0.6000
0.7000
0.8000
0.9000
1.0000
1.1000
1.2000
1.3000
1.4000
1.5000
1.6000
1.7000
1.8000
1.9000
2.0000
2.1000
2.2000
2.3000
2.4000
2.5000
2.6000
2.7000
2.8000
2.9000
3.0000
3.1000
3.2000
3.3000
3.4000
3.5000
3.6000
3.7000
3.8000
3.9000
4.0000
4.1000
4.2000
4.3000
4.4000
4.5000
4.6000
4.7000
4.8000
4.9000
5.0000
0.6225
0.7225
0.8225
0.9225
1.0225
1.1225
1.2225
1.3225
1.4225
1.5225
1.6240
1.7255
1.8270
1.9285
2.0300
2.1315
2.2330
2.3345
2.4360
2.5375
2.6390
2.7405
2.8420
2.9435
3.0450
3.1465
3.2480
3.3495
3.4510
3.5525
3.6540
3.7555
3.8570
3.9585
4.0600
4.1615
4.2630
4.3645
4.4660
4.5675
4.6690
4.7705
4.8720
4.9735
5.0750
0.5625
0.6625
0.7625
0.8625
0.9625
1.0625
1.1625
1.2625
1.3625
1.4625
1.5600
1.6575
1.7550
1.8525
1.9500
2.0475
2.1450
2.2425
2.3400
2.4375
2.5350
2.6325
2.7300
2.8275
2.9250
3.0225
3.1200
3.2175
3.3150
3.4125
3.5100
3.6075
3.7050
3.8025
3.9000
3.9975
4.0950
4.1925
4.2900
4.3875
4.4850
4.5825
4.6800
4.7775
4.8750
0.6000
0.7000
0.8000
0.9000
1.0000
1.1000
1.2000
1.3000
1.4000
1.5000
1.6000
1.7000
1.8000
1.9000
2.0000
2.1000
2.2000
2.3000
2.4000
2.5000
2.6000
2.7000
2.8000
2.9000
3.0000
3.1000
3.2000
3.3000
3.4000
3.5000
3.6000
3.7000
3.8000
3.9000
4.0000
4.1000
4.2000
4.3000
4.4000
4.5000
4.6000
4.7000
4.8000
4.9000
5.0000
0.6375
0.7375
0.8375
0.9375
1.0375
1.1375
1.2375
1.3375
1.4375
1.5375
1.6400
1.7425
1.8450
1.9475
2.0500
2.1525
2.2550
2.3575
2.4600
2.5625
2.6650
2.7675
2.8700
2.9725
3.0750
3.1775
3.2800
3.3825
3.4850
3.5875
3.6900
3.7925
3.8950
3.9975
4.1000
4.2025
4.3050
4.4075
4.5100
4.6125
4.7150
4.8175
4.9200
5.0225
5.1250
-VHYS [V]
Ta = 25°C
-40°C ≤ Ta ≤ 85°C
Min.
Typ.
Max.
Min.
Typ.
Max.
0.0240
0.0280
0.0320
0.0360
0.0400
0.0440
0.0480
0.0520
0.0560
0.0600
0.0640
0.0680
0.0720
0.0760
0.0800
0.0840
0.0880
0.0920
0.0960
0.1000
0.1040
0.1080
0.1120
0.1160
0.1200
0.1240
0.1280
0.1320
0.1360
0.1400
0.1440
0.1480
0.1520
0.1560
0.1600
0.1640
0.1680
0.1720
0.1760
0.1800
0.1840
0.1880
0.1920
0.1960
0.2000
0.0330
0.0385
0.0440
0.0495
0.0550
0.0605
0.0660
0.0715
0.0770
0.0825
0.0880
0.0935
0.0990
0.1045
0.1100
0.1155
0.1210
0.1265
0.1320
0.1375
0.1430
0.1485
0.1540
0.1595
0.1650
0.1705
0.1760
0.1815
0.1870
0.1925
0.1980
0.2035
0.2090
0.2145
0.2200
0.2255
0.2310
0.2365
0.2420
0.2475
0.2530
0.2585
0.2640
0.2695
0.2750
0.0420
0.0490
0.0560
0.0630
0.0700
0.0770
0.0840
0.0910
0.0980
0.1050
0.1120
0.1190
0.1260
0.1330
0.1400
0.1470
0.1540
0.1610
0.1680
0.1750
0.1820
0.1890
0.1960
0.2030
0.2100
0.2170
0.2240
0.2310
0.2380
0.2450
0.2520
0.2590
0.2660
0.2730
0.2800
0.2870
0.2940
0.3010
0.3080
0.3150
0.3220
0.3290
0.3360
0.3430
0.3500
0.0210
0.0245
0.0280
0.0315
0.0350
0.0385
0.0420
0.0455
0.0490
0.0525
0.0560
0.0595
0.0630
0.0665
0.0700
0.0735
0.0770
0.0805
0.0840
0.0875
0.0910
0.0945
0.0980
0.1015
0.1050
0.1085
0.1120
0.1155
0.1190
0.1225
0.1260
0.1295
0.1330
0.1365
0.1400
0.1435
0.1470
0.1505
0.1540
0.1575
0.1610
0.1645
0.1680
0.1715
0.1750
0.0330
0.0385
0.0440
0.0495
0.0550
0.0605
0.0660
0.0715
0.0770
0.0825
0.0880
0.0935
0.0990
0.1045
0.1100
0.1155
0.1210
0.1265
0.1320
0.1375
0.1430
0.1485
0.1540
0.1595
0.1650
0.1705
0.1760
0.1815
0.1870
0.1925
0.1980
0.2035
0.2090
0.2145
0.2200
0.2255
0.2310
0.2365
0.2420
0.2475
0.2530
0.2585
0.2640
0.2695
0.2750
0.0450
0.0525
0.0600
0.0675
0.0750
0.0825
0.0900
0.0975
0.1050
0.1125
0.1200
0.1275
0.1350
0.1425
0.1500
0.1575
0.1650
0.1725
0.1800
0.1875
0.1950
0.2025
0.2100
0.2175
0.2250
0.2325
0.2400
0.2475
0.2550
0.2625
0.2700
0.2775
0.2850
0.2925
0.3000
0.3075
0.3150
0.3225
0.3300
0.3375
0.3450
0.3525
0.3600
0.3675
0.3750
7
R3118x
No. EA-242-211026
THEORY OF OPERATION
R3118xxxxA (Nch. OPEN-DRAIN OUTPUT)
SENSE
VDD
Comparator
Ra
Delay
Circuit
DOUT
∗) DOUT pin should be pulled-up to
VDD or an external voltage level.
Rb
Vref
Nch
Tr.1
Rc
GND
CD
R3118xxxxA Block Diagram with External Capacitor
1
2
3
Supply Voltage (VDD)
Minimum Operating VDDL
Voltage
Step
1
2
3
Released Voltage +VDET
Comparator (−)
Pin Input Voltage
I
II
I
Comparator Output
L
H
L
Tr.1
OFF
ON
OFF
OFF
ON
OFF
Detector Threshold −VDET
A
Detector Threshold
Hysteresis (1)
B
SENSE Pin Voltage
(VSENSE)
Output Tr.
GND
I
Pull-up Voltage
Detect Output Delay Time
Output Voltage
(VOUT)
treset
Release Output Delay Time
tdelay
II
Nch
Rb+Rc
×VSENSE
Ra+Rb+Rc
Rb
Ra+Rb
×VSENSE
GND
Operation Diagram
1
Step 1. The output voltage is equal to the pull-up voltage.
Step 2. At Point "A", VREF ≤ VSENSE x (Rb+Rc)/(Ra+Rb+Rc) is true, as a result, the output of comparator is
reversed from "L" to "H", therefore the output voltage becomes the GND level. The voltage level of
Point A means a detector threshold voltage (-VDET). (When the supply voltage is lower than the
minimum operating voltage, the operation of the output transistor becomes indefinite. The output
voltage is equal to the GND level.)
Step 3. At Point "B", VREF ≤ VSENSE x Rb/(Ra+Rb) is true, as a result, the output of comparator is reversed from
"H" to "L", then the output voltage is equal to the pull-up voltage. The voltage level of Point B means a
released voltage (+VDET).
(1)
The difference between a released voltage and a detector threshold voltage is a detector threshold hysteresis.
8
R3118x
No. EA-242-211026
R3118xxxxC (CMOS OUTPUT)
SENSE
VDD
Comparator
Ra
Pch
Delay
Circuit
DOUT
Rb
Vref
Nch
Tr.1
Rc
GND
CD
R3118xxxC Block Diagram with External Capacitor
1
2
3
Step
1
2
3
Comparator (−)
Pin Input Voltage
I
II
I
Comparator Output
L
H
L
Tr.1
OFF
ON
OFF
Pch
ON
OFF
ON
Nch
OFF
ON
OFF
Supply Voltage (VDD)
Minimum Operating VDDL
Voltage
Released Voltage
+VDET
Detector Threshold −VDET
A
Detector Threshold
Hysteresis (1)
B
Output Tr.
SENSE Pin Voltage
(VSENSE)
GND
I
Supply Voltage (VDD)
Detect Output Delay Time
Output Voltage
(VOUT)
tRESET
Release Output Delay Time
tDELAY
II
Rb+Rc
×VSENSE
Ra+Rb+Rc
Rb
Ra+Rb
×VSENSE
GND
Operation Diagram
1
Step 1. The output voltage is equal to the supply voltage (VDD).
Step 2. At Point "A", VREF ≥ VSENSE × (Rb+Rc)/(Ra+Rb+Rc) is true, as a result, the output of comparator is
reversed from "L" to "H", therefore the output voltage becomes the GND level. The voltage level of
Point A means a detector threshold voltage (-VDET). (When the supply voltage is lower than the
minimum operating voltage, the operation of the output transistor becomes indefinite. The output
voltage is equal to the GND level.)
Step 3. At Point "B", VREF ≤ VSENSE × Rb/(Ra+Rb) is true, as a result, the output of comparator is reversed from
"H" to "L", then the output voltage is equal to the supply voltage (VDD). The voltage level of Point B
means a released voltage (+VDET).
(1)
The difference between a released voltage and a detector threshold voltage is a detector threshold hysteresis.
9
R3118x
No. EA-242-211026
WHEN POWER TO SENSE PIN TURNING-ON AFTER VDD PIN’S POWER-ON
VDD pin voltage VDD
6V
1V
Time t
SENSE pin voltage
VSENSE
Released Voltage
+VDET
Detector Threshold
-VDET
Time t
DOUT pin voltage
VDOUT
Indefinite
Release Output
Delay Time (tDELAY)
Detect Output
Delay Time (tRESET)
Time t
If a voltage is applied to SENSE pin after a power (in the range from 1 V to 6 V) is applied to VDD pin, DOUT
pin becomes "L" when the SENSE pin voltage is less than released voltage +VDET, ,and DOUT pin becomes
"H" when the SENSE pin voltage is equal or more than the released voltage +VDET.
10
R3118x
No. EA-242-211026
WHEN POWER TO VDD PIN TURNING-ON AFTER SENSE PIN’S POWER-ON
VDD pin voltage VDD
6V
1V
Time t
SENSE pin voltage
VSENSE
Released Voltage
+VDET
Detector Threshold
-VDET
Time t
DOUT pin voltage
VDOUT
Release Output
Delay Time (tDELAY)
Indefinite
Release Output
Delay Time (tDELAY)
Detect Output
Delay Time (tRESET)
Time t
In the case of the SENSE pin voltage is less than released voltage +VDET, when the VDD pin voltage becomes
to 1 V or more, "L" output of DOUT is determined. In case of the SENSE pin voltage is equal or more than the
released voltage +VDET, when the VDD pin voltage becomes to 1 V or more, "H" output of DOUT is determined.
If the turn on speed of the supply voltage of the VDD pin up to 1 V is slower than the1 V/s, connect 0.001 µF
or more capacitor to CD pin, otherwise, powering-up of the VDD pin with the SENSE pin output voltage of
−VDET < VSENSE < +VDET may result in an unstable DOUT pin output, “H” or “L”, at the point where the VDD pin
voltage exceeds 1 V.
TIMING CHART
Supply Voltage
(VDD)
Minimum Operating VDDL
Voltage
Released Voltage +VDET
Detector Threshold -VDET
Detector Threshold
Hysteresis
Detector Threshold
Hysteresis
SENSE Pin Voltage
(VSENSE)
GND
Pull-up Voltage
Supply Voltage
(VDD)
Output Voltage
(VOUT)
GND
tRESET
tDELAY
R3118xxxxA
tRESET
tDELAY
R3118xxxxC
11
R3118x
No. EA-242-211026
OUTPUT DELAY OPERATION
Released Voltage (+VDET)
SENSE pin voltage
Detector Threshold (-VDET)
Time t
GND
CD pin Threshold voltage
(VTCD)
CD pin voltage
Time t
GND
DOUT pin voltage
Time t
Release Output Delay Time
(tDELAY)
GND
Detect Output Delay Time
(tRESET)
Output Delay Operation Diagram
A higher voltage than the released voltage is forced to the SENSE pin, charge to the capacitor connected to
CD pin is started, then the CD pin voltage increases. Until CD pin voltage reaches to CD pin threshold voltage,
the output of DOUT pin voltage keeps "L", then when CD pin voltage is higher than CD pin threshold voltage,
the DOUT pin voltage changes from "L" to "H". The released output delay time means the time interval from
when the released voltage threshold or more voltage level is forced to SENSE pin to when DOUT voltage
changes from "L" to "H".
When the voltage of DOUT pin reverses from "L" to "H", the discharge of the external capacitor connected to
CD pin starts. Therefore, the time interval from when the voltage lower than the detector threshold is forced to
SENSE pin, to when the output voltage reverses from "H" to "L", or detector output delay time is constant and
independent from the external capacitance value. However, after the DOUT pin voltage reverses from "L" to
"H", if a voltage lower than the detector threshold is forced to SENSE pin before the capacitor connected to
CD pin is discharged, delay time will increase. The time interval (tDIS) from when the capacitor connected to
CD pin is discharged completely to when the capacitor is charged to a certain CD pin voltage (described as
VCD herein) can be calculated by power supply voltage (VDD), external capacitance (CD), on resistance of the
CD pin discharge transistor (RDIS) as in the next formula:
tDIS = -RDIS × CD × ln(VCD / (VDD × 0.45))
RELEASED OUTPUT DELAY TIME
The release output delay time (tDELAY) can be calculated as in the next formula with an external capacitance
value (CD):
tDELAY(s) = 4.545 × 106 × CD(F)
During the released delay operation, only a small current will charge the external capacitor connected to CD
pin. If the leakage current between CD pin and GND is large, the released delay time may increase or the
detector may not be released. And, if the VDD pin voltage varies, the released output delay time will be also
shift.
12
R3118x
No. EA-242-211026
APPLICATION INFORMATION
TYPICAL APPLICATION
R3118xxxxA (Nch. Open-drain Output) CPU Reset Circuit
VDD
470kΩ R
VS
VDD
VDD
SENSE
R3118xxxxA
CPU
RESET
DOUT
GND
CD
GND
When using a shared input voltage between R3118x and CPU
VDD1
VDD2
470kΩ R
VS
VDD
SENSE
R3118xxxxA
DOUT
GND
CD
VDD
CPU
RESET
GND
When using different input voltages between R3118x and CPU
R3118xxxxC (CMOS Output) CPU Reset Circuit
VDD
VS
VDD
SENSE
R3118xxxxC
DOUT
GND
CD
VDD
CPU
RESET
GND
13
R3118x
No. EA-242-211026
TYPICAL CHARACTERISTICS
Note: Typical Characteristics are intended to be used as reference data; they are not guaranteed.
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
R3118xxxxA/C (VSENSE = 6 V)
Topt=-40°C
Topt=25°C
Topt=85°C
0
1
2
Supply Current ISS (μA)
Supply Current ISS (μA)
1) Supply Current vs. Supply Voltage
R3118xxxxA/C (VSENSE = 0 V)
3
4
5
Supply Voltage VDD (V)
6
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
Topt=-40°C
Topt=25°C
Topt=85°C
0
2
4
6
Supply Voltage VDD (V)
2) Detector Threshold vs. Temperature
R3118x06xA/C (VDD = 5.3 V)
R3118x27xA/C (VDD = 5.3 V)
-VDET
0.636
Detector Threshold VDET (V)
Detector Threshold VDET (V)
0.645
+VDET
0.627
0.618
0.609
0.600
0.591
-50
-25
0
25
50
75
100
2.903
-VDET
+VDET
2.862
2.822
2.781
2.741
2.700
2.660
-50
-25
0
25
50
75
100
Temperature Topt (°C)
Temperature Topt (°C)
Detector Threshold VDET (V)
R3118x50xA/C (VDD = 5.3 V)
5.375
5.300
5.225
-VDET
5.150
+VDET
5.075
5.000
4.925
-50
-25
0
25
50
75
100
Temperature Topt (°C)
14
R3118x
No. EA-242-211026
3) Detector Threshold vs. Supply Voltage
R3118x06xA/C
R3118x27xA/C
Detector Threshold VDET (V)
Detector Threshold VDET (V)
0.609
Topt=-40°C
0.606
Topt=25°C
Topt=85°C
0.603
0.600
0.597
0.594
0.591
1
2
3
4
5
6
5
6
2.741
Topt=-40°C
2.727
Topt=25°C
2.714
Topt=85°C
2.700
2.687
2.673
2.660
1
3
5
Supply Voltage VDD (V)
Supply Voltage VDD (V)
R3118x50xA/C
Detector Threshold VDET (V)
5.075
Topt=-40°C
5.050
Topt=25°C
Topt=85°C
5.025
5.000
4.975
4.950
4.925
1
2
3
4
Supply Voltage VDD (V)
4) Hysteresis vs. Temperature
R3118x27xA/C (VDD = 5.3 V)
0.042
0.039
0.036
0.033
0.030
0.027
0.024
0.021
-50
-25
0
25
50
75
Temperature Topt (°C)
100
Detector Threshold Hysteresis VHYS
(V)
Detector Threshold
Hysteresis VHYS (V)
R3118x06xA/C (VDD = 5.3 V)
0.045
0.203
0.190
0.176
0.163
0.149
0.136
0.122
0.109
0.095
-50
-25
0
25
50
75
100
Temperature Topt (°C)
15
R3118x
No. EA-242-211026
Detector Threshold Hysteresis
VHYS (V)
R3118x50xA/C (VDD = 5.3 V)
0.375
0.350
0.325
0.300
0.275
0.250
0.225
0.200
0.175
-50
-25
0
25
50
75
100
Temperature Topt (°C)
5) Hysteresis vs. Supply Voltage
R3118x27xA/C
Detector Threshold
Hysteresis VHYS (V)
Detector Threshold
Hysteresis VHYS (V)
R3118x06xA/C
0.045
Topt=-40°C
0.042
Topt=25°C
0.039
Topt=85°C
0.036
0.033
0.030
0.027
0.024
0.021
0.203
Topt=-40°C
0.189
Topt=25°C
0.176
Topt=85°C
0.162
0.149
0.135
0.122
0.108
1
2
3
4
5
6
0.095
1
2
3
4
5
6
Supply Voltage VDD (V)
Supply Voltage VDD (V)
R3118x50xA/C
Detector Threshold
Hysteresis VHYS (V)
0.375
Topt=-40°C
0.35
Topt=25°C
0.325
Topt=85°C
0.3
0.275
0.25
0.225
0.2
0.175
1
2
3
4
5
6
Supply Voltage VDD (V)
16
R3118x
No. EA-242-211026
6) Output Voltage vs. SENSE Voltage (DOUT pin is pulled up to VDD pin via 470 kΩ)
R3118x06xA/C
R3118x27xA/C
VDD=1V
6
VDD=3V
6
Output Voltage VDOUT (V)
Output Voltage VDOUT (V)
VDD=5V
5
4
3
2
1
0
0
1
2
3
4
5
6
VDD=1V
VDD=3V
5
VDD=5V
4
3
2
1
0
0
1
SENSE Voltage VSENSE (V)
2
3
4
5
6
SENSE Voltage VSENSE (V)
R3118x50xA/C
Output Voltage VDOUT (V)
6
VDD=1V
VDD=3V
VDD=5V
5
4
3
2
1
0
0
1
2
3
4
5
6
SENSE Voltage VSENSE (V)
7) Nch. Driver Output Current vs. Supply Voltage
8）Nch. Driver Output Current vs. Output Voltage
R3118xxxxA/C (VDOUT = 0.4 V)
Topt=-40°C
8
Topt=25°C
7
Topt=85°C
6
5
4
3
2
1
0
1
2
3
4
Supply Voltage [V]
5
6
Nch Driver Output Current
IDOUT (mA)
9
Nch Driver Output Current
[mA]
R3118xxxxA/C
20
18
VDD=1V
16
VDD=3V
14
VDD=5V
12
10
8
6
4
2
0
0
1
2
Output Voltage VDOUT (V)
3
17
R3118x
No. EA-242-211026
9) Pch. Driver Output Current vs. Supply Voltage
10) Pch Driver Output current vs. Output voltage
0
R3118xxxxA/C
Pch Driver Output Current
IDOUT (mA)
Pch Driver Output Current
IDOUT (μA)
R3118xxxxA/C (VDOUT = VDD - 0.1 V)
Topt=-40°C
Topt=25°C
-20
Topt=85°C
-40
-60
-80
-100
1
2
3
4
5
6
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
-1.2
-1.4
-1.6
VDD=1V
-1.8
-2.0
VDD=3V
0
1
2
3
VDD=5V
4
5
Output Voltage VDOUT (V)
Supply Voltage VDD (V)
11) CD pin Discharge Tr. On Resistance vs. Supply Voltage
R3118xxxxA/C (VCD = 0.4 V)
CD Pin Discharge Tr. On
Resistor RDIS (k ohm)
6
Topt=-40°C
5
Topt=25°C
4
Topt=85°C
3
2
1
0
1
2
3
4
5
6
Supply Voltage VDD (V)
12) CD pin Discharge Transistor On Resistance vs. CD pin Voltage
R3118xxxxA/C
CD Pin Discharge Tr On
Resistor RDIS (k ohm)
6
VDD=1V
5
VDD=3V
VDD=5V
4
3
2
1
0
0.0
1.0
2.0
CD Pin Voltage VCD (V)
18
R3118x
No. EA-242-211026
13) Release Output Delay Time vs. Temperature
14) Release Output Delay Time vs. Supply Voltage
R3118xxxxA/C (VDD = 4 V, CD = 0.022 µF)
135
125
115
105
95
85
75
65
R3118xxxxA/C (CD = 0.022 µF)
Release Delay Time tdelay
(ms)
Release Delay Time
tdelay (ms)
145
-50
-25
0
25
50
75
100
Temperature Topt (°C)
145
Topt=-40°C
Topt=25°C
Topt=85°C
135
125
115
105
95
85
75
65
1
3
5
Supply Voltage VDD (V)
15) Detect Output Delay Time/Release Output Delay Time vs. CD pin External Capacitance
R3118xxxxA/C (VDD = 4 V)
Release / Detect
Delay Time tdelay / treset (ms)
1000
100
10
1
tdelay
treset
0.1
0.01
0.0001
0.0010
0.0100
0.1000
External Capacitance CD (μF)
19
R3118x
No. EA-242-211026
16) Detect Output Delay time vs. Over-drive Voltage
100
90
80
70
60
50
40
30
20
10
0
R3118x50xA/C (CD = none)
VDD=1V
VDD=6V
10
100
1000
Detect Delay Time treset (μs)
Detect Delay Time treset (μs)
R3118x06xA/C (CD = none)
140
VDD=1V
120
VDD=6V
100
80
60
40
20
0
10
100
1000
Over Drive Voltage VOD (mV)
Over Drive Voltage VOD (mV)
SENSE pin Voltage
VSENSE
Over-drive Voltage
(VOD)
Detector Threshold
(-VDET)
Time t
DOUT pin Voltage
VDOUT
Detect Output
DelayTime (tRESET)
Time t
Note: The pulse shorter than the detect output delay time cannot be detected, and "L" does not output from
DOUT pin.
20
R3118x
No. EA-242-211026
17) Release Output Delay time vs. Over-drive Voltage
500
450
400
350
300
250
200
150
100
50
0
R3118x50xA/C (CD = none)
VDD=1V
VDD=6V
10
100
1000
Release Delay Time tdelay (μs)
Release Delay Time tdelay (μs)
R3118x06xA/C (CD = none)
3500
VDD=1V
3000
VDD=6V
2500
2000
1500
1000
500
0
10
100
1000
Over Drive Voltage VOD (mV)
Over Drive Voltage VOD (mV)
SENSE pin Voltage
VSENSE
Over-drive Voltage
(VOD)
Released Voltage
(+VDET)
Time t
DOUT pin Voltage
VDOUT
Release Output
Delay Time (tDELAY)
Time t
Notes:
• If the pulse is shorter than the output release delay time, the R3118x cannot be released and "H" does not
output from DOUT pin.
• If the attachment capacitor for CD pin for setting a delay time is too small and the difference between the
released voltage threshold and the actual released voltage is too small or the slope for rising voltage of the
SENSE pin is too slow, the output delay time tolerance will be worse.
Ex. Attachment capacitor = 0.0001 µF, Released voltage threshold = 4.725 V, Actual released voltage =
4.75 V. In this case, the calculated delay time = 0.4545 ms, however, over-drive voltage is only 25 mV.
Therefore, the actual delay time will be approximately 2.4545 ms. If the attachment capacitor = 0.001 µF
and other conditions are same as above, the calculated delay time = 4.545 ms, and the actual delay time
will be approximately 6.545 ms. If the attachment capacitor = 0.01 µF and other conditions are same as
above, the calculated delay time = 45.45 ms, and the actual delay time will be approximately 47.45 ms.
21
POWER DISSIPATION
DFN(PLP)1212-6
Ver. A
The power dissipation of the package is dependent on PCB material, layout, and environmental conditions.
The following measurement conditions are based on JEDEC STD. 51-7.
Measurement Conditions
Item
Measurement Conditions
Environment
Mounting on Board (Wind Velocity = 0 m/s)
Board Material
Glass Cloth Epoxy Plastic (Four-Layer Board)
Board Dimensions
76.2 mm × 114.3 mm × 0.8 mm
Copper Ratio
Outer Layer (First Layer): Less than 95% of 50 mm Square
Inner Layers (Second and Third Layers): Approx. 100% of 50 mm Square
Outer Layer (Fourth Layer): Approx. 100% of 50 mm Square
Through-holes
0.2 mm × 14 pcs
Measurement Result
(Ta = 25°C, Tjmax = 125°C)
Item
Measurement Result
Power Dissipation
450 mW
Thermal Resistance (ja)
ja = 218°C/W
Thermal Characterization Parameter (ψjt)
ψjt = 105°C/W
ja: Junction-to-Ambient Thermal Resistance
ψjt: Junction-to-Top Thermal Characterization Parameter
600
Power Dissipation (mW)
500
450
400
300
200
100
0
0
25
50
75 85
Ambient Temperature (°C)
100
Power Dissipation vs. Ambient Temperature
125
Measurement Board Pattern
i
PACKAGE DIMENSIONS
DFN(PLP)1212-6
Ver. B
DFN(PLP)1212-6 Package Dimensions
i
POWER DISSIPATION
SC-88A
Ver. B
The power dissipation of the package is dependent on PCB material, layout, and environmental conditions.
The following conditions are used in this measurement.
Measurement Conditions
Item
Standard Test Land Pattern
Environment
Mounting on Board (Wind Velocity = 0 m/s)
Board Material
Glass Cloth Epoxy Plastic (Double-Sided Board)
Board Dimensions
40 mm × 40 mm × 1.6 mm
Top Side: Approx. 50%
Copper Ratio
Bottom Side: Approx. 50%
Through-holes
φ 0.5 mm × 44 pcs
Measurement Result
(Ta = 25°C, Tjmax = 125°C)
Item
Standard Test Land Pattern
Power Dissipation
380 mW
Thermal Resistance (θja)
θja = 263°C/W
Thermal Characterization Parameter (ψjt)
ψjt = 75°C/W
θja: Junction-to-Ambient Thermal Resistance
ψjt: Junction-to-Top Thermal Characterization Parameter
500
40
380
300
200
40
Power Dissipation (mW)
400
100
0
0
25
50
75 85
100
125
Ambient Temperature (°C)
Power Dissipation vs. Ambient Temperature
Measurement Board Pattern
i
PACKAGE DIMENSIONS
SC-88A
Ver. A
SC-88A Package Dimensions
i
POWER DISSIPATION
SOT-23-5
Ver. A
The power dissipation of the package is dependent on PCB material, layout, and environmental conditions.
The following measurement conditions are based on JEDEC STD. 51-7.
Measurement Conditions
Item
Measurement Conditions
Environment
Mounting on Board (Wind Velocity = 0 m/s)
Board Material
Glass Cloth Epoxy Plastic (Four-Layer Board)
Board Dimensions
76.2 mm × 114.3 mm × 0.8 mm
Copper Ratio
Outer Layer (First Layer): Less than 95% of 50 mm Square
Inner Layers (Second and Third Layers): Approx. 100% of 50 mm Square
Outer Layer (Fourth Layer): Approx. 100% of 50 mm Square
Through-holes
0.3 mm × 7 pcs
Measurement Result
Item
(Ta = 25°C, Tjmax = 125°C)
Measurement Result
Power Dissipation
660 mW
Thermal Resistance (ja)
ja = 150°C/W
Thermal Characterization Parameter (ψjt)
ψjt = 51°C/W
ja: Junction-to-Ambient Thermal Resistance
ψjt: Junction-to-Top Thermal Characterization Parameter
Power Dissipation vs. Ambient Temperature
Measurement Board Pattern
i
SOT-23-5
PACKAGE DIMENSIONS
Ver. A
2.9±0.2
1.1±0.1
1.9±0.2
0.8±0.1
(0.95)
4
1
2
0～0.1
0.2min.
+0.2
1.6-0.1
5
2.8±0.3
(0.95)
3
0.4±0.1
+0.1
0.15-0.05
SOT-23-5 Package Dimensions
i
1. The products and the product specifications described in this document are subject to change or discontinuation of
production without notice for reasons such as improvement. Therefore, before deciding to use the products, please
refer to Ricoh sales representatives for the latest information thereon.
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4. The technical information described in this document shows typical characteristics of and example application circuits
for the products. The release of such information is not to be construed as a warranty of or a grant of license under
Ricoh's or any third party's intellectual property rights or any other rights.
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damage arising from misuse or inappropriate use of the products.
7. Anti-radiation design is not implemented in the products described in this document.
8. The X-ray exposure can influence functions and characteristics of the products. Confirm the product functions and
characteristics in the evaluation stage.
9. WLCSP products should be used in light shielded environments. The light exposure can influence functions and
characteristics of the products under operation or storage.
10. There can be variation in the marking when different AOI (Automated Optical Inspection) equipment is used. In the
case of recognizing the marking characteristic with AOI, please contact Ricoh sales or our distributor before attempting
to use AOI.
11. Please contact Ricoh sales representatives should you have any questions or comments concerning the products or
the technical information.
Halogen Free
Ricoh is committed to reducing the environmental loading materials in electrical devices
with a view to contributing to the protection of human health and the environment.
Ricoh has been providing RoHS compliant products since April 1, 2006 and Halogen-free products since
April 1, 2012.
Official website
https://www.n-redc.co.jp/en/
Contact us
https://www.n-redc.co.jp/en/buy/
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