RS5C372A-E2-F

RS5C372A/B I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC NO.EA-044-160219 OUTLINE The RS5C372A is a CMOS type real-time clock which is connected to the CPU via 2-wires and capable of serial transmission of clock and calendar data to the CPU. The RS5C372A can generate various periodic interrupt clock pulses lasting for long period (one month), and alarm interrupt can be made by days of the week, hours, and minutes by two incorporated systems. Since an oscillation circuit is driven at a constant voltage, it undergoes fluctuations of few voltage and consequently offers low current consumption (Typ. 0.5A at 3V). It also provides an oscillator halt sensing function applicable for data validation at power-on and other occasions and 32-kHz clock output for an external micro computer. (Nch. open drain output) The product also incorporates a time trimming circuit that adjusts the clock with higher precision by adjusting any errors in crystal oscillator frequencies based on signals from the CPU. The crystal oscillator may be selected from 32.768kHz or 32.000kHz types. Integrated into an ultra compact and ultra thin 8 pin SSOP package, the RS5C372A is the optimum choice for equipment requiring small sized and low power consuming products. FEATURES                 Time keeping voltage: 1.3V to 6.0V Lowest supply current: 0.5A Typ. (0.9A Max.) : 3V (25C) (1.0A Max.) : 3V (40 to 85C) Connected to the CPU via only 2wires (I2C bus Interface, Max.400kHz, address 7bit) A clock counter (counting hours, minutes, and seconds) and a calendar counter (counting leap years, years, months, and days of the week) in BCD codes Interrupt to the CPU (period of one month to one second, interrupt flag, interrupt halt function)( INTRA , INTRB ) Two systems of alarm functions (days of the week, hours, and minutes) ( INTRA , INTRB ) Oscillation halt sensing to judge internal data validity Clock output of 32.768kHz (32.000kHz) (output controllable via a register)  (Nch. open drain output) Second digit adjustment by 30 seconds Automatic leap year recognition up to the year 2099 12-hour or 24-hour time display selectable Oscillation stabilizing capacity (CG, CD) incorporated High precision time trimming circuit Oscillator of 32.768kHz or 32.000kHz may be used CMOS logic Package: 8pin SSOP 1 RS5C372A BLOCK DIAGRAM COMPARATOR_A ALARM_A REGISTER (WEEK,MIN,HOUR) COMPARATOR_B ALARM_B REGISTER (WEEK,MIN,HOUR) 32kHz OUTPUT CONTROL OSCIN OSC OSCOUT DIVIDER CORREC -TION DIV OSC DETECT TIME COUNTER (SEC,MIN,HOUR,WEEK,DAY,MONTH,YEAR) ADDRESS DECODER VSS ADDRESS REGISTER INTRA SCL I/O CONTROL INTRB INTERRUPT CONTROL SHIFT REGISTER SELECTION GUIDE Part Number is designated as follows: R S 5C372A - E2 - F Part Number    R a 5C372A - bb - c Code a bb c 2 VDD Description Designation of the package. S: SSOP8 Designation of the taping type. Only E2 is available. Designation of the lead plating. F: Lead free plating FB: Sn-Bi plating SDA RS5C372A APPLICATIONS       Communication devices (multi function phone, portable phone, PHS or pager) OA devices (fax, portable fax) Computer (desk-top and mobile PC, portable word-processor, PDA, electric note or video game) AV components (portable audio unit, video camera,camera, digital camera or remote controller) Home appliances (rice cooker, electric oven) Other(car navigation system,multi-function watch) PIN CONFIGURATION  8pin SSOP INTRB 1 8 VDD SCL 2 7 OSCIN SDA 3 6 OSCOUT VSS 4 5 INTRA 3 RS5C372A PIN DESCRIPTIONS Pin No. Symbol Name Description 2 SCL Serial Clock Line 3 SDA Serial Data Line 5 INTRA Interrupt Output A 1 INTRB Interrupt Output B 7 6 OSCIN OSCOUT 8 4 VDD VSS Oscillator Circuit Input/Output Positive Power Supply Input Negative Power Supply Input This pin is used to input shift clock pulses to synchronize data input/output to and from the SDA pin with this clock. Up to 6V beyond VDD may be input. This pin inputs and outputs written or read data in synchronization with shift clock pulses from the SCL pin. Up to 6V beyond VDD may be input. This pin functions as an Nch open drain output. This pin outputs periodic interrupt pulses and alarm interrupt (Alarm_A, Alarm_B) to the CPU. This pin is off when power is activated from 0V. This pin functions as an Nch open drain output. This pin outputs 32.768kHz clock pulses (when 32.768kHz crystal is used), periodic interrupt pulses to the CPU or alarm interrupt (Alarm_B). It outputs 32.768kHz when power source is activated from 0V. This pin functions as an Nch open drain output. These pins configure an oscillator circuit by connecting a 32.768kHz or 32.000kHz crystal oscillator between the OSCIN-OSCOUT pins. (Any other oscillator circuit components are built into the RS5C372A.) The VDD pin is connected to the positive power supply and VSS to the ground. ABSOLUTE MAXIMUM RATINGS (Vss0V) Symbol VDD VI Item Conditions Ratinge Unit 0.3 to 7.0 V SCL, SDA 0.3 to 7.0 V Supply Voltage Input Voltag VO1 Output Voltage 1 SDA 0.3 to 7.0 VO2 Output Voltage 2 INTRA , INTRB 0.3 to 12 PD Power Dissipation Topt25C 300 mW V Topt Operating Temperature 40 to 85 C Tstg Storage Temperature 55 to 125 C ABSOLUTE MAXIMUM RATINGS Absolute Maximum ratings are threshold limit values that must not be exceeded even for an instant under any conditions. Moreover, such values for any two items must not be reached simultaneously. Operation above these absolute maximum ratings may cause degradation or permanent damage to the device. These are stress ratings only and do not necessarily imply functional operation below these limits. 4 RS5C372A RECOMMENDED OPERATING CONDITIONS (Vss0V,Topt40 to 85C) Symbol Item Conditions Min. Typ. Max. Unit VDD Supply Voltage 1.7 6.0 V VCLK Timekeeping Voltage 1.3 6.0 V FXT Oscillation Frequency 32.768 or 32.000 kHz VPUP1 Pull-up Voltage 1 SCL, SDA 6.0 V VPUP2 Pull-up Voltage 2 INTRA , INTRB 10.0 V DC CHARACTERISTICS Unless otherwise specified: Vss0V, VDD3V, Topt40 to 85C, Oscillation frequency32.768kHz, or 32.000kHz(R130k) Symbol Item Pin name Conditions Min. Typ. Max. Unit VIH “H” Input Voltage SCL, SDA 0.8VDD 6.0 V VIL “L” Input Voltage SCL, SDA 0.3 0.2VDD V IOL1 IOL2 Output Current INTRA , INTRB VOL10.4V 1 mA SDA VOL20.6V 6 mA IILK Input Leakage Current SCL VI6V or Vss VDD6V 1 1 A IOZ Output Off State Leakage Current SDA, INTRA , INTRB VO6V or Vss VDD6V 1 1 A VDD VDD3V Topt25C SCL, SDA3V OutputOPEN1 0.9 A VDD VDD3V Topt40 to 85C SCL, SDA3V OutputOPEN1 1.0 A VDD VDD6V SCL, SDA6V OutputOPEN1 2.0 A IDD1 IDD2 Standby Current IDD3 CG CD Internal Oscillation Capacitance 1 Internal Oscillation Capacitance 2 0.5 0.8 OSCIN 10 pF OSCOUT 10 pF 1) The mode outputs no clock pulses when output is open (output off state). For consumption current (output: no load) when 32kHz pulses are output from INTRB , see “USAGES, 6. Typical Characteristic Measurements” 5 RS5C372A AC CHARACTERISTICS  2 VDD1.7V (supports standard mode I C bus) Unless otherwise specified : VSS0V, Topt=40 to 85, Crystal=32.768kHz or 32.000kHz, Input and Output Conditions:VIH=0.8VDD,VIL=0.2VDD,VOL=0.2VDD,CL=50pF Symbol Item Conditions Min. Typ. 0 Max. Unit 100 kHz fSCL SCL Clock Frequency tLOW SCL Clock “L” Time 4.7 s tHIGH SCL Clock “H” Time 4.0 s tHD ; STA Start Condition Hold Time 4.0 s tSU ; STO Stop Condition Setup Time 4.0 s tSU ; STA Start Condition Setup Time 4.7 s tSU ; DAT Data Setup Time 250 ns tHDH ; DAT “H”Data Hold Time 0 ns tHDL ; DAT “L”Data Hold Time VDD2.0V 35 ns tHDL ; DAT “L”Data Hold Time VDD1.7V 150 ns tPL ; DAT SDA “L”Stable Time After Falling of SCL 2.0 s tPZ ; DAT SDA off Stable Time After Falling of SCL 2.0 s tR Rising Time of SCL and SDA (Input) 1000 ns tF Falling Time of SCL and SDA (Input) 300 ns tSP Spike Width that can be Removed with Input Filter 50 ns S Sr P SCL tLOW tHD;STA tHIGH tSP SDA(IN) tHD;STA tSU;DAT tHDH;DAT tHDL;DAT tSU;STA SDA(OUT) tPL;DAT S Start condition tPZ;DAT P Stop condition Sr Repeated start condition ) For detailed information refer to “USAGES, 1.2 Transmission System of I2C bus.” 6 tSU;STO RS5C372A  2 VDD2.5V (supports fast mode I C bus) Unless otherwise specified : VSS0V, Topt=40 to 85, Crystal=32.768kHz or 32.000kHz, Input and Output Conditions:VIH=0.8VDD,VIL=0.2VDD,VOL=0.2VDD,CL=50pF Symbol Item Conditions Min. Typ. 0 Max. Unit 400 kHz fSCL SCL Clock Frequency tLOW SCL Clock “L” Time 1.3 s tHIGH SCL Clock “H” Time 0.6 s tHD ; STA Start Condition Hold Time 0.6 s tSU ; STO Stop Condition Setup Time 0.6 s tSU ; STA Start Condition Setup Time 0.6 s tSU ; DAT Data Setup Time 100 ns tHDH ; DAT “H”Data Hold Time 0 ns tHDL ; DAT “L”Data Hold Time 35 ns tPL ; DAT SDA “L” Stable Time After Falling of SCL 0.9 s tPZ ; DAT SDA off Stable Time After Falling of SCL 0.9 s tR Rising Time of SCL and SDA (Input) 300 ns tF Falling Time of SCL and SDA (Input) 300 ns tSP Spike Width that can be Removed with Input Filter 50 ns S Sr P SCL tLOW tHD;STA tHIGH tSP SDA(IN) tHD;STA tSU;DAT tHDH;DAT tHDL;DAT tSU;STA tSU;STO SDA(OUT) tPL;DAT S Start condition tPZ;DAT P Stop condition Sr Repeated start condition ) For detailed information refer to “USAGES, 1.2 Transmission System of I2C bus.” 7 RS5C372B I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC OUTLINE The RS5C372B is a CMOS type real-time clock which is connected to the CPU via 2-wires and capable of serial transmission of clock and calendar data to the CPU. The RS5C372B can generate various periodic interrupt clock pulses lasting for long period (one month), and alarm interrupt can be made by days of the week, hours, and minutes by two incorporated systems. Since an oscillation circuit is driven at a constant voltage, it undergoes fluctuations of few voltage and consequently offers low current consumption (Typ. 0.5A at 3V). It also provides an oscillator halt sensing function applicable for data validation at power-on and other occasions and 32-kHz clock output for an external micro computer. (CMOS output) The product also incorporates a time trimming circuit that adjusts the clock with higher precision by adjusting any errors in crystal oscillator frequencies based on signals from the CPU. The crystal oscillator may be selected from 32.768kHz or 32.000kHz types. Integrated into an ultra compact and ultra thin 8 pin SSOP package, the RS5C372B is the optimum choice for equipment requiring small sized and low power consuming products. FEATURES                 Time keeping voltage: 1.45V to 6.0V Lowest supply current: 0.5A Typ. .................. (0.9A Max.) : 3V (25C) .......................................................................... (1.0A Max.) : 3V (40 to 85C) Connected to the CPU via only 2-wires (I2C bus Interface, Max.400kHz, address 7bit) A clock counter (counting hours, minutes, and seconds) and a calendar counter (counting leap years, years, months, days, and days of the week) in BCD codes Interrupt to the CPU (period of one month to one second, interrupt flag, interrupt halt function) ( INTR ) Two systems of alarm functions (days of the week, hours, and minutes) ( INTR ) Oscillation halt sensing to judge internal data validity Clock output of 32.768kHz (32.000kHz) (output controllable via a register) (CMOS output) Second digit adjustment by 30 seconds Automatic leap year recognition up to the year 2099 12-hour or 24-hour time display selectable Oscillation stabilizing capacity (CG, CD) incorporated High precision time trimming circuit Oscillator of 32.768kHz or 32.000kHz may be used CMOS logic Package: 8pin SSOP 7 RS5C372B BLOCK DIAGRAM 32kHz OUTPUT CONTROL 32KOUT OSCIN OSC OSCOUT DIVIDER CORREC -TION COMPARATOR_A ALARM_A REGISTER (WEEK,MIN,HOUR) COMPARATOR_B ALARM_B REGISTER (WEEK,MIN,HOUR) DIV TIME COUNTER (SEC,MIN,HOUR,WEEK,DAY,MONTH,YEAR) ADDRESS DECODER OSC DETECT VDD VSS ADDRESS REGISTER SCL I/O CONTROL INTR INTERRUPT CONTROL SHIFT REGISTER SELECTION GUIDE Part Number is designated as follows: R S 5C372B - E2 - F Part Number    R a 5C372B - bb - c Code a bb c 8 Description Designation of the package. S: SSOP8 Designation of the taping type. Only E2 is available. Designation of the lead plating. F: Lead free plating FB: Sn-Bi plating SDA RS5C372B APPLICATIONS       Communication devices (multi function phone, portable phone, PHS or pager) OA devices (fax, portable fax) Computer (desk-top and mobile PC, portable word-processor, PDA, electric note or video game) AV components (portable audio unit, video camera,camera, digital camera or remote controller) Home appliances (rice cooker, electric oven) Other(car navigation system,multi-function watch) PIN CONFIGURATION  8pin SSOP 32KOUT 1 8 VDD SCL 2 7 OSCIN SDA 3 6 OSCOUT VSS 4 5 INTR 9 RS5C372B PIN DESCRIPTIONS Pin No. Symbol Name Description 2 SCL Serial Clock Line 3 SDA Serial Data Line 5 INTR Interrupt Output 1 32KOUT 32-kHz Clock Output 7 6 OSCIN OSCOUT Oscillator Circuit Input/Output 8 4 VDD VSS Positive Power Supply Input Negative Power Supply Input This pin is used to input shift clock pulses to synchronize data input/output to and from the SDA pin with this clock. Up to 6V beyond VDD may be input. This pin inputs and outputs written or read data in synchronization with shift clock pulses from the SCL pin. Up to 6V beyond VDD may be input. This pin functions as an Nch open drain output. This pin outputs periodic interrupt pulses and alarm interrupt (Alarm_A, Alarm_B) to the CPU. This pin is off when power is activated from 0V. This pin functions as an Nch open drain output. The 32KOUT pin is used to output 32.768kHz clock pulses(when 32.768kHz crystal is used).Enabled at power-on from 0volts. CMOS output. The RS5C372B can disable 32-kHz clock output in response to a command from the host computer. These pins configure an oscillator circuit by connecting a 32.768kHz or 32.000kHz crystal oscillator between the OSCIN -OSCOUT pins. (Any other oscillator circuit components are built into the RS5C372A.) The VDD pin is connected to the positive power supply and VSS to the ground. ABSOLUTE MAXIMUM RATINGS (VSS0V) Symbol VDD VI VO PD Item Conditions Ratinge Unit 0.3 to 7.0 V SCL, SDA 0.3 to 7.0 V Output Voltage 1 SDA 0.3 to 7.0 Output Voltage 2 INTR 0.3 to 12 Output Voltage 3 32KOUT 0.3 to VDD0.3 Power Dissipation Topt25C 300 mW Supply Voltage Input Voltag V Topt Operating Temperature 40 to 85 C Tstg Storage Temperature 55 to 125 C ABSOLUTE MAXIMUM RATINGS Absolute Maximum ratings are threshold limit values that must not be exceeded even for an instant under any conditions. Moreover, such values for any two items must not be reached simultaneously. Operation above these absolute maximum ratings may cause degradation or permanent damage to the device. These are stress ratings only and do not necessarily imply functional operation below these limits. 10 RS5C372B RECOMMENDED OPERATING CONDITIONS (Vss0V,Topt40 to 85C) Symbol Item Conditions Min. Typ. Max. Unit VDD Supply Voltage 2.0 6.0 V VCLK Timekeeping Voltage 1.45 6.0 V FXT Oscillation Frequency 32.768 or 32.000 kHz VPUP1 Pull-up Voltage 1 SCL, SDA 6.0 V VPUP2 Pull-up Voltage 2 INTR 10.0 V DC CHARACTERISTICS Unless otherwise specified: Vss0V, VDD3V, Topt40 to 85C, Oscillation frequency32.768kHz, or 32.000kHz(R130k) Symbol Item Pin name Conditions Min. Typ. Max. Unit VIH “H” Input Voltage SCL, SDA 0.8VDD 6.0 V VIL “L” Input Voltage SCL, SDA 0.3 0.2VDD V IOH “H” Output Current 32KOUT VOHVDD0.5V -0.5 mA INTR ,32KOUT VOL10.4V 1 mA SDA VOL20.6V 6 mA IOL1 “L” Output Current IOL2 IILK Input Leakage Current SCL VI6V or Vss VDD6V 1 1 A IOZ Output Off State Leakage Current SDA, INTR , 32KOUT VO6V or Vss VDD6V 1 1 A VDD VDD3V Topt25C SCL, SDA3V OutputOPEN 0.9 A VDD VDD3V Topt40 to 85C SCL, SDA3V OutputOPEN1 1.0 A VDD VDD6V SCL, SDA6V OutputOPEN1 2.0 A IDD1 IDD2 Standby Current IDD3 0.5 0.8 CG Internal Oscillation Capacitance 1 OSCIN 10 pF CD Internal Oscillation Capacitance 2 OSCOUT 10 pF 1) The mode outputs no clock pulses when output is open (output off state). For consumption current (output: no load) when 32kHz pulses are output from 32KOUT, see “USAGES, 6. Typical Characteristic Measurements” 11 RS5C372B AC CHARACTERISTICS  2 VDD2.0V (supports standard mode I C bus) Unless otherwise specified : VSS0V, Topt40 to 85, Crystal32.768kHz or 32.000kHz, Input and Output Conditions:VIH0.8VDD,VIL=0.2VDD,VOL=0.2VDD,CL=50pF Symbol Item Conditions Min. Typ. 0 Max. Unit 100 kHz fSCL SCL Clock Frequency tLOW SCL Clock “L” Time 4.7 s tHIGH SCL Clock “H” Time 4.0 s tHD ; STA Start Condition Hold Time 4.0 s tSU ; STO Stop Condition Setup Time 4.0 s tSU ; STA Start Condition Setup Time 4.7 s tSU ; DAT Data Setup Time 250 ns tHDH ; DAT “H”Data Hold Time 0 ns tHDL ; DAT “L”Data Hold Time 35 ns tHDL ; DAT SDA “L”Stable Time After Falling of SCL 2.0 s tPZ ; DAT SDA Off Stable Time After Falling of SCL 2.0 s tR Rising Time of SCL and SDA (Input) 1000 ns tF Falling Time of SCL and SDA (Input) 300 ns tSP Spike Width that can be Removed with Input Filter 50 ns S Sr P SCL tLOW tHD;STA tHIGH tSP SDA(IN) tHD;STA tSU;DAT tHDH;DAT tHDL;DAT tSU;STA SDA(OUT) tPL;DAT S Start condition tPZ;DAT P Stop condition Sr Repeated start condition ) For detailed information refer to “USAGES, 1.2 Transmission System of I2C bus.” 12 tSU;STO RS5C372B  2 VDD2.5V (supports fast mode I C bus) Unless otherwise specified : VSS0V, Topt40 to 85, Crystal32.768kHz or 32.000kHz, Input and Output Conditions:VIH0.8VDD,VIL=0.2VDD,VOL=0.2VDD,CL=50pF Symbol Item Conditions Min. Typ. 0 Max. Unit 400 kHz fSCL SCL Clock Frequency tLOW SCL Clock “L” Time 1.3 s tHIGH SCL Clock “H” Time 0.6 s tHD ; STA Start Condition Hold Time 0.6 s tSU ; STO Stop Condition Setup Time 0.6 s tSU ; STA Start Condition Setup Time 0.6 s tSU ; DAT Data Setup Time 100 ns tHDH ; DAT “H”Data Hold Time 0 ns tHDL ; DAT “L”Data Hold Time 35 ns tPL ; DAT SDA “L” Stable Time After Falling of SCL 0.9 s tPZ ; DAT SDA Off Stable Time After Falling of SCL 0.9 s tR Rising Time of SCL and SDA (Input) 300 ns tF Falling Time of SCL and SDA (Input) 300 ns tSP Spike Width that can be Removed with Input Filter 50 ns S Sr P SCL tLOW tHD;STA tHIGH tSP SDA(IN) tHD;STA tSU;DAT tHDH;DAT tHDL;DAT tSU;STA tSU;STO SDA(OUT) tPL;DAT S Start condition tPZ;DAT P Stop condition Sr Repeated start condition ) For detailed information refer to “USAGES, 1.2 Transmission System of I2C bus.” 13 RS5C372A/B GENERAL DESCRIPTION 1. Interfacing with the CPU The RS5C372A/B read/write data over I2C bus interface via 2-wires: SDA (data) and SCL (clock). Since the output of the I/O pin of SDA is open drain, data interfacing with a CPU with different supply voltage is possible by applying pull-up resistor on the circuit board. The maximum clock frequency of 400kHz of SCL enables data transfer in I2C bus fast mode. 2. Clock function The clock function of the RS5C372A/B allows write/read data from lower two digits of the dominical year to seconds to and from the CPU. When lower two digits of the dominical year are multiples of 4, the year is recognized as a leap year automatically. Up to the year 2099 leap years will be automatically recognized. ) The year 2000 is a leap year while the year 2100 is not. 3. Alarm function  RS5C372A The RS5C372A has an alarm function that outputs an interrupt signal from INTRA or INTRB output pins to the CPU when the day of the week, hour or minute corresponds to the setting. These two systems of alarms (Alarm_A, Alarm_B), each may output interrupt signal separately at a specified time. The alarm may be selectable between on and off for each day of the week, thus allowing outputting alarm everyday or on a specific day of the week. The Alarm_A is output from the INTRA pin while the Alarm_B is output from either the INTRA or the INTRB pins. Polling is possible separately for each alarm function.  RS5C372B The RS5C372B has an alarm function that outputs an interrupt signal from INTR output pin to the CPU when the day of the week, hour or minute corresponds to the setting. These two systems of alarms (Alarm_A, Alarm_B), each may output interrupt signal separately at a specified time. The alarm may be selectable between on and off for each day of the week, thus allowing outputting alarm everyday or on a specific day of the week. Polling is possible separately for each alarm function. 4. High precision time trimming function The RS5C372A/B have an internal oscillation circuit capacitance CG and CD so that an oscillation circuit may be configured simply by externally connecting a crystal. Either 32.768kHz or 32.000kHz may be selected as a crystal oscillator by setting the internal register appropriately. The RS5C372A/B incorporate a time trimming circuit that adjusts gain or loss of the clock from the CPU up to approx. 189ppm (194ppm when 32.000kHz crystal is used) by approximately 3ppm steps to correct discrepancy in oscillation frequency. (Error after correction: 1.5ppm: 25C) Thus by adjusting frequencies for each system,  Clock display is possible at much higher precision than conventional real-time clock while using a crystal with broader fluctuation in precision.  Even seasonal frequency fluctuation may be corrected by adjusting seasonal clock error.  For those systems that have temperature detection precision of clock function may be increased by correcting clock error according to temperature fluctuations. 14 RS5C372A/B 5. Oscillation halt sensing The oscillation halt sensing function uses a register to store oscillation halt information. This function may be used to determine if the RS5C372A/B supply power has been booted from 0V and if it has been backed up. This function is useful for determining if clock data is valid or invalid. 6. Periodic interrupt  RS5C372A The RS5C372A can output periodic interrupt pulses in addition to alarm function from the INTRA and INTRB pins. This frequency may be selected from 2Hz (every 0.5 seconds), 1Hz (every second), 1/60Hz (every minute), 1/3600Hz (every hour) and monthly (1st of month). Output wave form for periodic interrupt may be selected from regular pulse waveform (2Hz and 1Hz) and waveforms (every second, every minute, every hour and every month) that are appropriate for CPU level interrupt. Outputs may be selected either INTRA or INTRB . The RS5C372A has polling function that monitors pin status in the register.  RS5C372B The RS5C372B can output periodic interrupt pulses in addition to alarm function from the INTR pin. This frequency may be selected from 2Hz (every 0.5 seconds), 1Hz (every second), 1/60Hz (every minute), 1/3600Hz (every hour) and monthly (1st of month). Output wave form for periodic interrupt may be selected from regular pulse waveform (2Hz and 1Hz) and waveforms (every second, every minute, every hour and every month) that are appropriate for CPU level interrupt. Periodic Interrupt outputs from INTR . The RS5C372B has polling function that monitors pin status in the register. 7. 32-kHz clock output  RS5C372A The RS5C372A may output oscillation frequency from the INTRB pin. This clock output is set for output by default, which is set to on or off by setting the register.  RS5C372B The RS5C372B may output oscillation frequency from the 32KOUT pin. This clock output is set for output by default, which is set to on or off by setting the register. The 32KOUT pin is CMOS push-pull output terminal. Note The year-digit counter of RS5C372A/B counts only lower two digits of a year and no counter is supplied for upper two digits. When you are going to use this product in a system that must cope with “2000 year problem” which shall be corrected by software. 15 RS5C372A/B FUNCTIONAL DESCRIPTIONS 1. Allocation of Internal Addresses Internal address Data1 Contents A3 A2 A1 A0 D7 2 D6 D5 D4 D3 D2 D1 D0 S40 S20 S10 S8 S4 S2 S1 0 0 0 0 0 Second Counter 1 0 0 0 1 Minute Counter — M40 M20 M10 M8 M4 M2 M1 2 0 0 1 0 Hour Counter — — H20 P/ A H10 H8 H4 H2 H1 3 0 0 1 1 Day of the Week Counter — — — — — W4 W2 W1 4 0 1 0 0 Day Counter — — D20 D10 D8 D4 D2 D1 5 0 1 0 1 Month Counter — — — MO10 MO8 MO4 MO2 MO1 6 0 1 1 0 Year Counter Y80 Y40 Y20 Y10 Y8 Y4 Y2 Y1 7 0 1 1 1 Time Trimming Register XSL F6 F5 F4 F3 F2 F1 F0 8 1 0 0 0 Alarm_A (Minute Register) — AM40 AM20 AM10 AM8 AM4 AM2 AM1 9 1 0 0 1 Alarm_A (Hour Register) — — AH20 AP/ A AH10 AH8 AH4 AH2 AH1 A 1 0 1 0 Alarm_A (Day of the Week Register) — AW6 AW5 AW4 AW3 AW2 AW1 AW0 B 1 0 1 1 Alarm_B (Minute Register) — BM40 BM20 BM10 BM8 BM4 BM2 BM1 C 1 1 0 0 Alarm_B (Hour Register) — — BH20 BP/ A BH10 BH8 BH4 BH2 BH1 D 1 1 0 1 Alarm_B (Day of the Week Register) — BW6 BW5 BW4 BW3 BW2 BW1 BW0 E 1 1 1 0 Control Register 1 AALE BALE SL25 SL15 TEST CT2 CT1 CT0 CTFG AAFG BAFG — 3 F 1 1 1 1 Control Register 2 — — 12 /24 ADJ XSTP4 CLEN 1) All the listed data can be read and written except for ADJ/XSTP. 2) The “–” mark indicates data which can be read only and set to “0” when read. 3) The ADJ/XSTP bit of the control register2 is set to ADJ for write and XSTP for read operation. The XSTP bit is set to “0” by writing data into the control register2 for normal oscillation. 4) When XSTP is set to “1”, the XSL , F6 to F0, CT2 to CT0, AALE, BALE, SL2, SL1, CLEN and TEST bits are reset to “0”. 5) SL1 and SL2 apply to the RS5C372A. For the RS5C372B, these bits must be filled with “0”. 16 RS5C372A/B 2. Registers 2.1 Control Register 1 (at internal address Eh) D7 D6 D5 D4 D3 D2 D1 D0 AALE BALE SL22 SL12 TEST CT2 CT1 CT0 (For write operation) AALE BALE SL22 SL12 TEST CT2 CT1 CT0 (For read operation) 0 0 0 0 0 0 0 0 Default 1) The default means read value when XSTP bit is set to “1” by starting up from 0V, or supply voltage drop, etc. 2) SL1 and SL2 apply to the RS5C372A. For the RS5C372B, these bits must be filled with “0”. 2.1-1 AALE, BALE Alarm_A, Alarm_B enable bits AALE, BALE Description 0 Alarm_A (Alarm_B) Correspondence action invalid 1 Alarm_A (Alarm_B) Correspondence action valid (Default) 2.1-2 SL2, SL1 (RS5C372A only) Interrupt output select bits SL2 SL1 Description 0 0 Outputs Alarm_A, Alarm_B, INT to the INTRA . Outputs 32k clock pulses to the INTRB . (Default) 0 1 Outputs Alarm_A, INT to the INTRA . Outputs 32k clock pulses, Alarm_B to the INTRB . 1 0 Outputs Alarm_A, Alarm_B to the INTRA . Outputs 32k clock pulses, INT to the INTRB . 1 1 Outputs Alarm_A to the INTRA . Outputs 32k clock pulses, Alarm_B, INT to the INTRB . By setting SL1 and SL2 bits, two alarm pulses (Alarm_A and alarm_B), periodic interrupt output (INT), 32k clock pulses may be output to the INTRA or INTRB pins selectively. 2.1-3 TEST Test bit TEST Description 0 Ordinary operation mode 1 Test mode (Default) The test bit is used for IC test. Set the TEST bit to 0 in ordinary operation. 17 RS5C372A/B 2.1-4 CT2, CT1, CT0 Periodic interrupt cycle select bit CT2 CT1 CT0 Description Wave Form Mode Cycle and Falling Timing 0 0 0 — off (“H”) (Default) 0 0 1 — Fixed at “L” 0 1 0 Pulse Mode 2Hz (Duty50%) 0 1 1 Pulse Mode 1Hz (Duty50%) 1 0 0 Level Mode Every second (synchronized with second count up) 1 0 1 Level Mode Every minute (00 second of every minute) 1 1 0 Level Mode Every hour (00 minute(s) 00 second(s) of every hour) 1 1 1 Level Mode Every month (the 1st day 00 A.M. 00 minute(s) 00 second(s) of every month) 1) Pulse mode : Outputs 2Hz, 1Hz clock pulses. For relationships with counting up of seconds see the diagram below. ) When 32.000kHz crystal is used, In the 2Hz clock pulse mode, 0.496s clock pulses and 0.504s clock pulse are output alternately. Duty cycle for 1Hz clock pulses becomes 50.4% (“L” duration is 0.496s while “H” duration is 0.504s). 2) Level mode : One second, one minute or one month may be selected for an interrupt cycle. Counting up of seconds is matched with falling edge of interrupt output. 3) When the time trimming circuit is used, periodic interrupt cycle changes every 20 seconds. Pulse mode : “L” duration of output pulses may change in the maximum range of 3.784ms (3.875ms when 32.000kHz crystal is used.) For example, Duty will be 500.3784% (or 500.3875% when 32.000kHz crystal is used) at 1Hz. Level mode : Frequency in one second may change in the maximum range of 3.784ms (3.875ms when 32.000kHz crystal is used.) Relation Between Mode Waveforms and CTFG Bit  Pulse mode CTFG bit INTRA or INTRB pins (INTR pin for the RS5C372B) Approx. 92μs (32.768kHz crystal is used) Approx. 94μs (32.000kHz crystal is used) (Counting up of seconds) ) Since counting up of seconds and the falling edge has a time lag of approx. 92s (at 32.768kHz) (approx. 94s when 32.000kHz crystal is used), time with apparently approx. one second of delay from time of the real-time clock may be read when time is read in synchronization with the falling edge of output. 18 RS5C372A/B  Level mode CTFG bit INTRA or INTRB pins (INTR pin for the RS5C372B) Write 0 to CTFG (Second count-up) Write 0 to CTFG (Second count-up) (Second count-up) 2.2 Control Register 2 (at internal address Fh) D7 D6 D5 D4 D3 D2 D1 D0 — — 12 /24 ADJ CLEN CTFG AAFG BAFG (For write operation) 0 0 12 /24 XSTP CLEN CTFG AAFG BAFG (For read operation) 0 0 Undefined 1 0 0 0 0 Default )The default means read value when XSTP bit is set to “1” by starting up from 0V, or supply voltage drop, etc. 2.2-1 12 /24 12 /24-hour Time Display System Selection bit Description 12 /24 0 12-hour time display system (separate for mornings and afternoons) 1 24-hour time display system Being set this bit at “0” indicates 12-hour display system while “1” indicates 24-hour system. Time Display Digit Table 24-hour time display system 12-hour time display system 24-hour time display system 12-hour time display system ) 00 12 (AM12) 12 32 (PM12) 01 01 (AM 1) 13 21 (PM 1) 02 02 (AM 2) 14 22 (PM 2) 03 03 (AM 3) 15 23 (PM 3) 04 04 (AM 4) 16 24 (PM 4) 05 06 07 08 09 10 11 05 (AM 5) 06 (AM 6) 07 (AM 7) 08 (AM 8) 09 (AM 9) 10 (AM10) 11 (AM11) 17 18 19 20 21 22 23 25 (PM 5) 26 (PM 6) 27 (PM 7) 28 (PM 8) 29 (PM 9) 30 (PM10) 31 (PM11) Either the 12-hour or 24-hour time display system should be selected before writing time data. 19 RS5C372A/B 2.2-2 ADJ 30 Second Adjust Bit ADJ Description 0 Ordinary operation 1 Second digit adjustment  The following operations are performed by setting the second ADJ bit to 1.   1) For second digits ranging from “00” to “29” seconds: Time counters smaller than seconds are reset and second digits are set to “00”. 2) For second digits ranging from “30” to “59” seconds: Time counters smaller than seconds are reset and second digits are set to “00”. Minute digits are incremented by 1. Second digits are adjusted within 122s (within 125s: when 32.000kHz crystal is used) from writing operation to ADJ. The ADJ bit is for write only and allows no read operation. 2.2-3 XSTP Oscillator Halt Sensing Bit XSTP Description 0 Ordinary oscillation 1 Oscillator halt sensing (Default) The XSTP bit senses the oscillator halt.  When oscillation is halted after initial power on from 0V or drop in supply voltage the bit is set to “1” and which   remains to be “1” after it is restarted. This bit may be used to judge validity of clock and calendar count data after power on or supply voltage drop. When this bit is set to “1”, XSL , F6 to F0, CT2, CT1, CT0, AALE, BALE, SL2, SL1, CLEN and TEST bits are reset to “0”. INTRA ( INTR ) will stop output and the INTRB (32KOUT) will output 32kHz clock pulses. The XSTP bit is set to “0” by setting the control register 2 (address Fh) during ordinary oscillation. ) INTRA and INTRB for the RS5C372A, INTR and 32KOUT for the RS5C372B. 2.2-4 CLEN 32-kHz Clock Output Bit Description CLEN 0 32-kHz clock output enabled 1 32-kHz clock output disabled (Default) By setting this bit to “0”, output of clock pulses of the same frequency as the crystal oscillator is enabled. 20 RS5C372A/B 2.2-5 CTFG Periodic Interrupt Flag Bit CTFG Description 0 Periodic interrupt outputOFF (“H”) 1 Periodic interrupt outputON (“L”) (Default) This bit is set to “1” when periodic interrupt pulses are output ( INTRA or INTRB “L”) 1. The CTFG bit may be set only to “0” in the interrupt level mode. Setting this bit to “0” sets either the INTRA or the INTRB to OFF (“H”)2. When this bit is set to “1” nothing happens. 1) INTR “L” for the RS5C372B. 2) INTR OFF (“H”) for the RS5C372B. 2.2-6 AAFG, BAFG Alarm_A (Alarm_B) Flag Bit AAFG, BAFG Description 0 Unmatched alarm register with clock counter 1 Matched alarm register with clock counter (Default)  The alarm interruption is enabled only when the AALE, BALE bits are set to “1”. This bit turns to “1” when   matched time is sensed for each alarm. The AAFG, BAFG bit may be set only to “0”. Setting this bit to “0” sets either the INTRA or the INTRB to the OFF “H”. When this bit is set to “1” nothing happens. When the AALE, BALE bit is set to “0”, alarm operation is disabled and “0” is read from the AAFG, BAFG bit. ) INTR to the OFF (“H” ) for the RS5C372B. Output Relationships Between the ALFG Bit and INTRA or INTRB ( INTR for the RS5C372B) AAFG (BAFG) bit INTRA or INTRB pins (INTR pin for the RS5C372B) Setting of the AAFG (BAFG) bit to 0 (Matched alarm time) (Matched alarm time) Setting of the AAFG (BAFG) bit to 0 (Matched alarm time) 21 RS5C372A/B 2.3 Clock Counter (at internal address 0-2h)  Time digit display (in BCD code)  Second digits : Range from 00 to 59 and carried to minute digits when incremented from 59 to 00. Minute digits : Range from 00 to 59 and carried to hour digits when incremented from 59 to 00. Hour digits : See descriptions on the 12 /24 bit (Section 2.2-1). Carried to day and day-of-the-week digits when incremented from 11 p.m. to 12 a.m. or 23 to 00. Any registered imaginary time should be replaced with correct time as carrying to such registered imaginary time digits from lower-order ones cause the clock counter malfunction. 2.3-1 Second digit register (at internal address 0h) D7 D6 D5 D4 D3 D2 D1 D0 — S40 S20 S10 S8 S4 S2 S1 (For write operation) 0 S40 S20 S10 S8 S4 S2 S1 (For read operation) 0 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Default 2.3-2 Minute digit register (at internal address 1h) D7 D6 D5 D4 D3 D2 D1 D0 — M40 M20 M10 M8 M4 M2 M1 (For write operation) 0 M40 M20 M10 M8 M4 M2 M1 (For read operation) 0 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Default 2.3-3 Hour digit register (at internal address 2h) D7 D6 D5 D4 D3 D2 D1 D0 — — P/ A or H20 H10 H8 H4 H2 H1 (For write operation) 0 0 P/ A or H20 H10 H8 H4 H2 H1 (For read operation) 0 0 Undefined Undefined Undefined Undefined Undefined Undefined Default )The default means read value when XSTP bit is set to “1” by starting up from 0V, or supply voltage drop, etc. 22 RS5C372A/B 2.4 Day-of-the-week Counter (at internal address 3h)  Day-of-the-week digits are incremented by 1 when carried to 1-day digits.  Day-of-the-week digits display (incremented in septimal notation): (W4, W2, W1)(0,0,0)  (0,0,1)    (1,1,0)  (0,0,0)  The relation between days of the week and day-of-the-week digits is user changeable (e.g. Sunday0,0,0).  The (W4, W2, W1) should not be set to (1, 1, 1). D7 D6 D5 D4 D3 D2 D1 D0 — — — — — W4 W2 W1 (For write operation) 0 0 0 0 0 W4 W2 W1 (For read operation) 0 0 0 0 0 Undefined Undefined Undefined Default )The default means read value when XSTP bit is set to “1” by starting up from 0V, or supply voltage drop, etc. 2.5 Calendar Counter (at internal address 4 to 6h)  The automatic calendar function provides the following calendar digit displays in BCD code. Day digits  : Range from 1 to 31 (for January, March, May, July, August, October, and December). Range from 1 to 30 (for April, June, September, and November). Range from 1 to 29 (for February in leap years). Range from 1 to 28 (for February in ordinary years). Carried to month digits when cycled to 1. Month digits : Range from 1 to 12 and carried to year digits when cycled to 1. Year digits : Range from 00 to 99 and 00, 04, 08,..., 92, and 96 are counted as leap years. Any registered imaginary time should be replaced with correct time as carrying to such registered imaginary time digits from lower-order ones cause the clock counter malfunction. 2.5-1 Day digit register (at internal address 4h) D7 D6 D5 D4 D3 D2 D1 D0 — — D20 D10 D8 D4 D2 D1 (For write operation) 0 0 D20 D10 D8 D4 D2 D1 (For read operation) 0 0 Undefined Undefined Undefined Undefined Undefined Undefined Default 2.5-2 Month digit register (at internal address 5h) D7 D6 D5 D4 D3 D2 D1 D0 — — — MO10 MO8 MO4 MO2 MO1 (For write operation) 0 0 0 MO10 MO8 MO4 MO2 MO1 (For read operation) 0 0 0 Undefined Undefined Undefined Undefined Undefined Default 23 RS5C372A/B 2.5-3 Year digit register (at internal address 6h) D7 D6 D5 D4 D3 D2 D1 D0 Y80 Y40 Y20 Y10 Y8 Y4 Y2 Y1 (For write operation) Y80 Y40 Y20 Y10 Y8 Y4 Y2 Y1 (For read operation) Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Default )The default means read value when XSTP bit is set to “1” by starting up from 0V, or supply voltage drop, etc. 2.6 Time Trimming Register (at internal address 7h) D7 D6 D5 D4 D3 D2 D1 D0 XSL F6 F5 F4 F3 F2 F1 F0 (For write operation) XSL F6 F5 F4 F3 F2 F1 F0 (For read operation) 0 0 0 0 0 0 0 0 Default )The default means read value when XSTP bit is set to “1” by starting up from 0V, or supply voltage drop, etc. 2.6-1 XSL bit The XSL bit is used to select a crystal oscillator. Set the XSL to “0” (default) to use 32.768kHz. Set the XSL to “1” to use 32.000kHz. 2.6-2 F6 to F0 The time trimming circuit adjust one second count based on this register readings when second digit is 00, 20, or 40 seconds. Normally, counting up to seconds is made once per 32,768 of clock pulse (or 32,000 when 32.000kHz crystal is used) generated by the oscillator. Setting data to this register activates the time trimming circuit. Register counts will be incremented as ((F5, F4, F3, F2, F1, F0)–1)2 when F6 is set to “0”. Register counts will be decremented as (( F5,F4,F3,F2,F1,F0 )1)2 when F6 is set to “1”. Counts will not change when (F6, F5, F4, F3, F2, F1, F0) are set to (, 0, 0, 0, 0, 0,). For example, when 32.768kHz crystal is used. When (F6, F5, F4, F3, F2, F1, F0) are set to (0, 0, 0, 0, 1, 1, 1), counts will change as: 32,768(7–1)232,780 (clock will be delayed) when second digit is 00, 20, or 40. When (F6, F5, F4, F3, F2, F1, F0) are set to (0, 0, 0, 0, 0, 0, 1), counts will remain 32,768 without changing when second digit is 00, 20, or 40. When (F6, F5, F4, F3, F2, F1, F0) are set to (1, 1, 1, 1, 1, 1, 0), counts will change as: 32,768(–2)232,764 (clock will be advanced) when second digit is 00, 20, or 40. Adding 2 clock pulses every 20 seconds: 2/(32,76820)3.051ppm (or 3.125ppm when 32.000kHz crystal is used), delays the clock by approx. 3ppm. Likewise, decrementing 2 clock pulses advances the clock by 3ppm. Thus the clock may be adjusted to the precision of 1.5ppm. Note that the time trimming function only adjust clock timing and oscillation frequency and 32-kHz clock output is not adjusted. 24 RS5C372A/B 2.7 Alarm_A, Alarm_B Register (Alarm_A: internal address 8 to Ah; Alarm_B: internal address B to Dh) 2.7-1 Alarm_A minute register (internal address 8h) D7 D6 D5 D4 D3 D2 D1 D0 — AM40 AM20 AM10 AM8 AM4 AM2 AM1 (For write operation) 0 AM40 AM20 AM10 AM8 AM4 AM2 AM1 (For read operation) 0 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Default 2.7-2 Alarm_B minute register (internal address Bh) D7 D6 D5 D4 D3 D2 D1 D0 — BM40 BM20 BM10 BM8 BM4 BM2 BM1 (For write operation) 0 BM40 BM20 BM10 BM8 BM4 BM2 BM1 (For read operation) 0 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Default 2.7-3 Alarm_A hour register (internal address 9h) D7 D6 D5 D4 D3 D2 D1 D0 — — AH20, AP/ A AH10 AH8 AH4 AH2 AH1 (For write operation) 0 0 AH20, AP/ A AH10 AH8 AH4 AH2 AH1 (For read operation) 0 0 Undefined Undefined Undefined Undefined Undefined Undefined Default 2.7-4 Alarm_B hour register (internal address Ch) D7 D6 D5 D4 D3 D2 D1 D0 — — BH20, AP/ A BH10 BH8 BH4 BH2 BH1 (For write operation) 0 0 BH20, AP/ A BH10 BH8 BH4 BH2 BH1 (For read operation) 0 0 Undefined Undefined Undefined Undefined Undefined Undefined Default 2.7-5 Alarm_A day-of-the-week register (internal address Ah) D7 D6 D5 D4 D3 D2 D1 D0 — AW6 AW5 AW4 AW3 AW2 AW1 AW0 (For write operation) 0 AW6 AW5 AW4 AW3 AW2 AW1 AW0 (For read operation) 0 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Default 25 RS5C372A/B 2.7-6 Alarm_B day-of-the-week register (internal address Dh) D7 D6 D5 D4 D3 D2 D1 D0 — BW6 BW5 BW4 BW3 BW2 BW1 BW0 (For write operation) 0 BW6 BW5 BW4 BW3 BW2 BW1 BW0 (For read operation) 0 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Default )The default means read value when XSTP bit is set to “1” by starting up from 0V, or supply voltage drop, etc.  Alarm_A, Alarm_B hour register D5 is set to 0 for AM and 1 for PM in the 12-hour display system at AP/ A . The register D5 indicates 10 digit of hour digit in 24-hour display system at AH20.  To activate alarm operation, any imaginary alarm time setting should not be left to avoid unmatching.  In hour digit display midnight is set to 12, noon is set to 32 in 12-hour display system. (See section 2.2-1)  AW0 to AW6 correspond to the day-of-the-week counter (W4, W2, W1) being set at (0, 0, 0) to (1, 1, 0).  No alarm pulses are output when all of AW0 to AW6 are set to “0”. Example of Alarm Time Settings Day-of-the-week Alarm Time Settings Sun. Mon. Tue. Wed. Thu. AW0 AW1 AW2 AW3 AW4 12-hour system Fri. AW5 Sat. 10-hour 1-hour 10-min AW6 1-min 10-hour 1-hour 10-min 1-min 00:00 AM every day 1 1 1 1 1 1 1 1 2 0 0 0 0 0 0 01:30 AM every day 1 1 1 1 1 1 1 0 1 3 0 0 1 3 0 11:59 AM every day 00:00 PM on Monday through Friday 01:30 PM on Sunday 11:59 PM on Monday, Wednesday, and Friday 1 1 1 1 1 1 1 1 1 5 9 1 1 5 9 0 1 1 1 1 1 0 3 2 0 0 1 2 0 0 1 0 0 0 0 0 0 2 1 3 0 1 3 3 0 0 1 0 1 0 1 0 3 1 5 9 2 3 5 9 Designation of days of the week and AW0 to AW6 in the above table is an example. 26 24-hour system RS5C372A/B USAGES 1. Interfacing with the CPU The RS5C372A/B employ the I2C bus system to be connected to the CPU via 2-wires. Connection and transfer system of I2C bus are described in the following sections. 1.1 Connection of I2C bus 2-wires, SCL and SDA which are connected to I2C bus are used for transmit clock pulses and data respectively. All ICs that are connected to these lines are designed that will be not be clamped when a voltage beyond supply voltage is applied to input or output pins. Open drain pins are used for output. This construction allows communication of signals between ICs with different supply voltages by adding a pull-up resistor to each signal line as shown in the figure below. Each IC is designed not to affect SCL and SDA signal lines when power to each of these is turned off separately. 1) For data interface, the following conditions must be met: VDD4  VDD1 VDD4  VDD2 VDD4  VDD3 2) When the master is one, the microcontroller is ready for driving SCL to “H” and Rp of SCL may not be required. VDD1 VDD2 VDD3 VDD4 RP RP SCL SDA Microcontroller RS5C372A/B Other Peripheral Device 27 RS5C372A/B Cautions on Determining Rp Resistance (1) Voltage drop at Rp due to sum of input current or output current at off conditions on each IC pin connected to the I2C bus shall be adequately small. (2) Rising time of each signal shall be kept short even when all capacity of the bus is driven. (3) Current consumed in I2C bus is small compared to the consumption current permitted for the entire system. When all ICs connected to I2C bus are CMOS type, condition (1) may usually be ignored since input current and off state output current is extremely small for the many CMOS type ICs. Thus the maximum resistance of Rp may be determined based on (2) while the minimum on (3) in most cases. In actual cases a resistor may be place between the bus and input/output pins of each IC to improve noise margins in which case the Rp minimum value may be determined by the resistance. Consumption current in the bus to review (3) above may be expressed by the formula below: (Sum of input current and off state output current of all devices in standby mode)  Bus standby duration Bus consumption current Bus standby duration  bus operation duration  Supply voltage  bus operation duration  2 RP resistance  2  (bus standby duration  bus operation duration)  supply voltage  bus capacity  charging/discharging times per unit time Operation of “ 2” h in the second member denominator in the above formula is derived from assumption that “L” duration of SDA and SCL pins are the half of bus operation duration. “ 2” in the numerator of the same member is because there are two pins of SDA and SCL. The third member, (charging/discharging times per unit time) means number of transition from “H” to “L” of the signal line. Calculation example is shown below: Pull-up resistor (RP)10k, Bus capacity50pF (both for SCL and SDA), VDD3V In as system with sum of input current and off state output current of each pin0.1A, I2C bus is used for 10ms every second while the rest of 990ms is in the stand-by mode. In this mode number of transitions of the SCL pin from “H” to “L” state is 100 while SDA 50, every second. 0.1A  990ms Bus consumption current 990ms  10ms  3V  10ms  2 10k 2  (990ms  10ms)  3V  50pF  (100  50)  0.099A  3.0A  0.0225A  3.12A Generally, the second member of the above formula is larger enough than the first and the third members, bus consumption current may be determined by the second member in many cases. 28 RS5C372A/B 1.2 Transmission System of I2C bus 1.2-1 Start and stop conditions In I2C bus, SDA must be kept at a certain state while SCL is at the “H” state as shown below during data transmission. SCL SDA tSU;DAT tHDL;DAT or tHDH;DAT The SCL and SDA pins are at the “H” level when no data transmission is made. Changing the SDA from “H” to “L” when the SCL and the SDA are “H” activates the start condition and access is started. Changing the SDA from “L” to “H” when the SCL is “H” activates stop condition and accessing stopped. Generation of start and stop conditions are always made by the master (see the figure below). Start condition Stop condition SCL SDA tSU;STO tHD;STA 1.2-2 Data transmission and its acknowledge After start condition is entered, data is transmitted by 1byte (8bits). Any bytes of data may be serially transmitted. The receiving side will send an acknowledge signal to the transmission side each time 8bit data is transmitted. The acknowledge signal is sent immediately after falling to “L” of SCL8bit clock pulses of data transmission, by releasing the SDA by the transmission side that has asserted the bus at that time and by turning the SDA to “L” by the receiving side. When transmission of 1byte data next to preceding 1byte of data is received, the receiving side releases the SDA pin at falling edge of the SCL9bit of clock pulses or when the receiving side switches to the transmission side it starts data transmission. When the master is the receiving side, it generates no acknowledge signal after the last 1byte of data from the slave to tell the transmitter that data transmission has completed when the slave side (transmission side) continues to release the SDA pin so that the master will be able to generate stop condition. SCL from the master 1 SDA from the transmission side 2 8 9 SDA from the receiving side Start condition Acknowledge signal 29 RS5C372A/B 1.2-3 Data transmission format in I2C bus I2C bus generates no CE signals. In place of it each device has a 7bit slave address allocated. The first 1byte is allocated to this 7bit of slave address and to the command (R/ W) for which data transmission direction is designated by the data transmission thereafter. 7bit address is sequentially transmitted from the MSB and 2 and after bytes are read, when 8bit is “H” and write when “L”. The slave address of the RS5C372A/B are specified at (0110010). At the end of data transmission/receiving stop condition is generated to complete transmission. However, if start condition is generated without generating stop condition, repeated start condition is met and transmission/receiving data may be continued by setting the slave address again. Use this procedures when the transmission direction needs to be changed during one transmission. Data is written into the slave from the master When data is read from the slave immediately after 7bit addressing from the master S Slave address (0110010) S S Slave address A Data A Data A P 1 A Data A Data A P Inform read has been completed by not generating an acknowledge signal, to the slave side. R/W=1 (Read) Slave address (0110010) Data R/W=0 (Write) (0110010) When the transmission direction is to be changed during transmission. 0 A 0 A A Sr Data R/W=0 (Write) A 1 Slave address (0110010) R/W=1 (Read) A P Data Inform read has been completed by not generating an acknowledge signal, to the slave side. Master to slave S Start condition 30 Slave to master P Stop condition A A A Acknowledge signal Sr Repeated start condition RS5C372A/B 1.2-4 Data transmission write format in the RS5C372A/B Although the I2C bus standard defines a transmission format for the slave address allocated for each IC, transmission method of address information in IC is not defined. The RS5C372A/B transmit data the internal address pointer (4bit) and the transmission format register (4bit) at the 1byte next to one which transmitted a slave address and a write command. For write operation only one transmission format is available and (0000) is set to the transmission format register. The 3byte transmits data to the address specified by the internal address pointer written to the 2byte. Internal address pointer settings are automatically incremented for 4byte and after. Note that when the internal address pointer is Fh, it will change to 0h on transmitting the next byte. Example of data writing (When writing to internal address Eh to Fh) R/W=0 (Write) S 0 1 1 0 0 1 0 0 A 1 1 1 0 0 0 0 0 A Transmission of slave address (0110010) Setting of Eh to the internal address pointer Setting of 0h to the transmission format register Master to slave S Start condition A A Data Writing of data to the internal address Eh. A Data A P Writing of data to the internal address Fh. Slave to master P Stop condition A Acknowledge signal 31 RS5C372A/B 1.2-5 Data transmission read format of the RS5C372A/B The RS5C372A/B allow the following three readout methods of data from an internal register. 1) The first method to reading data from the internal register is to specify an internal address by setting the internal address pointer and the transmission format register described 1.2-4, generate the repeated start condition (see section 1.2-3) to change the data transmission direction to perform reading. The internal address pointer is set to Fh when the stop condition is met. Therefore, this method of reading allows no insertion of the stop condition before the repeated start condition. Set 0h to the transmission format register. Example 1 of data read (when data is read from 2h to 4h) R/W=0 (Write) Repeated start condition R/W=1 (Read) S 0 1 1 0 0 1 0 0 A 0 0 1 0 0 0 0 0 A Sr 0 1 1 0 0 1 0 1 A Transmission of slave address (0110010) Setting of 2h to the internal address pointer Data A Reading of data from the internal address 2h. Master to slave S Start condition A 32 A A Acknowledge signal Transmission of slave address (0110010) Setting of 0h to the transmission format register Data A Reading of data from the internal address 3h. Data A P Reading of data from the internal address 4h. Slave to master Sr Repeated start condition P Stop condition RS5C372A/B 2) The second method to reading data from the internal register is to start reading immediately after writing to the internal address pointer and the transmission format register. Although this method is not based on the I2C bus standard in a strict sense it still effective to shorten read time to ease load to the master. Set 4h to the transmission format register when this method is used. Example 2 of data read (when data is read from internal addresses Eh to 1h). R/W=0 (Write) S 0 1 1 0 0 1 0 0 A 1 1 1 0 0 1 0 0 A Transmission of slave address (0110010) Setting of Eh to the internal address pointer Data A Reading of data from the internal address Fh. Master to slave S Start condition A A Setting of 4h to the transmission format register A Data Reading of data from the internal address Eh Data A Reading of data from the internal address 0h. Data A P Reading of data from the internal address 1h. Slave to master P Stop condition A Acknowledge signal 33 RS5C372A/B 3) The third method to reading data from the internal register is to start reading immediately after writing to the slave address and the R/ W bit. Since the internal address pointer is set to Fh by default as described in 1), this method is only effective when reading is started from the internal address Fh. Example 3 of data read (when data is read from internal addresses Fh to 3h). R/W=1 (Read) S 0 1 1 0 0 1 0 1 A Transmission of slave address (0110010) Reading of data from the internal address Fh. Data A Reading of data from the internal address 1h. Master to slave S Start condition A 34 A A Data A Acknowledge signal A Data Reading of data from the internal address 0h. Data A Reading of data from the internal address 2h. Slave to master P Stop condition Data Reading of data from the internal address 3h. A P RS5C372A/B 1.2-6 Data transmission under special condition The RS5C372A/B hold the clock tentatively for duration from start condition to stop condition to avoid invalid read or write clock on carrying clock. When clock is carried during this period, which will be adjusted within approx. 61s from stop condition. To prevent invalid read or write clock shall be made during one transmission operation (from start condition to stop condition). When 0.5 to 1.0 second elapses after start condition any access to the RS5C372A/B are automatically released to release tentative hold of the clock, set Fh to the address pointer, and access from the CPU is forced to be terminated (the same action as made stop condition is received: automatic resume function from the I2C bus interface). Therefore, one access must be completed within 0.5 seconds. The automatic resume function prevents delay in clock even if the SCL is stopped from sudden failure of the system during clock read operation. Also a second start condition after the first condition and before the stop condition is regarded as the “repeated start condition.“ Therefore, when 0.5 to 1.0 seconds passed after the first start condition, access to the RS5C372A/B are automatically released. If access is tried after automatic resume function is activated, no acknowledge signal will be output for writing while FFh will be output for reading. Access to the Real-time Clock 1) No stop condition shall be generated until clock read/write is started and completed. 2) One cycle read/write operation shall be completed within 0.5 seconds. 3) Do not make start condition within 62s from stop condition. When clock is carried during the access, which will be adjusted within approx.61s from stop condition. The user shall always be able to access the real-time clock as long as these three conditions are met. Bad example of reading from seconds to hours (invalid read) (Start condition)  (Read of seconds)  (Read of minutes)  (Stop condition)  (Start condition)  (Read of hour)  (Stop condition) Assuming read was started at 05:59:59 P.M. and while reading seconds and minutes the time advanced to 06:00:00 P.M. At this time second digit is hold so the read as 05:59:59. Then the RS5C372A/B confirm (Stop condition) and carry second digit being hold and the time changes to 06:00:00 P.M. Then, when the hour digit is read, it changes to 6. The wrong results of 06:59:59 will be read. 35 RS5C372A/B 2. Configuration of Oscillating Circuit and Time Trimming 2.1 Configuration of Oscillating Circuit RS5C372A/B VDD VDD 8 7 OSCIN CG RF RD 32kHz 6 CD OSCOUT Typical external device: X'tal: 32.768kHz or 32.000kHz (R130k Typ.) (CL6pF to 8pF) Typical values of internal devices: RF 15M (Typ.) RD 60k (Typ.) CG, CD 10pF (Typ.) A The oscillation circuit is driven at a constant voltage of about 1.2V relative to the Vss level. Consequently, it generates a wave form having a peak-to-peak amplitude of about 1.2V on the positive side of the Vss level. Considerations on Crystal Oscillator Basic characteristics of a crystal oscillator includes R1 (equivalent series resistance: ease of oscillation) and CL (load capacitance: rank of center frequency). R1Typ. of 30k, CL6 to 8pF is recommended for the RS5C372A/B. Confirm recommended values to the manufacturer of the crystal oscillator used. Considerations in Mounting Components Surrounding Oscillating Circuit 1) Mount the crystal oscillators in the closest possible position to the IC. 2) Avoid laying any signal or power line close to the oscillation circuit (particularly in the area marked with “ A ” in the above figure). 3) Apply the highest possible insulation resistance between the OSCIN or OSCOUT pin and the PCB. 4) Avoid using any long parallel line to wire the OSCIN and OSCOUT pin. 5) Take extreme care not to cause condensation, which leads to various problems such as oscillation halt. Other Relevant Considerations 1) When applying an external input of clock pulses (32.768kHz or 32.000kHz) to the OSCIN pin: DC coupling : Prohibited due to mismatching of input levels. AC coupling : Permissible except that unpredictable results may occur in oscillator halt sensing due to possible sensing errors caused by noises, etc. 2) Avoid using the oscillator output of the RS5C372A/B (from the OSCOUT pin) to drive any other IC for the purpose of ensuring stable oscillation. 36 RS5C372A/B 2.2 Measurement of Oscillation Frequency RS5C372A/B VDD *34 * OSCIN OSCOUT *4 INTRB (32KOUT) 32.768kHz or 32.000kHz Frequency counter VSS *1) Clock pulse of 32.768kHz or 32.000kHz is output from the INTRB output pin on powering on (XSTP is set to 1). *2) Use a frequency counter having at least 6 digits (7digits or more recommended). *3) Pull-up the INTRB output pin to VDD for the RS5C372A. *4) INTRB applies to the RS5C372A, and 32KOUT applies to the RS5C372B. The RS5C372B does not need pull-up resistor. 2.3 Oscillation Frequency Adjustment Adjustment amount of oscillation frequency may differ dependent on how the RS5C372A/B is used or how much clock error is permissible in the system it is installed. Use the flow chart shown below find an optimal oscillation frequency adjustment method. Start 32kHz clock used? NO YES For clock precision errors derived by adding deflection in crystal oscillator*1 + deflection in IC*2 is permissible*3. YES YES NO (A) course (B) course 32kHz clock output is used, but clock frequency precision is not considered (C) course NO YES For clock precision errors derived by adding deflection in crystal oscillator*1 + deflection in IC*2 is permissible*3. NO (D) course *1) In general crystal oscillators are classified by their central frequency of CL (load capacitance) and available further grouped in several ranks as 10, 20 and 50ppm of fluctuations in precision. *2) Fluctuations in frequency due to the IC used is generally from 5 to 10ppm at a room temperature. *3) Clock precision here is at a room temperature and is subjected to change due to temperature characteristics of the crystal itself. 37 RS5C372A/B (A) course Adjustment of clock is not made for IC (no adjustment) and any CL value may be used for the crystal oscillator. Precision fluctuations of a crystal oscillator may be selected as long as clock precision allows. Obtain the central frequency as described in section 2.2 using several crystal oscillator and ICs, determine an adjustment value as described in “2.4 Time Trimming Circuit” which shall be set to the RS5C372A/B. (B) course To keep clock precision within the range of (fluctuation in crys-tal oscillator  fluctuation in IC), clock shall be adjustment is required for each IC. On adjusting procedures see “2.4 Time Trimming Circuit.” Available selection range for the frequency precision fluctuations and CL (load capacitance) for a crystal oscillator may be widened by adjusting clock frequency. Obtain the central frequency as described in section 2.2 using the crystal oscillator and IC to be used, determine if an adjustment is possible or not using the clock adjustment circuit, perform adjustment for each IC using the clock adjustment circuit. Up to 1.5ppm may be adjusted at a room temperature. (C) course In (C) and (D) courses, adjustment of 32-kHz clock output frequency as well as clock is necessary. Frequency adjustment for the crystal oscillator is made by adjusting both of CG and CD connected to the both ends of the oscillator. Since the RS5C372A/B incorporate the CG and CD, oscillating frequency is required using CL of the crystal oscillator as the reference. Generally, relation between CL and CG or CD is as follows: CG CD CL   CS CG  CD CS : Board floating capacitance Although a crystal oscillator having CL value of around 6 to 8pF is recommended for the RS5C372A/B, measure oscillation frequency as described in section 2.2 and if frequency is high (clock gains) switch to a crystal oscillator with smaller CL while if frequency is small (clock loses) switch to an oscillator with larger CL. Using these procedures select a crystal oscillator with optimal CL and set unadjusted value to the clock adjustment circuit. (See section 2.4, “Time Trimming Circuit”.) We recommend to consult the crystal manufacturer on compatibility of CL values. High oscillation frequency (clock gains) may be adjusted by externally adding CGOUT as shown below. RS5C372A/B 1) CGOUT shall be from 0 to 15pF. VDD VDD 8 7 CG RF RD 32kHz 6 CD OSCIN CGOUT*1 OSCOUT (D) course Select a crystal oscillator as in the (C) course, then adjust clock error for each IC as in (B) course. For clock adjusting procedures, see “2.4 Time Trimming Circuit.” 38 RS5C372A/B 2.4 Time Trimming Circuit Using the time trimming circuit gain or lose of clock may be adjusted with high precision by changing clock pulses for one second every 20 seconds. When adjustment with this circuit is not necessary, set (F6, F5, F4, F3, F2, F1, F0) to (, 0, 0, 0, 0, 0,) to disable adjustment. ( mark indicates 0 or 1.) Adjustment amount may be calculated using the following formula. 2.4-1 When oscillation frequency1 >target frequency2 (clock gains) Adjustment amount3  (Oscillation frequency  Target frequency  0.1) Oscillation frequency  3.051  106 (Oscillation frequency  Target frequency)  10  1 When 32.000kHz crystal oscillator is used, the same formula, Adjustment amount  (Oscillation frequency  Target frequency  0.1) Oscillation frequency  3.125  106 (Oscillation frequency  Target frequency)  10  1 is used. 1) Oscillation frequency : Clock frequency output from the INTRB (32KOUT for the RS5C372B) pin as in “2.2 Oscillation Frequency Measurement” at a room temperature. 2) Target frequency : A frequency to be adjusted to. Since temperature characteristics of a 32.768kHz crystal oscillator are such that it will generally generates the highest frequency at a room temperature, we recommend to set the target frequency to approx. 32768.00Hz to 32768.10Hz (3.05ppm to 32768Hz). We also recommend setting of approx. 32000.00Hz to 32000.10Hz (3.125ppm to 32000Hz) also for the 32.000kHz crystal. Note that this value may differ based on the environment or place where the device will be used. 3) Adjustment amount : A value to be set finally to F6 to F0 bits. This value is expressed in 7bit binary digits with sign bit (two's compliment). 2.4-2 When oscillation frequencytarget frequency (no clock gain or loss) Set the adjustment value to 0 or 1, or 64 or 63 to disable adjustment. 2.4-3 When oscillation frequency