RV5C338A

3-WIRE SERIAL INTERFACE REAL-TIME CLOCK ICS WITH VOLTAGE MONITORING FUNCTION R × 5C338A APPLICATION MANUAL ELECTRONIC DEVICES DIVISION NO.EA-053-9908 NOTICE 1. The products and the product specifications described in this application manual are subject to change or discontinuation of production without notice for reasons such as improvement. Therefore, before deciding to use the products, please refer to Ricoh sales representatives for the latest information thereon. 2. This application manual may not be copied or otherwise reproduced in whole or in part without prior written consent of Ricoh. 3. Please be sure to take any necessary formalities under relevant laws or regulations before exporting or otherwise taking out of your country the products or the technical information described herein. 4. The technical information described in this application manual shows typical characteristics of and example application circuits for the products. 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June 1995 R × 5C338A APPLICATION MANUAL CONTENTS ......................................................................................................1 FEATURES....................................................................................................1 BLOCK DIAGRAM .........................................................................................2 APPLICATIONS .............................................................................................2 PIN CONFIGURATION ...................................................................................2 PIN DESCRIPTIONS ......................................................................................3 ABSOLUTE MAXIMUM RATINGS ...................................................................4 RECOMMENDED OPERATING CONDITIONS .................................................4 DC ELECTRICAL CHARACTERISTICS ...........................................................5 AC ELECTRICAL CHARACTERISTICS ...........................................................6 GENERAL DESCRIPTION ..............................................................................7 FUNCTIONAL DESCRIPTIONS ......................................................................9 1. Address Mapping .........................................................................................9 2. Register Settings .......................................................................................10 USAGES......................................................................................................21 1. Data Transfer Formats ..................................................................................21 2. Configuration of Oscillation Circuit and Correction of Time Count Deviations...................27 3. Oscillation Halt Sensing and Supply Voltage Monitoring ...........................................32 4. Alarm and Periodic Interrupt ...........................................................................34 5. 32-kHz Clock Output ....................................................................................37 6. Typical Applications .....................................................................................38 7. Typical Characteristics ..................................................................................41 8. Typical Software-based Operations ...................................................................43 PACKAGE DIMENSIONS ..............................................................................47 TAPING SPECIFICATIONS ...........................................................................48 OUTLINE 3-WIRE SERIAL INTERFACE REAL-TIME CLOCK ICS WITH VOLTAGE MONITORING FUNCTION R × 5C338A OUTLINE The R × 5C338A are CMOS real-time clock ICs connected to the CPU by three signal lines CE (Chip Enable), SCLK (Serial Clock), and SIO (Serial Input/Output), and configured to perform serial transmission of time and calendar data to the CPU. These models incorporate different functional circuits. The periodic interrupt circuit is configured to generate interrupt signals with six selectable interrupts ranging from 0.5 seconds to 1 month. The 2 alarm circuits generate interrupt signals at preset times. The oscillation circuit is driven under constant voltage so that fluctuations in oscillation frequency due to voltage are small and supply current is also small (TYP. 0.35µA at 3 volts). The oscillation halt sensing circuit can be used to judge the validity of internal data in such events as poweron. The supply voltage monitoring circuit is configured to record a drop in supply voltage below two selectable supply voltage monitoring threshold settings. The 32-kHz clock output function is intended to output sub-clock pulses for the external microcomputer. The oscillation adjustment circuit is intended to adjust time counts with high precision by correcting deviations in the oscillation frequency of the crystal oscillator. These models come in an ultra-compact 10-pin SSOP (RS5C338A with a height of 1.25mm and a pin pitch of 0.5mm)and 10-pin SSOP-G (RV5C338A with a height of 1.2mm and a pin pitch of 0.5mm). FEATURES • Timekeeping supply voltage ranging from 1.45 to 5.5 volts • Low supply current: TYP. 0.35µA (MAX. 0.8µA) at 3 volts (at 25˚C) • Only three signal lines (SCLK, SIO, and CE) required for connection to the CPU. Maximum clock frequency of 2 MHz (with VDD of 5 volts) • Time counters (counting hours, minutes, and seconds) and calendar counters (counting years, months, days, and weeks) (in BCD format) • 1900/2000 identification bit for Year 2000 compliance • Interrupt circuit configured to generate interrupt signals (with interrupts ranging from 0.5 seconds to 1 month) to the CPU and provided with an interrupt flag and an interrupt halt circuit • 2 alarm circuits (Alarm_W for week , hour , and minute alarm settings and Alarm_D for hour and minute alarm settings) • 32-kHz clock circuit (CMOS output, equipped with a control pin) • Oscillation halt sensing circuit which can be used to judge the validity of internal data • Supply voltage monitoring circuit with two supply voltage monitoring threshold settings • Automatic identification of leap years up to the year 2099 • Selectable 12-hour and 24-hour mode settings • High precision oscillation adjustment circuit • Built-in oscillation stabilization capacitors (CG and CD) • CMOS process • Ultra-compact 10-pin SSOP (RS5C338A with a height of 1.25mm and size of 6.4×3.5mm) Ultra-compact 10-pin SSOP-G (RV5C338A with a height of 1.20mm and size of 4.0×2.9mm) 1 R × 5C338A BLOCK DIAGRAM 32KOUT CLKC 32kHz OUTPUT CONTROL COMPARATOR_W ALARM_W REGISTER (MIN,HOUR,WEEK) VDD COMPARATOR_D OSCIN OSC OSCOUT ALARM_D REGISTER (MIN,HOUR) VOLTAGE DETECT VSS DIVIDER CORREC -TION DIV TIME COUNTER (SEC,MIN,HOUR,WEEK,DAY,MONTH,YEAR) OSC DETECT ADDRESS DECODER ADDRESS REGISTER I/O CONTROL SCLK SIO INTR INTERRUPT CONTROL SHIFT REGISTER CE APPLICATIONS • Communication devices (multi function phone, portable phone, PHS or pager) • OA devices (fax, portable fax) • Computer (desk-top and mobile PC, portable word-processor, PDA, electric note or video game) • AV components (portable audio unit, video camera,camera, digital camera or remote controller) • Home appliances (rice cooker, electric oven) • Other (car navigation system, multi-function watch) PIN CONFIGURATION • 10-pin SSOP-G, 10-pin SSOP 32KOUT SCLK SIO CE VSS 1 2 3 4 5 10 9 8 7 6 VDD OSCIN OSCOUT CLKC INTR 2 R × 5C338A PIN DESCRIPTIONS Pin No. Symbol Name Description The CE pin is used for interfacing with the CPU. Should be held high to allow 4 CE Chip Enable Input access to the CPU. Incorporates a pull-down resistor. Should be held low or open when the CPU is powered off. Allows a maximum input voltage of 5.5 volts regardless of supply voltage. The SCLK pin is used to input clock pulses synchronizing the input and output of 2 SCLK Serial Clock Input data to and from the SIO pin. Allows a maximum input voltage of 5.5 volts regardless of supply voltage. 3 SIO Serial Input/Output The SIO pin is used to input and output data intended for writing and reading in synchronization with the SCLK pin. CMOS input/output. The INTR pin is used to output periodic interrupt signals to the CPU and alarm 6 INTR Interrupt Output interrupt signals (Alarm_W, Alarm_D). Disabled at power-on from 0 volts. Nch. open drain output. The 32KOUT pin is used to output 32.768-kHz clock pulses. Enabled at power-on 1 32KOUT 32-kHz Clock Output from 0 volts. CMOS output. This pin is disabled if the CLKC pin is set to low or open. The CLCK pin is used to control output of the 32KOUT pin. The clock output is 7 CLKC Clock Control Input disabled and held low when the pin is set to low or open. Incorporates a pull-down resistor. 9 8 10 5 OSCIN OSCOUT VDD VSS Oscillation Circuit Input/Output Positive Power Supply Input Negative Power Supply Input The OSCIN and OSCOUT pins are used to connect the 32.768-kHz crystal oscillator (with all other oscillation circuit components built into the R × 5C338A.) The VDD pin is connected to the power supply. The VSS pin is grounded. 3 R × 5C338A ABSOLUTE MAXIMUM RATINGS Symbol Item Conditions Ratings (Vss=0V) Unit VDD VI Supply Voltage Input Voltage 1 Input Voltage 2 Output Voltage 1 SIO SCLK, CE,CLKC SIO, 32KOUT INTR Topt=25˚C –0.3 to +6.5 –0.3 to VDD+0.3 V V –0.3 to +6.5 –0.3 to VDD+0.3 V –0.3 to +6.5 300 –40 to +85 –55 to +125 mW ˚C ˚C VO Output Voltage 2 PD Topt Tstg Power Dissipation Operating Temperature Storage Temperature ABSOLUTE MAXIMUM RATINGS Absolute Maximum ratings are threshold limit values that must not be exceeded even for an instant under any conditions. Moreover, such values for any two items must not be reached simultaneously. Operation above these absolute maximum ratings may cause degradation or permanent damage to the device. These are stress ratings only and do not necessarily imply functional operation below these limits. RECOMMENDED OPERATING CONDITIONS Symbol Item Conditions MIN. (Vss=0V,Topt=–40 to +85˚C) TYP. MAX. Unit VDD VCLK Supply Voltage Timekeeping Voltage Oscillation Frequency Pull-up Voltage INTR 2.0 1.45 32.768 5.5 5.5 V V kHz fXT VPUP 5.5 V 4 R × 5C338A DC ELECTRICAL CHARACTERISTICS Unless otherwise specified : Vss=0V,VDD=3V,Topt=–40 to +85˚C Symbol Item Pin name Conditions MIN. TYP. MAX. Unit VIH1 VIH2 VIL IOH IOL1 “H” Input Voltage “H” Input Voltage “L” Input Voltage “H” Output Current ”L” Output Current SCLK,CE,CLKC SIO SCLK,CE,SIO,CLKC SIO,32KOUT INTR SIO,32KOUT VOH=VDD–0.5V VOL=0.4V VOL=0.4V VI=5.5V or Vss VDD=5.5V VDD=2.5 to 5.5V 0.8VDD 0.8VDD –0.3 5.5 VDD+0.3 0.2VDD –0.5 mA mA V 2 0.5 –1 40 120 0.35 1 400 1.0 µA kΩ µA IOL2 IIL RDNCE ICLKC Input Leakage Current SCLK Pull-down Resistance Pull-down Resistance Input Current Output Off-state Leakage Current CE CLKC IOZ1 IOZ2 SIO INTR Vo=5.5V or Vss VDD=5.5V VO=5.5V VDD=3V,CE=OPEN –1 –1 1 µA 1 IDD1 Standby Current VDD Output=OPEN 32KOUT=Off mode*1 0.35 0.8 µA VDETH Supply Voltage Monitoring Voltage (“H”) Supply Voltage Monitoring Voltage (“L”) VDD Topt=–30 to +70˚C 1.90 2.10 2.30 V VDETL CG CD VDD Topt=–30 to +70˚C 1.45 1.60 12 12 1.80 V Internal Oscillation Capacitance 1 OSCIN Internal Oscillation Capacitance 2 OSCOUT pF *1) For standby current for outputting 32.768-kHz clock pulses from the 32KOUT pin, see “USAGES, 7. Typical Characteristics”. 5 R × 5C338A AC ELECTRICAL CHARACTERISTICS Unless otherwisespecified : Vss=0V, Topt=–40 to +85˚C Input/output conditions : VIH=0.8 × VDD, VIL=0.2 × VDD, VOH=0.8 × VDD, VOL=0.2 × VDD, CL=50pF Symbol Item Conditions VDD≥2.5V MIN. TYP. MAX. MIN. VDD≥4.5 TYP. MAX. Unit tCES tCEH tCR fSCLK tCKH tCKL tCKS tRD tRZ tCEZ tDS tDH CE Set-up Time CE Hold Time CE Recovery Time SCLK Clock Frequency SCLK Clock “H” Time SCLK Clock “L” Time SCLK Set-up Time Data Output Delay Time Data Output Floating Time Data Output Floating Time After Falling of CE Input Data Set-up Time Input Data Hold Time 400 400 62 1.0 400 400 200 300 300 300 200 200 200 200 62 2.0 200 200 100 150 150 150 100 100 ns ns µs MHz ns ns ns ns ns ns ns ns tCKH tCKL CE tCEH tCKS SCLK tCES tCR tDS SIO (Write cycle) tDH tCEZ SIO (Read cycle) tRD tRD tRZ *) For read/write timing, see Paragraph “USAGES, 1.5 Considerations in Reading and Writing Time Data” 6 R × 5C338A GENERAL DESCRIPTION 1. Interface with CPU The R × 5C338A are connected to the CPU by three signal lines CE (Chip Enable), SCLK (Serial Clock), SIO (Serial Input/Output), through which it reads and write data from and to the CPU. The CPU can access when the CE pin is held high. Access clock pulses have a maximum frequency of 2MHz (at 5 volts), allowing high-speed data transfer to the CPU. 2. Clock and Calendar Function The R × 5C338A read and write time data from and to the CPU in units ranging from seconds to the last two digits of the calendar year. The calendar year will automatically be identified as a leap year when its last two digits are a multiple of 4. Also available is the 1900/2000 identification bit for Year 2000 compliance. Consequently, leap years up to the year 2099 can automatically be identified as such. *) The year 2000 is a leap year while the year 2100 is not a leap year. 3. Alarm Function The R × 5C338A incorporate an alarm circuit configured to generate interrupt signals to the CPU for output at preset times. The alarm circuit allows two types of alarm settings specified by the Alarm_W registers and the Alarm_D registers. The Alarm_W registers allow week, hour, and minute alarm settings including combinations of multiple day-of-week settings such as “Monday, Wednesday, and Friday” and “Saturday and Sunday”. The Alarm_D registers allow hour and minute alarm settings. Both Alarm_W and Alarm_D signals are output from the INTR pin. The current alarm settings specified by these two registers can be checked from the CPU by using a polling function.. 4. High-precision Oscillation Adjustment Function The R × 5C338A have built-in oscillation stabilization capacitors (CG and CD), which can be connected to an external crystal oscillator to configure an oscillation circuit. To correct deviations in the oscillation frequency of the crystal oscillator, the oscillation adjustment circuit is configured to allow correction of a time count gain or loss (up to ±1.5 ppm at 25˚C) from the CPU within a maximum range of approximately ±189 ppm in increments of approximately 3 ppm. Such oscillation frequency adjustment in each system has the following advantages: · Allows timekeeping with much higher precision than conventional real-time clocks while using a crystal oscillator with a wide range of precision variations. · Corrects seasonal frequency deviations through seasonal oscillation adjustment. · Allows timekeeping with higher precision particularly in systems with a temperature sensing function through oscillation adjustment in tune with temperature fluctuations. 7 R × 5C338A 5. Oscillation Halt Sensing Function and Supply Voltage Monitoring Function The R × 5C338A incorporate an oscillation halt sensing circuit equipped with internal registers configured to record any past oscillation halt, thereby identifying whether they are powered on from 0 volts or battery backed-up. As such, the oscillation halt sensing circuit is useful for judging the validity of time data. The R × 5C338A also incorporate a supply voltage monitoring circuit equipped with internal registers configured to record any drop in supply voltage below a certain threshold value. Supply voltage monitoring threshold settings can be selected between 2.1 and 1.6 volts through internal register settings. The oscillation halt sensing circuit is configured to confirm the established invalidation of time data in contrast to the supply voltage monitoring circuit intended to confirm the potential invalidation of time data. Further, the supply voltage monitoring circuit can be applied to battery supply voltage monitoring. 6. Periodic Interrupt Function The R × 5C338A incorporate a periodic interrupt circuit configured to generate periodic interrupt signals aside from interrupt signals generated by the alarm circuit for output from the INTR pin. Periodic interrupt signals have five selectable frequency settings of 2Hz (once per 0.5 seconds), 1Hz (once per 1 second), 1/60Hz (once per 1 minute), 1/3600Hz (once per 1 hour), and monthly (the first day of every month). Further, periodic interrupt signals also have two selectable waveforms of a normal pulse form (with a frequency of 2Hz or 1Hz) and special form adapted to interruption from the CPU in the level mode (with second, minute, hour, and month interrupts). The register records of periodic interrupt signals can be monitored by using a polling function. 7. 32-kHz Clock Output Function The R × 5C338A incorporate a 32-kHz clock circuit configured to generate clock pulses with the oscillation frequency of a 32.768-kHz crystal oscillator for output from the 32KOUT pin. The 32KOUT pin is CMOS output and the output from this pin is enabled and disabled when the CLKC pin is held high, and low or open, respectively. The 32-kHz clock output can be disabled by certain register settings. But it cannot be disabled without manipulation of any two registers with different addresses, to prevent disabling in such events as the runaway of the CPU. The 32-kHz clock circuit is enabled at power-on, when the CLKC pin is held high. 8 R × 5C338A FUNCTIONAL DESCRIPTIONS 1. Address Mapping Address A3 A2 A1 A0 Register Data*1 D7 D6 D5 D4 D3 D2 D1 D0 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Second Counter Minute Counter Hour Counter Day-of-week Counter Day-of-month Counter – *2 – – – – S40 M40 – – – – Y40 F6 S20 M20 H20 P/A – D20 – Y20 F5 S10 M10 H10 – D10 MO10 Y10 F4 S8 M8 H8 – D8 MO8 Y8 F3 S4 M4 H4 W4 D4 MO4 Y4 F2 WM4 WH4 WW2 DM4 DH4 – CT2 S2 M2 H2 W2 D2 MO2 Y2 F1 WM2 WH2 WW1 DM2 DH2 – CT1 S1 M1 H1 W1 D1 MO1 Y1 F0 WM1 WH1 WW0 DM1 DH1 – CT0 Month Counter and Century Bit 19/20 Year Counter Y80 Oscillation Adjustment Register*3 (0)*4 Alarm_W (minute register) Alarm_W (hour register) Alarm_W (day-of-week register) Alarm_D (minute register) Alarm_D (hour register) – – – – – – Control Register 1*3 Control Register 2*3 WM40 WM20 WM10 WM8 – WW6 WH20 WP/A WW5 WH10 WW4 DM10 DH10 – WH8 WW3 DM8 DH8 – DM40 DM20 – – DH20 DP/A – WALE DALE 12/24 CLEN2 TEST VDSL VDET SCRATCH XSTP CLEN1 CTFG WAFG DAFG *1) All the data listed above accept both reading and writing. *2) The data marked with “–” is invalid for writing and reset to 0 for reading. *3) When the XSTP bit is set to 1 in control register 2, all the bits are reset to 0 in oscillation adjustment register 1, control register 1 and control register 2 * excluding the XSTP bit. 4) Writing to the oscillation adjustment register requires zero filling the (0) bit. 9 R × 5C338A 2. Register Settings 2.1 Control Register 1 (at Address Eh) D7 WALE WALE 0 D6 DALE DALE 0 D5 12/24 12/24 0 D4 CLEN2 CLEN2 0 D3 TEST TEST 0 D2 CT2 CT2 0 D1 CT1 CT1 0 D0 CT0 CT0 0 (For writing) (For reading) Default settings* *) Default settings: Default value means read/written values when the XSTP bit is set to “1” due to power-on from 0 volts or supply voltage drop. 2.1-1 WALE, DALE Alarm_W Enable Bit and Alarm_D Enable Bit WALE, DALE Description 0 Disabling the alarm interrupt circuit (under the control of the settings of the Alarm_W registers and the Alarm_D registers). Enabling the alarm interrupt circuit (under the control of the settings of the Alarm_W registers and the Alarm_D registers) (Default setting) 1 2.1-2 12/24-hour Mode Selection Bit 12/24-hour Time Display System Selection bit 12/24 Description 0 1 Selecting the 12-hour mode with a.m. and p.m. indications. Selecting the 24-hour mode Setting the 12/24 bit to 0 and 1 specifies the 12-hour mode and the 24-hour mode, respectively. Table of Time Digit Indications 24-hour mode 12-hour mode 24-hour mode 12-hour mode 00 01 02 03 04 05 06 07 08 09 10 11 12 (AM12) 01 (AM 1) 02 (AM 2) 03 (AM 3) 04 (AM 4) 05 (AM 5) 06 (AM 6) 07 (AM 7) 08 (AM 8) 09 (AM 9) 10 (AM10) 11 (AM11) 12 13 14 15 16 17 18 19 20 21 22 23 32 (PM12) 21 (PM 1) 22 (PM 2) 23 (PM 3) 24 (PM 4) 25 (PM 5) 26 (PM 6) 27 (PM 7) 28 (PM 8) 29 (PM 9) 30 (PM10) 31 (PM11) *) Setting the 12/24 bit should precede writing time data. 10 R × 5C338A 2.1-3 CLEN2 32-kHz Clock Output Bit 2 CLEN2 Description 0 1 Enabling the 32-kHz clock circuit Disabling the 32-kHz clock circuit (Default setting) For the R × 5C338A, setting the CLEN2 bit or the CLEN1 bit (D3 in the control register 2) to 0, and the CLKC pin to high specifies generating clock pulses with the oscillation frequency of the 32.768-kHz crystal oscillator for output from the 32KOUT pin. Conversely, setting both the CLEN1 and the CLEN2 bit to 1 or CLKC pin to low specifies disabling (“L”) such output. 2.1-4 TEST Test Bit TEST Description 0 1 Normal operation mode Test mode (Default setting) The TEST bit is used only for testing in the factory and should normally be set to 0. 2.1-5 CT2, CT1, and CT0 Periodic Interrupt Selection Bits Description CT2 CT1 CT0 Waveform mode Interrupt cycle and falling timing 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 — — Pulse Mode Pulse Mode Level Mode Level Mode Level Mode Level Mode Off (“H”) Fixed at low (“L”) 2Hz (Duty cycle of 50%) 1Hz (Duty cycle of 50%) Once per 1 second (Synchronized with second counter increment) Once per minute (at 00 seconds of every minute) Once per hour (at 00 minutes and 00 seconds of every hour) Once per month (at 00 hours, 00 minutes, and 00 seconds of first day of every month) (Default setting) 1) Pulse Mode : 2-Hz and 1-Hz clock pulses are output in synchronization with the increment of the second counter as illustrated in the timing chart on the next page. 11 R × 5C338A 2) Level Mode : periodic interrupt signals are output with selectable interrupt cycle settings of 1 second, 1 minute, 1 hour, and 1 month. The increment of the second counter is synchronized with the falling edge of periodic interrupt signals. For example, periodic interrupt signals with an interrupt cycle setting of 1 second are output in synchronization with the increment of the second counter as illustrated in the timing chart below. 3) When the oscillation adjustment circuit is used, the interrupt cycle will fluctuate once per 20 seconds as follows: Pulse Mode : the “L” period of output pulses will increment or decrement by a maximum of ±3.784ms. For example, 1-Hz clock pulses will have a duty cycle of 50 ±0.3784%. Level Mode : a periodic interrupt cycle of 1 second will increment or decrement by a maximum of ±3.784ms. Relation Between the Mode Waveform and the CTFG Bit • Pulse mode CTFG bit INTR pin Approx. 92µs (Increment of second counter) Rewriting of the second counter *) In the pulse mode, the increment of the second counter is delayed by approximately 92µs from the falling edge of clock pulses. Consequently, time readings immediately after the falling edge of clock pulses may appear to lag behind the time counts of the real-time clocks by approximately 1 second. Rewriting the second counter will reset the other time counters of less than 1 second, driving the INTR pin low. • Level mode CTFG bit INTR pin Setting CTFG bit to 0 (Increment of second counter) (Increment of second counter) Setting CTFG bit to 0 (Increment of second counter) 12 R × 5C338A 2.2 Control Register 2 (at Address Fh) D7 VDSL VDSL 0 D6 VDET VDET 0 D5 SCRATCH SCRATCH 0 D4 XSTP XSTP 1 D3 CLEN1 CLEN1 0 D2 CTFG CTFG 0 D1 WAFG WAFG 0 D0 DAFG DAFG 0 (For writing) (For reading) Default setting* *) Default settings: Default value means read/written values when the XSTP bit is set to “1” due to power-on from 0 volts or supply voltage drop. 2.2-1 VDSL Supply Voltage Monitoring Threshold Selection Bit VDSL Description 0 1 Selecting the supply voltage monitoring threshold setting of 2.1 volts. Selecting the supply voltage monitoring threshold setting of 1.6 volts. (Default setting) The VDSL bit is intended to select the supply voltage monitoring threshold settings. 2.2-2 VDET Supply Voltage Monitoring Result Indication Bit VDET Description 0 1 Indicating supply voltage above the supply voltage monitoring threshold settings. Indicating supply voltage below the supply voltage monitoring threshold settings. (Default setting) Once the VDET bit is set to 1, the supply voltage monitoring circuit will be disabled while the VDET bit will hold the setting of 1. The VDET bit accepts only the writing of 0, which restarts the supply voltage monitoring circuit. Conversely, setting the VDET bit to 1 causes no event. 2.2-3 SCRATCH Scratch Bit SCRATCH Description 0 1 (Default setting) The SCRATCH bit is intended for scratching and accepts the reading and writing of 0 and 1. The SCRATCH bit will be set to 0 when the XSTP bit is set to 1 in the control register 2. 13 R × 5C338A 2.2-4 XSTP Oscillator Halt Sensing Bit XSTP Description 0 1 Sensing a normal condition of oscillation Sensing a halt of oscillation (Default setting) The XSTP bit is for sensing a halt in the oscillation of the crystal oscillator. The oscillation halt sensing circuit operates only when the CE pin is “L”. · The XSTP bit will be set to 1 once a halt in the oscillation of the crystal oscillator is caused by such events as power-on from 0 volts and a drop in supply voltage. The XSTP bit will hold the setting of 1 even after the restart of oscillation. As such, the XSTP bit can be applied to judge the validity of clock and calendar data after power-on or a drop in supply voltage. · When the XSTP bit is set to 1, all bits will be reset to 0 in the oscillation adjustment register, control register 1, and control register 2, stopping the output from the INTR pin and starting the output of 32.768-kHz clock pulses from the 32KOUT pin. (32KOUT output is disabled when CLKC pin is set to low.) · The XSTP bit accepts only the writing of 0, which restarts the oscillation halt sensing circuit. Conversely, setting the XSTP bit to 1 causes no event. 2.2-5 CLEN1 32-kHz Clock Output Bit 1 CLEN1 Description 0 1 Enabling the 32-kHz clock output Disabling the 32-kHz clock output (Default setting) Setting the CLEN1 bit or the CLEN2 bit (D4 in control register 1) to 0, and the CLKC pin to high specifies generating clock pulses with the oscillation frequency of the 32.768-kHz crystal oscillator for output from the 32KOUT pin. Conversely, setting both the CLEN1 bit and the CLEN2 bit to 1 or the CLKC pin to low specifies disabling (“L”) such output. 2.2-6 CTFG Periodic Interrupt Flag Bit CTFG Description 0 1 Periodic interrupt output “H” (OFF) Periodic interrupt output “L” (ON) (Default setting) The CTFG bit is set to 1 when the periodic interrupt signals are output from the INTR pin (“L”). The CTFG bit accepts only the writing of 0 in the level mode, which disables (“H”) the INTR pin until it is enabled (“L”) again in the next interrupt cycle. Conversely, setting the CTFG bit to 1 causes no event. 14 R × 5C338A 2.2-7 WAFG and DAFG Alarm_W Flag Bit and Alarm_D Flag Bit WAFG, DAFG Description 0 1 Indicating a mismatch between current time and preset alarm time Indicating a match between current time and preset alarm time (Default setting) The WAFG and DAFG bits are valid only when the WALE and DALE bits have the setting of 1, which is caused approximately 61µs after any match between current time and preset alarm time specified by the Alarm_W registers and the Alarm_D registers. The WAFG and DAFG bits accept only the writing of 0, which disables (“H”) the INTR pin until it is enabled (“L”) again at the next preset alarm time. Conversely, setting the WAFG and DAFG bits to 1 causes no event. The WAFG and DAFG bits will have the reading of 0 when the alarm interrupt circuit is disabled with the WALE and DALE bits set to 0. The settings of the WAFG and DAFG bits are synchronized with the output of the INTR pin as shown in the timing chart below. Output Relationships Between the WAFG or DAFG Bit and INTR Approx. 61µs Approx. 61µs Settings of WAFG (DAFG) bit Output of INTR pin Writing of 0 to WAFG (DAFG) bit (Match between current time and preset alarm time) (Match between current time and preset alarm time) Writing of 0 to WAFG (DAFG) bit (Match between current time and preset alarm time) 15 R × 5C338A 2.3 Time Counters (at Addresses 0h to 2h) · Time digit display (BCD format) as follows: The second digits range from 00 to 59 and are carried to the minute digit in transition from 59 to 00. The minute digits range from 00 to 59 and are carried to the hour digits in transition from 59 to 00. The hour digits range as shown in “2.1-2 12/24: 12-/24-hour Mode Selection Bit” and are carried to the day-ofmonth and day-of-week digits in transition from PM11 to AM12 or from 23 to 00. · Any writing to the second counter resets divider units of less than 1 second. · Any carry from lower digits with the writing of non-existent time may cause the time counters to malfunction. Therefore, such incorrect writing should be replaced with the writing of existent time data. 2.3-1 Second Counter (at Address 0h) D7 — 0 0 D6 S40 S40 Indefinite D5 S20 S20 Indefinite D4 S10 S10 Indefinite D3 S8 S8 Indefinite D2 S4 S4 Indefinite D1 S2 S2 Indefinite D0 S1 S1 Indefinite (For writing) (For reading) Default settings* 2.3-2 Minute Counter (at Address 1h) D7 — 0 0 D6 M40 M40 Indefinite D5 M20 M20 Indefinite D4 M10 M10 Indefinite D3 M8 M8 Indefinite D2 M4 M4 Indefinite D1 M2 M2 Indefinite D0 M1 M1 Indefinite (For writing) (For reading) Default settings* 2.3-3 Hour Counter (at Address 2h) D7 — 0 0 D6 — 0 0 D5 P/A or H20 P/A or H20 Indefinite D4 H10 H10 Indefinite D3 H8 H8 Indefinite D2 H4 H4 Indefinite D1 H2 H2 Indefinite D0 H1 H1 Indefinite (For writing) (For reading) Default settings* *) Default settings: Default value means read/written values when the XSTP bit is set to “1” due to power-on from 0 volts or supply voltage drop. 16 R × 5C338A 2.4 Day-of-week Counter (at Address 3h) D7 — 0 0 D6 — 0 0 D5 — 0 0 D4 — 0 0 D3 — 0 0 D2 W4 W4 Indefinite D1 W2 W2 Indefinite D0 W1 W1 Indefinite (For writing) (For reading) Default settings* *) Default settings: Default value means read/written values when the XSTP bit is set to “1” due to power-on from 0 volts or supply voltage drop. · The day-of-week counter is incremented by 1 when the day-of-week digits are carried to the day-of-month digits. · Day-of-week display (incremented in septimal notation): (W4, W2, W1) = (0, 0, 0) → (0, 0, 1) → ... → (1, 1, 0) → (0, 0, 0) · Correspondences between days of the week and the day-of-week digits are user-definable (e.g. Sunday = 0, 0, 0) · The writing of (1, 1, 1) to (W4, W2, W1) is prohibited except when days of the week are unused. 2.5 Calendar Counters (at Address 4h to 6h) · The calendar counters are configured to display the calendar digits in BCD format by using the automatic calendar function as follows: The day-of-month digits (D20 to D1) range from 1 to 31 for January, March, May, July, August, October, and December; from 1 to 30 for April, June, September, and November; from 1 to 29 for February in leap years; from 1 to 28 for February in ordinary years. The day-of-month digits are carried to the month digits in reversion from the last day of the month to 1. The month digits (MO10 to MO1) range from 1 to 12 and are carried to the year digits in reversion from 12 to 1. The year digits (Y80 to Y1) range from 00 to 99 (00, 04, 08, ... , 92, and 96 in leap years) and are carried to the 19/20 digits in reversion from 99 to 00. The 19/20 digits cycle between 0 and 1 in reversion from 99 to 00 in the year digits. · Any carry from lower digits with the writing of non-existent calendar data may cause the calendar counters to malfunction. Therefore, such incorrect writing should be replaced with the writing of existent calendar data. 2.5-1 Day-of-month Counter (at Address 4h) D7 — 0 0 D6 — 0 0 D5 D20 D20 Indefinite D4 D10 D10 Indefinite D3 D8 D8 Indefinite D2 D4 D4 Indefinite D1 D2 D2 Indefinite D0 D1 D1 Indefinite (For writing) (For reading) Default settings* 2.5-2 Month Counter + Century Bit (at Address 5h) D7 19/20 19/20 Indefinite D6 — 0 0 D5 — 0 0 D4 MO10 MO10 Indefinite D3 MO8 MO8 Indefinite D2 MO4 MO4 Indefinite D1 MO2 MO2 Indefinite D0 MO1 MO1 Indefinite (For writing) (For reading) Default settings* 17 RS5C338A 2.5-3 Year Counter (at Address 6h) D7 Y80 Y80 Indefinite D6 Y40 Y40 Indefinite D5 Y20 Y20 Indefinite D4 Y10 Y10 Indefinite D3 Y8 Y8 Indefinite D2 Y4 Y4 Indefinite D1 Y2 Y2 Indefinite D0 Y1 Y1 Indefinite (For writing) (For reading) Default settings* *) Default settings: Default value means read/written values when the XSTP bit is set to “1” due to power-on from 0 volts or supply voltage drop. 2.6 Oscillation Adjustment Register (at Address 7h) D7 (0) (0) 0 D6 F6 F6 0 D5 F5 F5 0 D4 F4 F4 0 D3 F3 F3 0 D2 F2 F2 0 D1 F1 F1 0 D0 F0 F0 0 (For writing) (For reading) Default settings* *) Default settings: Default value means read/written values when the XSTP bit is set to “1” due to power-on from 0 volts or supply voltage drop. 2.6-1 (0) Bit The (0) bit should be set to 0 to allow writing to the oscillation adjustment register. The (0) bit will be set to 0 when the XSTP bit is set to 1 in the control register 2. 2.6-2 F6 to F0 The oscillation adjustment circuit is configured to change time counts of 1 second on the basis of the settings of the oscillation adjustment register when the second digits read 00, 20, or 40 seconds. Normally, the second counter is incremented once per 32768 32.768-kHz clock pulses generated by the crystal oscillator. Writing to the F6 to F0 bits activates the oscillation adjustment circuit. · The oscillation adjustment circuit will not operate with the same timing (00, 20, or 40 seconds) as the timing of writing to the oscillation adjustment register. · The F6 bit setting of 0 causes an increment of time counts by ((F5, F4, F3, F2, F1, F0) –1) × 2. The F6 bit setting of 1 causes a decrement of time counts by (( F5, F4, F3, F2, F1, F0) +1) × 2. The settings of “*, 0, 0, 0, 0, 0, *” ( “*” representing either “0” or “1” ) in the F6, F5, F4, F3, F2, F1, and F0 bits cause neither an increment nor decrement of time counts. Example: When the second digits read 00, 20, or 40, the settings of “0, 0, 0, 0, 1, 1, 1” in the F6, F5, F4, F3, F2, F1, and F0 bits cause an increment of the current time counts of 32768 by (7–1) × 2 to 32780 (a current time count loss). When the second digits read 00, 20, or 40, the settings of “0, 0, 0, 0, 0, 0, 1” in the F6, F5, F4, F3, F2, F1, and F0 bits cause neither an increment nor a decrement of the current time counts of 32768. When the second digits read 00, 20, or 40, the settings of “1, 1, 1, 1, 1, 1, 0” in the F6, F5, F4, F3, F2, F1, and F0 bits cause a decrement of the current time counts of 32768 by (–2) × 2 to 32764 (a current time count gain). 18 R × 5C338A An increase of two clock pulses once per 20 seconds causes a time count loss of approximately 3ppm (2 / (32768 × 20=3.051ppm). Conversely, a decrease of two clock pulses once per 20 seconds causes a time count gain of 3ppm. Consequently, deviations in time counts can be corrected with a precision of ±1.5ppm. Note that the oscillation adjustment circuit is configured to correct deviations in time counts and not the oscillation frequency of the 32.768kHz clock pulses. For further details, see “USAGE, 2.4 Oscillation Adjustment Circuit”. 2.7 Alarm_W Register (at Address 8h to Ah) 2.7-1 Alarm_W Minute Register (at Address 8h) D7 — 0 0 D6 WM40 WM40 D5 WM20 WM20 D4 WM10 WM10 D3 WM8 WM8 D2 WM4 WM4 D1 WM2 WM2 D0 WM1 WM1 (For writing) (For reading) Default settings* Indefinite Indefinite Indefinite Indefinite Indefinite Indefinite Indefinite 2.7-2 Alarm_W Hour Register (at Address 9h) D7 — 0 0 D6 — 0 0 D5 WH20,WP/A WH20,WP/A D4 WH10 WH10 D3 WH8 WH8 D2 WH4 WH4 D1 WH2 WH2 D0 WH1 WH1 (For writing) (For reading) Default settings* Indefinite Indefinite Indefinite Indefinite Indefinite Indefinite 2.7-3 Alarm_W Day-of-week Register (at Address Ah) D7 — 0 0 D6 WW6 WW6 D5 WW5 WW5 D4 WW4 WW4 D3 WW3 WW3 D2 WW2 WW2 D1 WW1 WW1 D0 WW0 WW0 (For writing) (For reading) Default settings* Indefinite Indefinite Indefinite Indefinite Indefinite Indefinite Indefinite *) Default settings: Default value means read/written values when the XSTP bit is set to “1” due to power-on from 0 volts or supply voltage drop. · The D5 bit of the Alarm_W hour register represents WP/A when the 12-hour mode is selected (0 for a.m. and 1 for p.m.). and WH20 when the 24-hour mode is selected (tens in the hour digits). · The Alarm _W registers should not have any non-existent alarm time settings. (Note that any mismatch between current time and preset alarm time specified by the Alarm_W registers may disable the alarm circuit.) · When the 12-hour mode is selected, the hour digits read 12 and 32 for 0 a.m. and 0 p.m., respectively (see “2.1-2 12/24: 12-/24-hour Mode Selection Bit”). · WW0 to WW6 correspond to W4, W2, and W1 of the day-of-week counter with settings ranging from (0, 0, 0) to (1, 1, 0). · WW0 to WW6 with respective settings of 0 disable the outputs of the Alarm_W registers. 19 R × 5C338A Example of Alarm Time Setting Day-of-week Preset alarm time 12-hour mode 24-hour mode Sun. Mon. Tue. Wed. Thu. Fri. Sat. WW0 WW1 WW2 WW3 WW4 WW5 WW6 00:00 a.m. on all days 01:30 a.m. on all days 11:59 a.m. on all days 00:00 p.m. on Mondays to Fridays 01:30 p.m. on Sundays 11:59 p.m. on Mondays, Wednesdays, and Fridays 1 1 1 0 1 0 1 1 1 1 0 1 1 1 1 1 0 0 1 1 1 1 0 1 1 1 1 1 0 0 1 1 1 1 0 1 1 1 1 0 0 0 10-hour 1-hour 10-min 1-min 10-hour 1-hour 10-min 1-min 1 0 1 3 2 3 2 1 1 2 1 1 0 3 5 0 3 5 0 0 9 0 0 9 0 0 1 1 1 2 0 1 1 2 3 3 0 3 5 0 3 5 0 0 9 0 0 9 Note that the correspondence between WW0 to WW6 and the days of the week shown in the above table is only an example and not mandatory. 2.8 Alarm_D Register (at Address Bh and Ch) 2.8-1 Alarm_D Minute Register (at Address Bh) D7 — 0 0 D6 DM40 DM40 D5 DM20 DM20 D4 DM10 DM10 D3 DM8 DM8 D2 DM4 DM4 D1 DM2 DM2 D0 DM1 DM1 (For writing) (For reading) Default settings* Indefinite Indefinite Indefinite Indefinite Indefinite Indefinite Indefinite 2.8-2 Alarm_D Hour Register (at Address Ch) D7 — 0 0 D6 — 0 0 D5 DH20,DP/A DH20,DP/A D4 DH10 DH10 D3 DH8 DH8 D2 DH4 DH4 D1 DH2 DH2 D0 DH1 DH1 (For writing) (For reading) Default settings* Indefinite Indefinite Indefinite Indefinite Indefinite Indefinite *) Default settings: Default value means read/written values when the XSTP bit is set to “1” due to power-on from 0 volts or supply voltage drop. · The D5 bit represents DP/A when the 12-hour mode is selected (0 for a.m. and 1 for p.m.). and DH20 when the 24hour mode is selected (tens in the hour digits). · The Alarm_D registers should not have any non-existent alarm time settings. (Note that any mismatch between current time and preset alarm time specified by the Alarm_D registers may disable the alarm circuit.) · When the 12-hour mode is selected, the hour digits read 12 and 32 for 0 a.m. and 0 p.m., respectively (see “2.1-2 12/24: 12-/24-hour Mode Selection Bit”). 20 R × 5C338A USAGES 1. Data Transfer Formats 1.1 Timing Between CE Pin Transition and Data Input/Output The R × 5C338A adopt a 3-wire serial interface by which it uses the CE (Chip Enable), SCLK (Serial Clock), and SIO (Serial Input/Output), pins to receive and send data to and from the CPU. The 3-wire serial interface provides two types of input/output timings with which the output and input from the SIO pin output and input are synchronized with the rising and falling edges of the SCLK pin input, respectively, and vice versa. The R × 5C338A are configured to select either one of two different input/output timings depending on the level of the SCLK pin in the low to high transition of the CE pin. Namely, when the SCLK pin is held low in the low to high transition of the CE pin, the models will select the timing with which the output and input from the SIO pin are synchronized with the rising and falling edges of the SCLK pin input, respectively, as illustrated in the timing chart below. CE SCLK SIO (Input to the real-time clock) SIO (Output from the real-time clock) tCES tDS tDH tRD Conversely, when the SCLK pin is held high in the low to high transition of the CE pin, the models will select the timing with which the output and input from the SIO pin are synchronized with the falling and rising edges of the SCLK pin input, respectively as illustrated in the timing chart below. CE SCLK SIO (Input to the real-time clock) SIO (Output from the real-time clock) tCES tDS tDH tRD 21 R × 5C338A 1.2 Data Transfer Formats Data transfer is commenced in the low to high transition of the CE pin input and completed in its high to low transition. Data transfer is conducted serially in multiple units of 1 byte (8 bits). The former 4 bits are used to specify in the address pointer a head address with which data transfer is to be commenced from the host. The latter 4 bits are used to select either reading data transfer or writing data transfer and set the transfer format register to specify an appropriate data transfer format. All data transfer formats are designed to transfer the most significant bit (MSB) first. CE 1 2 3 4 5 6 7 8 1 2 3 SCLK SIO A3 A2 A1 A0 C3 C2 C1 C0 D7 D6 D3 D2 D1 D0 Setting the address pointer Setting the transfer format register Writing data transfer / Reading data transfer Two types of data transfer formats are available for reading data transfer and writing data transfer each. 1.3 Writing Data Transfer Formats 1.3-1 1-byte Writing Data Transfer Format The first type of writing data transfer format is designed to transfer 1-byte data at a time and can be selected by specifying in the address pointer a head address with which writing data transfer is to be commenced and then writing the setting of 8h to the transfer format register. This 1-byte writing data transfer can be completed by driving the CE pin low or continued by specifying a new head address in the address pointer and setting the transfer format. Example of 1-byte Writing Data Transfer (For Writing Data to Addresses Fh and 7h) CE SIO 11111000 Specifying Fh Setting 8h in the address in the transfer pointer format register Data Writing data to address Fh 01111000 Specifying 7h Setting 8h in the address in the transfer pointer format register Data Writing data to address 7h Data transfer from the host Data transfer from the real-time clocks 22 R × 5C338A 1.3-2 Burst Writing Data Transfer Format The second type of writing data transfer format is designed to transfer a sequence of data serially and can be selected by specifying in the address pointer a head address with which writing data transfer is to be commenced and then writing the setting of 0h to the transfer format register. The address pointer is incremented for each transfer of 1-byte data and cycled from Fh to 0h. This burst writing data transfer can be completed by driving the CE pin low. Example of Burst Writing Data Transfer (For Writing Data to Addresses Eh, Fh, and Oh) CE SIO 11100000 Specifying Eh Setting 0h in the address in the transfer pointer format register Data Writing data to address Eh Data Writing data to address Fh Data Writing data to address 0h Data transfer from the host Data transfer from the real-time clocks 1.4 Reading Data Transfer Formats 1.4-1 1-byte Reading Data Transfer Format The first type of reading data transfer format is designed to transfer 1-byte data at a time and can be selected by specifying in the address pointer a head address with which reading data transfer is to be commenced and then the setting of writing Ch to the transfer format register. This 1-byte reading data transfer can be completed by driving the CE pin low or continued by specifying a new head address in the address pointer and setting the transfer format. Example of 1-byte Reading Data Transfer (For Reading Data from Addresses Eh and 2h) CE SIO 11101100 Specifying Eh Setting Ch in the address in the transfer pointer format register Data Reading data from address Eh 00101100 Specifying 2h Setting Ch in the address in the transfer format register pointer Data Reading data from address 2h Data transfer from the host Data transfer from the real-time clocks 23 R × 5C338A 1.4-2 Burst Reading Data Transfer Format The second type of reading data transfer format is designed to transfer a sequence of data serially and can be selected by specifying in the address pointer a head address with which reading data transfer is to be commenced and then writing the setting of 4h to the transfer format register. The address pointer is incremented for each transfer of 1-byte data and cycled from Fh to 0h. This burst reading data transfer can be completed by driving the CE pin low. Example of Burst Reading Data Transfer (For Reading Data from Addresses Fh, 0h, and 1h) CE SIO 11110100 Specifying Fh Setting 4h in the address in the transfer pointer format register Data Reading data from address Fh Data Reading data from address 0h Data Reading data from address 1h Data transfer from the host Data transfer from the real-time clocks 1.4-3 Combination of 1-byte Reading and Writing Data Transfer Formats The 1-byte reading and writing data transfer formats can be combined together and further followed by any other data transfer format. Example of Combination of 1-byte Reading and Writing Data Transfer (For Reading and Writing Data from and to Address Fh) CE SIO 11111100 Specifying Fh Setting Ch in the address in the transfer pointer format register Data Reading data from address Fh 11111000 Specifying Fh Setting 8h in the address in the transfer pointer format register Data Writing data to address Fh Data transfer from the host Data transfer from the real-time clocks The reading and writing data transfer formats correspond to the settings in the transfer format register as shown in the table below. 1-byte transfer Burst (Successive) transfer Writing data transfer (for writing to real-time clock) Reading data transfer (for reading from real-time clock) 8h (1,0,0,0) Ch (1,1,0,0) 0h (0,0,0,0) 4h (0,1,0,0) 24 R × 5C338A 1.5 Considerations in Reading and Writing Time Data Any carry to the second digits in the process of reading or writing time data may cause reading or writing erroneous time data. For example, suppose a carry out of 13:59:59 into 14:00:00 occurs in the process of reading time data in the middle of shifting from the minute digits to the hour digits. At this moment, the second digits, the minute digits, and the hour digits read 59 seconds, 59 minutes, and 14 hours, respectively (indicating 14:59:59) to cause the reading of time data deviating from actual time virtually 1 hour. A similar error also occurs in writing time data. To prevent such errors in reading and writing time data, the R × 5C338A have the function of temporarily locking any carry of the time digits during the high interval of the CE pin and unlocking such a carry in its high to low transition. Note that a carry of the second digits can be locked for only 1 second, during which time the CE pin should be driven low. 13:59:59 Actual time CE MAX.61µs Time counts within real-time clocks 13:59:59 14:00:00 14:00:01 14:00:00 14:00:01 The effective use of this function requires the following considerations in reading and writing time data: (1) Hold the CE pin high in each session of reading or writing time data. (2) Ensure that the high interval of the CE pin lasts within 1 second. Should there be any possibility of the host going down in the process of reading or writing time data, make arrangements in the peripheral circuitry as to drive the CE pin low or open at the moment that the host actually goes down. (3) Leave a time span of 31µs or more from the low to high transition of the CE pin to the start of access to addresses 0h to 6h in order that any ongoing carry of the time digits may be completed within this time span. (4) Leave a time span of 61µs or more from the high to low transition of the CE pin to its low to high transition in order that any ongoing carry of the time digits during the high interval of the CE pin may be adjusted within this time span. (5) The considerations listed in (1), (3), and (4) above are not required when the process of reading or writing time data is obviously free from any carry of the time digits (e.g. reading or writing time data in synchronization with the periodic interrupt function in the level mode or the alarm interrupt function). Good and bad examples of reading and writing time data are illustrated on the next page. 25 R × 5C338A Good Example Time span of 31µs or more CE SIO F4h Data Data Reading from the second counter at address 0h Data Reading from the minute counter at address 1h Data Reading from the hour counter at address 2h Any address other than addresses 0h to 6h permits of immediate reading or writing without requiring a time span of 31µs. Specifying Fh in the Reading from the address pointer control register 2 Writing 4h to the at address Fh transfer format register Bad Example (1) (Where the CE pin is once driven low in the process of reading time data) Time span of 31µs or more CE SIO 0Ch Specifying 0h in the address pointer Writing Ch in the transfer format register Data Reading from the second counter at address 0h 14h Specifying 1h in the address pointer Writing 4h in the transfer format register Data Reading from the minute counter at address 1h Data Reading from the hour counter at address 2h Time span of 31µs or more Bad Example (2) (Where a time span of less than 31µs is left until the start of the process of writing time data) Time span of less than 31µs CE SIO F0h Data Data Writing to the second counter at address 0h Data Writing to the minute counter at address 1h Data Writing to the hour counter at address 2h Specifying Fh in the Writing to the address pointer control register 2 Writing 0h to the at address Fh transfer format register Bad Example (3) (Where a time span of less than 61µs is left between the adjacent processes of reading time data) Time span of less than 61µs CE SIO 0Ch Data 0Ch Data Specifying 0h in the Reading from the second counter address pointer at address 0h Writing Ch to the transfer format register 0Ch Specifying 0h in the Reading from the address pointer second counter Writing Ch to the at address 0h transfer format register Data Data transfer from the host Data transfer from the real-time clocks 26 R × 5C338A 2. Configuration of Oscillation Circuit and Correction of Time Count Deviations 2.1 Configuration of Oscillating Circuit R×5C338A VDD 10 OSCIN 32kHz 8 RD CD OSCOUT A VDD Typical externally-equipped element X'tal: 32.768kHz (R1=30kΩ TYP.) (CL=6pF to 8pF) Standard values of internal elements RF=15MΩ TYP. RD=120kΩ TYP. CG, CD=12pF TYP. 9 RF CG The oscillation circuit is driven at a constant voltage of approximately 1.2 volts relative to the level of the VSS pin input. As such, it is configured to generate an oscillating waveform with a peak-to-peak voltage on the order of 1.2 volts on the positive side of the VSS pin input. Considerations in Handling Crystal Oscillators Generally, crystal oscillators have basic characteristics including an equivalent series resistance (R 1) indicating the ease of their oscillation and a load capacitance (CL) indicating the degree of their center frequency. Particularly, crystal oscillators intended for use with the R × 5C338A are recommended to have a typical R1 value of 30kΩ and a typical CL value of 6 to 8pF. To confirm these recommended values, contact the manufacturers of crystal oscillators intended for use with these particular models. Considerations in Installing Components around the Oscillation Circuit 1) Install the crystal oscillator in the closest possible vicinity to the real-time clock ICs. 2) Avoid laying any signal lines or power lines in the vicinity of the oscillation circuit (particularly in the area marked “←A→” in the above figure). 3) Apply the highest possible insulation resistance between the OSCIN and OSCOUT pins and the printed circuit board. 4) Avoid using any long parallel lines to wire the OSCIN and OSCOUT pins. 5) Take extreme care not to cause condensation, which leads to various problems such as oscillation halt. Other Relevant Considerations 1) For external input of 32.768-kHz clock pulses to the OSCIN pin: DC coupling: Prohibited due to an input level mismatch. AC coupling: Permissible except that the oscillation halt sensing circuit does not guarantee perfect operation because it may cause sensing errors due to such factors as noise. 2) To maintain stable characteristics of the crystal oscillator, avoid driving any other IC through 32.768-kHz clock pulses output from the OSCOUT pin. 27 R × 5C338A 2.2 Measurement of Oscillation Frequency R×5C338A VDD OSCIN OSCOUT CLKC 32KOUT VSS Frequency counter 32.768kHz *1) The R × 5C338A are configured to generate 32.768-kHz clock pulses for output from the 32KOUT pin at power-on conditionally on setting the XSTP bit to 1 in the control register 2. *2) A frequency counter with 6 (more preferably 7) or more digits on the order of 1ppm is recommended for use in the measurement of the oscillation frequency of the oscillation circuit. *3) The CLKC input should be connected to the VDD pin with a pull-up resistor. 2.3 Adjustment of Oscillation Frequency The oscillation frequency of the oscillation circuit can be adjusted by varying procedures depending on the usage of the R × 5C338A in the system into which they are to be built and on the allowable degree of time count errors. The flow chart below serves as a guide to selecting an optimum oscillation frequency adjustment procedure for the relevant system. Start Use 32-kHz clock circuit? YES NO Allowable time count precision is on order of oscillation frequency variations of crystal oscillator *1 plus frequency variations of real-time clock? *2, *3 YES YES To Course (A) NO To Course (B) Use 32-kHz clock circuit without regard to its frequency precision? To Course (C) NO Allowable time count precision is on order of oscillation frequency variations of crystal oscillator *1 plus frequency variations of real-time clock? *2, *3 YES NO To Course (D) *1) Generally, crystal oscillators for commercial use are classified in terms of their center frequency depending on their load capacitance (CL) and further divided into ranks on the order of ±10, ± 20, and ±50 ppm depending on the degree of their oscillation frequency variations. *2) Basically, the R × 5C338A are configured to cause frequency variations on the order of ±5 to ±10ppm at normal temperature. *3) Time count precision as referred to in the above flow chart is applicable to normal temperature and actually affected by the temperature characteristics and other properties of crystal oscillators. 28 R × 5C338A Course (A) When the time count precision of each real-time clock is not to be adjusted, the crystal oscillator intended for use with that real-time clock may have any CL value requiring no presetting. The crystal oscillator may be subject to frequency variations which are selectable within the allowable range of time count precision. Several crystal oscillators and real-time clocks should be used to find the center frequency of the crystal oscillators by the method described in “2.2 Measurement of Oscillation Frequency” and then calculate an appropriate oscillation adjustment value by the method described in “2.4 Oscillation Adjustment Circuit” for writing this value to the R × 5C338A. Course (B) When the time count precision of each real-time clock is to be adjusted within the oscillation frequency variations of the crystal oscillator plus the frequency variations of the real-time clock ICs, it becomes necessary to correct deviations in the time count of each real-time clock by the method described in “2.4 Oscillation Adjustment Circuit”. Such oscillation adjustment provides crystal oscillators with a wider range of allowable settings of their oscillation frequency variations and their CL values. The real-time clock IC and the crystal oscillator intended for use with that real-time clock IC should be used to find the center frequency of the crystal oscillator by the method described in “2.2 Measurement of Oscillation Frequency” and then confirm the center frequency thus found to fall within the range adjustable by the oscillation adjustment circuit before adjusting the oscillation frequency of the oscillation circuit. At normal temperature, the oscillation frequency of the oscillator circuit can be adjusted by up to approximately ±1.5ppm. Course (C) Course (C) together with Course (D) requires adjusting the time count precision of each real-time clock as well as the frequency of 32.768-kHz clock pulses output from the 32KOUT pin. Normally, the oscillation frequency of the crystal oscillator intended for use with the real-time clocks should be adjusted by adjusting the oscillation stabilizing capacitors CG and CD connected to both ends of the crystal oscillator. The R × 5C338A, which incorporate the CG and the CD, require adjusting the oscillation frequency of the crystal oscillator through its CL value. Generally, the relationship between the CL value and the CG and CD values can be represented by the following equation: CL = CG × CD + CS CG + CD where “CS” represents the floating capacity of the printed circuit board The crystal oscillator intended for use with the R × 5C338A is recommended to have the CL value on the order of 6 to 8pF. Its oscillation frequency should be measured by the method described in “2.2 Measurement of Oscillation Frequency”. Any crystal oscillator found to have an excessively high or low oscillation frequency (causing a time count gain or loss, respectively) should be replaced with another one having a smaller and greater C L value, respectively until another one having an optimum CL value is selected. In this case, the bit settings disabling the oscillation adjustment circuit (see “2.4 Oscillation Adjustment Circuit”) should be written to the oscillation adjustment register. 29 R × 5C338A Another advisable way to select a crystal oscillator having an optimum CL value is to contact the manufacturer of the crystal oscillator intended for use with the R × 5C338A. Incidentally, the high oscillation frequency of the crystal oscillator can also be adjusted by adding an external oscillation stabilization capacitor CGOUT as illustrated in the diagram below. R × 5C338A VDD 10 OSCIN 32kHz 8 RD CD OSCOUT CGOUT *1 VDD *1) The CGOUT should have a capacitance ranging from 0 to 15pF. 9 RF CG Course (D) It is necessary to select the crystal oscillator in the same manner as in Course (C) as well as correct errors in the time count of each real-time clock in the same manner as in Course (B) by the method described in “2.4 Oscillation Adjustment Circuit”. 2.4 Oscillation Adjustment Circuit The oscillation adjustment circuit can be used to correct a time count gain or loss with high precision by varying the number of 1-second clock pulses once per 20 seconds. When such oscillation adjustment is not to be made, the oscillation adjustment circuit can be disabled by writing the settings of “*, 0, 0, 0, 0, 0, *” (“*” representing “0” or “1”) to the F6, F5, F4, F3, F2, F1, and F0 bits in the oscillation adjustment circuit. Conversely, when such oscillation adjustment is to be made, an appropriate oscillation adjustment value can be calculated by the equation below for writing to the oscillation adjustment circuit. 2.4-1 When Oscillation Frequency *1 is Higher than Target Frequency *2 (There is a Time Count Gain) Oscillation adjustment value*3 = . (Oscillation frequency – Target frequency + 0.1) Oscillation frequency × 3.051 × 10–6 . (Oscillation frequency – Target frequency) × 10 + 1 = *1) *2) Oscillation frequency: Target frequency: Frequency of clock pulses output from the 32KOUT pin at normal temperature in the manner described in “2.2 Measurement of Oscillation Frequency”. Desired frequency to be set. Generally, a 32.768-kHz crystal oscillator has such temperature characteristics as to have the highest oscillation frequency at normal temperature. Consequently, the crystal oscillator is recommended to have target frequency settings on the order of 32.768 to 32.76810kHz (+3.05ppm relative to 32.768kHz). Note that the target frequency differs depending on the environment or location where the equipment incorporating the real-time clocks is expected to be operated. *3) Oscillation adjustment value: Value that is to be finally written to the F0 to F6 bits in the oscillation adjustment register and is represented in 7-bit coded decimal notation. 30 R × 5C338A 2.4-2 When Oscillation Frequency is Equal to Target Frequency (There is Neither a Time Count Gain nor a Time Count Loss) Writing the oscillation adjustment value setting of “0”, “+1”, “–64”, or “–63” to the oscillation adjustment register disables the oscillation adjustment circuit. 2.4-3 When Oscillation Frequency is Lower than Target Frequency (There is a Time Count Loss) Oscillation adjustment value*3 = . (Oscillation frequency – Target frequency) Oscillation frequency × 3.051 × 10–6 . (Oscillation frequency – Target frequency) × 10 = Oscillation adjustment value calculations are exemplified below. (1) For an oscillation frequency of 32768.85Hz and a target frequency of 32768.05Hz: Oscillation adjustment value = (32768.85 – 32768.05 + 0.1) / (32768.85 × 3.051 × 10–6) .= (32768.85 – 32768.05) × 10 + 1 .= 9.001 = 9 . . In this instance, write the settings of “0, 0, 0, 1, 0, 0, 1” to the F6, F5, F4, F3, F2, F1, and F0 bits in the oscillation adjustment register. Thus, an appropriate oscillation adjustment value in the presence of any time count gain represents a distance from 01h. (2) For an oscillation frequency of 32763.95Hz and a target frequency of 32768.05Hz: Oscillation adjustment value = (32763.95 – 32768.05) / (32763.95 × 3.051 × 10–6) .= (32763.95 – 32768.05) × 10 . = –41.015 = –41 . . To represent an oscillation adjustment value of –41 in 7-bit coded decimal notation, subtract 41(29h) from 128(80h) to obtain 57h. In this instance, write the settings of “1, 0, 1, 0, 1, 1, 1” in the F6, F5, F4, F3, F2, F1, and F0 bits in the oscillation adjustment register. Thus, an appropriate oscillation adjustment value in the presence of any time count loss represents a distance from 80h. Oscillation adjustment involves an adjustment differential of approximately ±1.5ppm from the target frequency at normal temperature. Notes 1) Oscillation adjustment does not affect the frequency of 32.768-kHz clock pulses output from the 32KOUT pin. 2) Oscillation adjustment value range: When the oscillation frequency is higher than the target frequency (causing a time count gain), an appropriate time count gain ranges from –3.05ppm to –189.2ppm with the settings of “0, 0, 0, 0, 0, 1, 0” to “0, 1, 1, 1, 1, 1, 1” written to the F6, F5, F4, F3, F2, F1, and F0 bits in the oscillation adjustment register, thus allowing correction of a time count gain of up to +189.2ppm. Conversely, when the oscillation frequency is lower than the target frequency (causing a time count loss), an appropriate time count gain ranges from +3.05ppm to +189.2ppm with the settings of “1, 1, 1, 1, 1, 1, 1” to “1, 0, 0, 0, 0, 1, 0” written to the F6, F5, F4, F3, F2, F1, and F0 bits in the oscillation adjustment register, thus allowing correction of a time count loss of up to –189.2ppm. 31 R × 5C338A 3. Oscillation Halt Sensing and Supply Voltage Monitoring The oscillation halt sensing circuit is configured to record a halt in the oscillation of 32.768-kHz clock pulses. The supply voltage monitoring circuit is configured to record a drop in supply voltage below a threshold voltage of 2.1 or 1.6 volts. For these functions, the real-time clock has two flag bits (i.e. the XSTP bit for the former and the VDET bit for the latter) in which 1 is set once and this setting is maintained until 0 is written. When the XSTP bit is set to 1 for the oscillation halt sensing circuit, the VDET bit is reset to 0 for the supply voltage monitoring circuit. The relationship between the XSTP and VDET bits is shown in the table below. The Oscillation halt sensing circuit operates only when the CE pin is Low. The sensing result is maintained after the CE pin changes from “L” to “H” (See “6.4 Connection of CE Pin”). XSTP VDET Conditions of supply voltage and oscillation 0 0 1 0 1 No drop in supply voltage below threshold voltage and no halt in oscillation Drop in supply voltage below threshold voltage and no halt in oscillation Halt on oscillation Threshold voltage (2.1 or 1.6 volts) * Supply voltage Oscillation by 32.768-kHz clock pulses Normal voltage detector Supply voltage monitoring (VDET) Oscillation halt sensing (XSTP) Internal initialization period (1 to 2 seconds) Setting XSTP and VDET bits to 0 Setting VDET bit to 0 Setting XSTP and VDET bits to 0 When the XSTP bit is set to 1 in the control register 2, the (0), F6 to F0, WALE, DALE, 12/24, CLEN2, TEST, CT2, CT1, CT0, VDSL, VDET, SCRATCH, CLEN1, CTFG, WAFG, and DAFG bits are reset to 0 in the oscillation adjustment register, the control register 1, and the control register 2. When the CE pin is “H” at power on from 0 volts, the XSTP bit is undefined, and the above bits are undefined (See “6.4 Connection of CE Pin”). The XSTP bit is also set to 1 at power-on from 0 volts. Note that the XSTP bit may be locked to 0 and the internal register broken upon instantaneous power-down. 32 R × 5C338A Considerations in Using Oscillation Halt Sensing Circuit Be sure to prevent the oscillation halt sensing circuit from malfunctioning by preventing the following: 1) Instantaneous power-down on the VDD 2) Condensation on the crystal oscillator 3) On-board noise to the crystal oscillator 4) Applying to individual pins voltage exceeding their respective maximum ratings In particular, note that the XSTP bit may fail to be set to 1 in the presence of any applied supply voltage as illustrated below in such events as backup battery installation. Further, give special considerations to prevent excessive chattering to power supply. VDD < Supply Voltage Sensing Circuit > The supply voltage monitoring circuit is configured to conduct a sampling operation during an interval of 7.8ms per second to check for a drop in supply voltage below a threshold voltage of 2.1 or 1.6 volts for the VDSL bit setting of 0 (the default setting) or 1, respectively, in the control register 2, thus minimizing supply current requirements as illustrated in the timing chart below. This circuit suspends a sampling operation once the VDET bit is set to 1 in the control register 2. VDD XSTP 7.8ms Internal initialization period (1 or 2 seconds) Threshold voltage of 2.1 or 1.6 volts 1s Sampling operation by supply voltage monitoring circuit VDET (D6 at address Fh) Setting 0 to XSTP and VDET bits Setting VDET bit to 0 33 R × 5C338A 4. Alarm and Periodic Interrupt The R × 5C338A incorporate the alarm circuit and the periodic interrupt circuit that are configured to generate alarm signals and periodic interrupt signals, respectively, for output from the INTR pin as described below. 1)Alarm Circuit The alarm interrupt circuit is configured to generate alarm signals for output from the INTR, which is driven low (enabled) upon the occurrence of a match between current time read by the time counters (the day-of-week, hour, and minute counters) and alarm time preset by the alarm registers (the Alarm_W registers intended for the dayof-week, hour, and minute digit settings and the Alarm_D registers intended for the hour and minute digit settings). 2)Periodic Interrupt Circuit The periodic interrupt circuit is configured to generate either clock pulses in the pulse mode or interrupt signals in the level mode for output from the INTR pin depending on the CT2, CT1, and CT0 bit settings in the control register 1. The above two types of interrupt signals are monitored by the flag bits (i.e. the WAFG, DAFG, and CTFG bits in the control register 2) and enabled or disabled by the enable bits (i.e. the WALE, DALE, CT2, CT1, and CT0 bits in the control register 1) as listed in the table below. Flag bits Enable bits Alarm signals (under control of Alarm_W registers) Alarm signals (under control of Alarm_D registers) Periodic interrupt signals WAFG bit (D1 at Address Fh) DAFG bit (D0 at Address Fh) CTFG bit (D2 at Address Fh) WALE bit (D7 at Address Eh) DALE bit (D6 at Address Eh) CT2, CT1, and CT0 bits (D2 to D0 at Address Eh) (these bit settings of 0 disable the periodic interrupt circuit) · At power-on, when the WALE, DALE, CT2, CT1, and CT0 bits are set to 0 in the control register 1, the INTR pin is driven high (disabled). · When two or more types of interrupt signals are output simultaneously from the INTR pin, the output from the INTR pin becomes an OR waveform of their negative logic. Example: Combined Output of Alarm Interrupt Signals from the INTR pin Under Control of Alarm_D and Alarm_W Registers Alarm_W Alarm_D INTR In this event, which type of interrupt signal is output from the INTR pin can be confirmed by reading the WAFG, DAFG, and CTFG bit settings in the control register 2. 34 R × 5C338A 4.1 Alarm Interrupt The alarm circuit is controlled by the enable bits (i.e. the WALE and DALE bits in the control register 1) and the flag bits (i.e. the WAFG and DAFG bits in the control register 2). The enable bits can be used to enable this circuit when set to 1 and to disable it when set to 0. When intended for reading, the flag bits can be used to monitor alarm interrupt signals. When intended for writing, the flag bits will cause no event when set to 1 and will drive high (disable) the alarm circuit when set to 0. The enable bits will not be affected even when the flag bits are set to 0. In this event, therefore, the alarm circuit will continue to function until it is driven low (enabled) upon the next occurrence of a match between current time and preset alarm time. The alarm function can be set by presetting desired alarm time in the alarm registers (the Alarm_W registers for the day-of-week digit settings and both the Alarm_W registers and the Alarm_D registers for the hour and minute digit settings) with the WALE and DALE bits once set to 0 and then to 1 in the control register 1. Note that the WALE and DALE bits should be once set to 0 in order to disable the alarm circuit upon the coincidental occurrence of a match between current time and preset alarm time in the process of setting the alarm function. Interval (1 minute) during which a match between current time and preset alarm time occurs INTR pin MAX.61.1µs Setting WALE Match between current time and and DALE preset alarm time bit to 1 in the day-of-week and hour settings Setting WALE Setting WALE and DALE and DALE bit to 0 bit to 1 Setting WALE Match between current time and and DALE preset alarm time bit to 0 in the day-of-week and hour settings INTR pin Setting WALE Match between current time and and DALE preset alarm time bit to 1 in the day-of-week and hour settings Setting WAFG and DAFG bit to 0 Match between current time and preset alarm time in the day-of-week and hour settings 35 R × 5C338A 4.2 Periodic Interrupt Setting of the periodic selection bits (CT2 to CT0) enables periodic interrupt to the CPU. There are two waveform modes: pulse mode and level mode. In the pulse mode, the output has a waveform duty cycle of around 50%. In the level mode, the output is cyclically driven low and, when the CTFG bit is set to 0, the output is set to high (OFF). Waveform Mode, Cycle and Falling Timing Description CT2 CT1 CT0 Waveform mode Cycle and falling timing 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 — — Off (“H”) Fixed at low (“L”) (Default setting) Pulse Mode*1 2Hz (Duty cycle of 50%) Pulse Mode*1 1Hz (Duty cycle of 50%) Level Mode*2 Once per 1 second (Synchronized with second counter increment) Level Mode*2 Once per minute (at 00 seconds of every minute) Level Mode*2 Once per hour (at 00 minutes and 00 seconds of every hour) Level Mode*2 Once per month (at 00 hours, 00 minutes, and 00 seconds of first day of every month) 1) Pulse Mode : 2-Hz and 1-Hz clock pulses are output in synchronization with the increment of the second counter as illustrated in the timing chart on the next page. 2) Level Mode : periodic interrupt signals are output with selectable interrupt cycle settings of 1 second, 1 minute, 1 hour, and 1 month. The increment of the second counter is synchronized with the falling edge of periodic interrupt signals. For example, periodic interrupt signals with an interrupt cycle setting of 1 second are output in synchronization with the increment of the second counter as illustrated in the timing chart on the next page. 3) When the oscillation adjustment circuit is used, the interrupt cycle will fluctuate once per 20 seconds as follows: Pulse Mode : the “L” period of output pulses will increment or decrement by a maximum of ±3.784ms. For example, 1-Hz clock pulses will have a duty cycle of 50 ±0.3784%. Level Mode : a periodic interrupt cycle of 1 second will increment or decrement by a maximum of ±3.784ms. 36 R × 5C338A Relation Between the Mode Waveform and the CTFG Bit • Pulse mode CTFG bit INTR pin Approx. 92µs (Increment of second counter) Rewriting of the second counter *) In the pulse mode, the increment of the second counter is delayed by approximately 92 µs from the falling edge of clock pulses. Consequently, time readings immediately after the falling edge of clock pulses may appear to lag behind the time counts of the real-time clocks by approximately 1 second. Rewriting the second counter will reset the other time counters of less than 1 second, driving the INTR pin low. • Level mode CTFG bit INTR pin Setting CTFG bit to 0 (Increment of second counter) (Increment of second counter) Setting CTFG bit to 0 (Increment of second counter) 5. 32-kHz Clock Output 32.768-kHz clock pulses are output from the 32KOUT pin when either the CLEN1 bit in the control register 2 or the CLEN2 bit in the control register 1 is set to 0 when the CLKC pin is set to high. If the conditions described above are not satisfied, the output is set to high. CLEN1 (D3 at Address Fh) CLEN2 (D4 at Address Eh) 32KOUT pin output (CMOS output) CLKC pin output 1 1 * 0 1 1 “L” * 0 (Default) * * 0 (Default) Clock pulses * The 32KOUT pin output is synchronized with the CLEN1, CLEN2 bit, and CLKC pin settings as illustrated in the timing chart below. CLKC pin or CLEN1 or CLEN2 bit setting 32KOUT pin output MAX. 76.3µs 37 R × 5C338A 6. Typical Applications 6.1 Typical Power Circuit Configurations Sample circuit configuration 1 R × 5C338A *1) Install bypass capacitors for high-frequency and lowOSCIN System power supply OSCOUT VDD 32.768kHz frequency applications in parallel in close vicinity to the R × 5C338A. *1 VSS Sample circuit configuration 2 R × 5C338A *1) When using an OR diode as a power supply for the OSCIN System power supply OSCOUT VDD 32.768kHz R × 5C338A , ensure that voltage exceeding the absolute maximum rating of VDD+0.3 volts is not applied the SO and 32KOUT pins. *1 VSS 38 R × 5C338A 6.2 Connection of INTR Pin The INTR pin follows the N-channel open drain output logic and contains no protective diode on the power supply side. As such, it can be connected to a pull-up resistor of up to 5.5 volts regardless of supply voltage. R × 5C338A A INTR OSCIN B System power supply *1) Depending on whether the INTR pin is to be used during bat- *1 Backup power supply OSCOUT VDD 32.768kHz tery backup, it should be connected to a pull-up resistor at the following different positions: 1) Position A in the left diagram when it is not to be used during battery backup. 2) Position B in the left diagram when it is to be used during battery backup. VSS 6.3 Connection of 32KOUT Pin As the 32KOUT pin is CMOS output, the voltages of the R × 5C338A and any devices to be connected should be the same. When the device is powered down, the 32KOUT output should be disabled. When the CLKC pin is connected to the system power supply through the pull-up resistor, the pull-up resistor should be 0Ω to 10kΩ, and the 32KOUT pin should be connect to the host through the resistor (approx. 10kΩ). System power supply Voltage detector IC 1 R × 5C338A CLKC 32KOUT OSCIN R × 5C338A CLKC 32KOUT OSCIN System power supply 0 to 10kΩ * Backup power supply OSCOUT VDD VSS 32.768kHz OSCOUT VDD VSS Approx.10kΩ Backup power supply 32.768kHz Host *1) RN5VL××C by RICOH. 39 R × 5C338A 6.4 Connection of CE Pin Observe the following precautions when you connect the CE pin. 1) The CE pin is configured to enable the oscillation halt sensing circuit only when driven low. As such, it should be driven low or open at power-on from 0 volts. 2) The CE pin should also be driven low or open immediately upon the host going down (see “1.5 Considerations in Reading and Writing Time Count Data”). 3) The reading function should be disrupted when the CE signal goes to “low” during read cycle. While, the upper 4 bits of the data might be written to the inner shift register when the CE signal goes to “low” during write cycle. (Because the writing function is executed 4 bits by 4 bits.) In either case, after the CE signal returns to “High”, no trouble will occur in the next read or write cycle. 2 3 I/O CONTROL SCLK SIO VDD Lower limit operating voltage for the CPU Backup voltage 0.2×VDD CE 4 CE MIN. 0µs MIN. 0µs MIN. 0µs 40 R × 5C338A 7. Typical Characteristics • Test Circuit R × 5C338A X'tal : 32.768kHz VDD OSCIN 32.768kHz (R1=30kΩ TYP.) (CL=6pF to 8pF) Topt : 25˚C Output pins : Open Frequency counter OSCOUT 32KOUT VSS 7.1 Timekeeping Current vs. Supply Voltage (with no 32-kHz clock output) 1 0.8 0.6 0.4 0.2 0 (CE=Open, Output=Open, Topt=25˚C) 7.2 Timekeeping Current vs. Supply Voltage (with 32-kHz clock output) (CE=Open, Output=Open, Topt=25˚C) 3 2.5 2 1.5 1 0.5 0 Timekeeping Current IDD(µA) 0 1 2 3 4 5 6 Timekeeping Current IDD(µA) 0 1 2 3 4 5 6 Supply Voltage VDD(V) Supply Voltage VDD(V) 7.3 CPU Access Current vs. SCLK Clock Frequency 50 40 30 VDD=5V 20 10 0 VDD=3V (Output=Open, Topt=25˚C) 7.4 Timekeeping Current vs. Operating Temperature (with no 32-kHz clock output) (CE=Open, Output=Open, Topt=25˚C) Timekeeping Current IDD(µA) 2000 CPU Access Current IDD(µA) 2 1.5 1 0.5 0 500 1000 1500 0 –60 –40 –20 0 20 40 60 80 60 SCLK Clock Frequency (kHz) Operating Temperature Topt(˚C) 41 R × 5C338A 7.5 Oscillation Frequency Deviation vs. External CG Oscillation Frequency Deviation(ppm) (VDD=3V, Topt=25˚C, External CG=0pF as standard) 7.6 Oscillation Frequency Deviation vs. Supply Voltage Oscillation Frequency Deviation(ppm) (Topt=25˚C, VDD=3V as standard) 10 5 0 –5 –10 –15 –20 –25 –30 –35 –40 5 4 3 2 1 0 –1 –2 –3 –4 –5 0 5 10 15 20 0 1 2 3 4 5 6 External CG(pF) Supply Voltage VDD(V) 7.7 Oscillation Frequency Deviation vs. Operating Temperature Oscillation Frequency Deviation(ppm) 20 0 –20 –40 –60 –80 –100 –120 –140 –60 –40 –20 (VDD=3V, External CG=0pF, Topt=25˚C as standard) 7.8 Oscillation Start Time vs. Supply Voltage (Topt=25˚C) 500 Oscillation Start Time(ms) 400 300 200 100 0 0 20 40 60 80 100 0 1 2 3 4 5 6 Operating Temperature Topt(˚C) Supply Voltage VDD(V) 7.9 VOL vs. IOL (INTR Pin) 30 25 (Topt=25˚C) 7.10 Input Current to CLKC Pin vs. Supply Voltage 1 0.8 (Topt=25˚C) IOL(mA) 20 VDD=5V 15 10 VDD=3V 5 0 0 0.2 0.4 0.6 0.8 1.0 ICLKC(µA) 0.6 0.4 0.2 0 0 1 2 3 4 5 6 VOL(V) Supply Voltage VDD(V) 42 R × 5C338A 8. Typical Software-based Operations 8.1 Initialization at Power-on Start *1 Power-on XSTP=1? YES *2 *4 NO *3 VDET=0? YES NO Set Oscillation Adjustment Register and Control Registers 1 and 2, etc. Warning of Backup Battery Run-down *1) After power-on from 0 volts, the start of oscillation and the process of internal initialization require a time span on the order of 1 to 2 seconds, so that access should be done after the lapse of this time span or more. 2) The XSTP bit setting of 0 in the control register 1 indicates power-on from backup battery and not from 0 volt. The XSTP bit may fail to be set to 1 in the * presence of any excessive chattering in power supply in such events as installing backup battery. Should there be any possibility of this failure occurring, it is recommended to initialize the R × 5C338A regardless of the current XSTP bit setting. For further details, see “3. Oscillation Halt Sensing and Supply Voltage Monitoring”. *3) This step is not required when the supply voltage monitoring circuit is not used. 4) This step involves ordinary initialization including the oscillation adjustment register and interrupt cycle settings. * 8.2 Writing of Time and Calendar Data *1) This step of waiting is detailed in “1.5 Wait for 31µs Write to Time Counter and Calendar Counter *1 *2 Considerations in Reading and Writing Time Data”. *2) Any writing to the second counter will reset divider units lower than the second digits. 43 R × 5C338A 8.3 Reading Time and Calendar Data 8.3-1 Ordinary Process of Reading Time and Calendar Data *1) This step of waiting is detailed in “1.5 Considerations in Reading and Writing Time Data”. Wait for 31µs Read from Time Counter and Calendar Counter *1 8.3-2 Basic Process of Reading Time and Calendar Data Synchronized with Periodic Interrupt Set Periodic Interrupt Cycle Selection Bits * 1 *1) This step is intended to select the level mode as a waveform mode for the periodic interrupt function. 2) If this step is completed within 1 second, the step of waiting described in * “8.3-1 Ordinary Process of Reading Time and Calendar Data” above need not be conducted. This step is detailed in “1.5 Considerations in Reading and Writing Time Data”. Generate Interrupt in CPU CTFG=1? YES Read from Time Counter and Calendar Counter NO *3) This step is intended to set the CTFG bit to 0 in the control register 2 to cancel an interrupt to the CPU. *2 *3 Other Interrupt Processes Write “×,1,×,1,×,0,1,1” to Control Register 2 44 R × 5C338A 8.3-3 Applied Process of Reading Time and Calendar Data Synchronized with Periodic Interrupt Function Time data need not be read from all the time counters when used for such ordinary purposes as time count indication. This applied process can be used to read time and calendar data with substantial reductions in the load involved in such reading. For Time Indication in “Day-of-month, Day-of-week, Hour, Minute, and Second” Format: Write “×,×,×,×,0,1,0,0” to control Register 1 Write “×,1,×,1,×,0,1,1” to Control Register 2 *1 Generate Interrupt to CPU NO CTFG=1? YES Second Digit=00? YES Read Minute, Hour, Day-of-week, and Day-of-month Counters *2 NO Other Interrupt Processes *3 Use Previous Minute, Hour, Day-of-week, and Day-of-month Data Write “×,1,×,1,×,0,1,1” to Control Register 2 *4 *1) This step is intended to select the level mode as a waveform mode for the periodic interrupt function. *2) If this step is completed within 1 second, the step of waiting described in “8.3-1 Ordinary Process of Reading Time and Calendar Data” above need not be conducted. This step is detailed in “1.5 Considerations in Reading and Writing Time Data”. *3) This step is intended to read time data from all the time counters only in the first session of reading time data after writing time data. *4) This step is intended to set the CTFG bit to 0 in the control register 2 to cancel an interrupt to the CPU. 45 R × 5C338A 8.4 Interrupt Process 8.4-1 Periodic Interrupt Set Periodic Interrupt Cycle Selection Bits * 1 *1) This step is intended to select the level mode as a waveform mode for the periodic interrupt function. 2) This step is intended to set the CTFG bit to 0 in the control register 2 to * cancel an interrupt to the CPU. Generate Interrupt to CPU CTFG=1? YES Periodic Interrupt Process Write “×,1,×,1,×,0,1,1” to Control Register 2 NO Other Interrupt Processes *2 8.4-2 Alarm Interrupt WALE or DALE=0 Set Alarm Minute, Hour, and Day-of-week Registers WALE or DALE=1 *1 *1) This step is intended to once disable the alarm interrupt circuit by setting the WALE and DALE bits to 0 in anticipation of the coincidental occurrence of a match between current time and preset alarm time in the process of setting the alarm interrupt function. *2) This step is intended to enable the alarm interrupt function after completion *2 of all alarm interrupt settings. 3) This step is intended to once cancel the alarm interrupt function by writing * the settings of “ ×,1, ×,1, × ,1,0,1” and “ × ,1, × ,1, × ,1,1,0” to the Alarm_W registers and the Alarm_D registers, respectively. Generate Interrupt to CPU NO WAFG or DAFG=1? YES Conduct Alarm Interrupt Write “×,1,×,1,×,1,0,1” to Control Register 2 Other Interrupt Processes *3 46 R × 5C338A PACKAGE DIMENSIONS (Unit : mm) • RV5C338A (10-pin SSOP-G) +0.3 2.9-0.1 10 6 0° to 10° 2.8±0.2 4.0±0.3 1 5 +0.1 0.127 -0.05 1.1±0.1 0.5 0.1 0.2±0.1 0.15 M • RS5C338A (10-pin SSOP) 3.50±0.2 10 6 +0.1 0.1 -0.05 1.30MAX. 0.55±0.2 0° to 10° 4.4±0.2 6.4±0.2 1 5 0.50 0.9MAX. 1.15±0.1 +0.1 0.15 -0.05 0.1 0.2±0.1 0.1 0.1±0.1 M 0.5±0.2 47 R × 5C338A TAPING SPECIFICATIONS (Unit : mm) • RV5C338A (10-pin SSOP-10G) The RV5C338A has one designated taping direction. The product designation for the taping components is “RV5C338A-E2”. 0.3 +0.1 ø1.5 –0 4.0±0.1 2.0±0.05 1.75±0.1 5.5±0.05 4.4 8.0±0.1 2.0MAX. User Direction of Feed. • RS5C338A (10-pin SSOP) The RS5C338A has one designated taping direction. The product designation for the taping components is “RS5C338A-E2”. 4.0±0.1 1.75±0.1 0.3 +0.1 ø1.5–0 2.0±0.05 5.5±0.05 6.7 8.0±0.1 2.7MAX. User Direction of Feed. 48 3.9 12.0±0.3 12.0±0.3 3.2 RICOH COMPANY, LTD. ELECTRONIC DEVICES DIVISION HEADQUARTERS 13-1, Himemuro-cho, Ikeda City, Osaka 563-8501, JAPAN Phone +81-727-53-6003 Fax +81-727-53-2120 YOKOHAMA OFFICE (International Sales) 3-2-3, Shin-Yokohama, Kohoku-ku, Yokohama City, Kanagawa 222-8530, JAPAN Phone +81-45-477-1697 Fax +81-45-477-1694 · 1695 http://www.ricoh.co.jp/LSI/english/ RICOH CORPORATION ELECTRONIC DEVICES DIVISION SAN JOSE OFFICE 1996 Lundy Avenue, San Jose, CA 95131, U.S.A. Phone +1-408-944-3306 Fax +1-408-432-8375 http://www.ricoh-usa.com/semicond.htm