BA7630S

Multimedia ICs Video switch for CANAL-Plus decoder BA7630S / BA7630F The BA7630S and BA7630F are decoder switching ICs for the scrambled broadcasts in France. The ICs include a 3input multiplexer, 2-input multiplexers with 6dB amplifiers, and a 9-bit serial-to-parallel converter. These ICs greatly simplify decoder switching, and can be connected to a control microprocessor using just two lines. •Applications recorders Video cassette •Featuresswitching functions required for SECAM 1) All the CANAL plus decoder integrated onto one chip. 2) Built-in 9-bit serial-to-parallel converter for decoder and TV control reduces number of microprocessor wiring connections required. 3) Inputs have a sync-tip clamp. 4) The switch section can be used independently. 5) Low power consumption off a 5V supply. •Absolute maximum ratings (Ta = 25°C) Parameter Power supply voltage Power dissipation Operating temperature Storage temperature Symbol VCC Pd Topr Tstg BA7630S BA7630F Limits 9∗1 500∗2 600∗3 Unit V mW °C °C – 25 ~ + 70 – 55 ~ + 125 ∗1 13V for switches 1 to 9. ∗2 Reduced by 5.0mW for each increase in Ta of 1°C over 25°C. ∗3 Reduced by 6.0mW for each increase in Ta of 1°C over 25°C. •Recommended operating conditions (Ta = 25°C) Parameter Power supply voltage Symbol VCC Min. 4.5 Typ. 5.0 Max. 5.5 Unit V 1 Multimedia ICs BA7630S / BA7630F •Block diagram 22 21 20 19 18 17 16 15 14 13 12 BA7630S BUFF SW4 CONTROL LOGIC SW12 SW12 SHIFT REGISTER BIAS SW2 LOGIC SW1 6dB AMP BUFF LATCHES SW3 6dB AMP SW1 SW2 SW3 1 2 3 4 5 6 7 8 9 10 11 28 27 26 25 24 23 22 21 20 19 18 17 BIAS 16 SW4 15 BA7630F BUFF SW4 BUFF CONTROL LOGIC SW12 SW12 SHIFT REGISTER BIAS SW2 SW1 LOGIC LATCHES SW3 6dB AMP 6dB AMP SW4 SW1 SW2 SW3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 •Pin descriptions Pin No. 1 2 3 4 5 6 7 8 9 (5) (6) (7) (8) (9) (10) IN 4 VCC IN 1 RESET IN IN 2 GND IN 3 SW 1 IN / OUT SW 2 IN / OUT SW 3 IN / OUT OUT 3 Pin name Pin No. 12 (15) 13 (16) 14 (17) 15 (20) 16 (21) 17 (22) 18 (23) 19 (24) 20 (26) 21 (27) 22 (28) OUT 2 GND SW 4 IN / OUT SW 5 OUT SW 6 OUT SW 7 OUT SW 8 OUT CLOCK IN DATA IN SW 9 OUT OUT 1 Pin name 10 (13) 11 (14) Pin numbers in parentheses are for the BA7630F. 2 BUFF Multimedia ICs BA7630S / BA7630F CC •Electrical characteristics (unless otherwise noted Ta = 25°C and V Parameter Supply current 〈Analog〉 Maximum output level Voltage gain 1 Voltage gain 2 Frequency characteristic Interchannel crosstalk SW1 ~ SW4 switch level 〈Digital〉 "H" input voltage "L" input voltage "H" input current "L" input current "H" output leakage current 1 "H" output leakage current 2 "L" output voltage Maximum clock frequency Setup time VIH VIL IIH I IL IQH1 ~ 4 IQH5 ~ 9 VQL fMax. t su 3.0 — — – 80 150 — — 250 — — — 2 – 100 230 0 0.1 500 0.1 Vom GV1 GV2 Gf CTM VTH1 ~ 4 2.5 – 0.5 5.5 – 4.0 — 1.0 2.8 0 6.0 – 1.5 – 60 2.0 Symbol ICC Min. — Typ. 28 = 5.0V) Unit mA Conditions — Measurement Circuit Fig.1 Max. 40 — 0.5 6.5 + 1.0 – 45 3.0 VP-P dB dB dB dB V f = 1kHz, THD = 0.5% f = 1MHz, VIN = 1.0VP-P f = 1MHz, VIN = 1.0VP-P 10MHz / 1MHz VIN = 1.0VP-P f = 4.43MHz VIN = 1.0P-P — Fig.1 — 1.0 10 – 150 350 50 0.5 — 1.0 V V µA µA µA µA V kHz µs — — — — VCC = 12V VCC = 12V ICC = 2mA — — Fig.3 Fig.2 Fig.1 3 Multimedia ICs BA7630S / BA7630F •Measurement circuits BA7630S V ~ Distortion meter V ~ Distortion meter 1 2 SWK 1 2 SWJ 22 21 20 19 18 17 16 15 14 13 12 BUFF CONTROL LOGIC SW12 SHIFT REGISTER BIAS SW2 SW1 LOGIC LATCHES SW4 BUFF SW12 SW3 6dB AMP 6dB AMP BUFF 11 SWH 2 1 1 2 SWI 1 2 Distortion meter SW4 SW1 SW2 SW3 VCC5.0V 1 A 1µ + 47µ 1µ + 2 3 4 5 6 7 8 9 10 1µ + 1µ + SWA 1 OSC 50Ω 2 SWB 1 2 SWC 1 2 SWD 1 SWE 2 1 SWF 2 1 2 SWG 50Ω 50Ω ~ ~ ~ ~ 50Ω V ~ 3V 1V Fig.1 4 Multimedia ICs BA7630S BA7630S / BA7630F Output Measurement Circuit VCC = 5.0V 47µ Input Measurement Circuit 1 BIAS BUFF 22 + 5.0V A1 A Input Measurement Circuit Output Measurement Circuit 12V 2 SW12 3 SW1 SHIFT REGISTER 4 CONTROL LOGIC 21 Input Measurement Circuit 20 A2 V 19 Output Measurement Circuit 5 SW1SW2 A A3 SW0 6 SW12 7 SW1 18 17 LOGIC LATCHES Output Measurement Circuit 16 V V1 8 SW2 9 SW4 15 Output Measurement Circuit 14 Output Measurement Circuit 10 SW4 SW3 SW3 13 6dB AMP 6dB AMP Output Measurement Circuit Output Measurement Circuit 11 BUFF BUFF 12 Output Measurement Circuit Fig.2 5 Multimedia ICs BA7630S VCC = 5.0V 47µ BA7630S / BA7630F 12V + PG 1 BIAS BUFF 22 CL RL SW9 50Ω PG 2 SW12 3 SHIFT REGISTER 50Ω 4 CONTROL LOGIC 21 20 19 CL RL 18 CL SW1SW2 RL 17 SW12 CL RL 16 LATCHES SW1 CL RL 15 CL SW2 SW4 SW4 RL 14 SW4 SW5 SW6 SW7 PG SW8 50Ω 5 6 LOGIC 12V RL SW1 RL SW2 RL SW3 7 CL 8 CL 9 CL 10 SW3 SW3 BUFF 6dB AMP 6dB AMP BUFF 13 11 12 Fig.3 6 Multimedia ICs BA7630S / BA7630F •Measurement conditions Switch setting Parameter Current dissipation Symbol SWA 2 2 2 2 2 2 2 1 2 2 2 1 2 2 2 2 2 2 2 2 2 1 2 2 2 2 2 2 2 2 1 2 SWB 2 1 2 2 1 2 2 2 1 2 2 2 1 2 2 1 2 2 1 2 2 2 2 2 1 2 1 2 2 1 2 2 SWC 2 2 1 2 2 2 1 2 2 2 1 2 2 1 2 2 1 2 2 2 1 2 1 2 2 2 2 1 2 2 2 1 SWD 2 2 2 1 2 1 2 2 2 1 2 2 2 2 1 2 2 1 2 1 2 2 2 1 2 1 2 2 1 2 2 2 SWE 2 1 1 2 SWF 2 1 2 SWG 2 SWH 2 SW I SWJ SWK Measurement method — I CC Vom1-1 Vom2-1 Vom3-1 Maximum output level Vom1-2 Vom3-2 Vom2-3 Vom4-3 Gv11-2 Gv13-2 Gv12-3 Gv14-3 Gv21-1 Gv22-1 Gv23-1 Gf1-1 Gf2-1 Gf3-1 Frequency characteristics Gf1-2 Gf3-2 Gf2-3 G f4-3 CTM1-1-2 CTM1-1-3 CTM2-1-1 CTM2-1-3 CTM3-1-1 CTM3-1-2 CTM1-2-3 CTM3-2-1 CTM2-3-4 CTM4-3-2 × × × × × × 2 2 × × × × 2 2 × 2 2 2 Voltage gain 1 × × × × × × × × 1 1 2 1 1 2 × × × × × × × × × × × × × × × 1 1 2 2 2 2 1 2 1 2 × × × 2 2 × × × × × × × × × × 2 2 1 2 × × × × × 1 2 × × 1 2 × × 2 2 × × × × × × × × × × 2 2 1 2 Voltage gain 2 × × × × 1 1 1 1 2 2 Interchannel crosstalk × × × × × × × × × × × × × × × × 1 2 × × × × × × × × 1 2 × × × × × × × × 2 2 × × × × × × × × 1 1 1 2 2 2 Note 1 Note 2 × × × × × × × × × × 1 2 × × × × × × × × 1 1 × × × × × × × × 1 1 × × × × 1 1 1 1 1 1 Note 3 Note 4 × × × × × × The measurements in the above table were made with switching voltage levels for SW1 to SW4 of "L" = 1V, and "H" = 3V. Note 1: Connect distortion meters to the outputs. Adjust the input level so that the output distortion is 0.5% for a f = 1kHz sine wave input. This output voltage is the maximum output level Vom (VP-P). Note 2: Input a f = 1MHz, 1VP-P sine wave. The voltage gain GV = 20 log VOUT / VIN (dB). Note 3: Input a f = 1MHz and 10MHz, 1VP-P sine wave. The frequency characteristic Gf = 20 log VOUT (f = 10M) / VOUT (f = 1M) (dB). Note 4: Input a f = 4.43MHz, 1VP-P sine wave. 0dB amplifier SW crosstalk is CTM0, and the 6dB amplifier SW crosstalk is CTM6. CTM0 = 20 log VOUT / VIN (dB) CTM6 = 20 log VOUT / VIN + 6 (dB) 7 Multimedia ICs BA7630S / BA7630F •Circuit operationtable Digital block truth INPUT Reset H L L L L L L Clock Data OUTPUT SW1···························SW9 H····································H SW1-O ·····················SW 9-O SW1-O ·····················SW 9-O SW1-O ·····················SW 9-O SW1-O ·····················SW 9-O SW1-O ·····················SW 9-O SW1-N ·····················SW 9-N — — — Data "L" sent to internal shift register Data "H" sent to internal shift register Internal shift register data unchanged Contents of internal shift register sent to internal latch Note × L H ↑ ↑ ↓ ↓ × × × H L L H Note 1: H: high level Note 2: L: low level Note 3: ×: either H or L Note 4: ↑: L to H transition Note 5: ↓: H to L transition Note 6: SW1-O to SW9-O: SW1 to SW9 levels before establishing the input conditions shown in the table. Note 7: SW1-N to SW9-N nearest clock ↓ transition. Analog truth table (1) OUT1 switch SW1 L L H H SW2 L H L H RESET H H H H SELECT IN1 IN2 IN3 IN3 (2) OUT2 switch SW3 L H RESET H H SELECT IN1 IN3 (3) OUT3 switch SW4 L H RESET H H SELECT IN2 IN4 Note: When using the switches independently without the digital block, the RESET pin must be set to "H". 8 Multimedia ICs BA7630S / BA7630F •Digital circuit operation (1) Introduction The BA7630S has 9-bit serial-to-parallel converter and latch circuit that has been included to expand the number of microprocessor output ports. The breakdown voltage of the output pins is 13V, so switch them in the range 0 to 12V. In addition to controlling the BA7630S switching block, these outputs can be used to control audio switching, scrambling decoders, and television sets. (2) Using the serial-to-parallel convertor block Signal input is basically done using clock and date pulses. As shown in Fig.10, the date is read on the rising edge of the clock pulses. If the date is “H” on the rising edge of the clock pulse, a “L” data bit is input to the shift register, and if the data is “L” on the rising edge of the clock pulse, a “H” data bit is input to the shift register. The shift register is sequentially incremented by the bit corresponding to SW 1 . Data in excess of 9 bits is sequentially discarded. If the data is “H” on a falling edge of the clock, the contents of the shift register are read into the internal latch, and simultaneously output to the output port (the data polarity is inverted on output). This output is maintained until the latch is setup again. To reset, set the RESET pin to “H”. The internal shift register and latch contents go low (latch output all “H”), for the duration that RESET is held high. CLK (3) Pulse timing The pulse timing diagrams are given below. CLK DATA tsu tsu 0.1µs (Typ.) 1.0µs (Max.) Fig. 6 Clock rising edge and data relationship (setup time) CLK DATA tsu tsu 0.1µs (Typ.) 1.0µs (Max.) Fig. 7 Clock falling edge and data relationship (setup time) RESET SW1 ~ SW9 OUT tPLH DATA 1 2 3 4 tPHL 0.26µs (Typ.) 2.0µs (Max.) 5 Fig. 8 Reset and output relationship (reset transmission time) At points 1 to 4 data is input to the shift register. At point 5 the contents of the shift register are transferred to the latch and simultaneously output. Fig. 4 CLK and DATA relationship CLK Data flow DATA Data in 1 2 3 4 5 6 7 8 9 Shift register SW1 ~ SW9 OUT Latch Reset — Q — Q — Q — Q — Q — Q — Q — Q — Q Latch tPLH9 tPHL 1.2µs (Typ.) 5.0µs (Max.) SW1 SW2 SW9 Fig. 5 Digital block Fig. 9 Clock falling edge and output relationship (latch transmission time) 9 Multimedia ICs BA7630S / BA7630F •Timing chart RESET DATA CLOCK SW1 SW2 SW3 SW4 SW5 SW6 SW7 SW8 SW9 RESET DATA DATA RESET Fig.10 10 Multimedia ICs BA7630S / BA7630F •Application examples (1) Analog block BA7630S pin layout from VTR TUNER OUT IN1 VCC 3 2 + VCC1 5V 47µF 1µF 75Ω IN2 OUT1 5 22 + + from DECODER OUT OUT2 from TV OUT IN3 7 1µF 75Ω IN4 + 6dB AMP 12 470 ~ 1000µF 2SA933 VCC2 R + + 1µF 75Ω + VCC2 R to VCR 75Ω to DECODER IN + 75Ω OUT3 from VIDEO OUT 1 1µF 75Ω GND 6 6dB AMP 11 470 ~ 1000µF 2SA933 to TV IN VCC2 5V R 100 390 GND 13 12V Fig.11 (2) Digital block VCC 4.5 ~ 13V 22k SW OUT SW1 ~ SW9 OPEN COLLECTOR 50kΩ SW1 ~ SW4 ONLY 28kΩ Fig.12 11 Multimedia ICs BA7630S / BA7630F •Electrical characteristic curves 0 –2 –4 –6 –8 – 10 – 12 – 14 – 16 – 18 – 20 100k 200k 500k 1M 2M 3pin-22pin 5pin-22pin 7pin-22pin VIN = 10VP-P CROSSTALK: CT (dB) GAIN (dB) 0 – 10 – 20 – 30 – 40 – 50 – 60 – 70 3pin-22pin 5pin-22pin 7pin-22pin VIN = 1.0VP-P 6 4 2 0 –2 –4 –6 –8 – 10 – 12 – 14 1pin-11pin 5pin-11pin 3pin-12pin 7pin-12pin Input 1VP-P 5M 10M 20M 30M GAIN (dB) 100k 200k 500k 1M 2M 5M 10M 20M 100k 200k 500k 1M 2M 5M 10M 20M 30M FREQUENCY (Hz) FREQUENCY (Hz) FREQUENCY (Hz) Fig. 13 Frequency characteristic(OUT1) 0 – 10 – 20 CROSSTALK: CT (dB) – 30 – 40 – 50 – 60 – 70 100k 200k 500k 1M 2M 5M 10M 20M 1pin-11pin 5pin-11pin 3pin-12pin 7pin-12pin Input 1VP-P Fig. 14 Crosstalk characteristic (OUT1) Fig. 15 Frequency characteristic (OUT2 and OUT3) FREQUENCY (Hz) Fig. 16 Crosstalk characteristic (OUT2 and OUT3) •External dimensions (Units: mm) BA7630S BA7630F 18.5 ± 0.2 19.4 ± 0.3 22 12 6.5 ± 0.3 9.9 ± 0.3 7.5 ± 0.2 28 15 0.51Min. 3.4 ± 0.2 3.95 ± 0.3 0.3 ± 0.1 2.2 ± 0.1 1 14 1.778 0.5 ± 0.1 0° ~ 15° 0.11 1.27 0.4 ± 0.1 0.3Min. 0.15 SDIP22 SOP28 12 0.15 ± 0.1 1 11 7.62