Datasheet
Automotive LED Driver Series
16-channel Constant Current Driver
Embedded Automotive Backlight LED Driver
BD12801MUF-M
General Description
Key Specifications
BD12801MUF-M is 16-channel constant current driver
with 13 bit PWM dimming and 8 bit local DC dimming
individual channels. Communication with µController via
SPI is feasible.
◼Power Supply Voltage Range:
◼LED Output Current Range:
◼Operating Temperature Range:
Package
Features
VQFN48FAV070
◼AEC-Q100 Qualified(Note 1)
◼Integrated 16-channel 20 V LED Constant Current
Driver
◼SPI Interface
◼Independent 13 bit PWM Dimming Function
◼Independent 8 bit Local DC Dimming Function
◼Independent 8 bit Phase Shift Function
◼LSI Protection Function (UVLO, TSD, ISETSCP)
◼LED Abnormality Detection Function (Open/Short)
◼Integrated Abnormality Output FAIL Pin
◼Cascade Connection Feasible
3.0 V to 5.5 V
20 mA to 130 mA
-40 °C to +125 °C
W (Typ) x D (Typ) x H (Max)
7.0 mm x 7.0 mm x 1.0 mm
(Note 1) Grade 1
Applications
◼Cluster, Center Infotainment Display
◼Other Automotive Backlights
Typical Application Circuit
Buck
Buck-Boost DC/DC
Converter
・・・
VCC
LED1
LED2
LED3
EN
LED4
VREG33
LED5
LED6
LED7
SDI
LED8
SCLK
SCSB
SDO
LED9
BD12801MUF-M
VREG33
LED10
LED11
LED12
LED13
LED14
LED15
FAIL
LED16
VSYNC
EXTCLK
GND
〇Product structure : Silicon integrated circuit
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LGND
ISET
TEST1
TEST2
〇This product has no designed protection against radioactive rays.
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Contents
General Description ........................................................................................................................................................................ 1
Features.......................................................................................................................................................................................... 1
Applications .................................................................................................................................................................................... 1
Key Specifications .......................................................................................................................................................................... 1
Package .......................................................................................................................................................................................... 1
Typical Application Circuit ............................................................................................................................................................... 1
Contents ......................................................................................................................................................................................... 2
Pin Configuration ............................................................................................................................................................................ 3
Pin Descriptions .............................................................................................................................................................................. 3
Block Diagram ................................................................................................................................................................................ 5
Description of Blocks ...................................................................................................................................................................... 6
Absolute Maximum Ratings ............................................................................................................................................................ 9
Thermal Resistance ........................................................................................................................................................................ 9
Recommended Operating Conditions ........................................................................................................................................... 10
Electrical Characteristics............................................................................................................................................................... 10
Typical Performance Curves ......................................................................................................................................................... 12
Functions of Logic Blocks ............................................................................................................................................................. 14
Timing Chart ................................................................................................................................................................................. 40
Application Examples ................................................................................................................................................................... 59
I/O Equivalence Circuit ................................................................................................................................................................. 60
Operational Notes ......................................................................................................................................................................... 61
Ordering Information ..................................................................................................................................................................... 63
Marking Diagram .......................................................................................................................................................................... 63
Physical Dimension and Packing Information ............................................................................................................................... 64
Revision History ............................................................................................................................................................................ 65
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Pin Configuration
25 LED11
26 LED12
27 N.C.
28 LGND
29 N.C.
30 LED13
31 LED14
32 LED15
33 LED16
34 N.C.
35 N.C.
EXP-PAD (Note 1)
36 N.C.
(TOP VIEW)
EXP-PAD (Note 1)
N.C. 37
24 LED10
N.C. 38
23 LED9
N.C. 39
22 N.C.
ISET 40
21 LGND
VREG33 41
20 N.C.
VCC 42
19 TEST2
EN 43
18 TEST1
GND 44
17 SDO
FAIL 45
16 LGND
SCSB 46
15 N.C.
SDI 47
14 LED8
LED6 12
LED5 11
N.C. 10
9
LGND
8
13 LED7
N.C.
7
LED4
LED3
5
LED2
4
LED1
3
N.C.
2
VSYNC
EXP-PAD (Note 1)
EXTCLK
1
SCLK 48
6
EXP-PAD
EXP-PAD (Note 1)
(Note 1) EXP-PAD on the corner is comprised of three electrodes and is short-circuited inside.
Pin Descriptions
Pin No.
Pin Name
Function
1
EXTCLK
EXTCLK signal pin. Input the frequency 8,192 times of VSYNC (PWMFREQ[1:0] = 0).
2
VSYNC
VSYNC signal pin
3
N.C.
-
4
LED1
Constant current output pin. Connect to LED cathode.
5
LED2
Constant current output pin. Connect to LED cathode.
6
LED3
Constant current output pin. Connect to LED cathode.
7
LED4
Constant current output pin. Connect to LED cathode.
8
N.C.
-
9
LGND
10
N.C.
-
11
LED5
Constant current output pin. Connect to LED cathode.
12
LED6
Constant current output pin. Connect to LED cathode.
13
LED7
Constant current output pin. Connect to LED cathode.
14
LED8
Constant current output pin. Connect to LED cathode.
15
N.C.
-
16
LGND
Analog GND for constant current driver block
Analog GND for constant current driver block
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Pin Descriptions - continued
Pin No.
Pin Name
Function
17
SDO
18
TEST1
TEST mode output pin. Set this pin open.
19
TEST2
TEST mode input pin. Connect to GND.
20
N.C.
21
LGND
22
N.C.
-
23
LED9
Constant current output pin. Connect to LED cathode.
24
LED10
Constant current output pin. Connect to LED cathode.
25
LED11
Constant current output pin. Connect to LED cathode.
26
LED12
Constant current output pin. Connect to LED cathode.
27
N.C.
28
LGND
29
N.C.
30
LED13
Constant current output pin. Connect to LED cathode.
31
LED14
Constant current output pin. Connect to LED cathode.
32
LED15
Constant current output pin. Connect to LED cathode.
33
LED16
Constant current output pin. Connect to LED cathode.
34
N.C.
-
35
N.C.
-
36
N.C.
-
37
N.C.
-
38
N.C.
-
39
N.C.
-
40
ISET
LED current setting pin. LED current is set by resistor connected to GND.
41
VREG33
42
VCC
43
EN
44
GND
Small signal GND
45
FAIL
Abnormal detection output pin
46
SCSB
47
SDI
Data input pin
48
SCLK
CLK input pin
-
EXP-PAD
Data output pin.
Analog GND for constant current driver block
Analog GND for constant current driver block
-
Output 3.3 V constant voltage
Power supply pin
Engage Standby-mode with VEN = Low. Operation mode with VEN = High.
Chip select setting pin
Exposed Pad. Connect center EXP-PAD to the internal PCB ground plane using multiple via, it
will provide excellent heat dissipation characteristics.
(Note) LED1 to LED16 are defined as LEDn (n = 1 to 16) from this page.
If there is no use LEDn channel, set open for the pin. If LEDn pin connects to GND, standby current isn’t 0 µA (Typ) because there is a current path.
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Block Diagram
VCC
EN
VCCUVLO
Band
Gap
Voltage
－
3.3 V
REG
VREG33UVLO
TSD
VREG33
＋
ISET SHORT DET
VCC
ISET
Constant Current Driver
DTY01[12:0]
13
LCDAC1[7:0]
SDI
8
ERLOP[0]
ERLSH[0]
SCSB
DTY13[12:0]
13
LCDAC13[7:0]
Level
Shifter
8
ERLOP[12]
ERLSH[12]
LED1
LED SHORT DET
Thermal Warning
WARTSD[0]
SCLK
SDO
LED OPEN DET
・
・
・
LED OPEN DET
・
・
・
LED13
LED SHORT DET
Thermal Warning
WARTSD[12]
DTY14[12:0]
LOGIC
Control
VSYNC
13
LCDAC14[7:0]
8
ERLOP[13]
ERLSH[13]
LED OPEN DET
LED SHORT DET
Thermal Warning
WARTSD[13]
EXTCLK
DTY15[12:0]
13
LCDAC15[7:0]
FAIL
8
ERLOP[14]
PROTECT
LOGIC
ERLSH[14]
LED OPEN DET
Thermal Warning
WARTSD[14]
13
TEST2
LCDAC16[7:0]
TEST
MODE
LOGIC
8
ERLOP[15]
ERLSH[15]
LED OPEN DET
LED16
LED SHORT DET
Thermal Warning
WARTSD[15]
LGND
GND
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LED15
LED SHORT DET
DTY16[12:0]
TEST1
LED14
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Description of Blocks
If there is no description, the mentioned values are typical value.
1. Reference Voltage (3.3V REG)
3.3V REG Block generates 3.3 V at EN = High, and outputs to the VREG33 pin. This voltage (V VREG33) is used as I/O
interface power supply for internal circuit. The VREG33 pin has UVLO function, and it starts operation at VCC ≥ 2.8 V and
VVREG33 ≥ 2.7 V and stops when at VCC ≤ 2.7 V or VVREG33 ≤ 2.6 V. About the condition to release/detect VVREG33 voltage,
refer to Table 1. Protection Table. Connect a ceramic capacitor (CVREG33) to the VREG33 pin for phase margin. CVREG33
range is 1.0 µF to 4.7 µF and recommended value is 2.2 µF. If the CVREG33 is not connected, it might occur unstable
operation e.g. oscillation. In addition, VREG33 pin has the over current protection function. If the load current of
VREG33 pin exceeds 15 mA, the voltage drops. The following diagram shows the power supply system of MCU and
LED Driver. Select the suitable connection in accord with application structure.
Case 1: A power supply of MCU and LED Driver are different.
3.3 V
Case 2: A power supply of MCU and LED Driver are same.
3.3 V
5.0 V
5.0 V
VCC
VCC
SPI
MCU
SPI
VREG33
BD12801MUF-M
VCC
MCU
SPI
BD12801MUF-M VREG33
MCU
BD12801MUF-M VREG33
OCP in VREG33 is not activated.
Figure 1. VCC Pin and VREG33 Pin Connection
2. Constant Current Driver
This device integrates 16-channel constant current driver. Constant current drivers capability is defined by supply
voltage thus with VCC ≥ 4.2 V will be 130 mA/ch and with 3.0 V ≤ VCC < 4.2 V will be 100 mA/ch. Also 13 bit PWM
dimming function, 8 bit DC dimming function, 8 bit phase shift function are built in for independent channel.
(1)
Maximum LED Output Current Setting (RISET)
ILEDMAX [mA]
1000
100
LED
Driver
10
1
10
100
RISET [kΩ]
LEDn
(n=1 to 16)
ISET
RISET
Figure 2. ILEDMAX vs RISET
Figure 3. ISET Block Diagram
The Maximum LED Output Current ILEDMAX can be obtained by the following equation.
𝐼𝐿𝐸𝐷𝑀𝐴𝑋 = 757/𝑅𝐼𝑆𝐸𝑇
[A]
The operating range of the RISET value is from 6.3 kΩ to 30 kΩ. Additionally, the RISET value could not be changed
during operation. In this IC, ISET SHORT protection is built-in to protect an LED element from excess current when
the ISET pin and GND are shorted. If the RISETSCP is 2.2 kΩ (Typ) or less, the IC detects ISET SHORT protection
and LED current is turned off.
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2. Constant Current Driver - continued
(2) Local DC Dimming Control
Integrates 8 bit DC dimming function LCDACn[7:0], which controls LED current of each channel by SPI input from
the defined LED current by RISET. LED current under DC dimming can be calculated in below equation.
𝐼𝐿𝐸𝐷𝑛 = 𝐼𝐿𝐸𝐷𝑀𝐴𝑋 × {(𝐿𝐶𝐷𝐴𝐶𝑛[7: 0] + 1)/256}
>
0.02
[A]
(𝑛 = 1 𝑡𝑜 16)
In instance when RISET = 6.3 kΩ and LCDACn[7:0] = 0xFF, LED current will be 120 mA. As minimum LED current of
the device is minimum 20 mA, LCDACn[7:0] should be set from 0x2A to 0xFF. Note that LCDACn[7:0] minimum bit
cannot be set due to minimum current 20 mA. Step width will be 0.47 mA ( = 120 mA / 256 ). On the other hand RISET
= 19 kΩ and LCDACn[7:0] = 0xFF will set LED current as 40 mA, LCDACn[7:0] should be set from 0x80 to 0xFF.
Step width will be 0.156 mA ( = 40 mA / 256). LCDACn[7:0] setting range will differ by RISET.
(3)
Local PWM Dimming Control
PWM dimming frequency, pulse width, and phase shift can be controlled by SPI input. Constant current driver can be
controlled synchronized to PWM for independent channel set by SPI.
However constant current driver’s minimum pulse width depends on LED current value. When LED current value is
80 mA or more, set the minimum pulse width to more than 0.6 µs. If LED current value is less than 80 mA, set the
minimum pulse width to more than 2 µs. For example with PWM frequency 200 Hz at LED current of 100 mA setting,
it’s possible to set with 13 bit full range of PWM duty. Average LED current under PWM dimming can be calculated in
below equation.
𝐼𝐿𝐸𝐷𝑛_𝐴𝑉𝐸 = 𝐼𝐿𝐸𝐷𝑛 × {(𝐷𝑇𝑌𝑛[12: 0] + 1)/ 8,192}
(4)
[A]
(𝑛 = 1 𝑡𝑜 16)
Local Phase Shift Control
This device integrates 8 bit Phase Shift function. Control by independent channel based on set PWM cycle is
feasible. In case PWM frequency is 200 Hz, shift rate per channel can be set by about 20 µs steps. Refer to Figure 4.
To summarize (1) to (3), the LED current setting, PWM dimming, DC dimming are schematically shown as Figure 5.
LED Current
1 ms/div
ILED1 (50 mA/div)
Maximum setting
130 mA
(A)
ILEDMAX
ILED2(50 mA/div)
ILEDn
(B)
ILED3 (50 mA/div)
Minimum Setting
20 mA
t
(C)
Figure 4. Local Phase Shift Control
Figure 5. Setting Range by Dimming Method
(A) ILEDMAX is set to the maximum LED current value
from 20 mA to 130 mA by RISET.
(B) When ILEDMAX is set to 80 mA by RISET, DC dimming
range is limited from 64 to 256 because of
minimum LED current setting 20 mA.
(C) PWM dimming can be controlled by 13 bit range.
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Description of Blocks - continued
3. Protection Feature
Protection Name
LED OPEN
LED SHORT
(Note 4)
LEDn
LEDn
(Note 3)
(Note 3)
Release
Condition
Error
Enable
SSMASK
ERRMASK
ERRLAT
Error Register
DTYENn = 1
and
LEDOPEN = 1
and
[ PWMn = High
and
(Note 3)
≤ 0.2 V ]
VLEDn
DTYENn = 0
or
LEDOPEN = 0
or
[ PWMn = High
and
(Note 3)
VLEDn
> 0.2 V ]
LEDOPEN
O
O
O
ERLOP[15:0]
Low
Protection released
(ERRLAT = 0)
or
ERRCLR
(ERRLAT = 1)
DTYENn = 1
and
LEDSHEN = 1
and
[ PWMn = High
and
DTYENn = 0
or
LEDSHEN = 0
or
[ PWMn = High
and
LEDSHEN
O
O
O
ERLSH[15:0]
Low
Protection released
(ERRLAT = 0)
or
ERRCLR
(ERRLAT = 1)
(Note 3)
≥ register
setting ]
LEDn (Note 3)
Error Flag
Error Setting
Detection
Condition
Pin
VLEDn
LED SCP(Note 1)
Table 1. Protection Table
Protection
DTYENn = 0
and
LEDOPEN = 1
and
VLEDn(Note 3) ≤ 0.2 V during
SCP setting time
(after detecting LED Open
Error)
VLEDn
(Note 3)
< register
setting ]
Recommend Operation
target LEDn (Note 3) OFF
(DTYENn
(Note 3)
= 0)
target LEDn (Note 3) OFF
(DTYENn (Note 3) = 0)
LEDOPEN
O
-
-
WARSCP
VSYNC
WARISET
Low
Protection released
(ERRLAT = 0)
or
ERRCLR
(ERRLAT = 1)
LED1 to 16 OFF
(automaticaly)
(Note 2)
Low
Protection released
(ERRLAT = 0)
or
ERRCLR
(ERRLAT = 1)
target LEDn OFF
(DTYENn (Note 3) = 0)
Low
Protection released
ISET
RSETSCP ≤ 2.2 kΩ
RSETSCP > 2.2 kΩ
-
O
-
O
Thermal Warning
-
Tj ≥ 135 °C
Tj ≤ 125 °C
TSDWEN
O
-
O
-
Tj ≥ 175 °C
Tj ≤ 150 °C
-
-
-
-
-
(Note 5)
Clear Condition
TSD detect
or
EN detect
or
VCCUVLO detect
or
VREG33UVLO detect
ISET SHORT
TSD
(Note 6)
FAIL
WARTSD[15:0]
VCCUVLO(Note 5)
VCC
VCC ≤ 2.7 V
VCC ≥ 2.8 V
-
-
-
-
-
VREG33UVLO(Note 5)
VREG33
VVREG33 ≤ 2.6 V
VVREG33 ≥ 2.7 V
-
-
-
-
-
High
(Hi-z)
High
(Hi-z)
TSD detect
or
EN detect
or
All LEDn (Note 3) OFF
VCCUVLO detect
or
VREG33UVLO detect
-
All block initialized
(automaticaly)
All block initialized
(automaticaly)
All block initialized
(automaticaly)
(Note 1) It can’t detect “SCP error” if LEDn (n = 1 to 16) pin shorts GND before setting DTYEN = 1 and detecting “LED open error”. This function is available after
detecting “LED open error”.
(Note 2) WARTSD[n-1]: monitor LEDn
(Note 3) n = 1 to 16
(Note 4) O: It has this function. -: It doesn’t have this function.
(Note 5) When it detects “VREG33UVLO” or “VCCUVLO” or “TSD” or “EN”, it can’t detect other protection.
(Note 6) The FAIL pin is recommended to pull up to VVREG33. Recommended value for pull up resistance is 20 kΩ to 100 kΩ.
When above failure is detected, the FAIL pin voltage becomes Low. If the FAIL pin is not used pin, it shall be kept open or short to GND.
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Absolute Maximum Ratings (Ta = 25 °C)
Parameter
Symbol
Rating
Unit
Power Supply Voltage
VCC
-0.3 to +7.0
V
EN Pin Voltage
VEN
-0.2 to +7.0
V
VLED1 to VLED16
-0.2 to +20.0
V
VFAIL
LED1 to LED16 Pin Voltage
FAIL Pin Voltage
-0.3 to +7.0
V
VREG33, SCSB, SCLK, SDI, SDO,
VVREG33, VSCSB, VSCLK, VSDI, VSDO, VVSYNC, VEXTCLK,
VSYNC, EXTCLK, TEST1, TEST2,
VTEST1, VTEST2, VISET
ISET Pin Voltage
-0.2 to +7.0
V
Storage Temperature Range
Tstg
-55 to +150
°C
Tjmax
150
°C
Maximum Junction Temperature
Caution 1: Operating the IC over the absolute maximum ratings may damage the IC. The damage can either be a short circuit between pins or an open circuit
between pins and the internal circuitry. Therefore, it is important to consider circuit protection measures, such as adding a fuse, in case the IC is
operated over the absolute maximum ratings.
Caution 2: Should by any chance the maximum junction temperature rating be exceeded the rise in temperature of the chip may result in deterioration of the
properties of the chip. In case of exceeding this absolute maximum rating, design a PCB with thermal resistance taken into consideration by
increasing board size and copper area so as not to exceed the maximum junction temperature rating.
Thermal Resistance(Note 1)
Parameter
Symbol
Thermal Resistance (Typ)
Unit
1s(Note 3)
2s2p(Note 4)
θJA
71.4
24.2
°C/W
ΨJT
6.0
3.0
°C/W
VQFN48FAV070
Junction to Ambient
Junction to Top Characterization
Parameter(Note 2)
(Note 1) Based on JESD51-2A (Still-Air).
(Note 2) The thermal characterization parameter to report the difference between junction temperature and the temperature at the top center of the outside
surface of the component package.
(Note 3) Using a PCB board based on JESD51-3.
(Note 4) Using a PCB board based on JESD51-5, 7.
Layer Number of
Measurement Board
Single
Material
Board Size
FR-4
114.3 mm x 76.2 mm x 1.57 mmt
Top
Copper Pattern
Thickness
Footprints and Traces
70 μm
Layer Number of
Measurement Board
4 Layers
Material
Board Size
FR-4
114.3 mm x 76.2 mm x 1.6 mmt
Top
2 Internal Layers
Thermal Via(Note 5)
Pitch
Diameter
1.20 mm
Φ0.30 mm
Bottom
Copper Pattern
Thickness
Copper Pattern
Thickness
Copper Pattern
Thickness
Footprints and Traces
70 μm
74.2 mm x 74.2 mm
35 μm
74.2 mm x 74.2 mm
70 μm
(Note 5) This thermal via connects with the copper pattern of all layers.
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Recommended Operating Conditions
Parameter
Symbol
Min
Typ
Max
Unit
VCC
3.0
5.0
5.5
V
CVREG33
1.0
2.2
4.7
µF
ISET Pin Connection Resistance
RISET
6.3
-
30.0
kΩ
FAIL Pin Connection Resistance
RFAIL
20
-
100
kΩ
EXTCLK Frequency
fEXTCLK
409.6
-
5,000.0
kHz
EXTCLK Duty
DEXTCLK
40
-
60
%
VSYNC Frequency
fVSYNCCLK
50
-
600
Hz
VSYNC Minimum Pulse Width
tVSYNCMIN
50
-
-
µs
LEDn Output Current 1
ILEDMAX1
20
-
100
mA
3.0 V ≤ VCC < 4.2 V
LEDn Output Current 2
ILEDMAX2
20
-
130
mA
VCC ≥ 4.2 V
Operating Temperature
Topr
-40
+25
+125
°C
Power Supply Voltage
VREG33 Pin Connect Capacitance
Condition
(Note) Above operation range is referring to IC independently. Thorough verification of the coefficient setting in actual application shall be practiced.
Electrical Characteristics
(Unless otherwise specified, Ta = -40 °C to +125 °C, VCC = 3.0 V to 5.5 V)
Parameter
Symbol
Min
Typ
Max
Unit
Condition
Circuit Current
ICC
-
5.5
15.0
mA
VEN = High,
All Current drivers are OFF
Standby Current
ISTB
-
0
300
µA
VEN = Low
VVREG33
3.1
3.3
3.5
V
ΔVVREG33
-
30
80
mV
IVREG33OCP
10
-
-
mA
VCCUVLO Detection Voltage
VVCCUVLO
2.55
2.70
2.85
V
VCCUVLO Hysteresis Voltage
VVCCUHYS
-
100
-
mV
VREG33UVLO Detection Voltage
VVREG33UVLO
2.40
2.60
2.80
V
VREG33UVLO Hysteresis Voltage
VVREG33UHYS
-
100
-
mV
LED OPEN Detection Voltage
VOPDET
0.1
0.2
0.3
V
VLEDn: SWEEP UP
LED SHORT Detection Voltage
VSHDET
4.5
4.8
5.1
V
LEDSH = 0xF
RSETSCP
0.7
2.2
4.3
kΩ
tMON
-
135
-
°C
tMONHYS
-
10
-
°C
[Device Overview]
[VREG33 Block]
VREG33 Pin Output Voltage
VREG33 Pin
Load Regulation Voltage
VREG33 Pin
Over Current Protection
VCC = 3.5 V to 5.5 V,
IVREG33 = 0 mA
VCC = 3.5 V to 5.5 V,
IVREG33 = -5 mA
VCC = 5.0 V
[PROTECT LOGIC Block]
ISET GND Short Detection
Resistance
Thermal Warning Monitor Detection
Temperature
Thermal Warning Monitor
Hysteresis Width
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VCC: SWEEP DOWN
VVREG33: SWEEP DOWN
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BD12801MUF-M
Electrical Characteristics - continued
(Unless otherwise specified, Ta = -40 °C to +125 °C, VCC = 3.0 V to 5.5 V)
Parameter
Symbol
Min
Typ
Max
Unit
Condition
ISET Pin Reference Voltage
VISET
-
0.606
-
V
LEDn Pin ON Resistance
RLED1
-
-
6.5
Ω
LEDn Pin Output Current1(Note 1)
IOUT1
94
100
106
mA
-4
-
+4
%
-6
-
+6
%
-4
-
+4
%
-6
-
+6
%
45
50
55
mA
-6
-
+6
%
-7.5
-
+7.5
%
-6
-
+6
%
-7.5
-
+7.5
%
IEN
18
30
50
µA
EN Pin Input High Voltage
VENH
0.8 x
VVREG33
-
EN Pin Input Low Voltage
VENL
-0.2
-
IIN
-1
0
LOGIC Pin Input High Voltage
VINH
0.8 x
VVREG33
-
LOGIC Pin Input Low Voltage
VINL
-0.2
-
SDO Pin Output High Voltage
VSDOH
VVREG33
-0.2
-
VVREG33
+0.2
V
ISDO = -1 mA
SDO Pin Output Low Voltage
VSDOL
-
-
0.2
V
ISDO = +1 mA
RFAIL
0.5
1.0
2.0
kΩ
IFAIL = +1 mA
ILEAKFAIL
-
-
0.1
µA
VFAIL = 5.0 V
[Constant Current Driver Block]
LEDn Pin Output Current
Absolute Error1(Note 1)
ΔIOUTA1
LEDn Pin Output Current
Relative Error1(Note 1)
ΔIOUTR1
LEDn Pin Output
Current2(Note 2)
IOUT2
LEDn Pin Output Current
Absolute Error2(Note 2)
ΔIOUTA2
LEDn Pin Output Current
Relative Error2(Note 3)
ΔIOUTR2
Ta = 25 °C, VCC = 5 V
Ta = 25 °C, VCC = 5 V
Ta = 25 °C, VCC = 5 V
Ta = 25 °C, VCC = 5 V
[EN Input Pin]
EN Pin Input Current
VVREG33
+ 0.2
+0.2 x
VVREG33
VEN = 3.0 V
V
V
[LOGIC Input (SCSB, SCLK, SDI, EXTCLK, VSYNC)]
LOGIC Pin Input Current
+1
VVREG33
+ 0.2
+0.2 x
VVREG33
µA
VIN = VCC
V
V
[LOGIC Output Block (SDO)]
[FAIL Output Block]
FAIL Pin ON Resistance
FAIL Pin Leak Current
(Note 1) RISET = 7.5 kΩ, VLEDn = 0.65 V, SDI = w(0x18,0xFF), w(0x19,0x3F)
(Note 2) RISET = 15 kΩ, VLEDn = 0.65 V, SDI = w(0x18,0xFF), w(0x19,0x3F)
(Note 3) VLEDn describes either pin of LED1 to LED16 voltage.
ILEDn describes either pin of LED1 to LED16 current.
ΔIOUTA1 = (ILEDn/0.1 - 1) x 100
ΔIOUTR1 = (ILEDn/ILED_AVE - 1) x 100
ILED_AVE describes the average current of LED1 to LED16.
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BD12801MUF-M
Typical Performance Curves
200
175
150
125
100
75
50
25
0
1
2
3
4
5
Power Supply Voltage: VCC [V]
Figure 6. Standby Current
vs Power Supply Voltage
6
4
2
0
1
2
3
4
Power Supply Voltage: VCC [V]
5
Figure 7. Circuit Current vs Power Supply Voltage
(VEN = High)
0.30
VREG33 Pin Output Voltage: VVREG33 [V]
VCC = 3.3 V
VCC = 5.0 V
VCC = 5.5 V
3.45
3.40
3.35
3.30
3.25
3.20
3.15
-40 -20
+0
LED OPEN Detection Voltage: VOPDET [V]
3.50
3.10
8
0
0
Ta = -40 °C
Ta = +25 °C
Ta = +125 °C
10
Circuit Current: ICC [mA]
Standby Current: ISTB [µA]
12
Ta = -40 °C
Ta = +25 °C
Ta = +125 °C
+20 +40 +60 +80 +100 +120
Temperature [°C]
0.26
0.24
0.22
0.20
0.18
0.16
0.14
0.12
0.10
-40 -20
+0 +20 +40 +60 +80 +100 +120
Temperature [°C]
Figure 8. VREG33 Pin Output Voltage
vs Temperature
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TSZ22111 • 15 • 001
VCC = 3.3 V
VCC = 5.0 V
VCC = 5.5 V
0.28
Figure 9. LED OPEN Detection Voltage
vs Temperature
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BD12801MUF-M
Typical Performance Curves - continued
105
VCC = 3.3 V
VCC = 5.0 V
VCC = 5.5 V
5.0
4.9
4.8
4.7
4.6
4.5
-40
-20
+0
+20 +40 +60 +80 +100 +120
103
102
101
100
99
98
96
95
-40
100
LEDn Pin Output Current1: IOUT1 [mA]
100
LEDn Pin Output Current1: IOUT1 [mA]
120
80
Ta = -40 °C
Ta = +25 °C
Ta = +125 °C
40
RISET = 7.5 kΩ
VLED1 = 0.65 V
SDI = w(0x18,0xFF)
w(0x19,0x3F)
0
0.1
0.2
0.3 0.4 0.5 0.6
LEDn Pin Voltage [V]
0.7
0.8
Figure 12. LEDn Pin Output Current1 vs LED Pin Voltage
(VCC = 3.3 V)
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TSZ22111 • 15 • 001
+0
+20 +40 +60 +80 +100 +120
Figure 11. LEDn Pin Output Current1 vs Temperature
120
0
-20
Temperature [°C]
Figure 10. LED SHORT Detection Voltage
vs Temperature
20
RISET = 7.5 kΩ
VLED1 = 0.65 V
SDI = w(0x18,0xFF)
w(0x19,0x3F)
97
Temperature [°C]
60
VCC = 3.3 V
VCC = 5.0 V
VCC = 5.5 V
104
LEDn Pin Output Current1: IOUT1 [mA]
LED SHORT Detection Voltage: VSHDET [V]
5.1
80
Ta = -40 °C
Ta = +25 °C
Ta = +125 °C
60
40
RISET = 7.5 kΩ
VLED1 = 0.65 V
SDI = w(0x18,0xFF)
w(0x19,0x3F)
20
0
0
0.1
0.2
0.3 0.4 0.5 0.6
LED Pin Voltage [V]
0.7
0.8
Figure 13. LEDn Pin Output Current1 vs LED Pin Voltage
(VCC = 5.0 V)
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BD12801MUF-M
Functions of Logic Blocks
1.
Serial Interface and AC Electrical Characteristics
Serial Peripheral Interface (SPI) controls the IC with SCSB, SCLK, SDI, and SDO signals.
Start the SPI communication with the initial value of SCSB is ‘High’, and that of SCLK and SDI is ‘Low’.
When using several devices, connect the SDO pin to the SDI pin of the next device to make cascade connection.
SDO signal is output after SDI input from 8 datas. Example of the n byte Write is shown in the following.
SDO is in the state of output the signals. (initial value is ‘Low’)
SCSB
･･････････
1st 2nd 3rd 4th 5th 6th 7th 8th
SCLK
SDI
･･････････
B
S
DA DA DA DA DA
[5] [4] [3] [2] [1]
DevAddr[5:0]
8 bits
Low
SDO
RA RA RA RA RA RA RA DT DT DT DT DT DT DT DT
DA ND ND ND ND ND ND ND ND
[0] [7] [6] [5] [4] [3] [2] [1] [0] RW [6] [5] [4] [3] [2] [1] [0] [7] [6] [5] [4] [3] [2] [1] [0]
B
S
･･････････
Data1[7:0]
8 bits
RegAddr[6:0]
8 bits
NumOfData[6:0]
8 bits
RA RA RA RA RA RA RA DT
DA DA DA DA DA DA ND ND ND ND ND ND ND ND
[5] [4] [3] [2] [1] [0] [7] [6] [5] [4] [3] [2] [1] [0] RW [6] [5] [4] [3] [2] [1] [0] [7]
･･････････
･･････････
･･････････
DT DT DT DT DT DT DT DT DT DT DT
[2] [1] [0] [7] [6] [5] [4] [3] [2] [1] [0]
Data[7:0]
DT DT DT DT DT DT DT DT
[6] [5] [4] [3] [2] [1] [0] [7]
･･････････
Broadcast
Single
Read / Write
Device Address
Number Of Data
Register Address
Data
B:
S:
RW:
DA[5:0]:
ND[7:0]:
RA[6:0]:
DT[7:0]:
･･････････
Low
Figure 14. SPI Protocol (Write)
SCSB
･･････････
1st 2nd 3rd 4th 5th 6th 7th 8th
SCLK
SDI
･･････････
B
S
DA DA DA DA DA
[5] [4] [3] [2] [1]
DevAddr[5:0]
8 bits
SDO
Low
DA ND ND ND ND ND ND ND ND
RA RA RA RA RA RA RA
[0] [7] [6] [5] [4] [3] [2] [1] [0] RW [6] [5] [4] [3] [2] [1] [0]
NumOfData[6:0]
8 bits
B
S
0
･･････････
RegAddr[6:0]
8 bits
DA DA DA DA DA DA ND ND ND ND ND ND ND ND
RA RA RA RA RA RA RA RD
[5] [4] [3] [2] [1] [0] [7] [6] [5] [4] [3] [2] [1] [0] RW [6] [5] [4] [3] [2] [1] [0] [7]
･･････････
･･････････
･･････････
･･････････
0
8 bits
･･････････
RD RD RD RD RD RD RD RD RD RD
[6] [5] [4] [3] [2] [1] [0] [7] [6] [5]
RD
[0]
B:
S:
RW:
DA[5:0]:
ND[6:0]:
RA[6:0]:
DT[7:0]:
RD[7:0]:
Broadcast
Single
Read / Write
Device Address
Number Of Data
Register Address
Data
Read Data
Figure 15. SPI Protocol (Read)
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BD12801MUF-M
Functions of Logic Blocks - continued
2.
SPI AC Timing
VSYNC
tSCSBVS
tSCSBHP
tSCSBVH
high Vth
low Vth
SCSB
fSCLK
tSCSBS
tSCLKH
tSCSBH
SCLK
tSCLKL
tSDIH
tSDIS
tSDIH
tSDIS
SDI
tSDOD
tSDOD
SDO
High Vth
Low Vth
Figure 16. SPI AC Timing
Table 2. SPI AC Timing
Recommended Operation Condition (Unless otherwise specified, Ta = -40 °C to +125 °C, VCC = 3.0 V to 5.5 V)
Parameter
Symbol
Min
Rating
Typ
Max
Unit
SCLK Frequency
fSCLK
0.1
-
5
MHz
SCLK Duty
DSCLK
40
-
60
%
SCLK High Level Range
tSCLKH
70
-
-
ns
SCLK Low Level Range
tSCLKL
70
-
-
ns
SDI Input Setup Time
tSDIS
40
-
-
ns
SDI Input Hold Time
Comments
tSDIH
25
-
-
ns
SCSB Input Setup Time
tSCSBS
100
-
-
ns
SCSB Input Hold Time
tSCSBH
100
-
-
ns
25
-
140
ns
VCC = VVREG33: 3.0 V to 3.6 V
SDO Output Delay Time
tSDOD
15
-
100
ns
VCC = VVREG33: 4.5 V to 5.5 V
15
-
140
ns
VCC = VVREG33: 3.0 V to 5.5 V
SCSB High Pulse Width
tSCSBHP
1000
-
-
ns
SCSB Setup Time for VSYNC
tSCSBVS
10
-
-
µs
SCSB Hold Time for VSYNC
tSCSBVH
10
-
-
µs
(Output load capacitance: 15 pF)
(Note) It is not available to input VSYNC during SCSB = L.
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BD12801MUF-M
Functions of Logic Blocks - continued
3.
Cascade Connection
Each device can be controlled by connecting the SCLK and SCSB pins to all devices in parallel, and by connecting
each SDO to the SDI of the next device in series. The maximum number of devices that can be cascaded is 16.
MCU
Device #1
DO
SDO
SDI
Device #2
SDI
Device #n
SDO
SDI
SCSB
SCSB
SCSB
SCLK
SCLK
SCLK
CS
SDO
*n = Max 16
CLK
DI
Figure 17. Image of Cascade Connection
4.
SPI Data Flow
MCU Write and Read as following flow. This IC has 3 timing for update analog control data.
Type A (immediately):
Type B (VSYNC):
Type C (PWM):
It updates data after SPI access.
It updates data after SPI access and VSYNC rising edge.
It updates data after SPI access and VSYNC and PWM rising edge.
(PWM is internal signal set by SPI)
So, there is mismatch between “Read data” and “Control data”.
register
SPI Write
A
(update timing
"Immediately")
VSYNC rising edge
B
MCU
Control
Data
Analog
Circuit
(update timing
"VSYNC")
SPI Read
PWM rising
C
buffer
Control
Data
(update timing
"PWM")
Figure 18. SPI Data Flow
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BD12801MUF-M
Functions of Logic Blocks - continued
5.
SPI Protocol
(1) Device Address
Bit
bit7
bit6
B
S
Parameter
B
Broadcast
S
Single byte
Device
Address
DevAddr [5:0]
bit5
bit4 bit3 bit2
bit1
bit0
DevAddr [5:0]
Function
B = 1: All chips receive the data (Write only/No Read)
B = 0: Write/Read to the chip that assigned by DevAddr [5:0]
S = 1: 1 byte Write/Read mode
S = 0: block Write/Read mode
0x00: Write the same data to the same RegAddr of all devices (Provided, B = 1)
0x01 to 0x3E: Each Device Address
0x3F: Write the different data to the same RegAddr of all devices (Provided, B = 1)
DevAddr of each device will be calculated by counting the number of byte of 0x00 data after the fall-edge of SCSB.
When matching the received DevAddr and calculated DevAddr of the device, Write/Read function will occur.
When unmatching the received DevAddr and calculated DevAddr of the chip, not taking in the data and output to
SDO. Refer to the each protocol for the details.
(2) Number of transferred byte when block Write/Read
bit7 bit6 bit5 bit4 bit3 bit2
0
Bit
NumOfData [6:0]
bit1
bit0
NumOfData [6:0]
Parameter
Number of transferred byte for one
device
Function
0x02 to 0x48
When S = 0 (Block Write/Read) of DevAddr, set the number of transferred byte (NumOfData) after DevAddr.
When S = 1, it skip this packet. (“Device Address” ->“Register Address” ->….)
Transferred byte number = NumOfData
SPI setting
B
S
0
0
1
0
1
1
DevAddr
0x00
0x01 to 0x3E
0x3F
0x00
0x01 to 0x3E
0x3F
0x00
0x01 to 0x3E
0x3F
0x00
0x01 to 0x3E
0x3F
Table 3. Access Table for Write (RW = 0)
Access to devices
For All device
For single
NumOfData
Same
Different
device
data
data
0x02 to 0x48
O
Not sending
O
this data
O
0x02 to 0x48
O
O
Not sending
this data
O
(Note 1) X: This setting isn’t acceptable. Don’t set this condition.
SPI setting
B
S
0
0
1
1
0/1
DevAddr
0x00
0x01 to 0x3E
0x3F
0x00
0x01 to 0x3E
0x3F
0x00
0x01 to 0x3E
0x3F
Table 4. Access Table for Read (RW = 1)
Access to devices
For All device
For single
NumOfData
Same
Different
device
data
data
0x02 to 0x48
O
Not sending
O
this data
0x02 to 0x48
-
(Note 1) X: This setting isn’t acceptable. Don’t set this condition.
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Acceptable(Note 1)
X
O
X
X
O
X
O
X
O
O
X
O
Acceptable(Note 1)
X
O
X
X
O
X
X
X
X
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10.May.2021 Rev.001
BD12801MUF-M
5.
SPI Protocol - continued
(3) Register Address
bit7
bit6
bit5
bit4 bit3 bit2
RW
Bit
Function
RW = 0: Write the registers
RW = 1: Read the registers
0x00 to 0x4F
Read/Write
RegAddr [6:0]
bit0
RegAddr [6:0]
Parameter
RW
bit1
Register Address
(4) Data
bit7
bit6
bit5
bit4 bit3 bit2
bit1
bit0
Data [7:0]
Bit
Data [7:0]
Parameter
Data
Value
0x00 to 0xFF
(5) Single device, 1 byte Write (Write to Device #1)
B:
0
Target Device receives the data
S:
1
Single byte
DevAddr[5:0]:
0x01
Target Device Address
NumOfData[6:0]: 1 byte Write mode
RW:
0
Write
RegAddr[6:0]:
0x02
Address
SDI
SDO
: Transfer in the order of DevAddr, RegAddr, and Data.
: The data input to SDI is output with a 1 byte shift.
SCSB
SCSB = H stop the output
of this data.
SCLK
B S DevAddr[5:0] RW RegAddr[6:0]
SDI
01
0x01
0
0x02
Data1 [7:0]
1 byte shift
SDO
0x01
01
0x01
0
0x02
Ex) Detail of Timing Chart
SCSB
SCLK
B S DevAddr[5:0]
RW
RegAddr[6:0]
Data1[7:0]
SDI
8 bit shift every Device
SDO
Device #1
Register
0x07
0x06
0x05
0x04
0x03
0x02
0x01
0x00
Data1
Figure 19. SPI Protocol of the 1 Byte Write to Device #1
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5.
SPI Protocol - continued
(6) Single device, 1 byte Write (Write to Device #3)
B:
0
Target Device receives the data
S:
1
Single byte
DevAddr[5:0]:
0x03
Target Device Address
NumOfData[6:0]: 1 byte Write mode
RW:
0
Write
RegAddr[6:0]:
0x02
Address
SDI
SDO
: Transfer in the order of DevAddr, RegAddr, and Data.
: Output the transferred data to the next device after SDI input by 1 byte.
DevAddr of each device will be calculated by counting the number of byte of 0x00 data after the fall-edge of
SCSB.
DevAddr = (Number of byte of 0x00 data) + 1
SCSB
SCLK
B S DevAddr[5:0] RW RegAddr[6:0]
Device #1 SDI
01
0x03
0
0x02
01
0x03
Device #1 SDO
(Device #2 SDI)
0x00
Device #2 SDO
(Device #3 SDI)
0x00
0x00
Device #3 SDO
0x00
0x00
Data1 [7:0]
0
0x02
01
0x03
0x00
2 byte 00h after SCSB↓
⇒DevAddr of Device#3 = 2 + 1 = 0x03
0x00
0x00
Data1 [7:0]
0x00
0
01
0x02
0x03
Data1 [7:0]
0
0x02
Match to the DevAddr
of Device#3
This data will be written to
RegAddr02h, Device#3
Device #1
Device #2
Device #3
Register
Register
Register
0x07
0x06
0x05
0x04
0x03
0x02
0x01
0x00
0x07
0x06
0x05
0x04
0x03
0x02
0x01
0x00
0x07
0x06
0x05
0x04
0x03
0x02
0x01
0x00
Data1
Figure 20. SPI Protocol of the 1 Byte Write to Device #3
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BD12801MUF-M
5.
SPI Protocol - continued
(7) Single device, “n byte” Write (Write to the consecutive register of Device #1)
B:
0
Target Device receives the data
S:
0
Single byte
DevAddr[5:0]:
0x01
Target Device Address
NumOfData[6:0]: 0x03
3 byte Write mode
RW:
0
Write
RegAddr[6:0]:
0x02
Address
SDI
SDO
: Transfer in the order of DevAddr, NumOfData, RegAddr, and Data.
: Output the transferred data to the next device after SDI input by 1 byte.
SCSB
SCLK
B S DevAddr[5:0] NumOfData[6:0] RW RegAddr[6:0]
Device #1 SDI
01
0x01
0
0x03
0
0x02
00
0x01
0
0x03
Device #1 SDO
(Device #2 SDI)
0x00
Device #2 SDO
(Device #3 SDI)
0x00
0x00
Device #3 SDO
0x00
0x00
00
0x01
0x00
Data1 [7:0]
0
0x02
0
00
2byte 00h after SCSB↓
⇒DevAddr of Device#3=2+1=0x03
0x03
0x01
Data2 [7:0]
Data1 [7:0]
Data2 [7:0]
0
0x02
Data1 [7:0]
0
0x03
Match to the DevAddr
of Device#3
Device #1
Device #2
Device #3
Register
Register
Register
0x07
0x07
0x07
0x06
0x06
0x06
0x05
0x05
0x05
0x04
Data3
0x04
0x04
0x03
Data2
0x03
0x03
0x02
Data1
0x02
0x02
0x01
0x01
0x01
0x00
0x00
0x00
Data3 [7:0]
0
0x02
This data will be written to
RegAddr02h, Device#3
Figure 21. SPI Protocol of the n Byte Write to Device #1
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5.
SPI Protocol - continued
(8) All device, different “1 byte” Write (Write the same 1 byte data to the same RegAddr of all Devices)
B:
1
All device receive data
S:
1
Single byte
DevAddr[5:0]:
0x3F
All device different data
NumOfData[6:0]: 1 byte Write mode
RW:
0
Write
RegAddr[6:0]:
0x02
Address
SDI
SDO
: Transfer in the order of DevAddr, RegAddr, and Data.
: Output the transferred data to the next device after SDI input by 1 byte.
SCSB
SCLK
B S DevAddr[5:0] RW RegAddr[6:0]
Device #1 SDI
11
0x3F
0
0x02
11
0x3F
Device #1 SDO
(Device #2 SDI)
0x00
Device #2 SDO
(Device #3 SDI)
0x00
0x00
Device #3 SDO
0x00
0x00
Data1 [7:0]
Data2 [7:0]
Data3 [7:0]
0x02
Data1 [7:0]
Data2 [7:0]
Data3 [7:0]
0x00
Data1 [7:0]
Data2 [7:0]
Data3 [7:0]
Data1 [7:0]
Data2 [7:0]
0
11
0x3F
0x00
0
0x02
11
0x3F
0
0x00
0x02
Device #1
Device #2
Device #3
Register
Register
Register
0x07
0x07
0x07
0x06
0x06
0x06
0x05
0x05
0x05
0x04
0x04
0x04
0x03
0x03
0x02
Data1
0x02
0x00
0x03
Data2
0x02
0x01
0x01
0x01
0x00
0x00
0x00
Data3
Figure 22. SPI Protocol of the 1 Byte Distinct Data Write to All Devices
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5.
SPI Protocol - continued
(9) All device, same “1 byte” Write (Write the same 1 byte data to the same RegAddr of all Devices)
B:
1
All device receive data
S:
1
Single byte
DevAddr[5:0]:
0x00
All device same data
NumOfData[6:0]: 1 byte Write mode
RW:
0
Write
RegAddr[6:0]:
0x02
Address
SDI
SDO
: Transfer in the order of DevAddr, RegAddr, and Data.
: Output the transferred data to the next device after SDI input by 1 byte.
SCSB
SCLK
B S DevAddr[5:0] RW RegAddr[6:0]
Device #1 SDI
01
0x00
0
0x02
11
0x00
Device #1 SDO
(Device #2 SDI)
0x00
Device #2 SDO
(Device #3 SDI)
0x00
0x00
Device #3 SDO
0x00
0x00
Data1 [7:0]
0
11
0x00
0x02
0x00
Data1 [7:0]
0x00
0
0x00
11
0x02
0x00
Data1 [7:0]
0x00
0
0x02
Device #1
Device #2
Device #3
Register
Register
Register
0x07
0x07
0x07
0x06
0x06
0x06
0x05
0x05
0x05
0x04
0x04
0x04
0x03
0x03
0x02
Data1
0x02
0x03
Data1
0x02
0x01
0x01
0x01
0x00
0x00
0x00
Data1
Figure 23. SPI Protocol of the 1 Byte Distinct Data Write to All Devices
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5.
SPI Protocol - continued
(10) All device, different “n byte” Write (Write the different n byte data to the same RegAddr of all Devices)
B:
1
All device receive data
S:
0
multi byte
DevAddr[5:0]:
0x3F
All device different data
NumOfData[6:0]: 0x02
2 byte Write mode
RW:
0
Write
RegAddr[6:0]:
0x02
Address
SDI
SDO
: Transfer in the order of DevAddr, NumOfData, RegAddr, and Data.
: Output the transferred data to the next device after SDI input by 1 byte.
SCSB
SCLK
B S DevAddr[5:0]
Device #1 SDI
11
0x3F
NumOfData[6:0] RW RegAddr[6:0]
0
0x02
0
10
0x3F
0
Device #1 SDO
(Device #2 SDI)
0x00
Device #2 SDO
(Device #3 SDI)
0x00
0x00
Device #3 SDO
0x00
0x00
0x02
0x02
10
0x3F
0x00
Data1 [7:0]
0
0x02
0
0x02
10
0x3F
Data2 [7:0]
Data3 [7:0]
Data1 [7:0]
0
0x02
0
0x02
Data4 [7:0]
Data5 [7:0]
Data6 [7:0]
0x00
0x00
Data2 [7:0]
Data3 [7:0]
Data4 [7:0]
Data5 [7:0]
Data6 [7:0]
0x00
Data1 [7:0]
Data2 [7:0]
Data3 [7:0]
Data4 [7:0]
Data5 [7:0]
Data6 [7:0]
Data1 [7:0]
Data2 [7:0]
Data3 [7:0]
Data4 [7:0]
Data5 [7:0]
0
0x02
Device #1
Device #2
Device #3
Register
Register
Register
0x07
0x07
0x07
0x06
0x06
0x06
0x05
0x05
0x05
0x04
0x04
0x04
0x03
Data2
0x03
Data4
0x03
Data6
0x02
Data1
0x02
Data3
0x02
Data5
0x01
0x01
0x01
0x00
0x00
0x00
Figure 24. SPI Protocol of the n Byte Distinct Data Write to All Devices
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5.
SPI Protocol - continued
(11) All device, same “n byte” Write (Write the same n byte data to the same RegAddr of all Devices)
B:
1
All device receive data
S:
0
multi byte
DevAddr[5:0]:
0x00
All device same data
NumOfData[6:0]: 0x03
3 byte Write mode
RW:
0
Write
RegAddr[6:0]:
0x02
Address
SDI
SDO
: Transfer in the order of DevAddr, NumOfData, RegAddr, and Data.
: Output the transferred data to the next device after SDI input by 1 byte.
SCSB
SCLK
B S DevAddr[5:0] NumOfData[6:0] RW RegAddr[6:0]
Device #1 SDI
10
0x00
0
0x03
10
0x00
Device #1 SDO
(Device #2 SDI)
0x00
Device #2 SDO
(Device #3 SDI)
0x00
0x00
Device #3 SDO
0x00
0x00
0
0
10
0x02
0x03
0x00
0x00
Data1 [7:0]
0
0x02
0
0x03
10
Data2 [7:0]
Data3 [7:0]
Data1 [7:0]
0x00
0
0x02
0
0x03
0x00
0x00
Data2 [7:0]
Data3 [7:0]
0x00
Data1 [7:0]
Data2 [7:0]
Data3 [7:0]
Data1 [7:0]
Data2 [7:0]
0
0x02
Device #1
Device #2
Device #3
Register
Register
Register
0x07
0x07
0x07
0x06
0x06
0x06
0x05
0x05
0x05
0x04
Data3
0x04
Data3
0x04
Data3
0x03
Data2
0x03
Data2
0x03
Data2
0x02
Data1
0x02
Data1
0x02
Data1
0x01
0x01
0x01
0x00
0x00
0x00
Figure 25. SPI Protocol of the n Byte Same Data Write to All Devices
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5.
SPI Protocol - continued
(12) Single device, “1 byte” Read (Read the 1 byte data from Device #2)
B:
0
Target device receive each data
S:
1
single byte
DevAddr[5:0]:
0x02
Target Device Address
NumOfData[6:0]: 1 byte Read mode
RW:
1
Read
RegAddr[6:0]:
0x03
Address
SDI
SDO
: Transfer in the order of DevAddr and RegAddr.
: Output the transferred data to the next device after SDI input by 1 byte.
SCSB
SCLK
B S DevAddr[5:0] RW RegAddr[6:0]
Device #1 SDI
01
0x02
1
0x03
01
0x02
Device #1 SDO
(Device #2 SDI)
0x00
Device #2 SDO
(Device #3 SDI)
0x00
0x00
Device #3 SDO
0x00
0x00
0x00
1
0x00
0x03
0x00
0x00
0x00
0x00
0x00
Read Data[7:0]
01
0x02
0x00
1
01
Data1 [7:0]
0x03
0x02
1
0x03
Device #1
Device #2
Device #3
Register
Register
Register
0x07
0x07
0x07
0x06
0x06
0x06
0x05
0x05
0x05
0x04
0x04
0x04
0x03
0x03
0x02
0x02
0x02
0x01
0x01
0x01
0x00
0x00
0x00
Data1
0x00
Data1 [7:0]
0x03
Figure 26. SPI Protocol of the 1 Byte Read from Device #2
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5.
SPI Protocol - continued
(13) Single device, “n byte” Read (Read the n byte data from Device #2)
B:
0
Target device receive each data
S:
0
multi byte
DevAddr[5:0]:
0x02
Target Device Address
NumOfData:
0x02
1 byte Read mode
RW:
1
Read
RegAddr[6:0]:
0x03
Address
SDI
SDO
: Transfer in the order of DevAddr, NumOfData, and RegAddr.
: Output the transferred data to the next device after SDI input by 1 byte.
SCSB
SCLK
Device #1 SDI
B S DevAddr[5:0] NumOfData[6:0]
RW RegAddr[6:0]
00
1
0x02
0
0x02
00
0x02
Device #1 SDO
(Device #2 SDI)
0x00
Device #2 SDO
(Device #3 SDI)
0x00
0x00
Device #3 SDO
0x00
0x00
0
00
0x03
0x02
0x02
0x00
0x00
1
0x03
0
0x02
00
0x00
0x00
0x00
0x02
1
0x03
0
0x02
0x00
0x00
0x00
0x00
0x00
Data1 [7:0]
Data2 [7:0]
0x00
Data1 [7:0]
Data2 [7:0]
1
0x03
Device #1
Device #2
Device #3
Register
Register
Register
0x07
0x07
0x07
0x06
0x06
0x06
0x05
0x05
0x05
0x04
0x04
Data2
0x04
0x03
0x03
Data1
0x03
0x02
0x02
0x02
0x01
0x01
0x01
0x00
0x00
0x00
SCSB = H stop the output
of this data
Figure 27. SPI Protocol of the n Byte Read from Device #2
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5.
SPI Protocol - continued
(14) Example of n byte Write (Write the n byte data to Device #1 and #2)
Example of the transfer of 2 device Cascade Connection.
Transfer setting
Data
DevAddr
Number of transferred byte
RegAddr
Data for the duty setting of Duty
Dummy clock
for multi device transfer
SUM
1 byte
1 byte
1 byte
2 byte x 16 channel x 2 device
= 64 byte
1 byte
68 byte
DevAddr[5:0] NumOfData[6:0] RegAddr[6:0]
10
0x3F
0
0x20
0
0x18
Number of
transferred byte
for each device
device #1
DTYCNT01L
RegAddr of
DTYCNT01L
device #1
device #2
DTYCNT01U
device #1
DTYCNT01U
Date[7:0] x 2 x 16 ch
device #2
DTYCNT01L
Date[7:0] x 2 x 16 ch
device #2
DTYCNT16L
DTYCNT16L
device #1
DTYCNT16U
Dummy byte
device #2
DTYCNT16U
0x00
Dummy Clocks
Figure 28. Transfer Byte Number for Multi Access
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Functions of Logic Blocks - continued
6. Register Map
Each registers is updated at the 3 timings.
Provided for Type B and Type C, the registers are not updated when the update timing and SCSB = ‘Low’ are the same, and
wait for the next update timing when SCSB = ‘High’.
Reset Condition: “UVLO” condition = VREG33UVLO or VCCUVLO or TSD or EN is detected.
Register Update timing for control data
Type A : Updated to the newest data immediately when the data is written.
Type B : Updated to the newest data when the next VSYNC timing.
(rise-edge trigger) after the data is written.)
Type C : Updated to the newest data when the next VSYNC and PWM (PWM is internal signal) timing.
(rise-edge trigger of VSYNC, then rise-edge trigger of PWM (first PWM pulse when PWMFREQ[1:0] = 01h to 11h)
after the data is written.
Note: Don’t access (Write) register except for following register and write ‘0’ in ‘-’.
register
A
SPI Write
(update timing
"Immediately")
VSYNC rising edge
Control
Data
B
MCU
Analog
Circuit
(update timing
"VSYNC")
SPI Read
PWM rising
buffer
C
Control
Data
(update timing
"PWM")
Figure 29. SPI Data Flow
Address 0x01 to 0x16 (1/3)
Address
Bit[7]
Bit[6]
Bit[5]
Bit[4]
Bit[3]
Bit[2]
Bit[1]
Bit[0]
Register
Access
Initial
Reset
Condition
Update
Timing
-
0x00
-
-
-
-
-
-
-
-
R/W
0x00
UVLO
Type A
Blank
PWMFREQ
0x01
-
-
-
-
-
-
R/W
0x00
UVLO
Type A
PWM output frequency setting
ERRSET1
0x02
-
-
R/W
0x0F
UVLO
Type A
LED short voltage setting
SSMASK
0x03
SSMASK[7:0]
R/W
0x3C
UVLO
Type B
SS mask time
ERRMASK
0x04
ERRMASK[7:0]
R/W
0x29
UVLO
Type B
error mask time
ERREN
0x05
-
-
-
-
-
TSDWEN
LEDSHEN
R/W
0x07
UVLO
Type B
error enable setting
ERRSET2
0x06
FAILTEST
FAILCNT
-
ERRCLR
-
-
-
R/W
0x00
UVLO
Type A
Error controlling
Register Name
SCPTIME[1:0]
PWMFREQ[1:0]
LEDSH[3:0]
LEDOPEN
ERRLAT
(Note 1)
Comments
DLYCNT01
0x07
DLY01[7:0]
R/W
0x00
UVLO
Type B
LED1 PWM Delay setting upper 8bit
DLYCNT02
0x08
DLY02[7:0]
R/W
0x00
UVLO
Type B
LED2 PWM Delay setting upper 8bit
DLYCNT03
0x09
DLY03[7:0]
R/W
0x00
UVLO
Type B
LED3 PWM Delay setting upper 8bit
DLYCNT04
0x0A
DLY04[7:0]
R/W
0x00
UVLO
Type B
LED4 PWM Delay setting upper 8bit
DLYCNT05
0x0B
DLY05[7:0]
R/W
0x00
UVLO
Type B
LED5 PWM Delay setting upper 8bit
DLYCNT06
0x0C
DLY06[7:0]
R/W
0x00
UVLO
Type B
LED6 PWM Delay setting upper 8bit
DLYCNT07
0x0D
DLY07[7:0]
R/W
0x00
UVLO
Type B
LED7 PWM Delay setting upper 8bit
DLYCNT08
0x0E
DLY08[7:0]
R/W
0x00
UVLO
Type B
LED8 PWM Delay setting upper 8bit
DLYCNT09
0x0F
DLY09[7:0]
R/W
0x00
UVLO
Type B
LED9 PWM Delay setting upper 8bit
DLYCNT10
0x10
DLY10[7:0]
R/W
0x00
UVLO
Type B
LED10 PWM Delay setting upper 8bit
DLYCNT11
0x11
DLY11[7:0]
R/W
0x00
UVLO
Type B
LED11 PWM Delay setting upper 8bit
DLYCNT12
0x12
DLY12[7:0]
R/W
0x00
UVLO
Type B
LED12 PWM Delay setting upper 8bit
DLYCNT13
0x13
DLY13[7:0]
R/W
0x00
UVLO
Type B
LED13 PWM Delay setting upper 8bit
DLYCNT14
0x14
DLY14[7:0]
R/W
0x00
UVLO
Type B
LED14 PWM Delay setting upper 8bit
DLYCNT15
0x15
DLY15[7:0]
R/W
0x00
UVLO
Type B
LED15 PWM Delay setting upper 8bit
DLYCNT16
0x16
DLY16[7:0]
R/W
0x00
UVLO
Type B
LED16 PWM Delay setting upper 8bit
(Note) WO: Write Only, RO: Read Only, R/W: Read and Write
(Note 1) Update timing of ERRLAT is Type B.
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6. Register Map – continued
Address 0x17 to 0x47 (2/3)
Register
Access
Initial
Reset
Condition
Update
Timing
Comments
R/W
0x00
UVLO
Type C
PWM pulse number setting
R/W
0x00
UVLO
Type C
LED1 PWM ON duty Lower 8bit
R/W
0x00
UVLO
Type C
LED1 PWM ON duty Upper 5bit
R/W
0x00
UVLO
Type C
LED2 PWM ON duty Lower 8bit
R/W
0x00
UVLO
Type C
LED2 PWM ON duty Upper 5bit
R/W
0x00
UVLO
Type C
LED3 PWM ON duty Lower 8bit
R/W
0x00
UVLO
Type C
LED3 PWM ON duty Upper 5bit
R/W
0x00
UVLO
Type C
LED4 PWM ON duty Lower 8bit
R/W
0x00
UVLO
Type C
LED4 PWM ON duty Upper 5bit
R/W
0x00
UVLO
Type C
LED5 PWM ON duty Lower 8bit
R/W
0x00
UVLO
Type C
LED5 PWM ON duty Upper 5bit
R/W
0x00
UVLO
Type C
LED6 PWM ON duty Lower 8bit
R/W
0x00
UVLO
Type C
LED6 PWM ON duty Upper 5bit
R/W
0x00
UVLO
Type C
LED7 PWM ON duty Lower 8bit
R/W
0x00
UVLO
Type C
LED7 PWM ON duty Upper 5bit
R/W
0x00
UVLO
Type C
LED8 PWM ON duty Lower 8bit
R/W
0x00
UVLO
Type C
LED8 PWM ON duty Upper 5bit
R/W
0x00
UVLO
Type C
LED9 PWM ON duty Lower 8bit
R/W
0x00
UVLO
Type C
LED9 PWM ON duty Upper 5bit
R/W
0x00
UVLO
Type C
LED10 PWM ON duty Lower 8bit
R/W
0x00
UVLO
Type C
LED10 PWM ON duty Upper 5bit
R/W
0x00
UVLO
Type C
LED11 PWM ON duty Lower 8bit
R/W
0x00
UVLO
Type C
LED11 PWM ON duty Upper 5bit
R/W
0x00
UVLO
Type C
LED12 PWM ON duty Lower 8bit
R/W
0x00
UVLO
Type C
LED12 PWM ON duty Upper 5bit
R/W
0x00
UVLO
Type C
LED13 PWM ON duty Lower 8bit
R/W
0x00
UVLO
Type C
LED13 PWM ON duty Upper 5bit
R/W
0x00
UVLO
Type C
LED14 PWM ON duty Lower 8bit
R/W
0x00
UVLO
Type C
LED14 PWM ON duty Upper 5bit
R/W
0x00
UVLO
Type C
LED15 PWM ON duty Lower 8bit
R/W
0x00
UVLO
Type C
LED15 PWM ON duty Upper 5bit
R/W
0x00
UVLO
Type C
LED16 PWM ON duty Lower 8bit
R/W
0x00
UVLO
Type C
LED16 PWM ON duty Upper 5bit
LCDAC1[7:0]
R/W
0xFF
UVLO
Type C
LED1 local DAC setting
0x39
LCDAC2[7:0]
R/W
0xFF
UVLO
Type C
LED2 local DAC setting
0x3A
LCDAC3[7:0]
R/W
0xFF
UVLO
Type C
LED3 local DAC setting
0x3B
LCDAC4[7:0]
R/W
0xFF
UVLO
Type C
LED4 local DAC setting
LCDAC5
0x3C
LCDAC5[7:0]
R/W
0xFF
UVLO
Type C
LED5 local DAC setting
LCDAC6
0x3D
LCDAC6[7:0]
R/W
0xFF
UVLO
Type C
LED6 local DAC setting
LCDAC7
0x3E
LCDAC7[7:0]
R/W
0xFF
UVLO
Type C
LED7 local DAC setting
LCDAC8
0x3F
LCDAC8[7:0]
R/W
0xFF
UVLO
Type C
LED8 local DAC setting
LCDAC9
0x40
LCDAC9[7:0]
R/W
0xFF
UVLO
Type C
LED9 local DAC setting
LCDAC10
0x41
LCDAC10[7:0]
R/W
0xFF
UVLO
Type C
LED10 local DAC setting
LCDAC11
0x42
LCDAC11[7:0]
R/W
0xFF
UVLO
Type C
LED11 local DAC setting
LCDAC12
0x43
LCDAC12[7:0]
R/W
0xFF
UVLO
Type C
LED12 local DAC setting
LCDAC13
0x44
LCDAC13[7:0]
R/W
0xFF
UVLO
Type C
LED13 local DAC setting
LCDAC14
0x45
LCDAC14[7:0]
R/W
0xFF
UVLO
Type C
LED14 local DAC setting
LCDAC15
0x46
LCDAC15[7:0]
R/W
0xFF
UVLO
Type C
LED15 local DAC setting
LCDAC16
0x47
LCDAC16[7:0]
R/W
0xFF
UVLO
Type C
LED16 local DAC setting
Register Name
Address
Bit[7]
Bit[6]
Bit[5]
Bit[4]
Bit[3]
Bit[2]
PWMPLS
0x17
-
-
-
PLSSET
-
-
DTYCNT01L
0x18
DTYCNT01U
0x19
-
-
DTYEN01
DTYCNT02L
0x1A
DTYCNT02U
0x1B
DTYCNT03L
0x1C
DTYCNT03U
0x1D
DTYCNT04L
0x1E
DTYCNT04U
0x1F
DTYCNT05L
0x20
DTYCNT05U
0x21
DTYCNT06L
0x22
DTYCNT06U
0x23
DTYCNT07L
0x24
DTYCNT07U
0x25
DTYCNT08L
0x26
DTYCNT08U
0x27
DTYCNT09L
0x28
DTYCNT09U
0x29
DTYCNT10L
0x2A
DTYCNT10U
0x2B
DTYCNT11L
0x2C
DTYCNT11U
0x2D
DTYCNT12L
0x2E
DTYCNT12U
0x2F
DTYCNT13L
0x30
DTYCNT13U
0x31
DTYCNT14L
0x32
DTYCNT14U
0x33
DTYCNT15L
0x34
DTYCNT15U
0x35
DTYCNT16L
0x36
DTYCNT16U
0x37
LCDAC1
0x38
LCDAC2
LCDAC3
LCDAC4
DTY01[7:0]
DTY01[12:8]
DTY02[7:0]
-
-
DTYEN02
DTY02[12:8]
DTY03[7:0]
-
-
DTYEN03
DTY03[12:8]
DTY04[7:0]
-
-
DTYEN04
DTY04[12:8]
DTY05[7:0]
-
-
DTYEN05
DTY05[12:8]
DTY06[7:0]
-
-
DTYEN06
DTY06[12:8]
DTY07[7:0]
-
-
DTYEN07
DTY07[12:8]
DTY08[7:0]
-
-
DTYEN08
DTY08[12:8]
DTY09[7:0]
-
-
DTYEN09
DTY09[12:8]
DTY10[7:0]
-
-
DTYEN10
DTY10[12:8]
DTY11[7:0]
-
-
DTYEN11
DTY11[12:8]
DTY12[7:0]
-
-
DTYEN12
DTY12[12:8]
DTY13[7:0]
-
-
DTYEN13
DTY13[12:8]
DTY14[7:0]
-
-
DTYEN14
DTY14[12:8]
DTY15[7:0]
-
-
DTYEN15
DTY15[12:8]
DTY16[7:0]
-
-
DTYEN16
DTY16[12:8]
Bit[1]
Bit[0]
PLSNUM[1:0]
(Note) WO: Write Only, RO: Read Only, R/W: Read and Write
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6. Register Map - continued
Address 0x48 to 0x4F (3/3)
Register Name
-
Address
Bit[7]
Bit[6]
Bit[5]
Bit[4]
Bit[3]
Bit[2]
Bit[1]
Bit[0]
Register
Access
Initial
Reset
Condition
Update
Timing
0x48
-
-
-
-
-
-
-
-
-
-
-
-
RO
0x00
UVLO
Type A
error flag LEDn open
(n = 1 to 8)
RO
0x00
UVLO
Type A
error flag LEDn open
(n = 9 to 16)
RO
0x00
UVLO
Type A
error flag LEDn short
(n = 1 to 8)
RO
0x00
UVLO
Type A
error flag LEDn short
(n = 9 to 16)
RO
0x00
UVLO
Type A
error flag ISET short and SCP
RO
0x00
UVLO
Type A
error flag TSD warning
(n = 1 to 8)
RO
0x00
UVLO
Type A
error flag TSD warning
(n = 9 to 16)
ERRLEDOPA
0x49
ERRLEDOPB
0x4A
ERRLEDSHA
0x4B
ERRLEDSHB
ERLOP[7:0]
(Note 2)
ERLOP[15:8]
(Note 2)
ERLSH[7:0]
(Note 2)
ERLSH[15:8]
0x4C
ERRISETSCP
0x4D
ERRTSDA
0x4E
ERRTSDB
0x4F
(Note 2)
-
-
-
-
-
-
WARSCP
(Note 3)
WARISET
(Note 2)
WARTSD[7:0]
(Note 2)
WARTSD[15:8]
(Note 2)
Comments
blank
(Note) WO: Write Only, RO: Read Only, R/W: Read and Write
(Note 2) Released condition is referred in description of register.
(Note 3) Released condition is only reset.
7. Description of Registers
Address 0x01: PWMFREQ
Bit No
Bit[7]
Name
Initial value
0
Output PWM frequency setting [Read/Write]
Bit[6]
Bit[5]
Bit[4]
Bit[3]
0
0
0
0
Bit[2]
0
Initial value 0x00
Bit[1]
Bit[0]
PWMFREQ[1:0]
0
0
Update: Immediately
The data in register is updated to the newest data immediately when the new data is written.
Regarding EXTCLK frequency, refer to the following list.
If it is different from relation of PWMFREQ and EXTCLK frequency, it can’t control LED normally.
Don’t change value during dimming. (only initial setting before PWM setting)
PWMFREQ[1:0]
0
1
2
3
PWM Frequency
VSYNC x 1
VSYNC x 2
VSYNC x 4
VSYNC x 8
EXTCLK Frequency
VSYNC x 8,192
VSYNC x 16,384
VSYNC x 32,768
VSYNC x 65,536
Example of EXTCLK setting is referred. This IC can be acceptable to input EXTCLK under 5 MHz.
(Refer to frequency range of electric characteristics)
(Example) EXTCLK frequency and PWM frequency
PWMFREQ[1:0]
0
1
2
3
60
491,520
60
983,040
120
1,966,080
240
3,932,160
480
VSYNC Frequency [Hz]
120
240
983,040
1,966,080
120
240
1,966,080
3,932,160
240
480
3,932,160
480
-
Upper: EXTCLK frequency
Lower: PWM frequency
480
3,932,160
480
[Hz]
‘-’ is not acceptable to set this value in PWMFREQ register.
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7. Description of Registers - continued
PWMFREQ[1:0] = 0
VSYNC
EXTCLK = VSYNC x 8,192(213)[Hz]
EXTCLK
PWM:VSYNCx1[Hz]
PWMn
resolution:213
PWMFREQ[1:0] = 1
VSYNC
EXTCLK = VSYNC x 16,384(214)[Hz]
EXTCLK
PWM:VSYNCx2[Hz]
PWMn
resolution:213
PWMFREQ[1:0] = 2
VSYNC
EXTCLK = VSYNC x 32,768(215)[Hz]
EXTCLK
PWM:VSYNCx4[Hz]
PWMn
resolution:213
PWMFREQ[1:0] = 3
VSYNC
EXTCLK = VSYNC x 65,536(216)[Hz]
EXTCLK
PWM:VSYNCx8[Hz]
PWMn
resolution:213
Figure 30. PWMFREQ Setting
Address 0x02: ERRSET1
Bit No
Bit[7]
Name
Initial value
0
LED short detection voltage setting
Bit[6]
Bit[5]
Bit[4]
SCPTIME[1:0]
0
0
0
Bit[3]
1
[Read/Write]
Initial value 0x0F
Bit[2]
Bit[1]
Bit[0]
LEDSH[3:0]
1
1
1
Update: Immediately
The data in register is updated to the newest data immediately when the new data is written.
Bit[5:4]
SCPTIME
This register controls MASK time for SCP detected.
SCPTIME[1:0]
MASK Time
0
1 VSYNC cycle
1
2 VSYNC cycle
2
4 VSYNC cycle
3
8 VSYNC cycle
Bit[3:0]
LEDSH[3:0]
This register controls detection voltage LED short protection.
LEDSH[3:0]
0x0 to 0x8
0x9
0xA
0xB
0xC
0xD
0xE
0xF
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Detection Voltage [V]
Not available
3.00
3.30
3.60
3.90
4.20
4.50
4.80
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7. Description of Registers – continued
Address 0x03: SSMASK
Soft start mask register
Bit No
Bit[7]
Bit[6]
Bit[5]
Name
Initial value
0
0
1
[Read/Write]
Bit[4]
Bit[3]
SSMASK[7:0]
1
1
Bit[2]
Initial value 0x3C
Bit[1]
1
0
Update:
Bit[0]
0
VSYNC
The register data is updated to the newest data when the next VSYNC signal rises up after the data is written.
Set value more than 0x02.
It controls protect function (LED open protection, LED short protection, SCP, ISET short warning, TSD warning) after
SSMASK time. So, it is not available to operate protection function during SSMASK time.
The time of mask of ERROR detection is set by counting the number of VSYNC.
Time of mask = SSMASK x VSYNC
(except for waiting time until 1st VSYNC pulse)
VSYNC [Hz]
Max Mask time [ms]
Address 0x04: ERRMASK
Bit No
Bit[7]
Name
Initial value
0
60
4,250
120
2,125
240
1,062.5
ERROR output mask time setting register
Bit[6]
Bit[5]
Bit[4]
Bit[3]
ERRMASK[7:0]
0
1
0
1
480
531.3
[Read/Write]
Bit[2]
0
Initial value 0x29
Bit[1]
Bit[0]
0
Update:
1
VSYNC
The register data is updated to the newest data when the next VSYNC signal rises up after the data is written.
When 0 to 2 is written to this register, the register value becomes 3.
When over 3 is written to this register, writing value becomes register value.
This IC has mask function for “LED open protection” and “LED short protection”. It can’t detect these errors during this time.
ERROR mask time is set by counting the number of EXTCLK.
Mask time = ERRMASK x EXTCLK
Example) ERRMASK = 3: mask 3 clock to 4 clock (PWM = H and error signal (after synchronizing))
‘-’ column is not acceptable setting.
VSYNC/EXTCLK condition vs “Maximum Mask time” (Default 0x29 (41))
VSYNC [Hz]
PWMFREQ[1:0]
60
120
240
480
0
519
259
130
65
1
259
130
65
2
130
65
3
65
-
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7. Description of Registers – continued
Address 0x05: ERREN
Error enable setting
Bit No
Bit[7]
Bit[6]
Bit[5]
Name
Initial value
0
0
0
[Read/Write]
Bit[4]
Bit[3]
0
0
Bit[2]
TSDWEN
1
Initial value 0x07
Bit[1]
Bit[0]
LEDSHEN
LEDOPEN
1
1
Update: VSYNC
This register is updated to the newest data when the next VSYNC signal rises up after the data is written.
Bit[2]:
0:
1:
TSDWEN
disable (error register and error output (FAIL) is initial condition if “TSD warning” is occurred
enable (135 deg (Typ))
Bit[1]
0:
1:
LEDSHEN
disable (error register and error output (FAIL) is initial condition if “LED short protection” is occurred
enable
Bit[0]
0:
1:
LEDOPEN
disable (error register and error output (FAIL) is initial condition if “LED open protection” is occurred
enable
“LED open function” effects SCP detection. So, it is not available to change this enable during operation.
Address 0x06: ERRSET2
Bit No
Bit[7]
Name
FAILTEST
Initial value
0
Error Latch mode setting
[Read/Write]
Initial value 0x00
Bit[6]
Bit[5]
Bit[4]
Bit[3]
Bit[2]
Bit[1]
Bit[0]
FAILCNT
ERRCLR
ERRLAT
0
0
0
0
0
0
0
Update: FAILTEST, FAILCNT, ERRCLR: Immediately, ERRLAT: VSYNC
The data (ERRCLR) in register is updated to the newest data immediately when the new data is written.
The register data (ERRLAT) is updated to the newest data when the next VSYNC signal rises up after the data is written.
Bit[7]
0:
1:
FAILTEST
normal operation
It available to control the FAIL pin output by FAILCNT register.
Bit[4]
0:
1:
FAILCNT
It outputs Low from the FAIL pin when FAILTEST = 1
It outputs High from the FAIL pin when FAILTEST = 1
Bit[4]
0:
1:
ERRCLR
no operation
clear error register and return Hi-Z in FAIL output when ERRLAT = 1
ERRCLR return ‘0’ automatically. So, it can’t read ‘1’.
Bit[0]
0:
1:
ERRLAT
error register and FAIL output are returned to initial condition when error is released.
error register and FAIL output are kept until writing ‘1’ in ERRCLR.
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7. Description of Registers - continued
Address 0x07: DLYCNT01 (LED1 PWM Delay setting register) [Read/Write]
Bit No
Bit[7]
Bit[6]
Bit[5]
Bit[4]
Bit[3]
Name
DLY01[7:0]
Initial value
0
0
0
0
0
Initial value 0x00
Bit[2]
Bit[1]
0
0
Bit[0]
0
Update: VSYNC
The register data is updated to the newest data when the next VSYNC signal rises up after the data is written.
This register is used to make setting of delay width for PWM light modulation in a total of 8 bits,
i.e., Bit[7:0] when Address = 0x07.
DLY01[7:0]
0x00
0x01
0x02
0x03
…
0xXX
…
0xFC
0xFD
0xFE
0xFF
LED Delay Width (clock width@EXTCLK)
PWMFREQ[1:0]
PWMFREQ[1:0]
PWMFREQ[1:0]
PWMFREQ[1:0]
=0
=1
=2
=3
4 clock to 5 clock width@EXTCLK from posedge of VSYNC (*)
(*) + 0x01 x 25
(*) + 0x01 x 26
(*) + 0x01 x 27
(*) + 0x01 x 28
(*) + 0x02 x 25
(*) + 0x02 x 26
(*) + 0x02 x 27
(*) + 0x02 x 28
(*) + 0x03 x 25
(*) + 0x03 x 26
(*) + 0x03 x 27
(*) + 0x03 x 28
...
...
...
...
(*) + 0xXX x 25
(*) + 0xXX x 26
(*) + 0xXX x 27
(*) + 0xXX x 28
...
...
...
...
(*) + 0xFC x 25
(*) + 0xFC x 26
(*) + 0xFC x 27
(*) + 0xFC x 28
(*) + 0xFD x 25
(*) + 0xFD x 26
(*) + 0xFD x 27
(*) + 0xFD x 28
5
6
7
(*) + 0xFE x 2
(*) + 0xFE x 2
(*) + 0xFE x 2
(*) + 0xFE x 28
5
6
7
(*) + 0xFF x 2
(*) + 0xFF x 2
(*) + 0xFF x 2
(*) + 0xFF x 28
Decide “DLY01 setting” in VSYNC and EXTCLK jitter of MCU. Refer to “PWM behavior at close VSYNC interval”.
Address 0x08 to 0x16: DLYCNTn (n = 2 to 16)
This register is used to make PWM delay width setting for LED2 to LED16. The setting procedure is the same as that for
LED1 with Address set to 0x07.
The register data is updated to the newest data when the next VSYNC signal rises up after the data is written.
Address 0x17: PWMPLS (PWM pulse number setting)
Bit No
Bit[7]
Bit[6]
Bit[5]
Name
Initial value
0
0
0
[Read/Write]
Bit[4]
Bit[3]
PLSSET
0
0
Initial value 0x00
Bit[2]
Bit[1]
Bit[0]
PLSNUM[1:0]
0
0
0
Update: PWM
The register data is updated to the newest data when the next PWM signal rises up after the data is written.
PWMFREQ[1:0]
0
1
2
3
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0
4
8
PLSNUM (PWM pulse number)
1
2
1
2
1
3
2
6
4
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7.
Description of Registers - continued
It outputs PWM pulse in Head position When PLSSET = 0
Example) PWMFREQ[1:0] = 3, PLSSET = 0
PLSNUM[1:0] = 0
VSYNC
PWMn
PLSNUM[1:0] = 1
VSYNC
OFF
PWMn
PLSNUM[1:0] = 2
VSYNC
OFF
PWMn
PLSNUM[1:0] = 3
VSYNC
OFF
OFF
PWMn
Figure 31. PWM Pulse Number Setting (Tail OFF)
It outputs PWM pulse in Tail position When PLSSET = 1.
Example) PWMFREQ[1:0] = 3, PLSSET = 1
PLSNUM[1:0] = 0
VSYNC
PWMn
PLSNUM[1:0] = 1
VSYNC
OFF
OFF
PWMn
PLSNUM[1:0] = 2
VSYNC
OFF
OFF
OFF
OFF
PWMn
PLSNUM[1:0] = 3
VSYNC
PWMn
Figure 32. PWM Pulse Number Setting (Head OFF)
DLY = 0x7F, PWMFREQ = 3, PLSNUM[1:0] = 2, PLSSET = 0
VSYNC
EXTCLK = VSYNC x 65,536[Hz]
EXTCLK
SPI
delay
OFF
PWMn
update
LCDAC setting
analog signal(image)
Figure 33. PWM Pulse Number Setting
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7. Description of Registers - continued
Address 0x18: DTYCNT01L (LED1 PWM duty setting register - lower 8 bits)
Bit No
Bit[7]
Bit[6]
Bit[5]
Bit[4]
Bit[3]
Name
DTY01[7:0]
Initial value
0
0
0
0
0
[Read/Write]
Bit[2]
0
Initial value 0x00
Bit[1]
Bit[0]
0
0
Update: PWM
The register data is updated to the newest data when the next PWM signal rises up after the data is written.
Address 0x19: DTYCNT01U (LED1 PWM duty setting register - upper 5 bits)
Bit No
Bit[7]
Bit[6]
Bit[5]
Bit[4]
Bit[3]
Name
DTYEN01
Initial value
0
0
0
0
0
[Read/Write]
Bit[2]
DTY01[12:8]
0
Initial value 0x00
Bit[1]
Bit[0]
0
0
Update: PWM
The register data is updated to the newest data when the next PWM signal rises up after the data is written.
This register is used to make setting of pulse duty for PWM light modulation in a total of 13 bits,
i.e., Bit[7:0] when Address = 0x18 and Bit[4:0] when Address = 0x19.
DTYEN01
0
1
1
1
1
1
1
1
1
1
DTY01[12:0]
0x000 to 0x1FFF
0x0000
0x0001
0x0002
0x0003
...
0x1FFC
0x1FFD
0x1FFE
0x1FFF
LED Pulse Width
0 clock width@EXTCLK
1 clock width@EXTCLK
2 clock width@EXTCLK
3 clock width@EXTCLK
4 clock width@EXTCLK
...
8189 clock width@EXTCLK
8190 clock width@EXTCLK
8191 clock width@EXTCLK
Normally set to High (Duty 100 %)
If DTYEN01 = 0 is set when it detects LED open/LED short in channel 1, Error register (ERLOP[0]/ERLSH[0]) and FAIL turn
normal condition.
Address 0x1A to 0x37: DTYCNTn (n = 2 to 16)
This register is used to make setting of PWM pulse width for LED2 to LED16. The setting procedure is the same as that for
LED1 with Address set to 0x1A and 0x37.
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7. Description of Registers - continued
Address 0x38: LCDAC1 (Analog light modulation setting for LED1)
[Read/Write]
Bit No
Bit[7]
Bit[6]
Bit[5]
Bit[4]
Bit[3]
Name
LCDAC1[7:0]
Initial value
1
1
1
1
1
Bit[2]
Initial value 0xFF
Bit[1]
1
1
Bit[0]
1
Update: PWM
The register data is updated to the newest data when the next PWM signal rises up after the data is written.
Address 0x39 to 0x47: LCDACn (n = 2 to 16)
This register is used to make setting of PWM pulse width for LED2 to LED16. The setting procedure is the same as that for
LED1 with Address set to 0x38.
This register can be written 0x00 to 0xFF value.
The DAC setting is possible, but the guarantee levels become more than 20 mA.
LCDACn[7:0]
(Write value)
0x00
0x01
...
0xXX
...
0xFF
𝐼𝐿𝐸𝐷𝑀𝐴𝑋 = 757/𝑅𝐼𝑆𝐸𝑇
ILEDn
ILEDMAX x 1/256
ILEDMAX x 2/256
…
ILEDMAX x (LCDACn +1)/256
…
ILEDMAX x 256/256
(n = 1 to 16)
[A]
𝐼𝐿𝐸𝐷𝑛 = 𝐼𝐿𝐸𝐷𝑀𝐴𝑋 × {(𝐿𝐶𝐷𝐴𝐶𝑛[7: 0] + 1)/256}
>
0.02
𝐼𝐿𝐸𝐷𝑛_𝐴𝑉𝐸 = 𝐼𝐿𝐸𝐷𝑛 × {(𝐷𝑇𝑌𝑛[12: 0] + 1)/ 8,192}
[A]
[A]
(𝑛 = 1 𝑡𝑜 16)
(𝑛 = 1 𝑡𝑜 16)
LED Current
Maximum setting
130 mA
ILEDMAX
Variable Range
ILEDn
ILEDn_AVE
Minimum Setting
20 mA
PWM Duty
t
Figure 34. Current Setting Image
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7. Description of Registers - continued
Address 0x49: ERRLEDOPA (LED1 to LED8 pin open ERROR monitor)
Bit No
Bit[7]
Bit[6]
Bit[5]
Bit[4]
Bit[3]
Name
ERLOP[7:0]
Initial value
0
0
0
0
0
[Read]
Initial value 0x00
Bit[2]
Bit[1]
0
0
Bit[0]
0
Update: Immediately
The register data is updated to the newest data immediately when the data (“LED open protection”) is detected.
Address 0x4A: ERRLEDOPB (LED8 to LED16 pin open ERROR monitor)
Bit No
Bit[7]
Bit[6]
Bit[5]
Bit[4]
Bit[3]
Name
ERLOP[15:8]
Initial value
0
0
0
0
0
[Read]
Initial value 0x00
Bit[2]
Bit[1]
0
0
Bit[0]
0
Update: Immediately
The register data is updated to the newest data immediately when the data (“LED open protection”) is detected.
ERLOP[n-1]
0
1
Status
Normal
Detect protection(Note 1)
(n = 1 to 16 channel)
(Note 1) ERRLAT = 0: ERLOP[n-1] turns 0, if Error is released or “DTYENn = 0” is set or “LEDOPEN = 0” is set.
ERRLAT = 1: ERLOP[n-1] turns 0, if “ERRCLR = 1” is set.
Address 0x4B: ERRLEDSHA (LED1 to LED8 short ERROR monitor)
Bit No
Bit[7]
Bit[6]
Bit[5]
Bit[4]
Bit[3]
Name
ERLSH[7:0]
Initial value
0
0
0
0
0
[Read]
Bit[2]
0
Initial value 0x00
Bit[1]
Bit[0]
0
0
Update: Immediately
The register data is updated to the newest data immediately when the data (“LED short protection”) is detected.
Address 0x4C: ERRLEDSHB (LED8 to LED16 short ERROR monitor)
Bit No
Bit[7]
Bit[6]
Bit[5]
Bit[4]
Bit[3]
Name
ERLSH[15:8]
Initial value
0
0
0
0
0
[Read]
Bit[2]
0
Initial value 0x00
Bit[1]
Bit[0]
0
0
Update: Immediately
The register data is updated to the newest data immediately when the data (“LED short protection”) is detected.
ERLSH[n-1]
0
1
Status
Normal
Detect protection(Note 2)
(n = 1 to 16 channel)
(Note 2) ERRLAT = 0: ERLSH[n-1] turns 0, if Error is released or “DTYENn = 0” is set or “LEDSHEN = 0” is set.
ERRLAT = 1: ERLSH[n-1] turns 0, if “ERRCLR = 1” is set.
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7. Description of Registers - continued
Address 0x4D: ERRISETSCP (ISET short warning and SCP)
Bit No
Bit[7]
Bit[6]
Bit[5]
Bit[4]
Name
Initial value
0
0
0
0
[Read]
Bit[3]
0
Bit[2]
0
Initial value 0x00
Bit[1]
Bit[0]
WARSCP
WARISET
0
0
Update: Immediately
Bit[1]
The register data is updated to the newest data immediately when the data (“SCP”) are detected.
WARSCP
0
1
Status
Normal
Detect SCP(Note 1)
(Note 1) WARSCP turns 0 by only reset. It operates SCP circuit using “LED open circuit”.
Don’t change LEDOPEN = 0.
Bit[0]
The register data is updated to the newest data immediately when the data (“ISET short warning”) are detected.
WARISET
0
1
Status
Normal
Detect ISET short
(ISET resistor is under 2.5 kΩ)(Note 2)
(Note 2) ERRLAT = 0: WARISET turns 0, if Error is released.
ERRLAT = 1: WARISET turns 0, if “ERRCLR = 1” is set.
Address 0x4E: ERRTSDA (TSD warning)
Bit No
Bit[7]
Bit[6]
Name
Initial value
0
0
Bit[5]
[Read]
0
Initial value 0x00
Bit[4]
Bit[3]
Bit[2]
WARTSD[7:0]
0
0
0
Bit[1]
0
Bit[0]
0
Update: Immediately
The register data is updated to the newest data immediately when the data (“TSD warning”) are detected.
Address 0x4F: ERRTSDB (TSD warning)
Bit No
Bit[7]
Bit[6]
Name
Initial value
0
0
Bit[5]
0
[Read]
Initial value 0x00
Bit[4]
Bit[3]
Bit[2]
WARTSD[15:8]
0
0
0
Bit[1]
0
Bit[0]
0
Update: Immediately
The register data is updated to the newest data immediately when the data (“TSD warning”) are detected.
WARTSD[n-1]
0
1
Status
Normal
Detect protection(Note 3)
(n = 1 to 16 channel)
(Note 3) ERRLAT = 0: WARTSD[n-1] turns 0, if Error is released or “TSDWEN = 0” is set.
ERRLAT = 1: WARTSD[n-1] turns 0, if “ERRCLR = 1” is set.
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Timing Chart
1. PWM Delay and ON Duty Setting Procedure Each Dimming Mode
Available to access register for next frame
SPI
VSYNC
register
DLYn
DTYn
update at next VSYNC
DLYCNTn
DTYn_buf
update at next PWM output
DTYCNTn
DLYCNTn
DTYCNTn
DLYCNTn
PWMn
Figure 35. Head Control(PWMFREQ[1:0] = 0)
ex) DLY01[7:0] = 0x01,DTY01[12:0] = 0x05
VSYNC
1st
2nd
3rd
4th
5th
EXTCLK
r_vsync_ext_q
(internal signal)
r_vsync_ext_qq
(internal signal)
w_vsync_pls
(internal signal)
0 x 020
dly counter
(internal signal)
0
1
2
3
4
5
6
0
dly counter1
(internal signal)
0
1
2
3
4
5
6
1
2
3
7
dly complh
(internal signal)
dly comphl
(internal signal)
DLY01[7:0]x32
DTY01[11:0]+1
PWM1 L->H : 0
H->L : DTY01+1
(when max value : 0)
PWM1
(internal signal)
Figure 36. Setting for PWM Delay and ON Duty for Head Control
By making register setting, PWM output delay and ON duty time counts of LED1 to LED16 can be controlled.
The above timing chart shows an example for LED1.
(Example) To make delay time count setting, write “delay time” in Address 0x07.
To make ON duty time count setting, write “duty time” in Address 0x18 and 0x19.
The delay counter starts counting after 4 to 5 EXTCLKs from the rise-edge of VSYNC signal due to internal signal’s timing.
When the counter reaches the set delay value (0x07), the duty counter starts counting, also PWM1 signal is set to ‘High’.
Subsequently, when the duty counter reaches the set duty value (0x18 and 0x19), PWM1 signal is set to ‘Low’.
The sequence is continuously repeated. The procedure for LED2 to LED16 is the same as LED1.
It can set delay of 256 resolution of VSYNC period.
ntn frrame
(n+1)th frame
PWMFREQ[1:0] = 3
VSYNC
EXTCLK = VSYNC × 65,536 (216) [Hz]
EXTCLK
setting for (n+1)th frame
SPI
delay
256 clock (28)/bit
ntn frrame
PWMn
Figure 37. PWM Delay (PWMFREQ[1:0] = 3)
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Timing Chart - continued
2. PWM Behavior at Close VSYNC Interval
Basically, the frequency of EXTCLK pulse is 8,192(PWMFREQ[1:0] = 0) times of that of VSYNC.
Close-interval VSYNC up to 8,192 can make the stick to ‘High’/‘Low’ of PWM signals.
Example of PWM behavior for LED1 is shown as follows.
(1) Stick to High of PWM
Example: Delay = 0, Duty = 75 %
VSYNC: 8,192 divided
VSYNC: under 8,192 divided
VSYNC
EXTCLK
main counter
compdly
Duty counter
(each LED
Channel)
compdly
PWMn
PMW is stick to High
Figure 38. Waveform Function when PWM is Fixed to High
PWM is sets to ‘High’ at the trigger of compdly (internal signal that shows the arrival of Delay set value) = ‘High’, also is set
to ‘Low’ at the trigger of compdty (internal signal that shows the arrival of Duty set value) = ‘Low’.
“Main counter” is reset and starts counting up at the rise-edge of VSYNC. If it counts up until 8,191, it keeps 8,191 until
VSYNC pulse.
“duty counter” is reset and starts counting up at trigger of compdly. If trigger of compdty is generated, it keeps counter
value until next trigger of compdly.
For this example, compdly just after the rise-edge of VSYNC sets PWM = ‘High’ because Delay = 0 %.
“Duty counter” is reset and starts counting up at the pulse of compdly. For this example, as long as VSYNC is divided by
8,192 EXTCLK, PWM is set to ‘Low’ at the trigger of compdty after the arrival of Duty set value. While, If VSYNC is less
than 8,192 EXTCLK, PWM is stick to ‘High’. Because the counter is reset since VSYNC is input before the arrival of Duty
set value, and the trigger compdty to set PWM to ‘Low’ is not provided.
(2) Stick to Low of PWM
Example: Delay = 75 %, Duty = 50 %
VSYNC: 8,192 divided
VSYNC: under 8,192 divided
VSYNC
EXTCLK
main counter
compdly
no compdly pulse
duty counter
(each LED
Channel)
compdly
PWMn
PMW is stick to Low
Figure 39. Waveform Function when PWM is Fixed to Low
When the setting of Delay is not 0, PWM is also set to ‘High’ at the trigger of compdly and is set to L at the trigger of
compdty. When VSYNC is divided by up to 8,192 EXTCLK, PWM is also set to L after the arrival of Duty set value. But
when the interval of VSYNC is less than the setting of Delay, PWM is stick to ‘Low’. Because the counter is reset since
VSYNC is input before the arrival of Delay set value, and the trigger compdly to set PWM to ‘High’ is not provided.
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2. PWM Behavior at Close VSYNC Interval - continued
(3) Lower PWM duty
Example: Delay = 0, Duty = 75 %
VSYNC: 8,192 divided
VSYNC: over 8,192 divided
VSYNC
EXTCLK
main counter
compdly
duty counter
(each LED
channel)
compdly
PWMn
lower PWM duty
Figure 40. Waveform Function when PWM Duty is Low
For this example, compdly just after the rise-edge of VSYNC sets PWM = ‘High’ because Delay = 0 %.
“Duty counter” is reset and starts counting up at the pulse of compdly. For this example, If VSYNC is more than 8,192
EXTCLK, PWM is set to ‘Low’ at the trigger of compdty after the arrival of Duty set value. Counter keep 8,191 after count =
8,191 until next rise-edge of VSYNC. So PWM is lower than target duty in this case.
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Timing Chart - continued
3. ERROR Control
There are the following internal signals on timing chart:
PWM_OH[n-1] (n = 1 to 16)
PWM signal for LEDn (high: LED ON, low: LED OFF)
LOPDET_ID[n-1] (n = 1 to 16)
LED open error signal (low: error)
LSPDET_ID[n-1] (n = 1 to 16)
LED short error signal (low: error)
WARTSD_ID[n-1] (n = 1 to 16)
TSD warning signal (low: error)
WARISET_IL
ISET short warning (low: error)
SSEND
Soft start mask signal (low: mask)
r_lopdet, r_lspdet, r_vsync
retiming signal
r_wartsd, r_wariset
retiming signal
err_mskcnt
error mask counter
Timing chart of each ERROR detection is as follows
(1)
LED Short Protection
It operates as following when it detects (The LED pin voltage is over setting value) or released “LED short Error“.
(Example) Register setting: DLY02[7:0] = 0x00, ERRMASK[7:0] = 0x03, ERRLAT = 0
Enlarged view B
Enlarged view A
VSYNC
EXTCLK
PWM_OH[1]
LED2
VSHDET
VSHDET
LSPDET_ID[1]
r_lspdet[1]
SSEND
err_mskcnt[7:0]
0 x 00
ERRMASK register
0 x 03
Error register
All '0'
0 x 00
LED2 : 1 , other : 0
FAIL
Figure 41. LED Short Protection
(a) Enlarged chart (A)
VSYNC
EXTCLK
PWM_OH[1]
LED2
VSHDET
LSPDET_ID[1]
mask
2clock delay
(synchronize)
r_lspdet[1]
SSEND
err_mskcnt[7:0]
0 x 00
ERRMASK register
0 x 03
Error register
All '0'
0 x 01 0 x 02 0 x 03
0 x 00
LED2 : '1' , other : '0'
FAIL
(b) Enlarged chart (B)
Figure 42. LED Short Protection (Enlarged View A)
VSYNC
EXTCLK
PWM_OH[1]
High
LED2
VSHDET
LSPDET_ID[1]
High
r_lspdet[1]
High
mask
SSEND
err_mskcnt[7:0]
0 x 00
ERRMASK register
0 x 03
Error register
0 x 01 0 x 02 0 x 03
LED2 : '1' , other : '0'
0 x 00
All '0'
FAIL
Figure 43. LED Short Protection (Enlarged View B)
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3. ERROR Control – continued
(2)
LED Open Protection
It operates as following when it detects (The LED pin voltage is under 0.2 V) or released “LED open Error“.
(Example) Register setting: DLY02[7:0] = 0x00, ERRMASK[7:0] = 0x03, ERRLAT = 0
Enlarged view B
Enlarged view A
VSYNC
EXTCLK
PWM_OH[1]
LED2
VOPDET
VOPDET
LOPDET_ID[1]
r_lopdet[1]
SSEND
err_mskcnt[7:0]
0 x 00
ERRMASK register
0 x 03
Error register
All '0'
0 x 00
LED2 : 1 , other : 0
FAIL
Figure 44. LED Open Protection
(a) Detail of Enlarged chart (A)
VSYNC
EXTCLK
PWM_OH[1]
LED2
VOPDET
LOPDET_ID[1]
mask
2 clock delay
(synchronize)
r_lopdet[1]
SSEND
err_mskcnt[7:0]
0 x 00
ERRMASK register
0 x 03
Error register
All '0'
0 x 01 0 x 02 0 x 03
0 x 00
LED2 : '1' , other : '0'
FAIL
(b) Detail of Enlarged chart (B)
Figure 45. LED Open Protection (Enlarged View A)
VSYNC
EXTCLK
LED2
VOPDET
PWM_OH[1]
High
LOPDET_ID[1]
High
r_lopdet[1]
High
mask
SSEND
err_mskcnt[7:0]
0 x 00
ERRMASK register
0 x 03
Error register
0 x 01 0 x 02 0 x 03
LED2 : '1' , other : '0'
0 x 00
All '0'
FAIL
Figure 46. LED Open Protection (Enlarged View B)
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(2) LED Open Protection – continued
[Operation]
When PWM_OH[1] = ‘High’ and LOPDET_ID[1] = ‘Low’ with SSEND = ‘High’ (Soft Start end), ERRMASK starts counting
with EXTCLK (err_mskcnt_r) from the rise-edge of PWM_OH[1]. At the arriving to the set value (0x03), FAIL is set to
‘Low’, i.e. ERROR is started to be detected. When ERROR is detected and PWM_OH[1] = ‘High’ and LOPDET_ID[1] =
High, ERRMASK starts counting with EXTCLK (err_mskcnt_r) from the rise-edge of PWM_OH[1]. At the arriving to the
set value (0x03), FAIL is set to ‘High’, i.e. It released ERROR condition.
(Example) low width error case,
Register setting: DLY02[7:0] = 0x00, ERRMASK[7:0] = 0x03, ERRLAT = 0
Enlarged view B
Enlarged view A
VSYNC
EXTCLK
r_vsync
PWM_OH[1]
LED2
VOPDET
VOPDET
LOPDET_ID[1]
r_lopdet[1]
SSEND
err_mskcnt[7:0]
0 x 00
0 x 00
ERRMASK register
0 x 03
Error register
FAIL
Figure 47. LED Open Protection Mask Function
(a) Enlarged chart (A)
VSYNC
1st
2nd
3rd
EXTCLK
r_vsync
PWM_OH[1]
LED2
VOPDET
LOPDET_ID[1]
2clock delay
(synchronize)
mask(3 to 4 clock)
r_lopdet[1]
SSEND
err_mskcnt[7:0]
0 x 00
ERRMASK register
0 x 03
Error register
All '0'
FAIL
(b) Enlarged chart (B)
0 x 01 0 x 02 0 x 03
0 x 00
high
Figure 48. LED Open Protection Masked (Enlarged View A)
VSYNC
1st
2nd
3rd
4th
1st
2nd
3rd
4th
EXTCLK
r_vsync
PWM_OH[1]
LED2
VOPDET
LOPDET_ID[1]
High
r_lopdet[1]
High
SSEND
mask
High
err_mskcnt[7:0]
0 x 00
ERRMASK register
0 x 03
Error register
All '0'
0 x 01 0 x 02 0 x 03 0 x 00 0 x 01 0 x 02 0 x 03
LED2 : '1' , other : '0'
0 x 00
All '0'
FAIL
Figure 49. “LED Open Protection” (Enlarged View B)
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3. ERROR Control – continued
(3) TSD Warning
If It heats over 135 deg, it detects “TSD warning” (WARTSD_ID[1] = Low).
It update error register (WARTSD[1] = 1) and FAIL = Low after detection.
If it releases error condition, it updates error register (WARTSD[1] = 0) and FAIL = High.
This function has enabled (TSDWEN). If TSDWEN = 0, it doesn’t detect “TSD warning protection”
PWM_OH[n-1] signal don’t effect “TSD warning protection”.
Enlarged view A
Enlarged view B
VSYNC
EXTCLK
PWM_OH[1]
Temp.
tMON
tMON - tMONHYS
WARTSD_ID[1]
r_wartsd[1]
WARTSD[1] register
FAIL
Figure 50. “TSD Warning”
(a) Enlarged chart (A)
VSYNC
High
EXTCLK
PWM_OH[1]
High
Temp.
tMON
WARTSD_ID[1]
2 clock delay
(synchronize)
r_wartsd[1]
WARTSD[1] register
FAIL
Figure 51. “TSD Warning” Detected (Enlarged View A)
(b) Enlarged chart (B)
VSYNC
Low
EXTCLK
PWM_OH[1]
Low
Temp.
WARTSD_ID[1]
tMON - tMONHYS
2 clock delay
(synchronize)
r_wartsd[1]
WARTSD[1] register
FAIL
Figure 52. “TSD Warning” Released (Enlarged View B)
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3. ERROR Control – continued
(4) ISET Short Warning
If It set ISET resistor under 2.5 kΩ, it detect “ISET short warning” (WARISET_IL = Low).
It update error register (WARISET = 1) and FAIL = Low after detection.
If it release error condition, it update error register (WARISET = 0) and FAIL = High.
ERRMASK doesn’t effect this protection.
Enlarged view A
Enlarged view B
VSYNC
EXTCLK
PWM_OH[1]
RSETSCP
ISET resistor value
WARISET_IL
r_wariset
WARISET[0] register
FAIL
Figure 53. “ISET Short Warning”
(a) Enlarged chart (A)
VSYNC
High
EXTCLK
PWM_OH[1]
High
RSETSCP
ISET resistor value
WARISET_IL
2 clock delay
(synchronize)
r_wariset
WARISET[0] register
FAIL
Figure 54. “ISET Short Warning” Detected (Enlarged View A)
(b) Enlarged chart (B)
VSYNC
Low
EXTCLK
PWM_OH[1]
Low
RSETSCP
ISET resistor value
WARISET_IL
2 clock delay
(synchronize)
r_wariset
WARISET[0] register
FAIL
Figure 55. “ISET Short Warning” Released (Enlarged View B)
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3. ERROR Control – continued
(5) TSD
If It heat over 175 deg, it detect “TSD” (TSD_IL = Low).
It update FAIL = Low and initialized all circuit after detection.
It update FAIL = High after released.
ERRMASK and SSMASK don’t effect this protection.
Enlarged view (A)
Enlarged view (B)
VSYNC
EXTCLK
TSD_IL
PWM_OH[1]
SSEND
FAIL
Figure 56. TSD
(a) Enlarged chart (A)
VSYNC
High
EXTCLK
TSD_IL
High
asynchronous reset
PWM_OH[1]
SSEND
FAIL
Figure 57. “TSD” Detected (Enlarged View A)
(b) Enlarged chart (B)
VSYNC
Low
EXTCLK
TSD_IL
PWM_OH[1]
Low
SSEND
Low
reset released
FAIL
Figure 58. “TSD” Released (Enlarged View B)
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3. ERROR Control – continued
(6) Soft-Start Masking Function
The time of mask of ERROR detection at starting of IC is set by counting the number of VSYNC.
Time of mask = set value x VSYNC
(Example) Address = 0x03(SSMASK), DATA = 0x3C:
internal reset
VSYNC
EXTCLK
PWM
LOPDET_ID[0]
SSMASK[7:0]
0x3C
r_sscnt[7:0]
0x00 0x01 0x02 0x03 0x04 0x05 0x06
0x3A 0x3B 0x3C
0xFF
0x00
released "soft start mask"
SSEND
FAIL
mask
Figure 59. Setting for Soft Start Mask
(7)
LED SCP
LED SCP is operated after detecting “LED open error” and writing DTYENn = 0.
MASK time can be controlled by SCPTIME register.
FAIL outputs VSYNC pulse after the MASK time.
SPI
VSYNC
EXTCLK
LED1
LOPDET_ID[0]
DTYEN01 register
ledscp_det (internal signal)
SCPTIME register
'1'
PWM
MASK time
2VSYNC cycle
FAIL
Figure 60. SCP Function
(Note) It can’t detect “SCP error” if LEDn (n = 1 to 16) pin shorts GND before setting DTYEN = 1 and detecting LED open error”. This function is available
after detecting “LED open error”.
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Timing Chart - continued
4. Boot Sequence
(1) Normal Boot
(1)
VCC
(2)
EN
VREG33
UVLO
VSYNC
(3)
(4)
EXTCLK
SPI
PWM
IC condition
standby
OFF
dimming
OFF
Enlarged view
#all device
address
#device 1
address
#device N
address
SPI
Register
Enlarged view
#device1
address
#device N
address
SPI
PWMFREQ
ERRSET1
SSMASK
ERRMASK
ERREN
ERRSET2
DLYCNTn
PWMPLS
DTYCNTn
LCDACn
(n = 1 to16)
DLYCNTn
PWMPLS
DTYCNTn
LCDACn
(n = 1 to 16)
Register
DTYCTn
LCDACn
(n = 1 to 16)
DTYCTn
LCDACn
(n = 1 to 16)
Figure 61. Starting Sequence for Normal Operation
When you light the LED by general SPI control, follow the sequence below.
(1) Input the power supply of VCC.
(2) Launch the EN from ‘Low’ to ‘High’.
(3) Write the data to the register by SPI control, then set the LED driver.
(4) Input the VSYNC, EXTCLK signal and set register for PWM dimming.
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Timing Chart - continued
5. PWM Dimming Sequence
It has “register”, “buffer” and “control data” for DTYCNTn and LCDACn. 1st “register” are updated by SPI. 2nd “buffer” are
updated at VSYNC pulse, 3rd “control data” are updated at PWM timing as following for keeping data until finishing output.
(1)
PWM Duty (DTYCNTn)/Local DAC (LCDACn) Control
VCC
EN
VREG33
Current VSYNC
cycle
VSYNC
Next VSYNC cycle
EXTCLK
(1)
SCSB
SPI
dimming
(2)
register
Update data at VSYNC
buffer
(3)
Update data at PWM timing
control data
output
PWM
Enlarged view
#device 1
address
……
SPI
Register
#device N
address
DTYCNTn
LCDACn
(n = 1 to 16)
DTYCNTn
LCDACn
(n = 1 to 16)
Figure 62. Dimming Sequence for Normal Operation
When the LEDs are controlled by general SPI control, the sequence is the following.
(1) “SPI write sequence” should be finished in “current VSYNC cycle” until next VSYNC pulse.
(2) The buffer value is updated at VSYNC timing.
(3) The control data (DTYCNTn, LCDACn) are updated and PWM is updated at the same time.
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5. PWM Dimming Sequence – continued
(2) PWM Duty (DTYCNTn)/Local DAC (LCDACn) Control (Wrong SPI Access)
If MCU access at VSYNC pulse, it don’t update buffer data for any register (update timing VSYNC, PWM)
VCC
EN
VREG33
Current VSYNC
cycle
VSYNC
Next VSYNC cycle
EXTCLK
(1)
SCSB
SPI
dimming
(2)
register
not update data at VSYNC
Update data at VSYNC
(3)
buffer
update data at PWM timing
(same data)
Update data at PWM timing
control data
output
PWM
Enlarged view
#device 1
address
#device N
address
……
SPI
Register
DTYCNTn
LCDACn
( n =1 to 16)
DTYCNTn
LCDACn
(n = 1 to 16)
Figure 63. Dimming Sequence for Normal Operation (Wrong SPI Access)
When the LEDs are controlled by general SPI control, the sequence is the following.
(1) “SPI write sequence” is not finished in “current VSYNC cycle” until next VSYNC pulse.
(2) The buffer value is not updated at VSYNC timing. (because it occurred SCSB = Low and VSYNC pulse condition)
(3) The control data (DTYCNTn, LCDACn) are not updated, because buffer value is not updated.
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Timing Chart - continued
6. Error Sequence
(1) Error Sequence for “LED Open Protection” without ERRLAT
Example) It detects “LED open error” in LED1
VSYNC
(5)
LED1
Error
condition
nomal
LED1;LED open
(4)
(3)
SPI
ERRLAT(register)
Low
ERRCLR(register)
Low
LEDOPEN(register)
High
0
SCPTIME(register)
ERRLEDOPA(register)
0×00
ERRLEDOPB(register)
0×00
ERRLEDSHA(register)
0×00
ERRLEDSHB(register)
0×00
0×00
0×01
WARSCP(register)
DTYEN01(register)
DTYENn(other)
High
leden[0](LED1)
(internal signal)
(6)
PWM OFF
PWMn
(1)
(2)
(7)
FAIL
Enlarged view
SPI
SPI
Register
Enlarged view
Read:
ERRLEDOPA,B
ERRLEDSHA,B
ERRISETSCP
ERRTSD
Register
Write:
DTYEN01
Figure 64. Error Sequence for “LED OPEN Error” without ERRLAT
(1)
(2)
(3)
(4)
(5)
(6)
(7)
If it detects “LED OPEN error”, it outputs Low from FAIL after ERRMASK time.
If Error condition is released in this timing, it outputs high from FAIL after ERRMASK.
MCU read “Error register” after MCU receiving FAIL = Low condition.
MCU write “DTYEN01 = 0” of “Error Channel” for protection.
It pulls up the LED1 pin after DTYEN01 = 0. So LED1 voltage is over 0.2 V for LED1 open.
PWM output is OFF after next VSYNC and PWM timing.
“Error register” and FAIL return normal condition after next VSYNC and PWM timing.
MCU can’t detect Error condition if “error condition” is cleared before reading “error register”.
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6. Error Sequence – continued
(2) Error Sequence for SCP without ERRLAT
Example) It detects “SCP Error” in LED1.
VSYNC
(5)
LED1
Error
condition
(2)
nomal
LED1;LED pin GND short
(3)
SPI
ERRLAT(register)
Low
ERRCLR(register)
Low
LEDOPEN(register)
High
SCPTIME(register)
(4)
0
ERRLEDOPA(register)
0×00
ERRLEDOPB(register)
0×00
ERRLEDSHA(register)
0×00
ERRLEDSHB(register)
0×00
0×01
0×00
WARSCP(register)
DTYEN01(register)
DTYENn(other)
High
leden[0](LED1)
(internal signal)
(6)
PWM OFF
(7)
(8)
PWMn
(1)
FAIL
Enlarged view
SPI
Register
Enlarged view
SPI
Read:
ERRLEDOPA,B
ERRLEDSHA,B
ERRISETSCP
ERRTSD
Register
Write:
DTYEN01
Figure 65. Error Sequence for SCP without ERRLAT
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
If it detecs “LED OPEN error” after ERRMASK time, it outputs Low from FAIL.
If Error condition is released in this timing, it outputs high from FAIL after ERRMASK.
MCU read “Error register” after MCU receiving FAIL = Low condition.
MCU write “DTYEN01 = 0” of “Error Channel” for protection.
It pulls up the LED1 pin after DTYEN01 = 0. But it can’t be over 0.3 V because LED1 shorts to GND.
It doesn’t outputs PWM after next VSYNC and PWM timing.
It releases “Error register” and FAIL after next VSYNC and PWM timing.
It outputs VSYNC pulse from the FAIL pin after detecting SCP.
MCU can’t detect Error condition if “error condition” is cleared before reading “error register”.
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6. Error Sequence – continued
(3) Error Sequence for “LED Open Protection” with ERRLAT
Example) It detects “LED open error” in LED1
VSYNC
(2)
LED1
Error
Error
condition
nomal
nomal
(3)
SPI
ERRLAT(register)
Low
ERRCLR(register)
Low
LEDOPEN(register)
High
SCPTIME(register)
0
ERRLEDOPA(register)
0×00
ERRLEDOPB(register)
0×00
ERRLEDSHA(register)
0×00
ERRLEDSHB(register)
0×00
WARSCP(register)
(5)
(4)
0×00
0×01
Low
DTYEN01(register)
DTYENn(other)
High
leden[0](LED1)
(internal signal)
(7)
PWMn
(1)
(6)
FAIL
Enlarged view
SPI
SPI
Register
Enlarged view
Read:
ERRLEDOPA,B
ERRLEDSHA,B
ERRISETSCP
ERRTSD
Register
Write:
DTYEN01
Write:
ERRCLR
Figure 66. Error Sequence for “LED Open Protection” with ERRLAT
(1)
(2)
(3)
(4)
(5)
(6)
(7)
If it detects “LED open error”, it outputs Low from FAIL after ERRMASK time.
If Error condition is released in this timing, it keeps Low in FAIL and “Error register”.
MCU read “Error register” after MCU receiving FAIL = Low condition.
MCU write “DTYEN01 = 0” of “Error Channel” for protection condition released.
MCU write “ERRCLR = 1” for releasing “Latch condition”.
“Error register” and FAIL return normal condition after ERRCLR = 1.
PWM is OFF after next VSYNC and PWM timing.
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6. Error Sequence – continued
(4) Error Sequence SCP with ERRLAT
Example) It detects “SCP Error” in LED1.
VSYNC
(7)
LED1
Error
condition
nomal
LED1:LED pin GND short
(2)
SPI
ERRLAT(register)
High
ERRCLR(register)
Low
LEDOPEN(register)
High
SCPTIME(register)
0
ERRLEDOPA(register)
0×00
ERRLEDOPB(register)
0×00
ERRLEDSHA(register)
0×00
ERRLEDSHB(register)
0×00
WARSCP(register)
(3)
(4)
0×01
0×00
Low
DTYEN01(register)
DTYENn(other)
High
leden[0](LED1)
(internal signal)
(6)
PWMn
(5)
(1)
(8)
FAIL
Enlarged view
SPI
Register
Enlarged view
SPI
Read:
ERRLEDOPA,B
ERRLEDSHA,B
ERRISETSCP
ERRTSD
Register
Write:
DTYEN01
Write:
ERRCLR
Figure 67. Error Sequence for SCP with ERRLAT
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
If it detects “LED open error”, it outputs Low from FAIL after ERRMASK time.
MCU read “Error register” after MCU receiving FAIL = Low condition.
MCU write “DTYEN01 = 0” of “Error Channel” for protection condition released.
MCU write “ERRCLR = 1” for releasing “Latch condition”.
“Error register” and FAIL return normal condition after ERRCLR = 1
PWM is OFF after next VSYNC and PWM timing.
It pulls up LED1 pin. But it can’t be over 0.3 V because LED1 shorts to GND.
It detects SCP. So output VSYNC input from the FAIL pin.
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Timing Chart - continued
7. FAIL Control Sequence
FAIL output can be controlled by register setting.
(1)
(2)
(3)
SPI
FAILTEST(register)
High
FAILCNT(register)
Low
FAIL
Enlarged view
SPI
Enlarged view
SPI
Register
Write
FAILTEST
Enlarged view
SPI
Register
Write
FAILCNT
Register
Write
FAILCNT
Figure 68. FAIL Control Sequence
(1)
(2)
(3)
(1)
It is available to control FAIL output by FAILTEST = 1
FAILCNT = High, so it outputs High from the FAIL pin.
FAILCNT = Low, so it outputs Low from the FAIL pin.
LED Open Protection
When PWMn = high, If the LEDn pin becomes 0.1 V (Typ) or lower, FAIL = ‘Low’ is outputted and “LED open error” will
be detected. (n = 1 to 16)
VSYNC
EXTCLK
PWMn
(internal)
LEDn
0.2 V
(1)
(2)
(3)
(4)
(5)
(6)
FAIL
ERRMASK time
Figure 69. LED Open Protection
(1)
(2)
(3)
(4)
(5)
(6)
When PWMn = ‘High’, “LED open error” is detected. FAIL outputs ‘Low’ after ERRMASK time.
If LEDn pin voltage is release condition, FAIL outputs ‘High’ after ERRMASK.
If LEDn pin voltage is release condition when PWMn = ‘Low’, it keeps FAIL condition (High).
When PWMn = ‘High’, “LED open error” is detected. FAIL outputs ‘Low’ after ERRMASK time.
If LEDn pin voltage is release condition when PWMn = ‘Low’, it keeps FAIL condition (Low).
If LEDn pin voltage is release condition, FAIL outputs ‘High’ after ERRMASK.
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7. FAIL Control Sequence – continued
(2) LED Short Protection
If LEDn pin becomes LEDSH[3:0](Address 0x02) when PWMn = high, FAIL = ‘Low’ is outputted and “LED short error”
will be detected. (n = 1 to 16)
VSYNC
EXTCLK
PWMn
(internal)
4.8 V (default)
LEDn
(1)
(2)
(3)
(4)
(5)
(6)
FAIL
ERRMASK time
Figure 70. LED Short Protection
(1)
(2)
(3)
(4)
(5)
(6)
When PWMn = ‘High’, “LED short error” is detected. FAIL outputs ‘Low’ after ERRMASK time.
If LEDn pin voltage is release condition, FAIL outputs ‘High’ after ERRMASK.
If LEDn pin voltage is release condition when PWMn = ‘Low’, it keeps FAIL condition (High).
When PWMn = ‘High’, “LED short error” is detected. FAIL outputs ‘Low’ after ERRMASK time.
If LEDn pin voltage is release condition when PWMn = ‘Low’, it keeps FAIL condition (Low).
If LEDn pin voltage is release condition, FAIL outputs ‘High’ after ERRMASK.
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Application Examples
1. External Component Setting Example
CVOUT
DC/DC
10 μF
CVCC
VCC
5V
2.2 μF
VCC
LED1
VREG33
LED2
CVREG33
2.2 μF
LED3
LED4
LED5
RFAIL
100 kΩ
LED6
FAIL
LED7
SCSB
BD12801MUF- M
SDI
LED9
LED10
SCLK
MCU
LED8
LED11
SDO
LED12
VSYNC
LED13
EXTCLK
LED14
EN
LED15
LED16
TEST1
TEST2
GND ISET
LGND
RISET
7.5 kΩ
Figure 71. External Component Setting Example
2. Cascade Connection Application
DC/DC
Backlight
LED101
LED102
LED103
LED115
LED116
LED201
LED202
LED203
LED1 to LED24
LED215
LED216
LED1 to LED24
VCC
EN
VSYNC
EXTCLK
SCS B
SCLK
MOSI
VCC
EN
VSYNC
MCU
EXTCLK
VSYNC
VREG33
EXTCLK
(#1)
SCSB
SCLK
SDI
VREG3 3
BD12801MUF-M
BD12801MUF-M
SCSB
VCC
EN
(#2)
SCLK
SDO
SDI
FAIL
SDO
FAIL
FAIL
MISO
Figure 72. Cascade Connection Application
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I/O Equivalence Circuit
VCC
EXTCLK, VSYNC, SCLK, SDI, SCSB
FAIL
VREG33
EXTCLK
VSYNC
SCLK
SDI
SCSB
VCC
FAIL
GND
GND
GND
LED1 to LED16
GND
TEST1
SDO
VCC
LED1
to LED16
VREG33
TEST1
＋
GND
GND
SDO
－
LGND
GND
LGND
LGND
EN
GND
GND
TEST2
GND,LGND
VCC
VCC
EN
TEST2
30 kΩ
100 kΩ
70 kΩ
100 kΩ
GND
GND
GND
ISET
GND
200 kΩ
100 kΩ
GND
GND
LGND
GND
GND
VREG33
VCC
＋
＋
－
－
GND
VREG33
GND
GND
ISET
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Operational Notes
1.
Reverse Connection of Power Supply
Connecting the power supply in reverse polarity can damage the IC. Take precautions against reverse polarity when
connecting the power supply, such as mounting an external diode between the power supply and the IC’s power
supply pins.
2.
Power Supply Lines
Design the PCB layout pattern to provide low impedance supply lines. Furthermore, connect a capacitor to ground at
all power supply pins. Consider the effect of temperature and aging on the capacitance value when using electrolytic
capacitors.
3.
Ground Voltage
Ensure that no pins are at a voltage below that of the ground pin at any time, even during transient condition.
4.
Ground Wiring Pattern
When using both small-signal and large-current ground traces, the two ground traces should be routed separately but
connected to a single ground at the reference point of the application board to avoid fluctuations in the small-signal
ground caused by large currents. Also ensure that the ground traces of external components do not cause variations
on the ground voltage. The ground lines must be as short and thick as possible to reduce line impedance.
5.
Recommended Operating Conditions
The function and operation of the IC are guaranteed within the range specified by the recommended operating
conditions. The characteristic values are guaranteed only under the conditions of each item specified by the electrical
characteristics.
6.
Inrush Current
When power is first supplied to the IC, it is possible that the internal logic may be unstable and inrush current may flow
instantaneously due to the internal powering sequence and delays, especially if the IC has more than one power
supply. Therefore, give special consideration to power coupling capacitance, power wiring, width of ground wiring, and
routing of connections.
7.
Testing on Application Boards
When testing the IC on an application board, connecting a capacitor directly to a low-impedance output pin may
subject the IC to stress. Always discharge capacitors completely after each process or step. The IC’s power supply
should always be turned off completely before connecting or removing it from the test setup during the inspection
process. To prevent damage from static discharge, ground the IC during assembly and use similar precautions during
transport and storage.
8.
Inter-pin Short and Mounting Errors
Ensure that the direction and position are correct when mounting the IC on the PCB. Incorrect mounting may result in
damaging the IC. Avoid nearby pins being shorted to each other especially to ground, power supply and output pin.
Inter-pin shorts could be due to many reasons such as metal particles, water droplets (in very humid environment) and
unintentional solder bridge deposited in between pins during assembly to name a few.
9.
Unused Input Pins
Input pins of an IC are often connected to the gate of a MOS transistor. The gate has extremely high impedance and
extremely low capacitance. If left unconnected, the electric field from the outside can easily charge it. The small
charge acquired in this way is enough to produce a significant effect on the conduction through the transistor and
cause unexpected operation of the IC. So unless otherwise specified, unused input pins should be connected to the
power supply or ground line.
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Operational Notes – continued
10.
Regarding the Input Pin of the IC
This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them
isolated. P-N junctions are formed at the intersection of the P layers with the N layers of other elements, creating a
parasitic diode or transistor. For example (refer to figure below):
When GND > Pin A and GND > Pin B, the P-N junction operates as a parasitic diode.
When GND > Pin B, the P-N junction operates as a parasitic transistor.
Parasitic diodes inevitably occur in the structure of the IC. The operation of parasitic diodes can result in mutual
interference among circuits, operational faults, or physical damage. Therefore, conditions that cause these diodes to
operate, such as applying a voltage lower than the GND voltage to an input pin (and thus to the P substrate) should be
avoided.
Resistor
Transistor (NPN)
Pin A
Pin B
C
Pin A
N
P+
N
P
N
P+
N
Parasitic
Elements
N
P+
GND
E
N P
N
P+
B
N
C
E
Parasitic
Elements
P Substrate
P Substrate
Parasitic
Elements
Pin B
B
Parasitic
Elements
GND
Figure 73. Example of Monolithic IC Structure
GND
N Region
close-by
GND
11.
Ceramic Capacitor
When using a ceramic capacitor, determine a capacitance value considering the change of capacitance with
temperature and the decrease in nominal capacitance due to DC bias and others.
12.
Thermal Shutdown Circuit(TSD)
This IC has a built-in thermal shutdown circuit that prevents heat damage to the IC. Normal operation should always
be within the IC’s maximum junction temperature rating. If however the rating is exceeded for a continued period, the
junction temperature (Tj) will rise which will activate the TSD circuit that will turn OFF all output pins. When the Tj falls
below the TSD threshold, the circuits are automatically restored to normal operation.
Note that the TSD circuit operates in a situation that exceeds the absolute maximum ratings and therefore, under no
circumstances, should the TSD circuit be used in a set design or for any purpose other than protecting the IC from
heat damage.
13.
Over Current Protection Circuit (OCP)
This IC incorporates an integrated overcurrent protection circuit that is activated when the load is shorted. This
protection circuit is effective in preventing damage due to sudden and unexpected incidents. However, the IC should
not be used in applications characterized by continuous operation or transitioning of the protection circuit.
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BD12801MUF-M
Ordering Information
B
D
1
2
8
0
1
M
U
F
-
Package
MUF: VQFN48FAV070
ME2
Product Rank
M: for Automotive
Packaging and forming specification
E2: Embossed tape and reel
Marking Diagram
VQFN48FAV070 (TOP VIEW)
Part Number Marking
D12801
LOT Number
Pin 1 Mark
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©2017 ROHM Co., Ltd. All rights reserved.
TSZ22111 • 15 • 001
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Datasheet
BD12801MUF-M
Physical Dimension and Packing Information
Package Name
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©2017 ROHM Co., Ltd. All rights reserved.
TSZ22111 • 15 • 001
VQFN48FAV070
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TSZ02201-0V1V0B200010-1-2
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10.May.2021 Rev.001
BD12801MUF-M
Revision History
Date
Revision
10.May.2021
001
Changes
New Release
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©2017 ROHM Co., Ltd. All rights reserved.
TSZ22111 • 15 • 001
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Notice
Precaution on using ROHM Products
1.
If you intend to use our Products in devices requiring extremely high reliability (such as medical equipment (Note 1),
aircraft/spacecraft, nuclear power controllers, etc.) and whose malfunction or failure may cause loss of human life,
bodily injury or serious damage to property (“Specific Applications”), please consult with the ROHM sales
representative in advance. Unless otherwise agreed in writing by ROHM in advance, ROHM shall not be in any way
responsible or liable for any damages, expenses or losses incurred by you or third parties arising from the use of any
ROHM’s Products for Specific Applications.
(Note1) Medical Equipment Classification of the Specific Applications
JAPAN
USA
EU
CHINA
CLASSⅢ
CLASSⅡb
CLASSⅢ
CLASSⅢ
CLASSⅣ
CLASSⅢ
2.
ROHM designs and manufactures its Products subject to strict quality control system. However, semiconductor
products can fail or malfunction at a certain rate. Please be sure to implement, at your own responsibilities, adequate
safety measures including but not limited to fail-safe design against the physical injury, damage to any property, which
a failure or malfunction of our Products may cause. The following are examples of safety measures:
[a] Installation of protection circuits or other protective devices to improve system safety
[b] Installation of redundant circuits to reduce the impact of single or multiple circuit failure
3.
Our Products are not designed under any special or extraordinary environments or conditions, as exemplified below.
Accordingly, ROHM shall not be in any way responsible or liable for any damages, expenses or losses arising from the
use of any ROHM’s Products under any special or extraordinary environments or conditions. If you intend to use our
Products under any special or extraordinary environments or conditions (as exemplified below), your independent
verification and confirmation of product performance, reliability, etc, prior to use, must be necessary:
[a] Use of our Products in any types of liquid, including water, oils, chemicals, and organic solvents
[b] Use of our Products outdoors or in places where the Products are exposed to direct sunlight or dust
[c] Use of our Products in places where the Products are exposed to sea wind or corrosive gases, including Cl2,
H2S, NH3, SO2, and NO2
[d] Use of our Products in places where the Products are exposed to static electricity or electromagnetic waves
[e] Use of our Products in proximity to heat-producing components, plastic cords, or other flammable items
[f] Sealing or coating our Products with resin or other coating materials
[g] Use of our Products without cleaning residue of flux (Exclude cases where no-clean type fluxes is used.
However, recommend sufficiently about the residue.); or Washing our Products by using water or water-soluble
cleaning agents for cleaning residue after soldering
[h] Use of the Products in places subject to dew condensation
4.
The Products are not subject to radiation-proof design.
5.
Please verify and confirm characteristics of the final or mounted products in using the Products.
6.
In particular, if a transient load (a large amount of load applied in a short period of time, such as pulse, is applied,
confirmation of performance characteristics after on-board mounting is strongly recommended. Avoid applying power
exceeding normal rated power; exceeding the power rating under steady-state loading condition may negatively affect
product performance and reliability.
7.
De-rate Power Dissipation depending on ambient temperature. When used in sealed area, confirm that it is the use in
the range that does not exceed the maximum junction temperature.
8.
Confirm that operation temperature is within the specified range described in the product specification.
9.
ROHM shall not be in any way responsible or liable for failure induced under deviant condition from what is defined in
this document.
Precaution for Mounting / Circuit board design
1.
When a highly active halogenous (chlorine, bromine, etc.) flux is used, the residue of flux may negatively affect product
performance and reliability.
2.
In principle, the reflow soldering method must be used on a surface-mount products, the flow soldering method must
be used on a through hole mount products. If the flow soldering method is preferred on a surface-mount products,
please consult with the ROHM representative in advance.
For details, please refer to ROHM Mounting specification
Notice-PAA-E
© 2015 ROHM Co., Ltd. All rights reserved.
Rev.004
Precautions Regarding Application Examples and External Circuits
1.
If change is made to the constant of an external circuit, please allow a sufficient margin considering variations of the
characteristics of the Products and external components, including transient characteristics, as well as static
characteristics.
2.
You agree that application notes, reference designs, and associated data and information contained in this document
are presented only as guidance for Products use. Therefore, in case you use such information, you are solely
responsible for it and you must exercise your own independent verification and judgment in the use of such information
contained in this document. ROHM shall not be in any way responsible or liable for any damages, expenses or losses
incurred by you or third parties arising from the use of such information.
Precaution for Electrostatic
This Product is electrostatic sensitive product, which may be damaged due to electrostatic discharge. Please take proper
caution in your manufacturing process and storage so that voltage exceeding the Products maximum rating will not be
applied to Products. Please take special care under dry condition (e.g. Grounding of human body / equipment / solder iron,
isolation from charged objects, setting of Ionizer, friction prevention and temperature / humidity control).
Precaution for Storage / Transportation
1.
Product performance and soldered connections may deteriorate if the Products are stored in the places where:
[a] the Products are exposed to sea winds or corrosive gases, including Cl 2, H2S, NH3, SO2, and NO2
[b] the temperature or humidity exceeds those recommended by ROHM
[c] the Products are exposed to direct sunshine or condensation
[d] the Products are exposed to high Electrostatic
2.
Even under ROHM recommended storage condition, solderability of products out of recommended storage time period
may be degraded. It is strongly recommended to confirm solderability before using Products of which storage time is
exceeding the recommended storage time period.
3.
Store / transport cartons in the correct direction, which is indicated on a carton with a symbol. Otherwise bent leads
may occur due to excessive stress applied when dropping of a carton.
4.
Use Products within the specified time after opening a humidity barrier bag. Baking is required before using Products of
which storage time is exceeding the recommended storage time period.
Precaution for Product Label
A two-dimensional barcode printed on ROHM Products label is for ROHM’s internal use only.
Precaution for Disposition
When disposing Products please dispose them properly using an authorized industry waste company.
Precaution for Foreign Exchange and Foreign Trade act
Since concerned goods might be fallen under listed items of export control prescribed by Foreign exchange and Foreign
trade act, please consult with ROHM in case of export.
Precaution Regarding Intellectual Property Rights
1.
All information and data including but not limited to application example contained in this document is for reference
only. ROHM does not warrant that foregoing information or data will not infringe any intellectual property rights or any
other rights of any third party regarding such information or data.
2.
ROHM shall not have any obligations where the claims, actions or demands arising from the combination of the
Products with other articles such as components, circuits, systems or external equipment (including software).
3.
No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of ROHM or any
third parties with respect to the Products or the information contained in this document. Provided, however, that ROHM
will not assert its intellectual property rights or other rights against you or your customers to the extent necessary to
manufacture or sell products containing the Products, subject to the terms and conditions herein.
Other Precaution
1.
This document may not be reprinted or reproduced, in whole or in part, without prior written consent of ROHM.
2.
The Products may not be disassembled, converted, modified, reproduced or otherwise changed without prior written
consent of ROHM.
3.
In no event shall you use in any way whatsoever the Products and the related technical information contained in the
Products or this document for any military purposes, including but not limited to, the development of mass-destruction
weapons.
4.
The proper names of companies or products described in this document are trademarks or registered trademarks of
ROHM, its affiliated companies or third parties.
Notice-PAA-E
© 2015 ROHM Co., Ltd. All rights reserved.
Rev.004
Datasheet
General Precaution
1. Before you use our Products, you are requested to carefully read this document and fully understand its contents.
ROHM shall not be in any way responsible or liable for failure, malfunction or accident arising from the use of any
ROHM’s Products against warning, caution or note contained in this document.
2. All information contained in this document is current as of the issuing date and subject to change without any prior
notice. Before purchasing or using ROHM’s Products, please confirm the latest information with a ROHM sales
representative.
3.
The information contained in this document is provided on an “as is” basis and ROHM does not warrant that all
information contained in this document is accurate and/or error-free. ROHM shall not be in any way responsible or
liable for an y damages, expenses or losses incurred b y you or third parties resulting from inaccuracy or errors of or
concerning such information.
Notice – WE
© 2015 ROHM Co., Ltd. All rights reserved.
Rev.001
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