Datasheet
Constant Current LED Drivers
Constant Current Controller
for Automotive LED Lamps
BD18342FV-M
Key Specifications
General Description
BD18342FV-M is 70V-withstanding constant current
controller for automotive LED lamps. It is able to drive at
maximum 10 rows of PNP transistors. It can also
contribute to reduction in the consumption power of the
set as it has the built-in standby function. The IC provides
high reliability because it has LED open detection, short
circuit protection, over voltage mute function and LED
failure input/output function.
Input Voltage Range:
FB Pin Voltage Accuracy:
4.5 V to 19 V
650 mV ±3 %
@Ta=25 °C to 125 °C
Stand-by Current:
0 µA (Typ)
Operating Temperature Range: -40 °C to +125 °C
Package
W (Typ) x D (Typ) x H (Max)
SSOP-B16
5.00 mm x 6.40 mm x 1.35 mm
Features
AEC-Q100 Qualified(Note 1)
PWM Dimming Function
LED Open Detection
Short Circuit Protection (SCP)
Over Voltage Mute Function (OVM)
Disable LED Open Detection Function
at Reduced-Voltage
LED Failure Input/Output Functions (PBUS)
(Note 1) Grade1
SSOP-B16
Applications
Automotive LED Exterior Lamp
(Rear Lamp, Turn Lamp, DRL/Position Lamp, Fog
Lamp etc.)
Automotive LED Interior Lamp
(Air Conditioner Lamp, Interior Lamp, Cluster Light
etc.)
Typical Application Circuit
RFB1
RFB2
PWM_in
VIN
FB
D1
ZD1
CVIN1
CVIN2
EN
RLIM
BASE
D2
CRT
DC_in
D3
CCRT
OP
RCRT
DISC
SCP
RDCIN
VREG
D
CVREG
CD
PBUS
OPM
ROPM
GND
〇Product structure : Silicon integrated circuit
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CLED
BD18342FV-M
〇This product has no designed protection against radioactive rays
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BD18342FV-M
Pin Configuration
(TOP VIEW)
FB
1
16
VIN
BASE
2
15
EN
N.C.
3
14
DISC
OP
4
13
CRT
SCP
5
12
D
GND
6
11
N.C.
PBUS
7
10
VREG
N.C.
8
9
OPM
Pin Description
Pin No.
Pin Name
Function
1
FB
2
BASE
Connecting PNP Tr. BASE
3
N.C.
No internal connection(Note 1)
4
OP
LED open detection input
5
SCP
Short circuit protection input
6
GND
GND
7
PBUS
Output for fault flag / Input to disable Output current
8
N.C.
No internal connection(Note 1)
9
OPM
Connecting resistor for disable LED open detection voltage setting at reduced voltage
10
VREG
Internal reference voltage output
11
N.C.
12
D
13
CRT
Connect capacitor and resistor to set output current ON Duty
14
DISC
Connecting resistor to set output current on time
15
EN
Enable input
16
VIN
Power supply input
Feedback voltage input
No internal connection(Note 1)
Connecting capacitor for disable LED open detection time setting
(Note 1) Leave this pin unconnected
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BD18342FV-M
Block Diagram
VREG
VIN
FB
EN
VREG
PBUS
BASE
Over
Voltage
Mute
VREF
PBUS
LED OPEN
V RE G
OP
VI N
V RE G
OPEN
MASK
Control
Logic
SCP
D
V IN
1.2 V
1 mA
OPM
SCP
20 µs
Filter
D COMP
1.20 V ⇔1.25 V
Rise 1 µs
Filter
1.0 V
V RE G
CRT
CR
TIMER
DISC
GND
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BD18342FV-M
Absolute Maximum Ratings (Ta=25°C)
Parameter
Symbol
Rating
Unit
Power Supply Voltage(VIN)
VIN
-0.3 to +70.0
V
EN, CRT, DISC Pin Voltage
VEN, VCRT, VDISC
-0.3 to +70.0
V
VFB, VBASE, VOP,VSCP
-0.3 to VIN+0.3
V
VIN_FB, VIN_BASE
-0.3 to +5.0
V
VPBUS, VREG
-0.3 to +7.0
V
VOPM, VD
-0.3 to VREG+0.3
V
Tstg
-55 to +150
°C
Tjmax
150
°C
FB, BASE, OP, SCP Pin Voltage
VIN-FB, VIN-BASE
Inter-Pin Voltage
PBUS, VREG Pin Voltage
OPM, D Pin Voltage
Storage Temperature Range
Maximum Junction Temperature
Caution 1: Operating the IC over the absolute maximum ratings may damage the IC. The damage can either be a short circuit between pins or an open circuit
between pins and the internal circuitry. Therefore, it is important to consider circuit protection measures, such as adding a fuse, in case the IC is
operated over the absolute maximum ratings.
Caution 2: Should by any chance the maximum junction temperature rating be exceeded the rise in temperature of the chip may result in deterioration of the
properties of the chip. In case of exceeding this absolute maximum rating, design a PCB with thermal resistance taken into consideration by
increasing board size and copper area so as not to exceed the maximum junction temperature rating.
Thermal Resistance(Note 1)
Parameter
Symbol
Thermal Resistance (Typ)
Unit
1s(Note 3)
2s2p(Note 4)
θJA
140.9
77.2
°C/W
ΨJT
6
5
°C/W
SSOP-B16
Junction to Ambient
Junction to Top Characterization Parameter
(Note 2)
(Note 1) Based on JESD51-2A(Still-Air).
(Note 2) The thermal characterization parameter to report the difference between junction temperature and the temperature at the top center of the outside
surface of the component package.
(Note 3) Using a PCB board based on JESD51-3.
(Note 4) Using a PCB board based on JESD51-7.
Layer Number of
Measurement Board
Single
Material
Board Size
FR-4
114.3 mm x 76.2 mm x 1.57 mmt
Top
Copper Pattern
Thickness
Footprints and Traces
70 μm
Layer Number of
Measurement Board
4 Layers
Material
Board Size
FR-4
114.3 mm x 76.2 mm x 1.6 mmt
Top
2 Internal Layers
Bottom
Copper Pattern
Thickness
Copper Pattern
Thickness
Copper Pattern
Thickness
Footprints and Traces
70 μm
74.2 mm x 74.2 mm
35 μm
74.2 mm x 74.2 mm
70 μm
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Recommended Operating Conditions
Parameter
Symbol
Min
Typ
Max
Unit
Supply Voltage(Note 1) (Note 2)
VIN
4.5
13.0
19.0
V
CR TIMER Frequency Range
fPWM
100
-
5000
Hz
PWM Minimum Pulse Width(Note 3)
tMIN
10
-
-
µs
Operating Temperature
Topr
-40
-
+125
°C
(Note 1) ASO should not be exceeded
(Note 2) At start-up time, please apply a voltage 5 V or more once. The value is the voltage range after the temporary rise to 5 V or more.
(Note 3) At connecting the external PNP Tr. (2SAR573DFHG (ROHM), 1 pcs). That is the same when the pulse input to the CRT pin.
Operating Conditions
Parameter
Capacitor
Connecting VIN Pin 1
Capacitor
Connecting VIN Pin 2
Capacitor
Connecting VREG Pin
Capacitor
Connecting LED Anode
Capacitor
for Setting CRT Timer
Resistor
for Setting CRT Timer
Resistor
for Setting LED Current
Resistor for Disable LED Open
Detection Voltage Setting
at Reduced Voltage
Resistor for DCIN Pull-down
Capacitor for Setting Disable LED
Open Detection Time
Resistor for Limiting
Base Pin Current
External PNP Transistor
Symbol
Min
Max
Unit
CVIN1
1.0
-
μF
CVIN2(Note 4)
0.047
-
μF
CVREG(Note 5)
1.0
4.7
μF
CLED
0.10
0.68
μF
CCRT
0.01
0.22
μF
RCRT
0.1
50.0
kΩ
RFB1, RFB2(Note 6)
0.8
6.5
Ω
ROPM
25
55
kΩ
RDCIN
-
10
kΩ
CD(Note 5)
0.001
0.100
μF
RLIM
See Features Description 5
Ω
Q1
(Note 7)
-
(Note 4) Recommended ceramic capacitor. ROHM Recommended Value (0.1 μF GCM155R71H104KE37 murata)
(Note 5) Recommended ceramic capacitor. Please setting the Disable LED Open Detection Time less than PWM minimum pulse width.
(Note 6) At connecting the external PNP Tr. 2SAR573DFHG (ROHM), 1 pcs.
(Note 7) For external PNP transistor, please use the recommended device 2SAR573DFHG for this IC.
While using non-recommended part device, validate the design on actual board.
Please check hfe of the part to design base current limit resistor. (See Features Description, section 5).
As for parasitic capacitance, please evaluate over shoot of ILED on actual board. (See Features Description, Section 8 -Evaluation example,
ILED pulse width at PWM Dimming operation).
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Electrical Characteristics
(Unless otherwise specified Ta=-40 °C to +125 °C, VIN=13 V, CVREG=1.0 µF, Transistor PNP=2SAR573DFHG)
Limit
Parameter
Symbol
Unit
Conditions
Min
Typ
Max
[Circuit Current IVIN]
Circuit Current at Stand-by Mode
IVIN1
-
0
10
μA
VEN=0 V
VFB=VIN
Circuit Current at Normal Mode
IVIN2
-
2.0
5.0
mA
VEN=VIN, VFB=VIN-1.0 V
Base Current Subtracted
Circuit Current
at LED Open Detection
IVIN3
-
2.0
5.0
mA
VEN=VIN, VFB=VIN-1.0 V
Circuit Current at PBUS=Low
IVIN4
-
2.0
5.0
mA
VEN=VIN, VFB=VIN-1.0 V
VPBUS=0 V
4.85
5.00
5.15
V
4.75
5.00
5.25
V
-1.0
-
-
mA
630
650
670
mV
617
650
683
mV
IFB
7.5
15
30
μA
VFB=VIN
BASE Pin Sink
Current Capability
IBASE
10
-
-
mA
VFB=VIN, VBASE=VIN-1.5 V
Ta=25 °C
BASE Pin Pull-up Resistor
RBASE
0.5
1.0
1.5
kΩ
VCRT=0 V
VFB=VIN, VBASE=VIN-1.0 V
ΔVFB=10.0 mV
ΔVFB=VFB(@VIN=13 V)VFB(@VIN=VOVMS)
[VREG Voltage]
VREG Pin Voltage
VREG Pin Current Capability
VREG
IVREG
IVREG=-100 μA
Ta=25 °C to 125 °C
IVREG=-100μA
Ta=-40 °C to +125 °C
[DRV]
FB Pin Voltage
VFBREG
FB Pin Input Current
VFBREG=VIN-VFB
RFB1=RFB2=1.8 Ω,
Ta=25 °C to 125 °C
VFBREG=VIN-VFB
RFB1=RFB2=1.8 Ω,
Ta=-40 °C to +125 °C
[Over Voltage Mute Function (OVM)]
Over Voltage Mute Start Voltage
VOVMS
20.0
22.0
24.0
V
Over Voltage Mute Gain
VOVMG
-
-25
-
mV/V
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ΔVFB/ΔVIN
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BD18342FV-M
Electrical Characteristics – continued
(Unless otherwise specified Ta=-40 °C to +125 °C, VIN=13 V, CVREG=1.0 µF, Transistor PNP=2SAR573DFHG)
Limit
Parameter
Symbol
Unit
Conditions
Min
Typ
Max
[CR TIMER]
CRT Pin Charge Current
ICRT
36
40
44
μA
CRT Pin Charge Voltage
VCRT_CHA
0.72
0.80
0.88
V
CRT Pin Discharge Voltage 1
VCRT_DIS1
1.80
2.00
2.20
V
CRT Pin Discharge Voltage 2
VCRT_DIS2
2.10
2.40
3.00
V
When VCRT > VCRT_DIS2,
RD1 → RD2
RCHA
28.5
30.0
31.5
kΩ
RCHA=
(VCRT_DIS1-VCRT_CHA)/ICRT
VCRT_CHA/
VCRT_DIS1
0.38
0.40
0.42
V/V
DISC Pin ON Resistor 1
RDISC1
20
50
100
Ω
IDISC=10 mA
DISC Pin ON Resistor 2
RDISC2
2.5
5.0
10
kΩ
IDISC=100 μA
ICRT_LEAK
-
-
10
μA
VCRT=VIN
VOPD
1.1
1.2
1.3
V
VOPD=VIN-VOP
IOP
19
21
23
μA
VOP=VIN-0.5 V
CRT Pin Charge Resistor
CR Timer Discharge Constant
CRT Pin Leakage Current
[LED Open Detection]
LED Open Detection Voltage
OP Pin Input Current
[Disable LED Open Detection Function at Reduced-Voltage]
IOPM
38
40
42
μA
VIN Pin Disable LED Open
Detection Voltage
at Reduced-Voltage
VIN_OPM
VOPM
x 5.9
VOPM
x 6.0
VOPM
x 6.1
V
OPM Pin Input Voltage Range
VOPM_R
1.0
-
2.2
V
OPM Pin Source Current
[Disable LED Open Detection Time Setting D Function]
Input Threshold Voltage
D Pin Source Current
D Pin ON Resistor
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VDH
0.9
1.0
1.1
V
IDSOURCE
100
230
400
μA
RD
-
-
950
Ω
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ID_EXT=100 μA
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BD18342FV-M
Electrical Characteristics – continued
(Unless otherwise specified Ta=-40 °C to +125 °C, VIN=13 V, CVREG=1.0 µF, Transistor PNP=2SAR573DFHG)
Limit
Parameter
Symbol
Unit
Conditions
Min
Typ
Max
[Short Circuit Protection (SCP)]
Short Circuit Protection Voltage
VSCPD
1.10
1.20
1.30
V
Short Circuit Protection
Release Voltage
VSCPR
1.15
1.25
1.35
V
Short Circuit Protection
Hysteresis Voltage
VSCPHYS
-
50
-
mV
SCP Pin Source Current
ISCP
0.2
1.0
2.0
mA
SCP Pin Source Current
ON Voltage
VSCP2
1.15
1.30
1.45
V
tSCP
10
20
45
µs
Input High Voltage
VPBUSH
2.4
-
-
V
Input Low Voltage
VPBUSL
-
-
0.6
V
Hysteresis Voltage
VPBUSHYS
-
200
-
mV
IPBUS
75
150
300
μA
VEN=5 V
PBUS Pin Output Low Voltage
VPBUS_OL
-
-
0.6
V
IPBUS_EXT=3 mA
PBUS Pin Output High Voltage
VPBUS_OH
3.5
4.5
5.5
V
IPBUS_EXT=-10 μA
PBUS Pin Leakage Current
IPBUS_LEAK
-
-
10
μA
VPBUS=7 V
Input High Voltage
VENH
2.4
-
-
V
Input Low Voltage
VENL
-
-
0.6
V
Hysteresis Voltage
VENHYS
-
60
-
mV
IEN
-
7
15
μA
VEN=5 V
UVLO Detection Voltage
VUVLOD
3.88
4.10
4.32
V
VIN: Sweep down
UVLO Release Voltage
VUVLOR
4.25
4.50
4.75
V
VIN: Sweep up,
VREG > 3.75 V
VHYS
-
0.4
-
V
SCP Delay Time
[PBUS]
PBUS Pin Source Current
[EN]
Pin Input Current
[UVLO VIN]
UVLO Hysteresis Voltage
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Typical Performance Curves (Reference Data)
5.0
6.0
4.5
5.5
4.0
5.0
VREG Pin Voltage : VREG[V]
Circuit Current at Normal Mode : IVIN2[mA]
(Unless otherwise specified Ta=25 °C, VIN=13 V, CVREG=1.0 µF, Transistor PNP=2SAR573DFHG)
Ta=+125 °C
Ta=+25 °C
Ta=-40 °C
3.5
3.0
2.5
2.0
1.5
1.0
4.5
4.0
3.5
Ta=+125 °C
Ta=+25 °C
Ta=-40 °C
3.0
2.5
2.0
1.5
1.0
0.5
0.5
0.0
0
2
4
6
8
0.0
10 12 14 16 18 20
0
2
4
Supply Voltage : VIN[V]
6
8
10 12 14 16 18 20
Supply Voltage : VIN[V]
Figure 1. Circuit Current at Normal Mode vs Supply
Voltage
Figure 2. VREG Pin Voltage vs Supply Voltage
500
5.25
400
5.15
LED Current : ILED[mA]
VREG Pin Voltage : VREG[V]
5.20
5.10
5.05
5.00
4.95
4.90
4.85
300
200
100
4.80
4.75
0
-50 -25
0
25
50
75 100 125 150
0
4
6
8
10
12
14
Resistor for Setting LED Current :
RFB1+RFB2[Ω]
Temperature[°C]
Figure 3. VREG Pin Voltage vs Temperature
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Figure 4. LED Current vs Resistor for Setting LED Current
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Typical Performance Curves (Reference Data) – continued
5
690
4
680
FB Pin Voltage : VFBREG[mV]
LED Current Accuracy : ΔILED[%]
(Unless otherwise specified Ta=25 °C, VIN=13 V, CVREG=1.0 µF, Transistor PNP=2SAR573DFHG)
3
2
1
0
-1
-2
ΔILED=(ILED/{0.65 V/(RFB1+RFB2)}-1)
x100[%]
-3
670
660
650
640
630
620
-4
-5
610
0
2
4
6
8
10
12
14
-50 -25
Resistor for Setting LED Current :
RFB1+RFB2[Ω]
45
700
FB Pin Voltage : VFBREG[mV]
BASE Pin Sink Current Capability : IBASE[mA]
800
40
35
30
Ta=+125 °C
Ta=+25 °C
Ta=-40 °C
400
300
200
10
0
8
10
12
14
16
18
Ta=+125 °C
6
20
11 16 21 26 31 36 41 46 51 56
Supply Voltage : VIN[V]
Supply Voltage : VIN[V]
Figure 7. BASE Pin Sink Current Capability vs Supply
Voltage
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Ta=+25 °C
Ta=-40 °C
500
100
6
75 100 125 150
600
15
4
50
Figure 6. FB Pin Voltage vs Temperature
50
20
25
Temperature[°C]
Figure 5. LED Current Accuracy vs Resistor for Setting
LED Current
25
0
Figure 8. FB Pin Voltage vs Supply Voltage
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Typical Performance Curves (Reference Data) – continued
(Unless otherwise specified Ta=25 °C, VIN=13 V, CVREG=1.0 µF, Transistor PNP=2SAR573DFHG)
42.0
OPM Pin Source Current : IOPM[μA]
CRT Pin Charge Current : ICRT[μA]
42.0
41.5
41.0
40.5
40.0
39.5
39.0
38.5
38.0
41.5
41.0
40.5
40.0
39.5
39.0
38.5
38.0
-50 -25
0
25
50
75 100 125 150
-50 -25
Temp[℃]
Temperature[°C]
25
50
75 100 125 150
Temp[℃]
Temperature[°C]
Figure 9. CRT Pin Charge Current vs Temperature
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Figure 10. OPM Pin Source Current vs Temperature
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BD18342FV-M
Description of Function
(Unless otherwise specified, Ta=25 °C, VIN=13 V, Transistor PNP=2SAR573DFHG, and numbers are “Typical” values.)
1.
LED Current Setting
LED current ILED can be defined by setting resistances RFB1 and RFB2.
𝐼𝐿𝐸𝐷 = 𝑅
𝑉𝐹𝐵𝑅𝐸𝐺
𝐹𝐵1 +𝑅𝐹𝐵2
[A]
where:
𝑉𝐹𝐵𝑅𝐸𝐺
is the FB pin voltage 650 mV (Typ).
●How to connect LED current setting resistors
LED current setting resistors must always be connected at least two or more in series as below.
If only one current setting resistor is used, then in case of a possible resistor short (pattern short on the board
etc.), the external PNP Tr. and LED may be broken due to large current flow.
PNP Tr. rating current, LED rating current, RFB1 and RFB2 must have the following relations:
𝑉
𝐼𝐿𝐸𝐷_𝑀𝐴𝑋 > 𝐼𝑃𝑁𝑃_𝑀𝐴𝑋 > 𝑀𝑖𝑛(𝑅𝐹𝐵𝑅𝐸𝐺
,𝑅
𝐹𝐵1
𝐹𝐵2 )
[A]
where:
𝐼𝐿𝐸𝐷_𝑀𝐴𝑋
𝐼𝑃𝑁𝑃_𝑀𝐴𝑋
𝑉𝐹𝐵𝑅𝐸𝐺
𝑀𝑖𝑛(𝑅𝐹𝐵1 , 𝑅𝐹𝐵2 )
is the LED rating current.
is the PNP Tr. rating current.
is the FB pin voltage 650 mV (Typ).
is the lowest value of RFB1 and RFB2.
RFB1
VIN
RFB2
FB
+B
EN
VREG
VREG
BASE
VCE_PNP
VREF
GND
CVREG
ILED
Figure 11. LED Current Setting
●Constant current control dynamic range
Constant current control dynamic range of LED current I LED can be calculated as follows.
𝑉𝐼𝑁 ≥ 𝑉𝑓_𝐿𝐸𝐷 × 𝑁 + 𝑉𝐶𝐸_𝑃𝑁𝑃 + 𝑉𝐹𝐵𝑅𝐸𝐺
[V]
where:
𝑉𝐼𝑁
𝑉𝑓_𝐿𝐸𝐷
𝑁
𝑉𝐶𝐸_𝑃𝑁𝑃
𝑉𝐹𝐵𝑅𝐸𝐺
2.
is the VIN pin voltage.
is the LED Vf.
is the number of rows of LED.
is the external PNP Tr. collector-emitter saturation voltage.
is the FB pin voltage 650 mV (Typ).
Reference voltage (VREG)
Reference voltage VREG 5.0 V (Typ) is generated from VIN input voltage. This voltage is used as power source for the
internal circuit, and also used to fix the voltage of pins outside LSI to HIGH side. The VREG pin must be connected with
CVREG=1.0 μF to 4.7 μF to ensure capacity for the phase compensation. If CVREG is not connected, the circuit behavior
would become extraordinarily unstable, for example with the oscillation of the reference voltage.
The VREG pin voltage must not be used as power source for other devices than this LSI.
VREG circuit has a built-in UVLO function. The IC is activated when the VREG pin voltage rises to 4.00 V (Typ) or higher,
and shut down when the VREG pin voltage drops to 3.75 V (Typ) or lower.
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Description of Function – continued
3.
Table of Operations
The PWM dimming mode switches to DC control depending on the CRT pin voltage.
The switching conditions are as shown in the table below. When VIN > 22.0 V (Typ), LED current is limited to reduce the
heat dissipation of external PNP Tr..
Depending on the OP pin and the SCP pin voltage status, detect LED open or short circuit then LED current is turned
OFF. LED current is also turned OFF when Low signal is input to the PBUS pin.
In addition, UVLO and TSD further increases system reliability.
For each functions, please refer to Description of Function.
Detecting Condition
Operation
Mode
CRT
Pin
PBUS Pin
[Release]
LED Current
(ILED)
[Detect]
Stand-by
Mode(Note 1)
-
VEN ≤ 0.6 V
VEN ≥ 2.4 V
OFF(Note 3)
Hi-Z
DC
VCRT ≥
2.0 V (Typ)
-
-
50 mA to 400 mA
High
4.5 V (Typ)
PWM Dimming
See Features
Description 4
-
-
See Features
Description 4
High
4.5 V (Typ)
Over Voltage
Mute
-
VIN >
22.0 V (Typ)
VIN ≤
22.0 V (Typ)
See Features
Description 10
High
4.5 V (Typ)
LED Open
Detection(Note 2)
-
VOP ≥
VIN –1.2 V (Typ)
VOP <
VIN – 1.2 V (Typ)
OFF(Note 3)
Low
Short Circuit
Protection (SCP)
-
VSCP ≤
1.20 V (Typ)
VSCP ≥
1.25 V (Typ)
OFF(Note 3)
Low
PBUS Control
OFF
-
VPBUS ≤ 0.6 V
VPBUS ≥ 2.4 V
OFF(Note 3)
Input
VPBUS ≤ 0.6 V
UVLO
-
VIN ≤ 4.10 V (Typ)
or
VREG ≤ 3.75 V (Typ)
VIN ≥ 4.50 V (Typ)
or
VREG ≥ 4.00 V (Typ)
OFF(Note 3)
High
TSD
-
Tj ≥
175 C (Typ)
Tj ≤
150 C(Typ)
OFF(Note 3)
Hi-Z
(Note 1) Circuit current 0 μA (Typ)
(Note 2) In regard to the sequence of LED current OFF, see Features Description 5.
(Note 3) The BASE pin sink current: OFF, and LED current(ILED): OFF.
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Description of Function – continued
4.
PWM Dimming Operation
PWM Dimming is performed with the following circuit.
The dimming cycle and ON Duty Width, can be set by values of the external components (CCRT , RCRT ).
Connect the CRT pin to VIN and the DISC pin to GND or open if it is not used.
The CR timer function is activated if DC SW is OPEN. To perform PWM dimming of LED current, a triangular waveform
is generated at the CRT pin. The LED current (ILED) is turned OFF while CRT voltage is ramp up, and LED
current(ILED) is turned ON while CRT voltage is ramp down.
When VCRT ≥ VCRT_DIS1(2.0 V(Typ)), dimming mode turns to DC Control. When VCRT > VCRT_DIS2(2.4 V(Typ)), the DISC pin
ON resister changes from RDISC1(50 Ω(Typ)) to RDISC2(5 kΩ(Typ)), and the power consumption of the IC is reduced by
reducing the inflow current of the DISC pin.
PWM SW
ON
VIN
EN
VREG
DC SW
OPEN
FB
Control
Logic
VREG
BASE
I CRT
VREF
CRT
CCRT
RCRT
ILED
VCRT_DIS1
GND
VCRT_DIS2
DISC
RDISC1
R DISC2
Figure 12. PWM Dimming Operation
CRT Voltage
Ramp up
CRT Voltage
Ramp down
VCRT_DIS1
2.0 V(Typ)
CRT Pin
Waveform
ΔVCRT
VCRT_CHA
0.8 V(Typ)
t OFF
tOFF =
LED Current
ILED
ΔVCRT×CCRT
ICRT
ILED
OFF
t ON
=RCHA×CCRT
ILED
ON
tON= - (R CRT + RDISC1)×CCRT×ln
ILED
OFF
I LED
ON
VCRT_CHA
VCRT_DIS1
I LED
OFF
I LED
ON
Figure 13. PWM Dimming Operation
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4.
PWM Dimming Operation – continued
(1) CRT ramp up Time tOFF and CRT ramp down Time tON
CRT ramp up Time tOFF and CRT ramp down Time tON can be defined from the following equations.
Make sure that tON is set PWM Minimum Pulse Width tMIN 10 μs or more.
𝑡𝑂𝐹𝐹 =
∆𝑉𝐶𝑅𝑇 ×𝐶𝐶𝑅𝑇
𝐼𝐶𝑅𝑇
= 𝑅𝐶𝐻𝐴 × 𝐶𝐶𝑅𝑇
[s]
𝑉
𝑡𝑂𝑁 = −(𝑅𝐶𝑅𝑇 + 𝑅𝐷𝐼𝑆𝐶1 ) × 𝐶𝐶𝑅𝑇 × 𝐼𝑛 (𝑉 𝐶𝑅𝑇_𝐶𝐻𝐴 ) [s]
𝐶𝑅𝑇_𝐷𝐼𝑆1
where:
𝐼𝐶𝑅𝑇
𝑅𝐶𝐻𝐴
𝑅𝐷𝐼𝑆𝐶1
𝑉𝐶𝑅𝑇_𝐶𝐻𝐴
𝑉𝐶𝑅𝑇_𝐷𝐼𝑆1
is the CRT pin charge current, 40 μA (Typ).
is the CRT pin charge resistor, 30 kΩ (Typ).
is the DISC pin ON resistor1, 50 Ω (Typ).
is the CRT pin charge voltage, 0.8 V (Typ).
is the CRT pin discharge voltage1, 2.0 V (Typ).
(2) PWM Dimming Frequency fPWM
PWM frequency is defined by tON and tOFF.
𝑓𝑃𝑊𝑀 = 𝑡
1
𝑂𝑁 +𝑡𝑂𝐹𝐹
[Hz]
(3) ON Duty(DON)
PWM ON duty is defined by tON and tOFF.
𝐷𝑂𝑁 = 𝑡
𝑡𝑂𝑁
𝑂𝑁 +𝑡𝑂𝐹𝐹
[%]
(Example) In case of RCRT=3.6 kΩ, CCRT=0.1 μF (Typ)
𝑡𝑂𝐹𝐹 = 𝑅𝐶𝐻𝐴 × 𝐶𝐶𝑅𝑇 = 30 × 0.1 = 3.0
[ms]
𝑡𝑂𝑁 = −(𝑅𝐶𝑅𝑇 + 𝑅𝐷𝐼𝑆𝐶1 ) × 𝐶𝐶𝑅𝑇 × 𝐼𝑛(𝑉𝐶𝑅𝑇_𝐶𝐻𝐴 /𝑉𝐶𝑅𝑇_𝐷𝐼𝑆1 )
= −(3.6 + 50) × 0.1 × 𝐼𝑛(0.8/2.0) = 0.334 [ms]
𝑓𝑃𝑊𝑀 = 1/(𝑡𝑂𝑁 + 𝑡𝑂𝐹𝐹 ) = 1/(3.0 + 0.334) = 300 [Hz]
𝐷𝑂𝑁 = 𝑡𝑂𝑁 /(𝑡𝑂𝑁 + 𝑡𝑂𝐹𝐹 ) = 0.334/(3.0 + 0.334) = 10.0
[%]
[PWM Dimming Operation Using External Signal]
In case external PWM input to the CRT pin, make sure that input pulse high voltage ≥ 2.2 V and pulse low voltage ≤ 0.6
V. Also please open the DISC pin or connect to GND.
VIN
EN
VREG
FB
Control
Logic
V REG
BASE
I CRT
VREF
μ-Con
or
CRTIMER
CRT
ILED
GND
DISC
Figure 14. PWM Dimming Operation Using External Signal
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4.
PWM Dimming Operation – continued
●About deviation of CRT ramp up/down time with a reverse connection protection diode
If this LSI is used to drive LED like below schematic, there is a possibility of occur CRT ramp up/down time deviation
due to characteristics of reverse current Ir diode (D2, D3) .
Consider to choose a diode (D2, D3) which is recommended by Rohm or Ir value 1 μA (Max) or less.
Since reverse current flows even with the recommended diodes, connect a resistor of RDCIN of 10 kΩ or less between
Point A and GND so that the voltage at point A does not rise.
Mechanism of deviation of CRT ramp up/down time from set values.
① During the PWM dimming operation mode, Point A on Figure 15 is Hi-Z.
↓
② Reverse current Ir of D2 and D3 goes to Point A.
(Power supply voltage is being input into the cathode of D2, so mainly reverse current of D2 goes into C1.)
→Reverse current Ir of D3 is added to the CRT pin charge current and discharge current, so CRT ramp
up/down time deviates from the settings.
↓
③ C1 gets charged, voltage at Point A rises.
↓
④ Point A voltage ≥ the CRT pin voltage of each IC.
↓
⑤ Vf occurs in the diodes D3.
↓
⑥ D3 circulate forward current If
→Forward current If of D3 is added to the CRT pin charge current and discharge current, so CRT ramp
up/down time deviates from the settings.
↓
⑦ Repetition of ➁ to ➅.
D1
VIN
EN
D2
Point A
RDCIN
FB
Ir
D3
C1
BD18342FV-M
BASE
CRT
If
Vf
GND
DISC
Figure 15. How Reverse Protection Diode Affects the CRT Pin Ramp Up/Down Time
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Description of Function – continued
5.
LED Open Detection Function
In case any one of the LEDs is in the open state, the IC can detect LED open condition when the OP pin voltage (VOP)
meets the following condition: VOP ≥ VIN-1.2 V (Typ). As soon as VOP ≥ VIN-1.2 V (Typ) condition is achieved, the D pin
source current (230 μA (Typ)) turns on and starts charging the disable LED open detection time setting capacitor (CD).
Once the D pin voltage (VDH) becomes 1.0 V (Typ) or more and 1 μs (Typ) elapses, the BASE pin sink current (IBASE) is
latched OFF and the PBUS pin voltage (VPBUS) is switched to Low.
[Base Current Limit Resistance (RLIM)]
The OP pin voltage VOP at LED open is defined by the following formula:
(Note that the external PNP Tr. goes into the saturation mode when the collector is open, it becomes the following
formula.)
𝑉𝑂𝑃 = 𝑉𝐼𝑁 − {(𝑅𝐹𝐵1 + 𝑅𝐹𝐵2 ) × 𝐼𝐵𝐴𝑆𝐸𝑀𝐴𝑋 + 𝑉𝐶𝐸𝑃𝑁𝑃 } [V]
𝐼𝐵𝐴𝑆𝐸_𝑀𝐴𝑋 = 6.0𝑉/𝑅𝐿𝐼𝑀
[A]
(𝐼𝐵𝐴𝑆𝐸_𝑀𝐴𝑋 < 80 𝑚𝐴)
where:
𝑅𝐹𝐵1 , 𝑅𝐹𝐵2
𝐼𝐵𝐴𝑆𝐸_𝑀𝐴𝑋
𝑅𝐿𝐼𝑀
𝑉𝐶𝐸_𝑃𝑁𝑃
is the LED current setting resistance.
is the maximum BASE pin sink current.
is the resistor for limiting BASE pin current.
is the external PNP Tr. Collector-emitter voltage (Note: ICE=IOP (23 μA (Max))).
Please determine the BASE current limit resistance RLIM to ensure that the OP pin voltage when the LED is open should
meet the following condition: VOP > VIN-1.2 V (Typ).
Also note that the BASE current limit resistance must meet the following condition in order to obtain the BASE current to
be needed during normal LED operation.
4.0/𝑅𝐿𝐼𝑀 > 𝐼𝐿𝐸𝐷 /ℎ𝑓𝑒_𝑀𝐼𝑁
[A]
where:
ℎ𝑓𝑒_𝑀𝐼𝑁
is the minimum external PNP Tr. hfe.
For the D pin, it is possible to set the disable time tD from when the OP pin voltage meets the condition “VOP > VIN-1.2 V
(Typ)” until the BASE pin sink current (IBASE) is latched off, according to the following formula. Note that the disable
time must be shorter than or equal to the ON pulse width of the PWM dimming tON.
𝐶𝐷 ×𝑉𝐷𝐻
𝑡𝑂𝑁 > 𝑡𝐷 = 𝐼
[s]
𝐷𝑆𝑂𝑈𝑅𝐶𝐸
where:
𝑡𝑂𝑁
𝐶𝐷
𝑉𝐷𝐻
𝐼𝐷𝑆𝑂𝑈𝑅𝐶𝐸
is the ON pulse width of the PWM dimming(CRT ramp down time).
is the disable LED open detection time setting capacitor.
is the D pin input threshold voltage, 1.0 V (Typ).
is the D pin source current, 230 μA (Typ).
To reset the latched off LED current, EN must be turned-on again (The time when the EN Pin is “L” since the power is
turned on again: 50 μs or more) or the condition “UVLO (VIN ≤ 4.10 V or VREG ≤ 3.75 V)” must be fulfilled.
VIN
LED
OPEN
R FB1
FB
PBUS
DRV
R FB2
IBASE
R LIM
VCE_PNP
OPEN
LED OPEN
OP
1.2 V
VOP
21 μA
VIN
230 μA
D
D COMP
1 μs
Filter
CD
LED Open
Detection
Comparator
Output
D Pin
Voltage
VD
C LED
VD
Discharge Co
by the OP pin input current(21μA)
VIN
VIN - 1.2 V(Typ)
VF_LED
BASE
PBUS
Control
Logic
OP Pin
Voltage
VOP
ILED
1.0 V
(Typ)
1 μs
(Typ)
C D x 1.0 V
230 μA
PBUS Pin
Voltage
VPBUS
1.0 V
GND
I B A S E: ON
(DRV: ON)
I B A S E: OFF(DRV: OFF)
Latch Release Condtion :
EN: H -> L or UVLO: detect
Figure 16. LED Open Detection Timing Chart
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Description of Function – continued
6.
Disable LED Open Detection Function at Reduced-Voltage
The disable LED open detection function serves to prevent false detection of LED open at the reduced-voltage during
the ramp-up/ramp-down of the VIN pin voltage. Even though LED is in the open state, LED open will not be detected
until the VIN pin voltage becomes more than Disable Open Detection Voltage at Reduced-Voltage (VIN_OPM). Once
VIN_OPM is surpassed, the LED current will be latched OFF (The BASE pin sink current (IBASE) is latched OFF) and the
PBUS voltage will be switched to Low following the sequence explained in Description of Function 5.
VIN_OPM must be defined by the following formula. (The OPM pin voltage must be set between 1.0 V and 2.2 V.)
𝑉𝐼𝑁_𝑂𝑃𝑀 ≥ 𝑉𝐼𝑁_𝑂𝑃𝐸𝑅𝑅
[V]
VIN
where:
𝑉𝐼𝑁_𝑂𝑃𝑀
is the VIN pin disable open detection voltage
at reduced-voltage.
𝑉𝐼𝑁_𝑂𝑃𝐸𝑅𝑅 is the VIN pin open erroneous detection
voltage at reduced-voltage.
V RE G
OPM
ROPM
𝑉𝐼𝑁_𝑂𝑃𝐸𝑅𝑅 = 𝑉𝑓_𝐿𝐸𝐷 × 𝑁 + 𝑉𝑂𝑃𝐷
VCE_PNP
OPEN
MASK
LED OPEN
OP
Vf_LED ×N
VI N
[V]
BASE
VREF
I OP M
𝑉𝐼𝑁_𝑂𝑃𝑀 = 𝑉𝑂𝑃𝑀 × 6.0 (𝑇𝑦𝑝) [V]
𝑉𝑂𝑃𝑀 = 𝐼𝑂𝑃𝑀 × 𝑅𝑂𝑃𝑀
FB
Control
Logic
VOP D =1.2 V
[V]
GND
where:
Figure 17. Disable LED Open Detection Function
at Reduced-Voltage
𝑉𝑂𝑃𝑀 is the OPM pin voltage.
𝐼𝑂𝑃𝑀 is the pin source current, 40 μA (Typ)
𝑅𝑂𝑃𝑀 is the OPM pin connection resistance.
𝑉𝑓_𝐿𝐸𝐷 is the LED Vf.
𝑁
is the number of rows of LED.
𝑉𝑂𝑃𝐷 is the LED open-circuit detection voltage, 1.2 V (Typ)
●When connecting resistor for heat dispersion, or connecting resistor or diodes between the OP pin and LED
anode
The formula to calculate VIN_OPERR will be different from the one above when the current flowing the LED is large and it
is necessary to connect a resistor for heat dispersion in series with the LED to reduce the heat generation from the
external PNP Tr., when multiple rows of the LEDs are driven, or when connecting a resistor to adjust the threshold
voltage for detecting the LED open-circuit. Please read the Application Note of BD1834xFV-M series for details.
VIN_OPERR
VIN_OPM
VIN_OPM
VIN_OPERR
VIN >
Vf_LED × N + VCE_PNP + VFBREG
VIN
Controllable Range of
constant current
Disable
LED Open
Detection
Area
VIN
Disable
LED Open
Detection
Area
VOPD =VIN -1.2 V
LED Open
Detection
Area
LED Open
Detection
Area
VOP
VOP = Vf_LED × N
ILED
ILED
4.5 V
VPBUS
Figure 18. VIN Pin Disable LED Open Detection Voltage at Reduced-Voltage
and LED Open Erroneous Detection Voltage at Reduced-Voltage
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Description of Function – continued
7.
Short Circuit Protection (SCP)
Short Circuit Protection function will be activated by decreasing the SCP pin voltage when the collector of the external
PNP Tr. is short to GND. After a lapse of the short circuit protection delay time(tSCP)(20 μs(Typ)) following the drop of the
SCP pin voltage(VSCP) is 1.2 V(Typ) or less, the external PNP Tr. is turned OFF to prevent its thermal destruction, and it
can be notify the abnormally to the outside by changing the PBUS pin output to low.
In order to avoid malfunction since the power is turned on, the Short Circuit Protection function will not be activated until
VCRT > 2.0 V(Typ) after UVLO is reset.
If it is in the short circuit state (VSCP < 1.2 V(Typ)) since the power is turned on, the Short Circuit Protection function will
be activated when VCRT > 2.0 V(Typ) condition is reached and 60 µs(Typ) passes, after UVLO is reset.
VIN
FB
EN
VREG
BASE
VREF
PBUS
VIN
SCP
GND
ILED
1 mA
Control
Logic
PBUS
SCP
20 µs
Filter
SHORT
1.20 V ⇔1.25 V
Short
Circuit
Short Circuit
4.5 V
VIN
2.0 V
VCRT
1.25 V
1.25 V
1.20 V
VSCP
ON
60 μs
OFF
ILED
ON
ON
20 μs
OFF
OFF
High
High
High
Low
VPBUS
Low
Figure 19. Short Circuit Protection (SCP)
●SCP Pin Source Current
The SCP pin sources the current (1 mA(Typ)) once its voltage (VSCP) drops under 1.3 V in order to prevent the
malfunction of the short circuit protection.
VIN
FB
EN
1.3 V (Typ)
VREG
BASE
VSCP
VREF
0V
PBUS
PBUS
VIN
SCP
1 mA
Control
Logic
1.3 V
1.0 mA (Typ)
GND
SCP
20 µs
Filter
1.2 V⇔1.25 V
ISCP
ISCP
0 mA
Figure 20. SCP Pin Source Current
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Description of Function – continued
8.
About the Capacitor of Connecting LED Anode
There is a zone which the output (LED anode) will become high impedance (Hi-Z) at PWM dimming Mode. During this
time noise(Note 1) can couple on to this pin and cause false detection of SHORT condition.
To prevent this, it is necessary to connect a Capacitor CLED between LED anode and GND pin nearby pin.
Make sure that the capacitor of connecting LED anode is the following equation:
0.1 ≤ 𝐶𝐿𝐸𝐷 ≤ 0.68
[µF]
In case CLED is set the range from 0.1 μF to 0.68 μF, the ILED current becomes dull, so please evaluate I LED waveform in
PWM mode operation.
About the example of evaluation, please see evaluation example on page 21.
In case a capacitor exceeding the recommended range is connected to LED anode, there is a possibility that delay time
of start-up will reach about several ten ms, so special attention is needed.
(Note 1) Conducted noise, Radiated noise, Crosstalk of connecter and PCB pattern etc…
VIN
EN
VREG
FB
Control
Logic
VREG
BASE
ICRT
VREF
CRT
CLED
GND
DISC
ILED
Figure 21. About the Capacitor of Connecting LED Anode
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Description of Function – continued
Evaluation example (ILED pulse width at PWM Dimming operation)
Condition: +B=13 V
Ta=25 °C
LED=1 Strings
CCRT=0.01 μF
RDISC=1.0 kΩ
PWM Dimming Mode
ILED=50 mA
ILED=500 mA
ILED=50 mA
ILED=200 mA
CLED=0.1 μF
CLED=0.47 μF
CLED=0.1 μF
CLED=0.47 μF
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Description of Function – continued
9.
PBUS Function
The PBUS pin is the pin to input and output an error signal.
When abnormality such as LED open or output ground fault occurs, it can notify the abnormality to the outside by
changing the PBUS pin output from high to low. In addition, by externally controlling the PBUS pin from high to low, the
LED current is turned off. When using multiple LSIs to drive multiple LEDs, it is possible to turn off all LED lines at once
by connecting the PBUS pins of each CH as shown in the figure below, even if LED open or output ground fault occurs.
Caution of using the PBUS pin
Do not connect to the PBUS pins other than BD1834xFV-M series due to the difference of ratings, internal
threshold voltages, and so on.
FB
VIN
FB
VIN
BASE
BASE
EN
EN
BD18342FV-M
CH 1
BD18342FV-M
CH 2
OP
SCP
PBUS
GND
OP
SCP
PBUS
GND
LED
OPEN
LED
OFF
communication each other by PBUS
Figure 22. PBUS Function
▼Example of Protective Operation due to LED Open Circuit
①CH1 LED
Open
CH1 PNP Tr.
Collector
Voltage
ON
CH1 ILED
OFF
②After CH1LED Open Detection Mask time
I LE D： Latch OFF
VP B US：High→ Low
VPBUS
CH2 PNP Tr.
Collector
Voltage
③V P B US：High →Low
CH2 PNP Tr. : OFF
ON
CH2 ILED
OFF
Figure 23. Example of Protective Operation
If LED OPEN occurs, the PBUS pin of CH1 is switched from High to Low output. As the PBUS pin becomes Low, LED
drivers of other CH detect the condition and turns OFF their own LEDs. The collector voltage of PNP transistor clamps
to 1.3 V (Typ) during the OFF period, in order to prohibit ground fault detection.
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Description of Function – continued
10. Over Voltage Mute Function (OVM)
Once the VIN pin voltage (VIN) goes above 22.0 V (Typ), the over voltage mute function is activated to decrease the LED
current (ILED) in order to suppress heat generation from the external PNP Tr.
The FB pin voltage VFBREG which controls the LED current (ILED) will decay at -25 mV/V (Typ).
VIN
FB
EN
VREG
Over
Voltage
Mute
BASE
VREF
GND
VFBREG [mV]
22.0 V(Typ)
650
-25 mV/V(Typ)
Output current is
muted by power
supply overvoltage
0
VOVMS
VIN [V]
Figure 24. Overvoltage Mute Function (OVM)
11. Under Voltage Lockout (UVLO)
UVLO is a protection circuit to prevent malfunction of the IC when the power is turned on or when the power is suddenly
shut off.
This IC has two UVLO circuits; UVLO VIN for VIN and UVLO VREG for VREG.
As soon as UVLO status is detected, the BASE pin sink current will be turned off and switch OFF the LED current (ILED).
The following shows the threshold conditions of both UVLO circuits.
Detection Conditions
[Detect]
[Release]
LED Current
(ILED)
UVLO VIN
VIN ≤ 4.10 V (Typ)
VIN ≥ 4.50 V (Typ)
OFF(Note 1)
High
4.5 V (Typ)
UVLO VREG
VREG ≤ 3.75 V (Typ)
VREG ≥ 4.00 V (Typ)
OFF(Note 1)
High
4.5 V (Typ)
Operating Mode
PBUS Pin
(Note 1) The BASE pin sink current is turned OFF to switch OFF the LED current (ILED).
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Timing Chart
(Unless otherwise specified Ta=25 °C, VIN=13 V, Transistor PNP=2SAR573DFHG, LED 2 strings, and values are Typical.)
PWM Dimming Mode
DC Mode
EN
reclosing
EN
reclosing
OUTPUT
GND
SHORT
LED
OPEN
OUTPUT
GND
SHORT
LED
OPEN
13 V
VIN
4.5 V
4.1 V
13 V
VEN
0.6 V
2.4 V
0.6 V
4.0 V
2.4 V
4.0 V
VREG
13 V
VCRT
1.0 V
1.0 V
VD
VIN-1.2 V
VIN-1.2 V
1.25 V
VOP
VSC P
1.20 V
1.25 V 1.20 V
1.25 V
20 μs
1.25 V
20 μs
VPBU S
VFBREG
ILED
Output
Latch OFF
Output
Latch OFF
Figure 25. Timing Chart
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Application Examples
(1) ILED=120 mA
RFB1
DC_in
RFB2
VIN
FB
D1
ZD1
CVIN1
CVIN2
EN
BASE
CRT
OP
U1
DISC
Q1
SCP
CLED
BD18342FV-M
D
VREG
CD
CVREG
OPM
ROPM
PBUS
GND
Figure 26. Application Example 1
(ILED 120 mA, LED white 2 strings)
Recommended Parts List 1 (ILED 120 mA, LED white 2 strings)
Parts
No
Parts Name
IC
Diode
Transistor PNP
Resistor
Capacitor
Value
Unit
Product Maker
U1
BD18342FV-M
-
-
ROHM
D1
RFN2LAM6STF
-
-
ROHM
ZD1
TND12H-220KB00AAA0
-
-
NIPPON CHEMICON
Q1
2SAR573DFHG
-
-
ROHM
RFB1
LTR10EVHFL2R70
2.7
Ω
ROHM
RFB2
LTR10EVHFL2R70
2.7
Ω
ROHM
ROPM
MCR03EZPFX3902
39
kΩ
ROHM
CVIN1
GCM32ER71H475KA40
4.7
μF
murata
CVIN2
GCM155R71H104KE37
0.1
μF
murata
CVREG
GCM188R71E105KA49
1.0
μF
murata
CD
GCM155R11H103KA40
0.01
μF
murata
CLED
GCM155R71H104KE37
0.1
μF
murata
(Note 1) About ZD1, please place according to test standard of battery line.
Please note the following
1.
External PNP transistor
For external PNP transistor, please use the recommended device 2SAR573DFHG for this IC.
While using non-recommended device, validate the design on actual board with sufficient confirmation of the parts
specifications (hfe, parasitic capacitance).
Please check hfe of the part when designing base current limit resistor. (See Features Description, section 5). As for
parasitic capacitance (CLED connected at LED anode), the smaller it is, the smaller its overshoot is. Use devices that has
smaller parasitic capacitance than that of recommended device. Also parasitic capacitance is possible to be varied by PCB
layout so please evaluate overshoot of ILED on actual board. (See Features Description, Section 8 -Evaluation example, ILED
pulse width at PWM Dimming operation).
2.
Power supply steep variation
This IC is validated with test conditions as per ISO7637-2 standards.
There is possibility of unexpected LED regulation (peak current of output etc.) due to sudden transients outside the
specification range standards in input power supply. Please check the maximum ratings of LED and evaluate on actual
board for any unexpected LED regulation.
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Application Examples - continued
(2) ILED=120 mA, PWM ON Duty=10 %
RFB1
RFB2
PWM_in
VIN
FB
D1
ZD1
CVIN1
CVIN2
EN
BASE
Q1
D2
CRT
DC_in
D3
CCRT
OP
RCRT
U1
DISC
RDCIN
SCP
CLED
BD18342FV-M
D
VREG
CD
CVREG
OPM
ROPM
PBUS
GND
Figure 27. Application Example 2
(ILED 120 mA, LED white 2 strings, PWM ON Duty: 10 %(Pulse width: 0.334 ms), PWM frequency: 300 Hz)
Recommended Parts List 2
(ILED 120 mA, LED white 2 strings, PWM ON Duty: 10 %(Pulse width: 0.334 ms), PWM frequency: 300 Hz)
Parts
No
Parts Name
Value
Unit
Product Maker
IC
Diode
Transistor PNP
Resistor
Capacitor
U1
BD18342FV-M
-
-
ROHM
D1, D2
RFN2LAM6STF
-
-
ROHM
D3
RFN1LAM6STF
-
-
ROHM
ZD1
TND12H-220KB00AAA0
-
-
NIPPON CHEMICON
Q1
2SAR573DFHG
-
-
ROHM
RFB1
LTR10EVHFL2R70
2.7
Ω
ROHM
RFB2
LTR10EVHFL2R70
2.7
Ω
ROHM
RCRT
MCR03EZPFX3601
3.6
kΩ
ROHM
ROPM
MCR03EZPFX3902
39
kΩ
ROHM
RDCIN
ESR10EZPF2001
2
kΩ
ROHM
CVIN1
GCM32ER71H475KA40
4.7
μF
murata
CVIN2
GCM155R71H104KE37
0.1
μF
murata
CVREG
GCM188R71E105KA49
1.0
μF
murata
CCRT
GCM155R71H104KE37
0.1
μF
murata
CD
GCM155R11H103KA40
0.01
μF
murata
CLED
GCM155R71H104KE37
0.1
μF
murata
(Note 1) About ZD1, please place according to test standard of battery line.
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Application Examples - continued
(3) ILED=524 mA, PWM ON Duty=10 %
RFB1
RFB2
PWM_in
VIN
FB
D1
ZD1
CVIN1
CVIN2
EN
BASE
Q1 to Q3
D2
CRT
DC_in
D3
CCRT
OP
RCRT
U1
DISC
RDCIN
SCP
CLED
BD18342FV-M
D
VREG
CD
CVREG
OPM
ROPM
PBUS
GND
Figure 28. Application Example 3
(ILED 524 mA, LED white 2 strings, PWM ON Duty: 10 %(pulse width: 0.334 ms), PWM frequency: 300 Hz)
Recommended Parts List 3
(ILED 524 mA, LED white 2 strings, PWM ON Duty: 10 %(pulse width: 0.334 ms), PWM frequency: 300 Hz)
Parts
No
Parts Name
Value
Unit
Product Maker
IC
Diode
Transistor PNP
Resistor
Capacitor
U1
BD18342FV-M
-
-
ROHM
D1, D2
RFN2LAM6STF
-
-
ROHM
D3
RFN1LAM6STF
-
-
ROHM
ZD1
TND12H-220KB00AAA0
-
-
NIPPON CHEMICON
2SAR573DFHG
-
-
ROHM
Q1 to Q3
RFB1
LTR10EVHFLR620
0.62
Ω
ROHM
RFB2
LTR10EVHFLR620
0.62
Ω
ROHM
RCRT
MCR03EZPFX3601
3.6
kΩ
ROHM
ROPM
MCR03EZPFX3902
39
kΩ
ROHM
RDCIN
ESR10EZPF2001
2
kΩ
ROHM
CVIN1
GCM32ER71H475KA40
4.7
μF
murata
CVIN2
GCM155R71H104KE37
0.1
μF
murata
CVREG
GCM188R71E105KA49
1.0
μF
murata
CCRT
GCM155R71H104KE37
0.1
μF
murata
CD
GCM155R11H103KA40
0.01
μF
murata
CLED
GCM155R71H104KE37
0.1
μF
murata
(Note 1) About ZD1, please place according to test standard of battery line.
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Application Examples - continued
(4) ILED=150 mA, Three Rows Drive, PWM ON Duty=10 %
PWM_in
VIN
FB
D1
ZD1
CVIN1
CVIN2
EN
BASE
RLIM
RFB11
RFB21
RFB3 1
RFB12
RFB22
RFB3 2
R1
Q1
D2
D4
CRT
DC_in
D3
CCRT
RDCIN
D
R3
Q2
D5
Q3
D6
OP
SCP
RCRT
DISC
R2
U1
BD18342FV-M
VREG
CD
CLED1
CLED2
CLED3
CVREG
OPM
ROPM
PBUS
GND
ILED1
ILED2
ILED3
Figure 29. Application Example 4
(ILED1 to ILED 3 150 mA, LED white 2 strings x 3, PWM ON Duty: 10 %( pulse width: 0.334 ms), PWM frequency: 300 Hz)
Refer to Application Note of BD1834xFV-M series for details about the multiple rows drive such as the one above.
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Power Dissipation
Thermal design should meet the following equation.
𝑃𝑑 > 𝑃𝐶
𝑃𝑑 = (1/𝜃𝐽𝐴 ) × (𝑇𝑗𝑚𝑎𝑥 − 𝑇𝑎 )𝑜𝑟(1/𝛹𝐽𝑇 ) × (𝑇𝑗𝑚𝑎𝑥 − 𝑇𝑇 )
𝑃𝐶 = 𝑉𝐼𝑁 × 𝐼𝑉𝐼𝑁2 + 𝑉𝐵𝐴𝑆𝐸 × 𝐼𝐵𝐴𝑆𝐸
where:
𝑃𝑑
is the power dissipation.
𝑃𝐶
is the power consumption.
𝑉𝐼𝑁 is the VIN pin voltage.
𝐼𝑉𝐼𝑁2 is the circuit current at normal mode.
𝑉𝐵𝐴𝑆𝐸 is the BASE pin voltage.
𝐼𝐵𝐴𝑆𝐸 is the BASE pin sink current.
𝜃𝐽𝐴 is the thermal resistance of junction to ambient.
𝛹𝐽𝑇 is the thermal characterization parameter of junction to center case surface.
𝑇𝑗𝑚𝑎𝑥 is the maximum junction temperature(150 °C).
𝑇𝑎
is the ambient temperature.
𝑇𝑇
is the case surface temperature.
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I/O Equivalence Circuits
No.
Pin
Name
I/O Equivalence Circuit
No.
Pin
Name
VIN
(Pin 16 )
1
FB
VREG
(Pin 10 )
1 kΩ (Typ)
FB
(Pin 1 )
5.6 kΩ (Typ)
9
OPM
VIN
(Pin 16 )
BASE
VIN
(Pin 16 )
1 kΩ
(Typ)
BAS E
(Pin 2 )
10
VREG
N.C.
11
OP
370 kΩ
(Typ)
92.5 kΩ
(Typ)
10 kΩ (Typ)
N.C.
VIN
(Pin 16 )
4
VREG
(Pin 10 )
GND
(Pin 6 )
GND
(Pin 6 )
3
10 kΩ (Typ)
OPM
(Pin 9 )
GND
(Pin 6 )
GND
(Pin 6 )
2
I/O Equivalence Circuit
VREG
(Pin 10 )
OP
(Pin 4 )
100 kΩ (Typ)
12
D
D
(Pin 12 )
GND
(Pin 6 )
GND
(Pin 6 )
VIN
(Pin 16 )
VREG
(Pin 10 )
SCP
(Pin 5 )
CRT
(Pin 13 )
100 kΩ (Typ)
100 kΩ (Typ)
5
SCP
100 kΩ (Typ)
13
CRT
GND
(Pin 6 )
GND
(Pin 6 )
6
GND
-
DISC
(Pin 14 )
VREG
(Pin 10 )
14
7
PBUS
PBUS
(Pin 7 )
DISC
10 Ω
(Typ)
100 kΩ (Typ)
GND
(Pin 6 )
GND
(Pin 6 )
8
5 kΩ
(Typ)
5.2 V
(Typ)
EN
(Pin 15 )
150 kΩ
(Typ)
260 kΩ
(Typ)
N.C
15
1 kΩ (Typ)
EN
GND
(Pin 6 )
16
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VIN
1 kΩ (Typ)
5.2 V
(Typ )
1080 kΩ
(Typ)
5.2 V
(Typ)
1333 kΩ
(Typ)
143 kΩ
(Typ)
-
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BD18342FV-M
Operational Notes
1.
Reverse Connection of Power Supply
Connecting the power supply in reverse polarity can damage the IC. Take precautions against reverse polarity when
connecting the power supply, such as mounting an external diode between the power supply and the IC’s power
supply pins.
2.
Power Supply Lines
Design the PCB layout pattern to provide low impedance supply lines. Furthermore, connect a capacitor to ground at
all power supply pins. Consider the effect of temperature and aging on the capacitance value when using electrolytic
capacitors.
3.
Ground Voltage
Ensure that no pins are at a voltage below that of the ground pin at any time, even during transient condition.
4.
Ground Wiring Pattern
When using both small-signal and large-current ground traces, the two ground traces should be routed separately but
connected to a single ground at the reference point of the application board to avoid fluctuations in the small-signal
ground caused by large currents. Also ensure that the ground traces of external components do not cause variations
on the ground voltage. The ground lines must be as short and thick as possible to reduce line impedance.
5.
Recommended Operating Conditions
The function and operation of the IC are guaranteed within the range specified by the recommended operating
conditions. The characteristic values are guaranteed only under the conditions of each item specified by the electrical
characteristics.
6.
Inrush Current
When power is first supplied to the IC, it is possible that the internal logic may be unstable and inrush current may flow
instantaneously due to the internal powering sequence and delays, especially if the IC has more than one power
supply. Therefore, give special consideration to power coupling capacitance, power wiring, width of ground wiring, and
routing of connections.
7.
Testing on Application Boards
When testing the IC on an application board, connecting a capacitor directly to a low-impedance output pin may
subject the IC to stress. Always discharge capacitors completely after each process or step. The IC’s power supply
should always be turned off completely before connecting or removing it from the test setup during the inspection
process. To prevent damage from static discharge, ground the IC during assembly and use similar precautions during
transport and storage.
8.
Inter-pin Short and Mounting Errors
Ensure that the direction and position are correct when mounting the IC on the PCB. Incorrect mounting may result in
damaging the IC. Avoid nearby pins being shorted to each other especially to ground, power supply and output pin.
Inter-pin shorts could be due to many reasons such as metal particles, water droplets (in very humid environment) and
unintentional solder bridge deposited in between pins during assembly to name a few.
9.
Unused Input Pins
Input pins of an IC are often connected to the gate of a MOS transistor. The gate has extremely high impedance and
extremely low capacitance. If left unconnected, the electric field from the outside can easily charge it. The small
charge acquired in this way is enough to produce a significant effect on the conduction through the transistor and
cause unexpected operation of the IC. So unless otherwise specified, unused input pins should be connected to the
power supply or ground line.
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Operational Notes – continued
10. Regarding the Input Pin of the IC
This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them
isolated. P-N junctions are formed at the intersection of the P layers with the N layers of other elements, creating a
parasitic diode or transistor. For example (refer to figure below):
When GND > Pin A and GND > Pin B, the P-N junction operates as a parasitic diode.
When GND > Pin B, the P-N junction operates as a parasitic transistor.
Parasitic diodes inevitably occur in the structure of the IC. The operation of parasitic diodes can result in mutual
interference among circuits, operational faults, or physical damage. Therefore, conditions that cause these diodes to
operate, such as applying a voltage lower than the GND voltage to an input pin (and thus to the P substrate) should be
avoided.
Resistor
Transistor (NPN)
Pin A
Pin B
C
E
Pin A
N
P+
P
N
N
P+
N
Pin B
B
Parasitic
Elements
N
P+
N P
N
P+
B
N
C
E
Parasitic
Elements
P Substrate
P Substrate
GND
GND
Parasitic
Elements
GND
Parasitic
Elements
GND
N Region
close-by
Figure 30. Example of Monolithic IC Structure
11. Ceramic Capacitor
When using a ceramic capacitor, determine a capacitance value considering the change of capacitance with
temperature and the decrease in nominal capacitance due to DC bias and others.
12. Thermal Shutdown Circuit (TSD)
This IC has a built-in thermal shutdown circuit that prevents heat damage to the IC. Normal operation should always
be within the IC’s maximum junction temperature rating. If however the rating is exceeded for a continued period, the
junction temperature (Tj) will rise which will activate the TSD circuit that will turn OFF power output pins. When the Tj
falls below the TSD threshold, the circuits are automatically restored to normal operation.
Note that the TSD circuit operates in a situation that exceeds the absolute maximum ratings and therefore, under no
circumstances, should the TSD circuit be used in a set design or for any purpose other than protecting the IC from
heat damage.
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Ordering Information
B
D
1
8
3
4
Product Name
2
F
V
Package
FV: SSOP-B16
-
ME2
Product Rank
M: for Automotive
Packaging and forming specification
E2: Embossed tape and reel
Marking Diagram
SSOP-B16(TOP VIEW)
Part Number Marking
18342
LOT Number
Pin 1 Mark
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Physical Dimension and Packing Information
Package Name
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SSOP-B16
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Revision History
Date
Revision
18.Sep.2018
001
Changes
New Release
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Notice
Precaution on using ROHM Products
1.
(Note 1)
If you intend to use our Products in devices requiring extremely high reliability (such as medical equipment
,
aircraft/spacecraft, nuclear power controllers, etc.) and whose malfunction or failure may cause loss of human life,
bodily injury or serious damage to property (“Specific Applications”), please consult with the ROHM sales
representative in advance. Unless otherwise agreed in writing by ROHM in advance, ROHM shall not be in any way
responsible or liable for any damages, expenses or losses incurred by you or third parties arising from the use of any
ROHM’s Products for Specific Applications.
(Note1) Medical Equipment Classification of the Specific Applications
JAPAN
USA
EU
CHINA
CLASSⅢ
CLASSⅡb
CLASSⅢ
CLASSⅢ
CLASSⅣ
CLASSⅢ
2.
ROHM designs and manufactures its Products subject to strict quality control system. However, semiconductor
products can fail or malfunction at a certain rate. Please be sure to implement, at your own responsibilities, adequate
safety measures including but not limited to fail-safe design against the physical injury, damage to any property, which
a failure or malfunction of our Products may cause. The following are examples of safety measures:
[a] Installation of protection circuits or other protective devices to improve system safety
[b] Installation of redundant circuits to reduce the impact of single or multiple circuit failure
3.
Our Products are not designed under any special or extraordinary environments or conditions, as exemplified below.
Accordingly, ROHM shall not be in any way responsible or liable for any damages, expenses or losses arising from the
use of any ROHM’s Products under any special or extraordinary environments or conditions. If you intend to use our
Products under any special or extraordinary environments or conditions (as exemplified below), your independent
verification and confirmation of product performance, reliability, etc, prior to use, must be necessary:
[a] Use of our Products in any types of liquid, including water, oils, chemicals, and organic solvents
[b] Use of our Products outdoors or in places where the Products are exposed to direct sunlight or dust
[c] Use of our Products in places where the Products are exposed to sea wind or corrosive gases, including Cl2,
H2S, NH3, SO2, and NO2
[d] Use of our Products in places where the Products are exposed to static electricity or electromagnetic waves
[e] Use of our Products in proximity to heat-producing components, plastic cords, or other flammable items
[f] Sealing or coating our Products with resin or other coating materials
[g] Use of our Products without cleaning residue of flux (even if you use no-clean type fluxes, cleaning residue of
flux is recommended); or Washing our Products by using water or water-soluble cleaning agents for cleaning
residue after soldering
[h] Use of the Products in places subject to dew condensation
4.
The Products are not subject to radiation-proof design.
5.
Please verify and confirm characteristics of the final or mounted products in using the Products.
6.
In particular, if a transient load (a large amount of load applied in a short period of time, such as pulse. is applied,
confirmation of performance characteristics after on-board mounting is strongly recommended. Avoid applying power
exceeding normal rated power; exceeding the power rating under steady-state loading condition may negatively affect
product performance and reliability.
7.
De-rate Power Dissipation depending on ambient temperature. When used in sealed area, confirm that it is the use in
the range that does not exceed the maximum junction temperature.
8.
Confirm that operation temperature is within the specified range described in the product specification.
9.
ROHM shall not be in any way responsible or liable for failure induced under deviant condition from what is defined in
this document.
Precaution for Mounting / Circuit board design
1.
When a highly active halogenous (chlorine, bromine, etc.) flux is used, the residue of flux may negatively affect product
performance and reliability.
2.
In principle, the reflow soldering method must be used on a surface-mount products, the flow soldering method must
be used on a through hole mount products. If the flow soldering method is preferred on a surface-mount products,
please consult with the ROHM representative in advance.
For details, please refer to ROHM Mounting specification
Notice-PAA-E
© 2015 ROHM Co., Ltd. All rights reserved.
Rev.003
Precautions Regarding Application Examples and External Circuits
1.
If change is made to the constant of an external circuit, please allow a sufficient margin considering variations of the
characteristics of the Products and external components, including transient characteristics, as well as static
characteristics.
2.
You agree that application notes, reference designs, and associated data and information contained in this document
are presented only as guidance for Products use. Therefore, in case you use such information, you are solely
responsible for it and you must exercise your own independent verification and judgment in the use of such information
contained in this document. ROHM shall not be in any way responsible or liable for any damages, expenses or losses
incurred by you or third parties arising from the use of such information.
Precaution for Electrostatic
This Product is electrostatic sensitive product, which may be damaged due to electrostatic discharge. Please take proper
caution in your manufacturing process and storage so that voltage exceeding the Products maximum rating will not be
applied to Products. Please take special care under dry condition (e.g. Grounding of human body / equipment / solder iron,
isolation from charged objects, setting of Ionizer, friction prevention and temperature / humidity control).
Precaution for Storage / Transportation
1.
Product performance and soldered connections may deteriorate if the Products are stored in the places where:
[a] the Products are exposed to sea winds or corrosive gases, including Cl2, H2S, NH3, SO2, and NO2
[b] the temperature or humidity exceeds those recommended by ROHM
[c] the Products are exposed to direct sunshine or condensation
[d] the Products are exposed to high Electrostatic
2.
Even under ROHM recommended storage condition, solderability of products out of recommended storage time period
may be degraded. It is strongly recommended to confirm solderability before using Products of which storage time is
exceeding the recommended storage time period.
3.
Store / transport cartons in the correct direction, which is indicated on a carton with a symbol. Otherwise bent leads
may occur due to excessive stress applied when dropping of a carton.
4.
Use Products within the specified time after opening a humidity barrier bag. Baking is required before using Products of
which storage time is exceeding the recommended storage time period.
Precaution for Product Label
A two-dimensional barcode printed on ROHM Products label is for ROHM’s internal use only.
Precaution for Disposition
When disposing Products please dispose them properly using an authorized industry waste company.
Precaution for Foreign Exchange and Foreign Trade act
Since concerned goods might be fallen under listed items of export control prescribed by Foreign exchange and Foreign
trade act, please consult with ROHM in case of export.
Precaution Regarding Intellectual Property Rights
1.
All information and data including but not limited to application example contained in this document is for reference
only. ROHM does not warrant that foregoing information or data will not infringe any intellectual property rights or any
other rights of any third party regarding such information or data.
2.
ROHM shall not have any obligations where the claims, actions or demands arising from the combination of the
Products with other articles such as components, circuits, systems or external equipment (including software).
3.
No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of ROHM or any
third parties with respect to the Products or the information contained in this document. Provided, however, that ROHM
will not assert its intellectual property rights or other rights against you or your customers to the extent necessary to
manufacture or sell products containing the Products, subject to the terms and conditions herein.
Other Precaution
1.
This document may not be reprinted or reproduced, in whole or in part, without prior written consent of ROHM.
2.
The Products may not be disassembled, converted, modified, reproduced or otherwise changed without prior written
consent of ROHM.
3.
In no event shall you use in any way whatsoever the Products and the related technical information contained in the
Products or this document for any military purposes, including but not limited to, the development of mass-destruction
weapons.
4.
The proper names of companies or products described in this document are trademarks or registered trademarks of
ROHM, its affiliated companies or third parties.
Notice-PAA-E
© 2015 ROHM Co., Ltd. All rights reserved.
Rev.003
Datasheet
General Precaution
1. Before you use our Products, you are requested to carefully read this document and fully understand its contents.
ROHM shall not be in any way responsible or liable for failure, malfunction or accident arising from the use of any
ROHM’s Products against warning, caution or note contained in this document.
2. All information contained in this document is current as of the issuing date and subject to change without any prior
notice. Before purchasing or using ROHM’s Products, please confirm the latest information with a ROHM sales
representative.
3.
The information contained in this document is provided on an “as is” basis and ROHM does not warrant that all
information contained in this document is accurate and/or error-free. ROHM shall not be in any way responsible or
liable for an y damages, expenses or losses incurred b y you or third parties resulting from inaccuracy or errors of or
concerning such information.
Notice – WE
© 2015 ROHM Co., Ltd. All rights reserved.
Rev.001
