Datasheet
Matrix LED Driver
Automotive Dynamic Indicator Lamps
8ch Matrix LED Controller
BD18362EFV-M
General Description
Key Specifications
Features
Package
BD18362EFV-M is an 8-channel matrix LED controller
with an internal FET switch. Switching the FET on and off
allows a control of the sequential lighting.
An internal charge pump serves as a power supply for
the gate driver. Since sequential lighting pattern is built in,
the microcontroller is unnecessary.
AEC-Q100 Qualified(Note 1)
8-channel Matrix Switch
Up to 2LED’s per Switch Control
Built in Sequential Lighting pattern
Sequential Lighting Phase Time Setting
Sequential Lighting Start-up Delay Time Setting
All-light-up (Hazard Mode)
LED Open Protection
LED Short Detection
Thermal shutdown
Input Voltage Range:
5.5V to 60V
Maximum Total LED’s Voltage:
48V(Max)
Maximum SW Bypass Current
1.0A(Max)
Internal FET Switch ON Resistance: 230mΩ(Typ)
Operating Temperature Range:
-40°C to +125°C
W(Typ) x D(Typ) x H(Max)
9.70mm x 6.40mm x 1.00mm
HTSSOP-B28
(Note 1) Grade1
Applications
Automotive Exterior Lamps
(Dynamic Indicator)
HTSSOP-B28
Typical Application Circuit
ILED
CVCC1
CVCC2
RHAZ
CVREG
CSETDLY
CSETCLK
VCC
CFP
CNT
CFM
HAZ
VREG
CP
SETDLY
CH8
SETCLK
CH7
SET
CH6
R SET
R CMPLT
R FLAG
R SG
CH5
SEL1
CH4
SEL2
CH3
SEL3
CH2
CMPLT
CH1
FLAG
CH0
SG
ILED
CCF
CVCC1
R HAZ
CCP
CVREG
LED7
CSETDLY
CSETCLK
LED6
LED5
VCC
CFP
CNT
CFM
CP
HAZ
VREG
CH8
SETDLY
CH7
SETCLK
CH6
SET
CH5
R SET
LED4
LED3
LED2
LED1
RCMPLT
RFLAG
LED0
RSG
GND
〇Product structure: Silicon monolithic integrated circuit
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CVCC2
SEL1
CH4
SEL2
CH3
SEL3
CH2
CMPLT
CH1
FLAG
SG
GND
CH0
CCF
CCP
LED7b
LED7a
LED6b
LED6a
LED5b
LED5a
LED4b
LED4a
LED3b
LED3a
LED2b
LED2a
LED1b
LED1a
LED0b
LED0a
〇This product has no designed protection against radioactive rays
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Datasheet
General Precaution
1. Before you use our Products, you are requested to carefully read this document and fully understand its contents.
ROHM shall not be in any way responsible or liable for failure, malfunction or accident arising from the use of any
ROHM’s Products against warning, caution or note contained in this document.
2. All information contained in this document is current as of the issuing date and subject to change without any prior
notice. Before purchasing or using ROHM’s Products, please confirm the latest information with a ROHM sales
representative.
3.
The information contained in this document is provided on an “as is” basis and ROHM does not warrant that all
information contained in this document is accurate and/or error-free. ROHM shall not be in any way responsible or
liable for an y damages, expenses or losses incurred b y you or third parties resulting from inaccuracy or errors of or
concerning such information.
Notice – WE
© 2015 ROHM Co., Ltd. All rights reserved.
Rev.001
BD18362EFV-M
Pin Configuration
HTSSOP-B28
(TOP VIEW)
VCC
1
28
CFM
CNT
2
27
CFP
HAZ
3
26
CP
TEST
4
25
CH8
VREG
5
24
CH7
SEL1
6
23
CH6
SEL2
7
22
CH5
SEL3
8
21
CH4
SETCLK
9
20
CH3
SETDLY
10
19
CH2
SET
11
18
CH1
CMPLT
12
17
CH0
SG
13
16
TEST
FLAG
14
15
GND
Thermal PAD
Pin Description
PIN
No.
Symbol
PIN
No.
Symbol
1
VCC
Input power supply
15
GND
GND
2
CNT
Control input
16
TEST
TEST input (Note 1)
3
HAZ
Hazard mode switching input
17
CH0
LED0 cathode connection
4
TEST
TEST input (Note 1)
18
CH1
LED0 anode & LED1 cathode connection
5
VREG
Internal reference voltage output
19
CH2
LED1 anode & LED2 cathode connection
6
SEL1
Setting of the switch in use 1
20
CH3
LED2 anode & LED3 cathode connection
7
SEL2
Setting of the switch in use 2
21
CH4
LED3 anode & LED4 cathode connection
8
SEL3
Setting of the switch in use 3
22
CH5
LED4 anode & LED5 cathode connection
9
SETCLK
Sequential lighting phase time setting
23
CH6
LED5 anode & LED6 cathode connection
10
SETDLY
24
CH7
LED6 anode & LED7 cathode connection
11
SET
25
CH8
LED7 anode connection
12
CMPLT
Lighting complete signal output
26
CP
13
SG
Status good output
27
CFP
Connecting capacitor for charge pump +
14
FLAG
Error flag output
28
CFM
Connecting capacitor for charge pump -
Function
Sequential lighting start-up delay time
setting
Sequential lighting phase time/
start-up delay time setting
Function
Charge pump output for internal switch
(Note 1) Connect to GND
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BD18362EFV-M
Block Diagram
VCC
VREG
VREG
CFP
TSD
Internal
Regulator
CFM
TSD
Charge Pump
CP
VREG
UVLO
UVLO
UVLO
VREG
SETDLY
VCP
TSD
VREG
SETDLY
CH8
VREG
Local power
supply
VREG
SW7
Level
Shift
Internal
Oscillator
LED
Open/short det
CH7
VCP
SETCLK
SET
Local power
supply
VREG
WDTDLY
VREG
SW6
Level
Shift
SETCLK
LED
Open/short det
CH6
WDTCLK
CNT
VREG
CNT
HAZ
・
・
・
VREG
LOGIC
CH2
HAZ
VCP
SEL1
Local power
supply
VREG
VREG
SW1
Level
Shift
SEL2
SEL
CH1
SEL3
FLAG
LED
Open/short det
VCP
Local power
supply
VREG
VREG
SW0
DIAG Output
Level
Shift
FLAG
CMPLT
LED
Open/short det
CH0
CMPLT
SG
SG
TEST
TEST
GND
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BD18362EFV-M
Description of Blocks
1. Total Function
The BD18362EFV-M is a matrix LED controller able to implement a sequential lighting (Dynamic Indicator) of LEDs
without the need for a microcontroller.
An LSI meant for driving LEDs with eight switches connected in a series and is used in conjunction with an LED driver.
The switches are connected to the anodes and cathodes of the LED. When the switch is OFF, a current flow through the
LED and the LED is light. When the switch is ON, the current is bypassed and the LED is unlighted.
When the CNT pin is given a high input, the switches are turned OFF sequentially from SW0 after the sequential lighting
start-up delay time (tDLY) and the LEDs are lighting sequentially from LED0.
The tDLY can be set by means of a capacitor connected to the SETDLY pin and a resistor connected to the SET pin.
The sequential lighting phase time (tPS1), in which the switch is turned from the ON to the OFF position, can be set by
means of a capacitor connected to the SETCLK pin and a resistor connected to the SET pin.
When the CNT pin is given a low input, the LEDs are turned to the all-OFF position. However, the switches are turned ON
sequentially from SW7 (LEDs are unlighted sequentially) at a fixed time (tPSL). This avoids sudden output voltage
fluctuations.
Additionally, the BD18362EFV-M is built in hazard mode function. When the HAZ pin is given a high input at the lighting
condition, the LEDs are turned from the all-OFF to the all-ON position. However, the switches are turned OFF sequentially
from SW0 (LEDs are light sequentially) at a fixed time (tPSH). This avoids sudden output voltage fluctuations.
Although there are 8 switches to the BD18362EFV-M, it is also possible to use it with 7 switches or less. The number of
used switches can be set by pulling up the SEL1 pin, the SEL2 pin and the SEL3 pin to the VREG pin or by pulling down
to GND.
Also, it is possible to use two BD18362EFV-M if more than 9 switches are employed. A sequential lighting of more than 9
switches is possible by connecting the CMPLT pin and the CNT pin so the phase shift of the second BD18362EFV-M will
start after the phase shift of the first BD18362EFV-M has been completed.
The BD18362EFV-M is built in a diagnostic function for LED open and LED short on each switch. If the LED open
diagnosis detects an open during the period when the LED is light (the switch is OFF), the immediately corresponding
switch is turned ON and the current is bypassed. Additionally, the FLAG pin will have a low output in order to report the
LED open. In the same way, the LED short diagnosis detects a short during the period when the LED is light (the switch is
OFF). The FLAG pin will have a low output in order to report the LED short.
BD18362EFV-M built in an internal watchdog timer.
●Watchdog timer for sequential lighting start-up delay time
If the capacitor connected to the SETDLY pin has a short, the LED will be unlighted, since the sequential lighting start-up
delay time cannot be set. When tWDTDLY has passed, there is a time-out and the FLAG pin will have a low output. Also,
the LEDs are automatically all light. As in the hazard mode, the switches are turned OFF sequentially at fixed time.
●Watchdog timer for sequential lighting phase time
If the capacitor connected to the SETCLK pin has a short, the LED will be unlighted, since the phase shift time tPS1
cannot be set. When tWDTCLK has passed, there is a time-out and the FLAG pin will have a low output. Also, the LEDs are
automatically all light. As in the hazard mode, the switches are turned OFF sequentially at fixed time.
The BD18362EFV-M is built in charge pump serving as a power supply for the switch gate drive. All switches and gate
drive circuits form a floating circuit and operate under the voltage generated by the charge pump circuit.
The BD18362EFV-M has high voltage switches and each of switches can connect with up to 2 LEDs in series. Achieve
the 16 LEDs solution by 8-channels with 2LEDs in each of switches.
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BD18362EFV-M
Description of Blocks – continued
2. SG [Status Good]
After the VCC is supplied, the switches may happen to be OFF until the internal circuit comes to a stable condition.
In this condition, the LED might flicker when the LED current is supplied.
The BD18362EFV-M can report by the SG pin for internal condition as ready to switch in stable. In order to prevent a
flickering, it is recommended to provide an LED current after the SG pin switches from a low to Hiz.
If the VCC pin voltage rises above the UVLO release voltage (VUVR) and the SG delay time (tdSG) has passed, the SG pin
will switch from a low to Hiz.
During UVLO detection or thermal shutdown detection, the SG pin will switch to a low. If the SG delay time (tdSG) has
passed after a UVLO release and thermal shutdown release, the SG pin will switch from a low to Hiz.
(refer to Figure19 (b))
The SG pin is open drain and needed pulled up resistor for monitoring output signal.
VUVR
VCC
SETDLY
LED0
LED0 OFF
LED0 ON
tdSG
SG
L
HiZ
SWn
ALL ON
Phase Shift
ILED
Figure 1. Timing Chart
(Status Good Function)
To avoid the LED flicker, it is recommended to connect the SG pin and the current source LED drivers control pin (e.g.
enable pin and PWM pin). Pull up the SG pin to the VREG pin (BD18362EFV-M) with resister, connect the SG pin and the
current source LED drivers control pin. Design with sufficient consideration of the threshold voltage input, inside
impedance, pull up resister value and VREG voltage value.
control pin
Current Source
LED Driver
VREG
SG
BD18362EFV-M
Figure 2. Application of Connecting with the SG Pin to the current source LED Driver
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BD18362EFV-M
Description of Blocks – continued
3. SETDLY [Sequential Lighting Start-up Delay Time Setting]
The delay time until the switch is turned OFF must be set in order not to have a planned sequential operation where
BD18362EFV-M turns the switches OFF before the current supply to the LED (e.g. LED driver) operates. The setting can
be done the capacitor connected to the SETDLY pin (CSETDLY) and the resistor connected to the SET pin (RSET).
The charging of the capacitor connected to the SETDLY pin starts when the SG pin change from low to Hiz and the CNT
pin voltage has risen above the VCNTH voltage. SW0 turn OFF (LED0 turn ON) after the setting time (tDLY).
Sequential Lighting Start-up Delay Time
𝑡𝐷𝐿𝑌 = 𝐾𝐷𝐿𝑌 × 𝑅𝑆𝐸𝑇 × 𝐶𝑆𝐸𝑇𝐷𝐿𝑌
[s]
When the Sequential lighting start-up delay time is passed, the SETDLY pin is discharged.
A recharge is possible under the following 3 conditions: (1) or (2) or (3)
(1) UVLO detection → UVLO release → Status good delay time passed → Recharge
(2) Thermal shutdown detection → Thermal shutdown release → Status good delay time passed → Recharge
(3) Input VCNT ≤ VCNTH-VCNTHYS → Input VCNT≥VCNTH → Recharge
VUVR
VCC
CNT
VCNTH
SG
SETDLY
tDLY
LED0
LED0 OFF
LED0 ON
FLAG
(a) Start-up
VCC
VCC
VUVD
CNT
VCNTH
VCNTH-VCNTHYS
VUVR
CNT
tdSG
SG
SG
SETDLY
SETDLY
t DLY
LED
LED OFF
t DLY
phase shift
LED OFF
t DLY
phase shift
FLAG
LED
LED OFF
tDLY
LED OFF
phase shift
phase shift
FLAG
(b) CNT control
(c) Re-start
Figure 3. Timing Chart
(Sequential Lighting Start-up Delay Time)
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BD18362EFV-M
Description of Blocks – continued
4. SETCLK [Sequential Lighting Phase Time Setting]
Through the BD18362EFV-M it is possible to change the sequential lighting phase time.
The sequential lighting phase time (tPS1) is determined by the clock period (tCLK), which is set by the capacitor connected
to the SETCLK pin (CSETCLK) and the resistor connected to the SET pin (RSET).
Clock Period
𝑡𝐶𝐿𝐾 =
𝐾𝑃𝑆 ×𝑅𝑆𝐸𝑇 ×𝐶𝑆𝐸𝑇𝐶𝐿𝐾
256
[s]
Sequential Lighting Phase Time
𝑡𝑃𝑆1 = 𝐾𝑃𝑆 × 𝑅𝑆𝐸𝑇 × 𝐶𝑆𝐸𝑇𝐶𝐿𝐾
[s]
CMPLT
tPS1
LED7
LED OFF
LED ON
tPS1
LED6
・・・
LED ON
t PS1
LED1
LED OFF
LED ON
tPS1
LED0
LED OFF
LED ON
Figure 4. Timing Chart
(Sequential Lighting Phase Shift HAZ=L)
SET
RSET
Current
Setting
SETCLK
CSETCLK
OFF/ON
Oscillator
ON/OFF
CLK
Phase Shift
SETCLK
t CLK
CLK
Figure 5. CLK Generation Circuit for Sequential Lighting Phase Shift
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BD18362EFV-M
Description of Blocks – continued
5. HAZ [Hazard Mode Switching Input]
The BD18362EFV-M is built in hazard mode function. If the HAZ pin is given a high input (≥VHAZH), the LEDs are turned
from the all-OFF to the all-ON position after sequential lighting start-up delay (tDLY) passed. However, the switches are
turned OFF sequentially (LEDs are light sequentially) at a fixed time (tPSH), this avoids sudden output voltage fluctuations.
CMPLT
LED OFF
LED ON
LED6
LED OFF
LED ON
LED1
LED OFF
LED ON
LED0
LED OFF
LED ON
・・・
LED7
CMPLT
LED7
tPSH
LED6
・・・
LED ON
tPSH
LED1
LED OFF
LED ON
tPSH
LED0
LED OFF
LED ON
Figure 6. Timing Chart
(Hazard mode HAZ=H)
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BD18362EFV-M
Description of Blocks – continued
6. SEL [Setting pin for switches in use]
The BD18362EFV-M has 8 switches. Therefore, in cases where only 7 or less switches are used, please short-circuit the
board with the pins that are not used. The protective function must be disabled for those switches that are not being used,
so that the short detection will not run.
The switches in use determine if the SEL1pin, the SEL2 pin and the SEL3 pin are setting high input (≥VSELH) or low input
(≤VSELL).
Protective Function
Invalidity Switches
7
6, 7
5, 6, 7
4, 5, 6, 7
3, 4, 5, 6, 7
2, 3, 4, 5, 6, 7
1, 2, 3, 4, 5, 6, 7
Switches in use
0, 1, 2, 3, 4, 5, 6, 7
0, 1, 2, 3, 4, 5, 6
0, 1, 2, 3, 4, 5
0, 1, 2, 3, 4
0, 1, 2, 3
0, 1, 2
0, 1
0
SEL1
SEL2
SEL3
low
high
low
high
low
high
low
high
low
low
high
high
low
low
high
high
low
low
low
low
high
high
high
high
The setting will not be changed even if the SEL pin voltage switches temporarily during the sequential lighting phase shift
operation.
The settings are changed at a restart. A restart is possible under the following 3 conditions: (1) or (2) or (3)
(1) UVLO detection → UVLO release → Status good delay time passed → Set SEL condition
(2) Thermal shutdown detection → Thermal shutdown release → Status good delay time passed → Set SEL condition
(3) Input VCNT ≤ VCNTH-VCNTHYS → Input VCNT≥VCNTH → Set SEL condition
CP
CH8
SW7
CH7
SW6
CH6
SW5
CH5
SEL1
SW4
CH4
SEL2
SW3
SEL3
CH3
SW2
CH2
SW1
CH1
SW0
CH0
Figure 7. A Circuit for Setting SEL (for using 6 Switches)
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BD18362EFV-M
Description of Blocks – continued
7. CMPLT [Lighting Complete Signal Output]
When the sequential lighting is complete, the CMPLT pin changes from a low to Hiz.
The BD18362EFV-M has 8 switches. Therefore, in cases where 9 or more switches are used for sequential lighting, a
second BD18362EFV-M comes into use. When the lighting of LED by an IC (A) is complete, the CMPLT pin of an IC (A)
will give a Hiz output. By connecting the CMPLT pin of an IC (A) and the CNT pin of an IC (B), the LED lighting of an IC (B)
will start after the LED lighting of an IC (A) is complete.
Also, the “lighting complete” timing is changed according to the used switches set by the SEL1 pin, the SEL2 pin and the
SEL3 pin.
If the 6 and 7 switches are invalidated, the CMPLT pin will have a Hiz output at the time when the start-up of switch 5 is
completed.
The CMPLT pin will change Hiz to low under following conditions. (1) or (2) or (3) (refer to Figure19 (c))
(1) UVLO detection → CMPLT=L
(2) Thermal shutdown detection → CMPLT=L
(3) Input VCNT ≤ VCNTH-VCNTHYS → CMPLT=L
The CMPLT pin is open drain and needed pulled up resistor for monitoring output signal.
ILED
VCC
VCC
CNT
CNT
HAZ
HAZ
VREG
CP
SETDLY
CH8
SETDLY
CH8
SETCLK
CH7
SETCLK
CH7
SET
CH6
SEL1
CH4
CH3
SEL3
CH2
LED3
LED2
LED1
SEL1
CH4
SEL2
CH3
SEL3
CH2
CH1
LED0
CH0
CMPLT
CH5
LED4
CH1
CH6
SET
LED5
CH5
SEL2
CP
VREG
CH0
GND
CMPLT
IC (A)
LED5
LED4
LED3
LED2
LED1
LED0
GND
IC (B)
Figure 8. Application Example
(for using 12 Switches)
LED5
LED ON
・
・
・
IC (B)
t PS1
LED1
LED ON
tPS1
LED0
LED ON
CMPLT
IC (A)
t PS1
LED5
LED ON
・
・
・
tPS1
LED1
LED ON
tPS1
LED0
LED OFF
LED ON
Figure 9. Timing Chart
(for using 12 Switches)
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BD18362EFV-M
Description of Blocks – continued
CMPLT
tPS1
LED7
tPS1
LED6
LED OFF
LED ON
・・・
LED ON
tPS1
LED1
LED OFF
LED ON
tPS1
LED0
LED OFF
LED ON
Figure 10. Timing Chart
(CMPLT output function SEL1=L, SEL2=L, SEL3=L)
CMPLT
LED7
LED6
tPS1
LED5
・・・
LED ON
tPS1
LED1
LED OFF
LED ON
tPS1
LED0
LED OFF
LED ON
Figure 11. Timing Chart
(CMPLT output function SEL1=L, SEL2=H, SEL3=L)
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BD18362EFV-M
Description of Blocks – continued
8. CNT [Lighting On/Off Control]
It is possible to control the switches through the CNT pin.
If the CNT pin is given a high input (≥VCNTH), the switches will be turned OFF sequentially and the LEDs are light
sequentially after the sequential lighting start-up delay time tDLY.
If the CNT pin is given a low input (≤VCNTH-VCNTHYS), the switches will be turned ON sequentially and the LEDs are
unlighted sequentially. Also, the CMPLT pin will have a low output.
The switches are turned ON sequentially (LEDs are unlighted sequentially) at a fixed time (tPSL), this avoids sudden output
voltage fluctuations.
.
VCNTH
CNT
VCNTH-VCNTHYS
SETDLY
CMPLT
tPS1
LED7 LED OFF
LED ON
tPS1
LED6 LED OFF
t PSL
・・・
LED ON
LED1 LED OFF
LED ON
tPS1
LED0 LED OFF
tPSL
LED ON
Figure 12. Timing Chart
(The CNT Pin Function)
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BD18362EFV-M
Description of Blocks – continued
9. LED Short Detection
The BD18362EFV-M is built in LED short detection.
While switch is turned OFF, the voltage between CHn-CHn-1 is monitored. If the voltage between CHn-CHn-1 falls below
the LED short detection voltage (VLS), an LED short is detected. The FLAG pin will change to low. When SWn-1 turn OFF,
the short detection function will be disable in the time (t LS).
𝑡𝐿𝑆
= 𝑡𝑃𝑆1 × 0.5 (𝑇𝑦𝑝)
𝑡𝐿𝑆𝐻 = 𝑡𝑃𝑆𝐻 × 0.5 (𝑇𝑦𝑝)
when VHAZ=L(≤VHAZH -VHAZHYS)
when VHAZ=H(≥VHAZH)
The FLAG pin will change low to Hiz under following conditions. (1) or (2) or (3) (refer to Figure19 (a))
(1) UVLO detection → UVLO release → Status good delay time passed → FLAG=Hiz
(2) Thermal shutdown detection → Thermal shutdown release → FLAG=Hiz
(3) Input VCNT ≤ VCNTH-VCNTHYS → FLAG=Hiz
The LED short detection function is invalid with regard to the unused switches set by the SEL pin.
CHn+1
VLS
VCHn_CHn-1
SWn
CHn
tLS
SWn-1
FLAG
CHn-1
(a) Normal Operation
VLS
CHn+1
VCHn_CHn-1
SWn
tLS
FLAG
CHn
SWn-1
CHn-1
(b) LED Short Operation
Figure 13. Functionality of LED Short Detection
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BD18362EFV-M
Description of Blocks – continued
10. LED Open Protection
The BD18362EFV-M is built in LED open protection.
While switch is turned OFF, the voltage between CHn-CHn-1 is monitored. If the voltage between CHn-CHn-1 is detected
to be the LED open protection voltage (VLO) during the monitoring, SWn-1 will be turned ON immediately and this will
prevent a destruction of the switch. When the tLO time has passed after SWn-1 turned OFF, the FLAG pin will change to
low. The other switches keep lighting phase shift after detecting LED open.
𝑡𝐿𝑂
= 𝑡𝑃𝑆1 × 0.5 (𝑇𝑦𝑝)
𝑡𝐿𝑂𝐻 = 𝑡𝑃𝑆𝐻 × 0.5 (𝑇𝑦𝑝)
when VHAZ=L(≤VHAZH -VHAZHYS)
when VHAZ=H(≥VHAZH)
The FLAG pin will change low to Hiz under following conditions. (1) or (2) or (3) (refer to Figure 19)
(1) UVLO detection → UVLO release → FLAG=Hiz
(2) Thermal shutdown detection → Thermal shutdown release → FLAG=Hiz
(3) Input VCNT ≤ VCNTH-VCNTHYS → FLAG=Hiz
The LED open protection function is invalid with regard to the unused switches set by the SEL pin.
I LED
I LED
CHn+1
OFF
CHn+1
SWn
OFF
SWn
CHn
CHn
SWn-1
SWn-1
OFF
ON
CHn-1
(a) LED Open (SW=OFF)
CHn-1
(b) LED Open (SW=ON)
VLO
VCHn_CHn-1
tLO
FLAG
(c) LED Open (Timing chart)
Figure 14. Functionality of LED Open Protection
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BD18362EFV-M
Description of Blocks – continued
CP
VCC
ILED
LED7
ON
LED6
ON
CH8
LED5
ON
CH7
LED4
ON
CH6
LED3
ON
CH5
LED2
ON
LED1
ON
CH8
CH4
LED0
ON
CH3
CH2
CMPLT
CH1
LED7
LED6
LED5
LED4
LED3
LED2
LED1
LED0
CH0
FLAG
(a) Normal Operation
CP
VCC
LED7
ON
LED6
ON
CH7
LED5
ON
LED SHORT
DETECTION
CH6
LED4
ON
CH5
LED3
ON
LED1
ON
CH8
CH8
CH4
LED0
ON
CH3
CH2
CMPLT
CH1
ILED
LED7
LED6
LED5
LED4
LED3
LED2
LED1
LED0
CH0
FLAG
(b) LED Short Detection (e.g. LED2 Short Mode)
VCC
CP
ILED
LED7
ON
LED6
ON
CH8
LED5
ON
LED OPEN
PROTECTION
CH7
LED4
ON
CH6
LED3
ON
CH5
LED1
ON
CH8
CH4
LED0
ON
CH3
CMPLT
CH2
CH1
LED7
LED6
LED5
LED4
LED3
LED2
LED1
LED0
CH0
FLAG
(c) LED Open Protection (e.g. LED2 Open Mode)
Figure 15. Timing Chart
(LED Short/LED Open)
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Description of Blocks – continued
11. WDTDLY [Watchdog Timer for SETDLY]
The BD18362EFV-M monitors the tDLY (sequential lighting start-up delay time). Since the tDLY cannot be set if the
capacitor connected to the SETDLY pin has a short, the LEDs will come unlighted.
The WDTDLY starts monitoring when the SG pin output has a Hiz and the CNT pin is given a high input (≥VCNTH).
If the tDLY is not detected within tWDTDLY, there will be a time-out and the FLAG pin changes to low.
When there is a time-out, the LEDs will all-light automatically. However, the switches are turned OFF sequentially (LEDs
are light sequentially) at a fixed time (tPSH).
The FLAG pin will change low to Hiz under following conditions. (1) or (2) or (3) (refer to Figure 19 (a))
(1) UVLO detection → UVLO release → FLAG=Hiz
(2) Thermal shutdown detection → Thermal shutdown release → FLAG=Hiz
(3) Input VCNT ≤ VCNTH-VCNTHYS → FLAG=Hiz
VUVR
VCC
CNT
VCNTH
SG
SETDLY
CMPLT
LED7 OFF
LED7 ON
LED6
LED6 OFF
LED6 ON
LED1 OFF
LED1 ON
・・・
LED7
LED1
SETDLY
CSETDLY
LED0
LED0 OFF
LED0 ON
FLAG
tWDTDLY
Figure 16. Timing Chart
(The SETDLY short to GND)
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BD18362EFV-M
Description of Blocks – continued
12. WDTCLK [Watchdog Timer for SETCLK]
The BD18362EFV-M monitors the sequential lighting phase time. Since the tCLK cannot be set if the capacitor connected to
the SETCLK pin has a short, the LEDs will come unlighted.
The WDTCLK starts monitoring when the SG pin change from low to Hiz and the CNT pin is given a high input (≥VCNTH).
If the clock period (tCLK) is not detected within tWDTCLK, there will be a time-out and the FLAG pin changes to low.
When there is a time-out, the LEDs will all-light automatically. However, the switches are turned OFF sequentially (LEDs
are light sequentially) at a fixed time (tPSH).
The FLAG pin will change low to Hiz under following conditions. (1) or (2) or (3) (refer to Figure 19)
(1) UVLO detection → UVLO release → FLAG = Hiz
(2) Thermal shutdown detection → Thermal shutdown release → FLAG = Hiz
(3) Input VCNT ≤ VCNTH-VCNTHYS → FLAG = Hiz
VUVR
VCC
CNT
VCNTH
SG
SETDLY
SETCLK
CMPLT
LED7 OFF
LED7 ON
LED6
LED6 OFF
LED6 ON
LED1 OFF
LED1 ON
・・・
LED7
LED1
SETCLK
CSETCLK
LED0
LED0 OFF
LED0 ON
FLAG
tWDTCLK
Figure 17. Timing Chart
(The SETCLK Short to GND)
SETCLK
t CLK
CMPLT
LED7 OFF
LED7 ON
LED6
LED6 OFF
LED6 ON
LED1 OFF
LED1 ON
・・・
LED7
LED1
LED0
LED0 ON
FLAG
tWDTCLK
Figure 18. Timing Chart
(The CLK in Abnormal)
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BD18362EFV-M
Description of Blocks – continued
13. Monitor Function
BD18362EFV-M has pins (SG, FLAG and CMPLT) for monitoring condition. These pins are open drain and needed pull
up resistor for monitoring condition.
LED SHORT detection
SET
LED OPEN detection
RESET
WDTDLY detction
SET
WDTCLK detction
FLAG
RESET
VCNT ≤ VCNTH - V CNTHYS
TSD detction
UVLO detction
(a) The FLAG Pin Equivalence Circuit
SG
TIMER
TSD detction
UVLO detction
(b) The SG Pin Equivalence Circuit
Lighting Complet
CMPLT
VCNT ≤ VCNTH - V CNTHYS
TSD detction
UVLO detction
(c) The CMPLT Pin Equivalence Circuit
Figure 19. Monitor Pin Equivalence Circuits
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BD18362EFV-M
Absolute Maximum Ratings (Ta=25°C)
Parameter
Symbol
Rating
Unit
VCC
-0.3 to +70
V
VCNT, VHAZ
-0.3 to +70
V
VREG
-0.3 to +7 ≤ VCC
V
SETDLY, SETCLK Voltage
VSETDLY, VSETCLK
-0.3 to VREG+0.3 ≤ +7
V
SEL1, SEL2, SEL3 Voltage
VSEL1, VSEL2, VSEL3
-0.3 to VREG+0.3 ≤ +7
V
CMPLT, SG, FLAG Voltage
VCMPLT, VSG, VFLAG
-0.3 to +7
V
VCP
-0.3 to +67
V
CP to CH8 Voltage
VVCP_CH8
-0.3 to +7
V
CFP to CFM Voltage
VCFP_CFM
-0.3 to +7
V
VCHn
-0.3 to +60
V
VCHn_CHn-1
-0.3 to +20
V
Maximum SWn Bypass Current(Note 2)
ISWn
1.0
A
Storage Temperature Range
Tstg
-55 to +150
°C
Tjmax
150
°C
Power Supply Voltage (VCC)
CNT, HAZ Voltage
VREG Voltage
CP Voltage
CHn Voltage(Note 1)
CHn to CHn-1 Voltage(Note 1)
Maximum Junction Temperature
Caution 1: Operating the IC over the absolute maximum ratings may damage the IC. The damage can either be a short circuit between pins or an open circuit
between pins and the internal circuitry. Therefore, it is important to consider circuit protection measures, such as adding a fuse, in case the IC is
operated over the absolute maximum ratings.
Caution 2: Should by any chance the maximum junction temperature rating be exceeded the rise in temperature of the chip may result in deterioration of the
properties of the chip. In case of exceeding this absolute maximum rating, increase the board size and copper area to prevent exceeding the
maximum junction temperature rating.
(Note 1)
CHn: n=0 to 8
(Note 2)
SWn: n=0 to 7
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BD18362EFV-M
Thermal Resistance(Note 1)
Parameter
Symbol
Thermal Resistance (Typ)
Unit
1s(Note 3)
2s2p(Note 4)
θJA
107.0
25.1
°C/W
ΨJT
6
3
°C/W
HTSSOP-B28
Junction to Ambient
Junction to Top Characterization
Parameter(Note 2)
(Note 1) Based on JESD51-2A(Still-Air)
(Note 2) The thermal characterization parameter to report the difference between junction temperature and the temperature at the top center of the outside
surface of the component package.
(Note 3) Using a PCB board based on JESD51-3.
Layer Number of
Measurement Board
Single
Material
Board Size
FR-4
114.3mm x 76.2mm x 1.57mmt
Top
Copper Pattern
Thickness
Footprints and Traces
70μm
(Note 4)Using a PCB board based on JESD51-5, 7.
Layer Number of
Measurement Board
4 Layers
Material
Board Size
FR-4
114.3mm x 76.2mm x 1.6mmt
Top
Thermal Via(Note 5)
Pitch
Diameter
1.20mm
Φ0.30mm
2 Internal Layers
Bottom
Copper Pattern
Thickness
Copper Pattern
Thickness
Copper Pattern
Thickness
Footprints and Traces
70μm
74.2mm x 74.2mm
35μm
74.2mm x 74.2mm
70μm
(Note 5) This thermal via connects with the copper pattern of all layers.
Recommended Operating Conditions
Parameter
Symbol
Min
Typ
Max
Unit
Supply Input Voltage(Note 6) (Note 7)
VCC
5.5
13
60
V
Operating Temperature
Topr
-40
+25
+125
°C
Maximum Total LED Voltage
VLED
-
-
48
V
VCHn_CHn-1
1.2
-
9
V
tPS1
5
-
100
ms
tDLY
-
-
225
ms
CHn to CHn-1 LED Input Range
Sequential Lighting Phase Time Setting
Range
Sequential Lighting Start-up Delay Time
Setting Range
(Note 6) Supply input voltage range can be considered based on power dissipation.
(Note 7) At start-up time, please apply a voltage above 6.0V once. The value is the voltage range after the temporary rise to 6.0V.
Recommended Setting Parts Range
Parameter
Capacitor Connecting to the VREG Pin
Capacitor for Charge Pump
Resistor for
Sequential Lighting Phase Time/
Sequential Lighting Start-up Delay Time
Capacitor for Sequential Lighting
Start-up Delay Time
Capacitor for Sequential Lighting Phase
Time
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TSZ22111 • 15 • 001
Symbol
Min
Typ
Max
Unit
CVREG
1.0
2.2
4.7
μF
CCP, CCF
0.001
0.047
0.22
μF
RSET
6
-
40
kΩ
CSETDLY
-
-
10
μF
CSETCLK
0.001
-
0.047
μF
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BD18362EFV-M
Electrical Characteristics (Unless otherwise specified: VCC=13V Ta=-40°C to +125°C)
Parameter
Symbol
Limit
Min
Typ
Max
Unit
Conditions
[Total]
VCNT=0V, VCH0=0V
RSET=22kΩ, CSETCLK=0.01μF
VCC Input Current
IVCC
-
3.8
7.0
mA
UVLO Detection Voltage
VUVD
4.7
5.1
5.5
V
VCC: Sweep down
UVLO Release Voltage
VUVR
4.95
5.40
5.85
V
VCC: Sweep up
UVLO Hysteresis Voltage
VHYS
-
0.3
-
V
VREG
4.5
5.0
5.5
V
CVREG=2.2μF
IVREG=0mA to 2mA
Charge Pump Output Voltage
VCP
-
-
7
V
VCP-VCH8
Differential Voltage of Flying
Capacitor
VCF
-
-
7
V
VCFP-VCFM
Coefficient for
Sequential Lighting Phase Time
KPS
278
320
368
-
tPS1=KPS x RSET x CSETCLK [s]
VHAZ =0V
Coefficient for Sequential
Lighting Start-up Delay Time
KDLY
2.23
2.67
3.20
-
tDLY=KDLY x RSET x CSETDLY [s]
tPSH
105
140
180
μs
VHAZ=5V
tPSL
105
140
180
μs
VCNT=5V→0V
CMPLT Output Voltage Low
VCMPLTL
-
-
0.2
V
ICMPLT=1mA
CMPLT Leak Current
ICMPLTLK
-
-
1
μA
VCMPLT=5.5V
SG Output Voltage Low
VSGL
-
-
0.2
V
ISG=1mA
SG Leak Current
ISGLK
-
-
1
μA
VSG=5.5V
FLAG Output Voltage Low
VFLAGL
-
-
0.2
V
IFLAG=1mA
FLAG Leak Current
IFLAGLK
-
-
1
μA
VFLAG=5.5V
tdSG
415
590
765
μs
WDTDLY Time Out
tWDTDLY
245
350
455
ms
WDTCLK Time Out
tWDTCLK
80
115
150
ms
[Internal Reference Voltage]
Regulator Output
[Charge Pump]
[SET, SETDLY, SETCLK]
Sequential Lighting Phase Time
In the Hazard Mode
Turn Off Phase Time
In the CNT=L
[CMPLT, SG, FLAG]
SG Delay Time
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Electrical Characteristics – continued (Unless otherwise specified: VCC=13V Ta=-40°C to +125°C)
Parameter
Symbol
Limit
Min
Typ
Max
Unit
Conditions
[CNT, HAZ]
CNT Pin Input Current 1
ICNT1
-10
-2.5
-
μA
VCNT=0V
CNT Pin Input Current 2
ICNT2
-
0
5
μA
VCNT=60V
CNT Threshold Voltage
VCNTH
0.9
1.0
1.1
V
Sweep up
VCNTHYS
-
100
-
mV
HAZ Pin Input Current 1
IHAZ1
-10
-2.5
-
μA
VHAZ=0V
HAZ Pin Input Current 2
IHAZ2
-
0
5
μA
VHAZ=60V
VHAZH
0.9
1.0
1.1
V
Sweep up
VHAZHYS
-
100
-
mV
VSELH
3.6
-
VREG
V
VSELL
0
-
1.1
V
ISEL
10
20
30
μA
VSEL1=5V, VSEL2=5V, VSEL3=5V
RSW
-
230
460
mΩ
ISW=300mA
RSW70
-
0.95
2.2
Ω
All Switches On
ISW70=300mA
LED Open Detection Voltage
VLO
9.0
-
15
V
VCHn_CHn-1: Sweep up
LED Short Detection Voltage
VLS
-
-
1.2
V
VCHn_CHn-1: Sweep up
CNT Threshold Hysteresis
Voltage
Hazard Mode Threshold
Voltage
Hazard Mode Threshold
Hysteresis Voltage
[SEL1, SEL2, SEL3]
SEL1, SEL2, SEL3
High Level Input Voltage
SEL1, SEL2, SEL3
Low Level Input Voltage
SEL1, SEL2, SEL3
Pin Input Current
[CH]
CHn to CHn-1 Switch
ON Resistance
CH8 to CH0 Switch
Total ON Resistance
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BD18362EFV-M
Typical Performance Curves (Reference Data)
(Unless otherwise specified: Ta=25°C VCC=13V)
7.0
5.5
5.4
6.0
5.0
5.2
5.1
4.0
3.0
Ta=-40 °C
VREG[V]
IVCC[mA]
5.3
Ta=+125 °C
Ta=+25 °C
5.0
4.9
4.8
2.0
4.7
1.0
0.0
4.6
4.5
0
10
20
30
VCC[V]
40
50
60
-50
Figure 20. IVCC vs VCC
-25
0
25
50
75 100
Temperature [°C]
125
150
125
150
Figure 21. VREG vs Temperature
3.2
370
360
3.0
350
340
2.8
KDLY
KPS
330
320
310
2.6
300
290
2.4
280
270
-50
-25
0
25
50
75 100
Temperature [°C]
125
2.2
150
Figure 22. KPS vs Temperature
(CSETCLK=0.0047μF, RSET=10kΩ)
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TSZ22111 • 15 • 001
-50
-25
0
25
50
75 100
Temperature [°C]
Figure 23. KDLY vs Temperature
(CSETDLY=0.01μF, RSET=10kΩ)
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Typical Performance Curves (Reference Data) - continued
180
180
170
170
160
160
150
150
tPSL[μs]
tPSH[µs]
(Unless otherwise specified: Ta=25°C VCC=13V)
140
140
130
130
120
120
110
110
100
-50
-25
0
25
50
75 100
Temperature[°C]
125
100
150
-50
Figure 24. tPSH vs Temperature
25
50
75 100
Temperature[°C]
125
150
0.30
0.25
0.25
Ta=-40°C
0.20
Ta=-40°C
0.20
VSGL[V]
VCMPLTL[V]
0
Figure 25. tPSL vs Temperature
0.30
0.15
0.10
0.15
0.10
Ta=+125°C
Ta=+25°C
0.05
0.00
-25
Ta=+125°C
Ta=+25°C
0.05
0.0
0.5
1.0
ICMPLT[mA]
1.5
0.00
2.0
Figure 26. VCMPLTL vs ICMPLT
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TSZ22111 • 15 • 001
0.0
0.5
1.0
ISG[mA]
1.5
2.0
Figure 27. VSGL vs ISG
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Typical Performance Curves (Reference Data) - continued
(Unless otherwise specified: Ta=25°C VCC=13V)
740
0.30
700
0.25
Ta=-40°C
660
620
tdSG[μs]
VFLAGL[V]
0.20
0.15
580
540
0.10
Ta=+125°C
Ta=+25°C
500
0.05
0.00
460
420
0.0
0.5
1.0
IFLAG[mA]
1.5
2.0
-50
-25
Figure 28. VFLAGL vs IFLAG
0
25
50
75 100
Temperature[°C]
125
150
125
150
Figure 29. tdSG vs Temperature
450
140
425
130
120
375
tWDTCLK[ms]
tWDTDLY[ms]
400
350
325
110
100
300
90
275
250
-50
-25
0
25
50
75 100
Temperature[°C]
125
80
150
Figure 30. tWDTDLY vs Temperature
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TSZ22111 • 15 • 001
-50
-25
0
25
50
75 100
Temperature[°C]
Figure 31. tWDTCLK vs Temperature
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Typical Performance Curves (Reference Data) - continued
(Unless otherwise specified: Ta=25°C VCC=13V)
1.5
400
1.4
350
1.3
300
1.2
RSW70[Ω]
RSW[mΩ]
250
200
150
1.0
0.9
0.8
100
0.7
50
0
1.1
0.6
-50
-25
0
25
50
75
100
125
0.5
150
-50
-25
0
Temperature[℃]
15.0
1.2
14.0
1.1
13.0
1.0
12.0
0.8
10.0
0.7
-25
0
25
50
75 100
Temperature[°C]
125
0.6
150
Figure 34. VLO vs Temperature
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TSZ22111 • 15 • 001
75
100
125
150
125
150
0.9
11.0
-50
50
Figure 33. RSW70 vs Temperature
(ISW70=300mA)
VLS[V]
VLO[V]
Figure 32. RSW vs Temperature
(ISW=300mA)
9.0
25
Temperature[℃]
-50
-25
0
25
50
75 100
Temperature[°C]
Figure 35. VLS vs Temperature
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BD18362EFV-M
Timing Chart
VUVR
VCC
VUVD
tdSG
SG
SETDLY
tdSG
t PS1
SW0
Hiz
SW1
Hiz
SW2
Hiz
SW3
Hiz
SW4
Hiz
SW5
Hiz
SW6
Hiz
SW7
Hiz
tPS1
tPS1
tPS1
ON
t PS1
t PS1
tPS1
tPS1
OFF
ON
Hiz
OFF
ON
Hiz
OFF
ON
Hiz
OFF
ON
Hiz
OFF
ON
Hiz
OFF
ON
Hiz
OFF
ON
Hiz
OFF
Hiz
FLAG
CMPLT
ILED (External input)
Figure 36. Typical Timing Chart
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BD18362EFV-M
Recommended Application Circuit
VCC
CVCC
RHAZ
CVREG
CSETDLY
CSETCLK
U1
BD18362EFV-M
CNT
HAZ
CP
VREG
SETDLY
CH8
SETCLK
CH7
SET
To LED Driver
Recommended Parts List
(8 switches, tPS1=15ms, tDLY=1.25ms)
Parts
Symbol
IC
Resistor
Capacitor
CCF
CCP
LED7
LED6
CH6
LED5
CH5
SEL1
CH4
SEL2
CH3
SEL3
CH2
CMPLT
CH1
FLAG
CH0
RCMPLT
RSG
CFP
CFM
RSET
RFLAG
ILED
SG
LED4
LED3
LED2
LED1
LED0
GND
Parts Name
Value
Unit
Product Maker
BD18362EFV-M
-
-
ROHM
RHAZ
MCR03EZPJ103
10
kΩ
ROHM
RSET
MCR03EZPD1002
10
kΩ
ROHM
RCMPLT
MCR03EZPJ223
22
kΩ
ROHM
RFLAG
MCR03EZPJ223
22
kΩ
ROHM
RSG
MCR03EZPJ223
22
kΩ
ROHM
CVCC
GCM31CC72A225KE01L
2.2
μF
murata
U1
CVREG
GCM21BR71C225KA49
2.2
μF
murata
CSETDLY
GCM188R11H473JA40
0.047
μF
murata
CSETCLK
GCM2162C1H472JA01
0.0047
μF
murata
CCF
GCM188R11H473JA40
0.047
μF
murata
CCP
GCM188R11H473JA40
0.047
μF
murata
●CVCC: Choose rated voltage according to input voltage range.
●In case of BD18362EFV-M and the LEDs are connected with long wires, it might be triggered the malfunction of LED open
protection and LET short detection by ringing in the voltage which is produced by switching on and off of SW between IC
channels. Moreover, if the ringing level becomes higher than the case of above, it might damage the IC. Confirm the ringing
level with enough evaluation and respond to it by placing RC snubber circuit between CH n and CHn-1.
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BD18362EFV-M
I/O Equivalence Circuits
No.
Symbol
Equivalence Circuit
No.
Symbol
VREG
VREG
2
CNT
Equivalence Circuit
CNT
9
SETCLK
SETCLK
2MΩ (Typ)
GND
GND
VREG
VREG
3
HAZ
10
HAZ
SETDLY
SETDLY
2MΩ (Typ)
GND
GND
VREG
VCC
5
VREG
VREG
GND
11
SET
350kΩ (Typ)
50kΩ (Typ)
GND
VREG
6
7
8
SEL1
SEL2
SEL3
SEL1
SEL2
SEL3
250kΩ
(Typ)
12
13
14
CMPLT
SG
FLAG
CMPLT
SG
FLAG
GND
GND
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BD18362EFV-M
I/O Equivalence Circuits - continued
No.
Symbol
Equivalence Circuit
CFP
CFM
GND
CP
CH8
VREG
GND
GND
GND
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
CH8
CP
CFP
CFM
CH7
・・・
17
18
19
20
21
22
23
24
25
26
27
28
GND
CH2
GND
VCP
CH1
GND
CH0
GND
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BD18362EFV-M
Operational Notes
1.
Reverse Connection of Power Supply
Connecting the power supply in reverse polarity can damage the IC. Take precautions against reverse polarity when
connecting the power supply, such as mounting an external diode between the power supply and the IC’s power
supply pins.
2.
Power Supply Lines
Design the PCB layout pattern to provide low impedance supply lines. Furthermore, connect a capacitor to ground at
all power supply pins. Consider the effect of temperature and aging on the capacitance value when using electrolytic
capacitors.
3.
Ground Voltage
Ensure that no pins are at a voltage below that of the ground pin at any time, even during transient condition.
4.
Ground Wiring Pattern
When using both small-signal and large-current ground traces, the two ground traces should be routed separately but
connected to a single ground at the reference point of the application board to avoid fluctuations in the small-signal
ground caused by large currents. Also ensure that the ground traces of external components do not cause variations
on the ground voltage. The ground lines must be as short and thick as possible to reduce line impedance.
5.
Recommended Operating Conditions
The function and operation of the IC are guaranteed within the range specified by the recommended operating
conditions. The characteristic values are guaranteed only under the conditions of each item specified by the electrical
characteristics.
6.
Inrush Current
When power is first supplied to the IC, it is possible that the internal logic may be unstable and inrush current may flow
instantaneously due to the internal powering sequence and delays, especially if the IC has more than one power
supply. Therefore, give special consideration to power coupling capacitance, power wiring, width of ground wiring, and
routing of connections.
7.
Operation Under Strong Electromagnetic Field
Operating the IC in the presence of a strong electromagnetic field may cause the IC to malfunction.
8.
Testing on Application Boards
When testing the IC on an application board, connecting a capacitor directly to a low-impedance output pin may
subject the IC to stress. Always discharge capacitors completely after each process or step. The IC’s power supply
should always be turned off completely before connecting or removing it from the test setup during the inspection
process. To prevent damage from static discharge, ground the IC during assembly and use similar precautions during
transport and storage.
9.
Inter-pin Short and Mounting Errors
Ensure that the direction and position are correct when mounting the IC on the PCB. Incorrect mounting may result in
damaging the IC. Avoid nearby pins being shorted to each other especially to ground, power supply and output pin.
Inter-pin shorts could be due to many reasons such as metal particles, water droplets (in very humid environment) and
unintentional solder bridge deposited in between pins during assembly to name a few.
10. Unused Input Pins
Input pins of an IC are often connected to the gate of a MOS transistor. The gate has extremely high impedance and
extremely low capacitance. If left unconnected, the electric field from the outside can easily charge it. The small
charge acquired in this way is enough to produce a significant effect on the conduction through the transistor and
cause unexpected operation of the IC. So unless otherwise specified, unused input pins should be connected to the
power supply or ground line.
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Operational Notes – continued
11. Regarding the Input Pin of the IC
This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them
isolated. P-N junctions are formed at the intersection of the P layers with the N layers of other elements, creating a
parasitic diode or transistor. For example (refer to figure below):
When GND > Pin A and GND > Pin B, the P-N junction operates as a parasitic diode.
When GND > Pin B, the P-N junction operates as a parasitic transistor.
Parasitic diodes inevitably occur in the structure of the IC. The operation of parasitic diodes can result in mutual
interference among circuits, operational faults, or physical damage. Therefore, conditions that cause these diodes to
operate, such as applying a voltage lower than the GND voltage to an input pin (and thus to the P substrate) should be
avoided.
Resistor
Transistor (NPN)
Pin A
Pin B
C
Pin A
N
P+
N
P
N
P+
N
Parasitic
Elements
N
P+
GND
E
N P
N
P+
B
N
C
E
Parasitic
Elements
P Substrate
P Substrate
Parasitic
Elements
Pin B
B
Parasitic
Elements
GND
GND
N Region
close-by
GND
Figure 37. Example of monolithic IC structure
12. Ceramic Capacitor
When using a ceramic capacitor, determine a capacitance value considering the change of capacitance with
temperature and the decrease in nominal capacitance due to DC bias and others.
13. Area of Safe Operation (ASO)
Operate the IC such that the output voltage, output current, and the maximum junction temperature rating are all within
the Area of Safe Operation (ASO).
14. Thermal Shutdown Circuit(TSD)
This IC has a built-in thermal shutdown circuit that prevents heat damage to the IC. Normal operation should always
be within the IC’s maximum junction temperature rating. If however the rating is exceeded for a continued period, the
junction temperature (Tj) will rise which will activate the TSD circuit that will turn OFF all output pins. When the Tj falls
below the TSD threshold, the circuits are automatically restored to normal operation.
Note that the TSD circuit operates in a situation that exceeds the absolute maximum ratings and therefore, under no
circumstances, should the TSD circuit be used in a set design or for any purpose other than protecting the IC from
heat damage.
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BD18362EFV-M
Ordering Information
B
D
1
8
3
Part Number
6
2
E
F
V
Package
EFV: HTSSOP-B28
-
ME2
Product Rank
M: for Automotive
Packaging and forming specification
E2: Embossed tape and reel
(HTSSOP-B28)
Marking Diagrams
HTSSOP-B28 (TOP VIEW)
Part Number Marking
B D 1 8 3 6 2
LOT Number
1PIN MARK
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BD18362EFV-M
Physical Dimension, Tape and Reel Information
Package Name
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BD18362EFV-M
Revision History
Date
Rev.
13.Jun.2017
001
Changes
New Release
Page 21
28.Oct.2020
002
Electrical Characteristics
SET Pin Output Voltage
Delete
Page 33 Marking Diagrams
D18362 → BD18362
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Notice
Precaution on using ROHM Products
1.
If you intend to use our Products in devices requiring extremely high reliability (such as medical equipment (Note 1),
aircraft/spacecraft, nuclear power controllers, etc.) and whose malfunction or failure may cause loss of human life,
bodily injury or serious damage to property (“Specific Applications”), please consult with the ROHM sales
representative in advance. Unless otherwise agreed in writing by ROHM in advance, ROHM shall not be in any way
responsible or liable for any damages, expenses or losses incurred by you or third parties arising from the use of any
ROHM’s Products for Specific Applications.
(Note1) Medical Equipment Classification of the Specific Applications
JAPAN
USA
EU
CHINA
CLASSⅢ
CLASSⅡb
CLASSⅢ
CLASSⅢ
CLASSⅣ
CLASSⅢ
2.
ROHM designs and manufactures its Products subject to strict quality control system. However, semiconductor
products can fail or malfunction at a certain rate. Please be sure to implement, at your own responsibilities, adequate
safety measures including but not limited to fail-safe design against the physical injury, damage to any property, which
a failure or malfunction of our Products may cause. The following are examples of safety measures:
[a] Installation of protection circuits or other protective devices to improve system safety
[b] Installation of redundant circuits to reduce the impact of single or multiple circuit failure
3.
Our Products are not designed under any special or extraordinary environments or conditions, as exemplified below.
Accordingly, ROHM shall not be in any way responsible or liable for any damages, expenses or losses arising from the
use of any ROHM’s Products under any special or extraordinary environments or conditions. If you intend to use our
Products under any special or extraordinary environments or conditions (as exemplified below), your independent
verification and confirmation of product performance, reliability, etc, prior to use, must be necessary:
[a] Use of our Products in any types of liquid, including water, oils, chemicals, and organic solvents
[b] Use of our Products outdoors or in places where the Products are exposed to direct sunlight or dust
[c] Use of our Products in places where the Products are exposed to sea wind or corrosive gases, including Cl2,
H2S, NH3, SO2, and NO2
[d] Use of our Products in places where the Products are exposed to static electricity or electromagnetic waves
[e] Use of our Products in proximity to heat-producing components, plastic cords, or other flammable items
[f] Sealing or coating our Products with resin or other coating materials
[g] Use of our Products without cleaning residue of flux (Exclude cases where no-clean type fluxes is used.
However, recommend sufficiently about the residue.); or Washing our Products by using water or water-soluble
cleaning agents for cleaning residue after soldering
[h] Use of the Products in places subject to dew condensation
4.
The Products are not subject to radiation-proof design.
5.
Please verify and confirm characteristics of the final or mounted products in using the Products.
6.
In particular, if a transient load (a large amount of load applied in a short period of time, such as pulse, is applied,
confirmation of performance characteristics after on-board mounting is strongly recommended. Avoid applying power
exceeding normal rated power; exceeding the power rating under steady-state loading condition may negatively affect
product performance and reliability.
7.
De-rate Power Dissipation depending on ambient temperature. When used in sealed area, confirm that it is the use in
the range that does not exceed the maximum junction temperature.
8.
Confirm that operation temperature is within the specified range described in the product specification.
9.
ROHM shall not be in any way responsible or liable for failure induced under deviant condition from what is defined in
this document.
Precaution for Mounting / Circuit board design
1.
When a highly active halogenous (chlorine, bromine, etc.) flux is used, the residue of flux may negatively affect product
performance and reliability.
2.
In principle, the reflow soldering method must be used on a surface-mount products, the flow soldering method must
be used on a through hole mount products. If the flow soldering method is preferred on a surface-mount products,
please consult with the ROHM representative in advance.
For details, please refer to ROHM Mounting specification
Notice-PAA-E
© 2015 ROHM Co., Ltd. All rights reserved.
Rev.004
Precautions Regarding Application Examples and External Circuits
1.
If change is made to the constant of an external circuit, please allow a sufficient margin considering variations of the
characteristics of the Products and external components, including transient characteristics, as well as static
characteristics.
2.
You agree that application notes, reference designs, and associated data and information contained in this document
are presented only as guidance for Products use. Therefore, in case you use such information, you are solely
responsible for it and you must exercise your own independent verification and judgment in the use of such information
contained in this document. ROHM shall not be in any way responsible or liable for any damages, expenses or losses
incurred by you or third parties arising from the use of such information.
Precaution for Electrostatic
This Product is electrostatic sensitive product, which may be damaged due to electrostatic discharge. Please take proper
caution in your manufacturing process and storage so that voltage exceeding the Products maximum rating will not be
applied to Products. Please take special care under dry condition (e.g. Grounding of human body / equipment / solder iron,
isolation from charged objects, setting of Ionizer, friction prevention and temperature / humidity control).
Precaution for Storage / Transportation
1.
Product performance and soldered connections may deteriorate if the Products are stored in the places where:
[a] the Products are exposed to sea winds or corrosive gases, including Cl 2, H2S, NH3, SO2, and NO2
[b] the temperature or humidity exceeds those recommended by ROHM
[c] the Products are exposed to direct sunshine or condensation
[d] the Products are exposed to high Electrostatic
2.
Even under ROHM recommended storage condition, solderability of products out of recommended storage time period
may be degraded. It is strongly recommended to confirm solderability before using Products of which storage time is
exceeding the recommended storage time period.
3.
Store / transport cartons in the correct direction, which is indicated on a carton with a symbol. Otherwise bent leads
may occur due to excessive stress applied when dropping of a carton.
4.
Use Products within the specified time after opening a humidity barrier bag. Baking is required before using Products of
which storage time is exceeding the recommended storage time period.
Precaution for Product Label
A two-dimensional barcode printed on ROHM Products label is for ROHM’s internal use only.
Precaution for Disposition
When disposing Products please dispose them properly using an authorized industry waste company.
Precaution for Foreign Exchange and Foreign Trade act
Since concerned goods might be fallen under listed items of export control prescribed by Foreign exchange and Foreign
trade act, please consult with ROHM in case of export.
Precaution Regarding Intellectual Property Rights
1.
All information and data including but not limited to application example contained in this document is for reference
only. ROHM does not warrant that foregoing information or data will not infringe any intellectual property rights or any
other rights of any third party regarding such information or data.
2.
ROHM shall not have any obligations where the claims, actions or demands arising from the combination of the
Products with other articles such as components, circuits, systems or external equipment (including software).
3.
No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of ROHM or any
third parties with respect to the Products or the information contained in this document. Provided, however, that ROHM
will not assert its intellectual property rights or other rights against you or your customers to the extent necessary to
manufacture or sell products containing the Products, subject to the terms and conditions herein.
Other Precaution
1.
This document may not be reprinted or reproduced, in whole or in part, without prior written consent of ROHM.
2.
The Products may not be disassembled, converted, modified, reproduced or otherwise changed without prior written
consent of ROHM.
3.
In no event shall you use in any way whatsoever the Products and the related technical information contained in the
Products or this document for any military purposes, including but not limited to, the development of mass-destruction
weapons.
4.
The proper names of companies or products described in this document are trademarks or registered trademarks of
ROHM, its affiliated companies or third parties.
Notice-PAA-E
© 2015 ROHM Co., Ltd. All rights reserved.
Rev.004