BD2310G-TR

Datasheet 1ch 4 A High Speed Low-side Gate Driver BD2310G General Description Key Specifications BD2310G is 1ch Low-side Gate Driver, which can drive external Nch-FET and IGBT at high speed. BD2310G can supply output current 4 A at small package SSOP5. This driver has the VREF pin for external input logic supply voltage and this range is 2.0 V to 5.5 V. As a protection function, the driver includes an Undervoltage Lockout (UVLO) between VCC and GND.      Output Voltage Range: 4.5 V to 18 V Input Logic Voltage Range: 2.0 V to 5.5 V Output Current IO+/IO-: 4 A / 4 A (Typ) Turn-on / Turn-off Delay Time: 15 ns / 15 ns (Typ) Operating Temperature Range: -40 °C to +125 °C Package SSOP5 W (Typ) x D (Typ) x H (Max) 2.9 mm x 2.8 mm x 1.25 mm Features      Gate Drive Voltage Range 4.5 V to 18 V Built-in Undervoltage Lockout (UVLO) between VCC and GND Input Logic Voltage Range 2.0 V to 5.5 V In-phase Output with Input signal Small Package SSOP5 Applications    MOSFET / IGBT Driver Applications DC / DC Converters Motor Control Typical Application Circuit Load VCC VCC OUT Low-side GND PWM 〇Product structure : Silicon integrated circuit www.rohm.com © 2020 ROHM Co., Ltd. All rights reserved. TSZ22111 • 14 • 001 IN+ VREF VREF 〇This product has no designed protection against radioactive rays. 1/15 TSZ02201-0Q2Q0A800730-1-2 26.Mar.2020 Rev.001 BD2310G Pin Configuration (TOP VIEW) 5 OUT VCC 1 GND 2 4 VREF IN+ 3 Pin Descriptions Pin No. Pin Name Function 1 VCC Supply voltage 2 GND Ground 3 IN+ 4 VREF Logic supply voltage 5 OUT Gate drive output Logic input Block Diagram VREF IN+ VCC LEVEL SHIFT DRV OUT VCC UVLO GND www.rohm.com © 2020 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 2/15 TSZ02201-0Q2Q0A800730-1-2 26.Mar.2020 Rev.001 BD2310G Absolute Maximum Rating (Ta = 25 °C) Parameter Symbol Rating Unit VCC -0.3 to +20 V VIN -0.3 to VREF + 0.3 V Logic Supply Voltage VREF -0.3 to +6.0 V Output Voltage VOUT -0.3 to VCC + 0.3 V Tjmax 150 °C Tstg -55 to +150 °C Supply Voltage Logic Input Voltage Maximum Junction Temperature Storage Temperature Range Caution 1: Operating the IC over the absolute maximum ratings may damage the IC. The damage can either be a short circuit between pins or an open circuit between pins and the internal circuitry. Therefore, it is important to consider circuit protection measures, such as adding a fuse, in case the IC is operated over the absolute maximum ratings. Caution 2: Should by any chance the maximum junction temperature rating be exceeded the rise in temperature of the chip may result in deterioration of the properties of the chip. In case of exceeding this absolute maximum rating, design a PCB with thermal resistance taken into consideration by increasing board size and copper area so as not to exceed the maximum junction temperature rating. Thermal Resistance (Note 1) Parameter Symbol Thermal Resistance (Typ) 1s(Note 3) 2s2p(Note 4) Unit SSOP5 Junction to Ambient θJA 376.5 185.4 °C/W Junction to Top Characterization Parameter(Note 2) ΨJT 40 30 °C/W (Note 1) Based on JESD51-2A (Still-Air). (Note 2) The thermal characterization parameter to report the difference between junction temperature and the temperature at the top center of the outside surface of the component package. (Note 3) Using a PCB board based on JESD51-3. (Note 4) Using a PCB board based on JESD51-7. Layer Number of Measurement Board Single Material Board Size FR-4 114.3 mm x 76.2 mm x 1.57 mmt Top Copper Pattern Thickness Footprints and Traces 70 μm Layer Number of Measurement Board 4 Layers Material Board Size FR-4 114.3 mm x 76.2 mm x 1.6 mmt Top 2 Internal Layers Bottom Copper Pattern Thickness Copper Pattern Thickness Copper Pattern Thickness Footprints and Traces 70 μm 74.2 mm x 74.2 mm 35 μm 74.2 mm x 74.2 mm 70 μm www.rohm.com © 2020 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 3/15 TSZ02201-0Q2Q0A800730-1-2 26.Mar.2020 Rev.001 BD2310G Recommended Operating Conditions Parameter Symbol Min Typ Max Unit VCC 4.5 12 18 V VIN 0 - VREF V Logic Supply Voltage VREF 2.0 3.3 5.5 V Output Voltage VOUT 0 - VCC V Operating Temperature Topr -40 +25 +125 °C Supply Voltage Logic Input Voltage Electrical Characteristics (Unless otherwise specified VCC = 12 V, VREF = 3.3 V, Ta = 25 °C) Parameter Symbol Min Typ Max Unit Conditions VCC Static Supply Current ICC - 35 70 µA VIN = 0 V VREF Static Supply Current IREF - 4.5 9.0 µA VIN = 0 V Detect Threshold Voltage VUV- 2.9 3.6 4.3 V Reset Threshold Voltage VUV+ 3.1 3.8 4.5 V VUV_HYS - 0.2 - V Logic “0” Threshold Voltage VIN_L 0.2VREF 0.3VREF - V Logic “1” Threshold Voltage VIN_H - 0.5VREF 0.6VREF V “0” Input Circuit Current IIN_L - - 1 µA VIN = 0 V “1” Input Circuit Current IIN_H - 33 50 µA VIN = VREF OUT-VCC IO+ - 4 - A OUT-GND IO- - 4 - A Turn-on Propagation Delay tON - 15 30 ns Turn-off Propagation Delay tOFF - 15 30 ns Rise Time tR - 10 20 ns CL = 1000 pF Fall Time tF - 10 20 ns CL = 1000 pF tINMIN - - 50 ns Circuit Current Undervoltage Lockout (UVLO) Hysteresis Voltage Input Output Output Short Circuit Pulsed Current Minimum Input Pulse Width www.rohm.com © 2020 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 4/15 VOUT = 0 V Pulse Width ≤ 1 µs VOUT = VCC Pulse Width ≤ 1 µs TSZ02201-0Q2Q0A800730-1-2 26.Mar.2020 Rev.001 BD2310G Typical Performance Curves (Unless otherwise specified VCC = 12 V, VREF = 3.3 V, Ta = 25 °C) 60 VCC Static Supply Current : ICC[μA] VCC Undervoltage Lockout : VUV+, VUV-[V] 5.0 4.5 VUV+ 4.0 3.5 VUV- 3.0 2.5 2.0 40 30 20 10 0 -50 -25 0 25 50 75 100 125 Ambient Temperature : Ta[ºC] 0 Figure 1. VCC Undervoltage Lockout vs Ambient Temperature 2 4 6 8 10 12 14 16 18 20 Input Supply Voltage : VCC[V] Figure 2. VCC Static Supply Current vs Input Supply Voltage 3.0 60 VCC = 12 V Logic ”0” / ”1” Threshold Voltage: VIN_L, VIN_H[V] VCC Static Supply Current : ICC[μA] 50 50 40 30 20 10 VREF = 3.3 V 2.5 VIN_H 2.0 1.5 1.0 VIN_L 0.5 0.0 0 -50 -25 0 25 50 75 100 Ambient Temperature : Ta[ºC] -50 125 Figure 4. Logic ”0” / ”1” Threshold Voltage vs Ambient Temperature Figure 3. VCC Static Supply Current vs Ambient Temperature (VCC = 12 V) www.rohm.com © 2020 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 -25 0 25 50 75 100 125 Ambient Temperature : Ta[ºC] 5/15 TSZ02201-0Q2Q0A800730-1-2 26.Mar.2020 Rev.001 BD2310G Typical Performance Curves – continued (Unless otherwise specified VCC = 12 V, VREF = 3.3 V, Ta = 25 °C) 60 60 Input Circuit Current : IIN[μA] Input Circuit Current : IIN[μA] VIN = 3.3 V 50 40 30 20 10 0 40 30 20 10 0 0 1 2 3 4 5 Logic Input Voltage : VIN[V] 6 -50 Turn-on / Turn-off Propagation Delay : tON, tOFF[ns] 12 10 tR 8 tF 6 4 2 0 -50 Figure 7. -25 0 25 50 75 100 Ambient Temperature : Ta[ºC] 125 125 25 20 tON 15 tOFF 10 5 0 -50 Rise / Fall Time vs Ambient Temperature www.rohm.com © 2020 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 -25 0 25 50 75 100 Ambient Temperature : Ta[ºC] Figure 6. Input Circuit Current vs Ambient Temperature (VIN = 3.3 V) Figure 5. Input Circuit Current vs Logic Input Voltage Rise / Fall Time : t R, tF[ns] 50 -25 0 25 50 75 100 125 Ambient Temperature : Ta[ºC] Figure 8. Turn-on / Turn-off Propagation Delay vs Ambient Temperature 6/15 TSZ02201-0Q2Q0A800730-1-2 26.Mar.2020 Rev.001 BD2310G Timing Chart VIN_H IN+ VIN_H VIN_L VIN_L tON tOFF tF tR 90% 90% OUT 10% 10% Figure 9. Timing Chart VCC VUV_HYS VUV+ VUV- OUT IN+ Figure 10. UVLO Timing Chart Static Logic Function Table VCC VREF IN+ OUT ≤ VUV+ X(Note 5) X(Note 5) L ≥ 4.5 V < 2 V(Note 6) X(Note 5) L(Note 6) ≥ 4.5 V ≥2V L L ≥ 4.5 V ≥2V H H (Note 5) X is not depend on the value. (Note 6) VREF has the threshold between 0 V to 2 V. It does not definitely become OUT = L below 2 V. www.rohm.com © 2020 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 7/15 TSZ02201-0Q2Q0A800730-1-2 26.Mar.2020 Rev.001 BD2310G Application Components Selection Method (1) Gate Resistor The gate resistor RG(ON/OFF) is selected to the switching speed of the power device. The switching time (tSW) is defined as the time spent to reach the end of the plateau voltage, so the turn-on gate resistor RG(ON) can be calculated using the following formulas. 𝐼𝐺 = [1] 𝑡𝑆𝑊 𝑅𝑇𝑂𝑇𝐴𝐿(𝑂𝑁) = 𝑅𝑃𝑂𝑁 + 𝑅𝐺(𝑂𝑁) = 𝑄𝑔𝑠 +𝑄𝑔𝑑 𝐼𝐺 Cgd RPON 𝑄𝑔𝑠 +𝑄𝑔𝑑 𝑡𝑆𝑊 = VCC = 𝑉𝐶𝐶 −𝑉𝐺𝑆(𝑇𝐻) 𝐼𝐺 RG(ON) OUT RNOFF [2] Cgs RG(OFF) GND BD2310G (𝑄𝑔𝑠 +𝑄𝑔𝑑 )(𝑅𝑃𝑂𝑁 +𝑅𝐺(𝑂𝑁) ) [3] (𝑉𝐶𝐶 −𝑉𝐺𝑆(𝑇𝐻) ) Figure 11. Gate Driver Equivalent Circuit Where: 𝐼𝐺 is the gate current of the power device. 𝑄𝑔𝑠 is the charge between gate and source of the power device. 𝑄𝑔𝑑 is the charge between gate and drain of the power device. 𝑉𝐺𝑆(𝑇𝐻) is the threshold voltage of the power device. The turn-on gate resistance can be changed to control output slew rate (dVD/dt). The slew rate of the power device is determined by the following equation. 𝑑𝑉𝐷 𝑑𝑡 𝐼 = 𝐶𝐺 Qgs Qgd VDS [4] 𝑟𝑠𝑠 dVD/dt where: 𝐶𝑟𝑠𝑠 is the feedback capacitance. ID VGS The gate resistance is determined as follows by substituting equation [4] into equation [2]. 𝑅𝑇𝑂𝑇𝐴𝐿(𝑂𝑁) = 𝑅𝑃𝑂𝑁 + 𝑅𝐺(𝑂𝑁) = 𝑅𝐺(𝑂𝑁) = 𝑉𝐶𝐶 −𝑉𝐺𝑆(𝑇𝐻) 𝐶𝑟𝑠𝑠 × 𝑑𝑉𝐷 𝑑𝑡 − 𝑅𝑃𝑂𝑁 𝑉𝐶𝐶 −𝑉𝐺𝑆(𝑇𝐻) 𝐶𝑟𝑠𝑠 × 𝑑𝑉𝐷 𝑑𝑡 [5] tSW [6] Figure 12. Gate Charge Transfer Characteristics When other power devices are turned on, current flows in the power device which is off through C gd. At this point, the gate resistance (RG(off)) should be set so that the gate voltage does not exceed the threshold of the power device and turn on the power device itself. 𝑉𝐺𝑆(𝑇𝐻) ≥ (𝑅𝑁𝑂𝐹𝐹 + 𝑅𝐺(𝑂𝐹𝐹) ) × 𝐼𝐺 = (𝑅𝑁𝑂𝐹𝐹 + 𝑅𝐺(𝑂𝐹𝐹) ) × 𝐶𝑔𝑑 × 𝑅𝐺(𝑂𝐹𝐹) ≤ 𝑉𝐺𝑆(𝑇𝐻) 𝐶𝑔𝑑 × 𝑑𝑉𝐷 𝑑𝑡 − 𝑅𝑁𝑂𝐹𝐹 www.rohm.com © 2020 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 𝑑𝑉𝐷 𝑑𝑡 [7] [8] 8/15 TSZ02201-0Q2Q0A800730-1-2 26.Mar.2020 Rev.001 BD2310G Application Components Selection Method – continued (2) Input Capacitor A low-ESR ceramic capacitor should be used near the VCC pin and the VREF pin to reduce input ripple voltage. In considering of the DC bias characteristic, it is recommended 0.5 µF or more between VCC and GND, 8 nF or more between VREF and GND. PCB Layout The voltage of VCC pin may be risen by the parasitic inductance of the PCB and the bonding wire in the IC. The mechanism by which VCC voltage rises is Figure 13. (1) When the signal with short pulse width is input as an input signal, it is turned off in the state that Pch-FET of the final stage is turned on and flows current. (2) When Pch-FET is turned off while current is flowing, VCC voltage is risen by the parasitic inductance. When VCC voltage is risen and over absolute maximum ratings, it can damage the IC. To reduce the rising of VCC voltage, please locate a ceramic capacitor which is low-ESR near the VCC pin and the GND pin, and connect it so that parasitic inductance LVCC and LGND in the PCB becomes small. It is recommended 3 nH or less each LVCC and LGND. (1) (2) Parasitic inductance of the bonding wire in the IC and the PCB VCC The voltage of VCC pin is rose by parasitic inductance LVCC VCC ON LVCC OFF OUT OFF OUT GND ON LGND GND LGND Input capacitor Figure 13. Mechanism of Overshoot www.rohm.com © 2020 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 9/15 TSZ02201-0Q2Q0A800730-1-2 26.Mar.2020 Rev.001 BD2310G I/O Equivalence Circuits Pin No. Pin Name Pin No. Pin Equivalence Circuit Pin Name Pin Equivalence Circuit VCC VREF 3 4 IN+ VREF 1 5 IN+ VCC OUT OUT GND GND www.rohm.com © 2020 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 10/15 TSZ02201-0Q2Q0A800730-1-2 26.Mar.2020 Rev.001 BD2310G Operational Notes 1. Reverse Connection of Power Supply Connecting the power supply in reverse polarity can damage the IC. Take precautions against reverse polarity when connecting the power supply, such as mounting an external diode between the power supply and the IC’s power supply pins. 2. Power Supply Lines Design the PCB layout pattern to provide low impedance supply lines. Furthermore, connect a capacitor to ground at all power supply pins. Consider the effect of temperature and aging on the capacitance value when using electrolytic capacitors. 3. Ground Voltage Ensure that no pins are at a voltage below that of the ground pin at any time, even during transient condition. 4. Ground Wiring Pattern When using both small-signal and large-current ground traces, the two ground traces should be routed separately but connected to a single ground at the reference point of the application board to avoid fluctuations in the small-signal ground caused by large currents. Also ensure that the ground traces of external components do not cause variations on the ground voltage. The ground lines must be as short and thick as possible to reduce line impedance. 5. Recommended Operating Conditions The function and operation of the IC are guaranteed within the range specified by the recommended operating conditions. The characteristic values are guaranteed only under the conditions of each item specified by the electrical characteristics. 6. Inrush Current When power is first supplied to the IC, it is possible that the internal logic may be unstable and inrush current may flow instantaneously due to the internal powering sequence and delays, especially if the IC has more than one power supply. Therefore, give special consideration to power coupling capacitance, power wiring, width of ground wiring, and routing of connections. 7. Testing on Application Boards When testing the IC on an application board, connecting a capacitor directly to a low-impedance output pin may subject the IC to stress. Always discharge capacitors completely after each process or step. The IC’s power supply should always be turned off completely before connecting or removing it from the test setup during the inspection process. To prevent damage from static discharge, ground the IC during assembly and use similar precautions during transport and storage. 8. Inter-pin Short and Mounting Errors Ensure that the direction and position are correct when mounting the IC on the PCB. Incorrect mounting may result in damaging the IC. Avoid nearby pins being shorted to each other especially to ground, power supply and output pin. Inter-pin shorts could be due to many reasons such as metal particles, water droplets (in very humid environment) and unintentional solder bridge deposited in between pins during assembly to name a few. 9. Unused Input Pins Input pins of an IC are often connected to the gate of a MOS transistor. The gate has extremely high impedance and extremely low capacitance. If left unconnected, the electric field from the outside can easily charge it. The small charge acquired in this way is enough to produce a significant effect on the conduction through the transistor and cause unexpected operation of the IC. So unless otherwise specified, unused input pins should be connected to the power supply or ground line. www.rohm.com © 2020 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 11/15 TSZ02201-0Q2Q0A800730-1-2 26.Mar.2020 Rev.001 BD2310G Operational Notes – continued 10. Regarding the Input Pin of the IC This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them isolated. P-N junctions are formed at the intersection of the P layers with the N layers of other elements, creating a parasitic diode or transistor. For example (refer to figure below): When GND > Pin A and GND > Pin B, the P-N junction operates as a parasitic diode. When GND > Pin B, the P-N junction operates as a parasitic transistor. Parasitic diodes inevitably occur in the structure of the IC. The operation of parasitic diodes can result in mutual interference among circuits, operational faults, or physical damage. Therefore, conditions that cause these diodes to operate, such as applying a voltage lower than the GND voltage to an input pin (and thus to the P substrate) should be avoided. Resistor Transistor (NPN) Pin A Pin B C E Pin A N P+ P N N P+ N Pin B B Parasitic Elements N P+ N P N P+ B N C E Parasitic Elements P Substrate P Substrate GND GND Parasitic Elements GND Parasitic Elements GND N Region close-by Figure 18. Example of Monolithic IC Structure 11. Ceramic Capacitor When using a ceramic capacitor, determine a capacitance value considering the change of capacitance with temperature and the decrease in nominal capacitance due to DC bias and others. www.rohm.com © 2020 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 12/15 TSZ02201-0Q2Q0A800730-1-2 26.Mar.2020 Rev.001 BD2310G Ordering Information B D 2 3 1 Part Number 0 G - Package G: SSOP5 TR Packaging and forming specification TR: Embossed tape and reel Marking Diagram SSOP5 (TOP VIEW) 1 L Part Number Marking LOT Number www.rohm.com © 2020 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 13/15 TSZ02201-0Q2Q0A800730-1-2 26.Mar.2020 Rev.001 BD2310G Physical Dimension and Packing Information Package Name www.rohm.com © 2020 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 SSOP5 14/15 TSZ02201-0Q2Q0A800730-1-2 26.Mar.2020 Rev.001 BD2310G Revision History Date Revision 26.Mar.2020 001 Changes New Release www.rohm.com © 2020 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 15/15 TSZ02201-0Q2Q0A800730-1-2 26.Mar.2020 Rev.001 Notice Precaution on using ROHM Products 1. Our Products are designed and manufactured for application in ordinary electronic equipment (such as AV equipment, OA equipment, telecommunication equipment, home electronic appliances, amusement equipment, etc.). If you intend to use our Products in devices requiring extremely high reliability (such as medical equipment (Note 1), transport equipment, traffic equipment, aircraft/spacecraft, nuclear power controllers, fuel controllers, car equipment including car accessories, safety devices, etc.) and whose malfunction or failure may cause loss of human life, bodily injury or serious damage to property (“Specific Applications”), please consult with the ROHM sales representative in advance. Unless otherwise agreed in writing by ROHM in advance, ROHM shall not be in any way responsible or liable for any damages, expenses or losses incurred by you or third parties arising from the use of any ROHM’s Products for Specific Applications. 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However, recommend sufficiently about the residue.) ; or Washing our Products by using water or water-soluble cleaning agents for cleaning residue after soldering [h] Use of the Products in places subject to dew condensation 4. The Products are not subject to radiation-proof design. 5. Please verify and confirm characteristics of the final or mounted products in using the Products. 6. In particular, if a transient load (a large amount of load applied in a short period of time, such as pulse, is applied, confirmation of performance characteristics after on-board mounting is strongly recommended. Avoid applying power exceeding normal rated power; exceeding the power rating under steady-state loading condition may negatively affect product performance and reliability. 7. De-rate Power Dissipation depending on ambient temperature. When used in sealed area, confirm that it is the use in the range that does not exceed the maximum junction temperature. 8. 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Notice – WE © 2015 ROHM Co., Ltd. All rights reserved. Rev.001