BD26502GUL

System LED Drivers for Mobile Phones 7x17(Max.) Dot Matrix LED Display Driver BD26502GUL ●Description BD26502GUL is “Matrix LED Driver” that is the most suitable for the cellular phone. It can control 7x17(119 dot) LED Matrix by internal 7-channel PMOS SWs and 17-channel LED drivers. It can control the luminance and firefly lighting of the LED matrix by the setting of the internal register. It supports SPI and I2C interface. VCSP50L4 (4.1mm□0.55mm height max), small and thin type chip size package. It adopts the very thin CSP package that is the most suitable for the slim phone. ●Features 1) LED Matrix driver (7x17) ・It has 7-channel PMOS SWs and 17-channel current drivers with 1/7 timing driven sequentially. ・Put ON/OFF(for every dot). ・The current drivers can drive 0-20.00mA current with 16 step(for every dot). ・64 steps of the luminance control by PWM (common setting for all dots) ・Continuous (TDMA off ) lighting function for LED14-LED17 ・Easy register setting by A/B 2-side map for each dot. 2) Automatic Slope function ・Cycle time, Slope time can be set for each dot. 3) 8-direction automatic scroll function. 4) Interface 2 ・SPI and I C BUS FS mode(max 400kHz)Compatibility 2 2 ・For I C mode, I C Device address is selectable (74h or 75h) 5) Thermal shutdown 6) Small and thin CSP package 2 ・62pin VCSP50L4(4.1mm 0.55mm height max) *This chip is not designed to protect itself against radioactive rays. *This material may be changed on its way to designing. *This material is not the official specification. No.10041EAT01 o ●Absolute Maximum Ratings (Ta=25 C) Parameter Symbol VMAX VIOMAX Pd Topr Tstg Ratings 7 4.5 1550 -40 ~ +85 -55 ~ +150 Unit V V mW ℃ ℃ Maximum voltage (note2) Maximum voltage (note1) Power Dissipation (note3) Operating Temperature Range Storage Temperature Range note1) note2) note3) VIO,RESETB,CE,SDA,SCL,IFMODE,SYNC,CLKIN,CLKOUT,TEST1,TEST2,TEST3,TESTO, DO terminal Except the above Power dissipation deleting is 12.4mW/ oC , when it’s used in over 25 oC. (ROHM’s standard board has been mounted.) The power dissipation of the IC has to be less than the one of the package. ●Operating Conditions (VBAT≥VIO, VINSW≥VBAT, Ta=-40~85 oC) Parameter Symbol VBAT input voltage VINSW input voltage VIO pin voltage VBAT VINSW VIO Limits 2.7 ~ 5.5 2.7 ~ 5.5 1.65 ~ 3.3 Unit V V V www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 1/39 2010.02 - Rev.A BD26502GUL Technical Note ●Electrical Characteristics (Unless otherwise specified, Ta=25°C, VBAT=3.6V, VINSW=3.6V, VIO=1.8V) Limit Parameter Symbol Unit Condition Min. Typ. Max. [ Circuit Current ] VBAT Circuit current 1 VBAT Circuit current 2 VBAT Circuit current 3 [ UVLO ] UVLO Threshold UVLO Hysteresis [ LED Driver ] (LED1-17) Maximum output current Output current LED current Matching Driver pin voltage range LED OFF Leak current [ PMOS switch ] Leak current at OFF Resistor at ON [ OSC ] OSC frequency fosc 0.96 1.2 1.44 MHz ILEAKP RonP 1.0 1.0 μA Ω Isw=170mA, VINSW=4.5V ILEDMax ILED ILEDMT VLED ILKLED -7.0% 0.2 20.00 10.67 +7.0% 5 VBAT- 1.4 1.0 mA mA % V μA LED1-17 ,ISET＝100kΩ I=10.67mA setting, VLED=1V ILEDMT= (ILEDMax-ILEDMin)/(ILEDMax+ILEDMin) I=10.67mA setting, VLED=1V VUVLO VHYUVLO 50 2.1 2.5 V mV VBAT falling IBAT1 IBAT2 IBAT3 0 0.8 2.0 3.0 5.0 3.5 μA μA mA RESETB=0V, VIO=0V RESETB=0V, VIO=1.8V When LED1-17 are active with default settings. [ CE, SYNC, CLKIN, IFMODE ] L level input voltage H level input voltage L level input current H level input current [ SDA, SCL ] L level input voltage H level input voltage Input hysteresis L level output voltage (for SDA pin) Input current [ RESETB ] L level input voltage H level input voltage Input current [ CLKOUT ] L level output voltage H level output voltage VOL1 VOH1 0.75 x VIO 0.4 V V IOL=2mA IOH=-2mA VIL3 VIH3 Iin2 -0.3 0.75 x VIO 0 0.25 x VIO VIO +0.3 1 V V μA Input voltage = from (0.1 x VIO) to (0.9 x VIO) VIL2 VIH2 Vhys VOL2 Iin1 -0.3 0.75 x VIO 0.05 x VIO 0 -3 0.25 x VIO VIO +0.3 0.3 3 V V V V μA At 3mA sink current Input voltage = from (0.1 x VIO) to (0.9 x VIO) VIL1 VIH1 IIL1 IIH1 -0.3 0.75 x VIO 0 0 0.25 x VIO VIO +0.3 1 1 V V μA μA www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 2/39 2010.02 - Rev.A BD26502GUL ●Power Dissipation (on the ROHM’s Standard Board) Technical Note 1.8 1550mW 1.6 1.4 Power Dissipation Pd （W) 1.2 1.0 0.8 0.6 0.4 0.2 0.0 0 25 50 75 100 125 150 Ta(℃) Fig.1 Information of the ROHM’s standard board Material: glass-epoxy th Size : 50mm×58mm×1.75mm(8 layer) Wiring pattern figure Refer to after page. , www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 3/39 2010.02 - Rev.A BD26502GUL ●Block Diagram / Application Circuit Example 1 Technical Note VBAT VINSW VBAT1 VBAT2 VBAT3 10µF VINSW1 VINSW2 VINSW3 10μF T06 SW7 SW6 SW5 SW4 SW3 SW2 SW1 VREF OSC Logic TDMA T05 T04 ISET 100kΩ IREF T03 T02 T01 T00 20.00mA/ch 1.33mA step VIO TDMA LED17 LED16 Enable 1µF TDMA TDMA LED15 LED14 RESETB TDMA CE I2C or SPI selectable SDA SCL IFMODE SYNC CLKIN TDMA CLKOUT TDMA TDMA I/O Level Shift SPI / I2C interface Digital Control LED13 LED12 TDMA TDMA LED11 LED10 TDMA LED9 LED8 LED7 TDMA LED6 TDMA LED5 TDMA LED4 TDMA LED3 TDMA LED2 TDMA TDMA PWM LED1 GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8 GND9 GND10 GND11 7×17 Dot Matrix Unit LEDGND3 LEDGND4 LEDGND1 Fig.2 Block Diagram / Application Circuit example 1 www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. LEDGND2 TESTO TEST1 TEST2 TEST3 TEST4 TEST5 DO 4/39 2010.02 - Rev.A BD26502GUL ●Block Diagram / Application Circuit Example 2 Technical Note VBAT VINSW VBAT1 VBAT2 VBAT3 10µF VINSW1 VINSW2 VINSW3 10μF T06 SW7 SW6 SW5 SW4 SW3 SW2 SW1 VREF OSC Logic TDMA T05 T04 ISET 100kΩ IREF T03 T02 T01 T00 20.00mA/ch 1.33mA step VIO TDMA LED17 LED16 Enable 1µF TDMA TDMA LED15 LED14 RESETB CE I2C or SPI selectable SDA SCL IFMODE SYNC CLKIN TDMA TDMA LED13 LED12 I/O Level Shift SPI / I2C interface Digital Control TDMA TDMA LED11 LED10 TDMA LED9 TDMA LED8 TDMA LED7 TDMA LED6 TDMA LED5 TDMA LED4 TDMA LED3 TDMA LED2 TDMA TDMA PWM LED1 CLKOUT GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8 GND9 GND10 GND11 7×13 Dot Matrix Unit LEDGND3 LEDGND4 LEDGND1 Fig.3 Block Diagram / Application Circuit example 2 www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. LEDGND2 TESTO TEST1 TEST2 TEST3 TEST4 TEST5 DO 5/39 2010.02 - Rev.A BD26502GUL ●Pin Arrangement ［Bottom View］ Technical Note H TEST4 LED11 LED12 GND1 LED15 LED16 LED17 TESTO G LED9 LED10 LED13 LED14 GND2 CLKOUT CE SDA F LED8 ISET LEDGND3 LEDGND4 TEST1 IFMODE SCL VIO E LEDGND2 LED7 VBAT1 VBAT2 RESETB CLKIN SYNC DO D LED5 LED6 LED4 SW3 SW2 SW1 VINSW1 C LED3 LEDGND1 GND3 TEST2 SW5 SW4 VINSW2 B LED2 LED1 GND4 GND5 GND6 SW6 SW7 VINSW3 A TEST3 VBAT3 GND7 GND8 GND9 GND10 GND11 TEST5 1 2 3 4 5 6 7 8 index Total 62 Balls www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 6/39 2010.02 - Rev.A BD26502GUL ●Package 62pin VCSP50L4 CSP small package SIZE : 4.10mm□ Height : 0.55mm max A ball pitch : 0.5 mm Technical Note *INDEX POST has No Solder Ball www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 7/39 2010.02 - Rev.A BD26502GUL ●Pin Functions No 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 Ball No. A1 A2 A3 A4 A5 A6 A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 C1 C2 C4 C5 C6 C7 C8 D1 D2 D3 D5 D6 D7 D8 E1 E2 E3 E4 E5 E6 E7 E8 F1 F2 F3 F4 F5 F6 F7 Pin Name TEST3 VBAT3 GND7 GND8 GND9 GND10 GND11 TEST5 LED2 LED1 GND4 GND5 GND6 SW6 SW7 VINSW3 LED3 LEDGND1 GND3 TEST2 SW5 SW4 VINSW2 LED5 LED6 LED4 SW3 SW2 SW1 VINSW1 LEDGND2 LED7 VBAT1 VBAT2 RESETB CLKIN SYNC DO LED8 ISET LEDGND3 LEDGND4 TEST1 IFMODE SCL Unused Pull I/O Terminal down setting I I O O O O O I O O O O O O O O O I I I O O I I I I 94kΩ 94kΩ 94kΩ GND VBAT GND GND GND GND GND GND GND GND GND GND GND VINSW VINSW VINSW GND GND GND GND VINSW VINSW VINSW GND GND GND VINSW VINSW VINSW VINSW GND GND VBAT VBAT GND GND GND OPEN GND OPEN GND GND GND GND GND ESD Diode For Power VIO VBAT VBAT VBAT VBAT VBAT VINSW VBAT VBAT VBAT VINSW VINSW VBAT VBAT VIO VINSW VINSW VINSW VINSW VINSW VBAT VIO VIO VIO VIO VBAT VBAT VBAT VIO VIO VIO For Ground GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Test input pin 3 Battery is connected Ground Ground Ground Ground Ground Test input pin 5 LED2 driver output LED1 driver output Ground Ground Ground P-MOS SW6 output P-MOS SW7 output Power supply for SW1-7 LED3 driver output Ground Ground Test input pin 2 P-MOS SW５ output P-MOS SW4 output Power supply for SW1-7 LED5 driver output LED6 driver output LED4 driver output P-MOS SW3 output P-MOS SW2 output P-MOS SW1output Power supply for SW1-7 Ground LED7 driver output Battery is connected Battery is connected Functions Technical Note Equivalent Circuit E A B B B B B I K K B B B C C A K B B E C C A K K K C C C A B K A A D D D G K J B B E Reset input pin (L: reset, H: reset cancel) External CLK input pin External synchronous input pin Test output pin2 LED8 driver output LED Constant Current Driver Current setting pin Ground Ground Test input pin 1 I C/SPI select pin (L: I C, H: SPI) SPI, I2C CLK input pin 2 2 D D www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 8/39 2010.02 - Rev.A BD26502GUL Technical Note No 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 Ball No. F8 G1 G2 G3 G4 G5 G6 G7 G8 H1 H2 H3 H4 H5 H6 H7 H8 Pin Name VIO LED9 LED10 LED13 LED14 GND2 CLKOUT CE SDA TEST4 LED11 LED12 GND1 LED15 LED16 LED17 TESTO I/O O O O O O I I/O I O O O O O O Unused Pull Terminal down setting VIO GND GND GND GND GND OPEN GND GND GND GND GND GND GND GND GND OPEN ESD Diode For For Power Ground VBAT VIO VIO VIO VBAT VBAT VIO GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Functions I/O Power supply is connected LED9 driver output LED10 driver output LED13 driver output LED14 driver output Ground Reference CLK output pin SPI enable pin(H:Enable), or I2C slave address selection (L: 74h, H: 75h) SPI DATA input / I2C DATA input-output pin Test input pin 4 LED11 driver output LED12 driver output Ground LED15 driver output LED16 driver output LED17 driver output Test output pin1 Equivalent Circuit A K K K K B G D F H K K B K K K G * Please connect the unused LED pins to the ground. * It is prohibition to set the registers for unused LED. Total 62 pins ●Equivalent Circuit A B VBAT C VINSW VINSW D VIO VIO E VIO VIO F VIO VIO G VIO VIO H VBAT I VINSW J VBAT K www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 9/39 2010.02 - Rev.A BD26502GUL Technical Note ●Serial Interface 1. SPI format ・When IFMODE is set to “H”, it can interface with SPI format. ・The serial interface is four terminals (serial clock terminal (SCL), serial data input terminal (SDA), and chip selection input terminal (CE)). (1)Write operation ・Data is taken into an internal shift register with rising edge of CLK. (Max of the frequency is 13MHz.) ・The receive data becomes enable in the “H” section of CE. (Active “H”.) ・The transmit data is forwarded (with MSB-First) in the order of write command “0”(1bit), the control register address (7bit) and data (8bit). CE SCL SDA W A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Fig.4 Writing format (2)Timing diagram tcgh CE tcss tscyc tcsw SCL twhc SDA tss tsh twlc Fig.5 Timing diagram (SPI format) (3) Electrical Characteristics (Unless otherwise specified, Ta=25°C, VBAT=3.6V, VINSW=3.6V, VIO=1.8V) Limit Parameter Symbol Unit Condition Min Typ Max SCL cycle time H period of SCL cycle L period of SCL cycle SDA setup time SDA hold time Read and Write interval CE setup time CE hold time tscyc Twhc twlc tss tsh tcsw tcss tcgh 76 35 35 38 38 38 55 55 ns ns ns ns ns ns ns ns www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 10/39 2010.02 - Rev.A BD26502GUL 2. I2C BUS format 2 When IFMODE is set to “L”, it can interface with I C BUS format. Technical Note (1) Slave address CE A7 L H 1 1 A6 1 1 A5 1 1 A4 0 0 A3 1 1 A2 0 0 A1 0 1 R/W 0 (2) Bit Transfer SCL transfers 1-bit data during H. During H of SCL, SDA cannot be changed at the time of bit transfer. If SDA changes while SCL is H, START conditions or STOP conditions will occur and it will be interpreted as a control signal. SDA SCL SDA a state of stability： SDA It can change Data are effective Fig.6 Bit transfer (I2C format) (3) START and STOP condition When SDA and SCL are H, data is not transferred on the I2C- bus. This condition indicates, if SDA changes from H to L while SCL has been H, it will become START (S) conditions, and an access start, if SDA changes from L to H while SCL has been H, it will become STOP (P) conditions and an access end. SDA SCL S START condition P STOP condition Fig.7 START/STOP condition (I2C format) (4) Acknowledge It transfers data 8 bits each after the occurrence of START condition. A transmitter opens SDA after transfer 8bits data, and a receiver returns the acknowledge signal by setting SDA to L. DATA OUTPUT BY TRANSMITTER not acknowledge DATA OUTPUT BY RECEIVER acknowledge SCL 1 2 8 clock pulse for acknowledgement 9 S START condition Fig.8 Acknowledge (I2C format) www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 11/39 2010.02 - Rev.A BD26502GUL Technical Note (5) Writing protocol A register address is transferred by the next 1 byte that transferred the slave address and the write-in command. The 3rd byte writes data in the internal register written in by the 2nd byte, and after 4th byte or, the increment of register address is carried out automatically. However, when a register address turns into the last address (77h), it is set to 00h by the next transmission. After the transmission end, the increment of the address is carried out. *1 *1 S X X X X X X X 0 A A 7 A 6 A 5 A 4 A 3 A 2 A 1 A 0 A D7 D6 D5 D4 D3 D2 D1 D0 A slave address R /W=0(write) from master to slave from slave to master register address D ATA D7 D 6 D 5 D 4 D 3 D 2 D1 D0 A P DATA register address increment A =acknowledge(SD A LOW) A =not acknowledge(SDA HIGH) S=START condition P=STOP condition *1: Write Timing register address increment (6) Timing diagram SDA t BUF t LOW t SU;DAT t HD;STA SCL t SU;STO P S t HD;STA S t HD;DAT t HIGH Sr t SU;STA Fig.9 Timing diagram (I2C format) o (7) Electrical Characteristics(Unless otherwise specified, Ta=25 C, VBAT=3.6V, VINSW=3.6V, VIO=1.8V) Standard-mode Fast-mode Parameter Symbol Min. Typ. Max. Min. Typ. Max. Unit 【I2C BUS format】 SCL clock frequency LOW period of the SCL clock HIGH period of the SCL clock Hold time (repeated) START condition After this period, the first clock is generated Set-up time for a repeated START condition Data hold time Data set-up time Set-up time for STOP condition Bus free time between a STOP and START condition fSCL tLOW tHIGH tHD;STA tSU;STA tHD;DAT tSU;DAT tSU;STO tBUF 0 4.7 4.0 4.0 4.7 0 250 4.0 4.7 - 100 3.45 - 0 1.3 0.6 0.6 0.6 0 100 0.6 1.3 - 400 0.9 - kHz μs μs μs μs μs ns μs μs www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 12/39 2010.02 - Rev.A BD26502GUL ●Register List * Please be sure to write “0” in the register which is not assigned. * It is prohibition to write data to the address which is not assigned. Technical Note Control register Address Default 00h 01h 11h 12h 13h 17h 20h 21h 2Dh 2Eh 2Fh 30h 31h 7Fh 00h 00h 00h 00h 00h 0Fh 00h 00h 00h 00h 00h 00h 00h 00h D7 D6 SCLSPEED[2:0] D5 D4 D3 OSCEN D2 D1 D0 SFTRST Block RESET OSC R/W W W W W W W PWM CLKIN SCLEN SCLRST LEFT START CLRA RMCG RMAP MATRIX CLK W W W W W W W W Remark Software Reset OSC ON/OFF control LED1-6 Enable LED7-12 Enable LED13-17 Enable LED14-17 TDMA Enable LED1-17PWM DutySetting CLK selection, SYNC operation control PWM,SLOPE,SCROLL ON/OFF setting Reset SCROLL SCROLL Setting LED matrix control Matrix data clear Resister map change LED6ON LED5ON LED4ON LED3ON LED2ON LED1ON LED12ON LED11ON LED10ON LED9ON LED8ON LED7ON LED17ON LED16ON LED15ON LED14ON LED13ON LED17 LED16 LED15 LED14 TDMAON TDMAON TDMAON TDMAON PWMSET[5:0] SYNCACT SYNCON CLKOUT UP PWMEN DOWN IAB SLPEN RIGHT CLRB OAB LED driver www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 13/39 2010.02 - Rev.A BD26502GUL A-pattern register Address default D7 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h Technical Note D6 D5 D4 D3 D2 D1 D0 Block R/W W W W W W W W W W W W W W W W W W W W W W W W Remark Data for Matrix 00(DA00) Data for Matrix 01(DA01) Data for Matrix 02(DA02) Data for Matrix 03(DA03) Data for Matrix 04(DA04) Data for Matrix 05(DA05) Data for Matrix 06(DA06) Data for Matrix 10(DA10) Data for Matrix 11(DA11) Data for Matrix 12(DA12) Data for Matrix 13(DA13) Data for Matrix 14(DA14) Data for Matrix 15(DA15) Data for Matrix 16(DA16) Data for Matrix 20(DA20) Data for Matrix 21(DA21) Data for Matrix 22(DA22) Data for Matrix 23(DA23) Data for Matrix 24(DA24) Data for Matrix 25(DA25) Data for Matrix 26(DA26) Data for Matrix 30(DA30) Data for Matrix 31(DA31) Data for Matrix 32(DA32) Data for Matrix 33(DA33) Data for Matrix 34(DA34) Data for Matrix 35(DA35) Data for Matrix 36(DA36) Data for Matrix 40(DA40) Data for Matrix 41(DA41) Data for Matrix 42(DA42) Data for Matrix 43(DA43) Data for Matrix 44(DA44) Data for Matrix 45(DA45) Data for Matrix 46(DA46) Data for Matrix 50(DA50) Data for Matrix 51(DA51) Data for Matrix 52(DA52) Data for Matrix 53(DA53) Data for Matrix 54(DA54) Data for Matrix 55(DA55) Data for Matrix 56(DA56) Data for Matrix 60(DA60) Data for Matrix 61(DA61) Data for Matrix 62(DA62) Data for Matrix 63(DA63) Data for Matrix 64(DA64) Data for Matrix 65(DA65) SCYCA00[1:0] SDLYA00[1:0] SCYCA01[1:0] SDLYA01[1:0] SCYCA02[1:0] SDLYA02[1:0] SCYCA03[1:0] SDLYA03[1:0] SCYCA04[1:0] SDLYA04[1:0] SCYCA05[1:0] SDLYA05[1:0] SCYCA06[1:0] SDLYA06[1:0] SCYCA10[1:0] SDLYA10[1:0] SCYCA11[1:0] SDLYA11[1:0] SCYCA12[1:0] SDLYA12[1:0] SCYCA13[1:0] SDLYA13[1:0] SCYCA14[1:0] SDLYA14[1:0] SCYCA15[1:0] SDLYA15[1:0] SCYCA16[1:0] SDLYA16[1:0] SCYCA20[1:0] SDLYA20[1:0] SCYCA21[1:0] SDLYA21[1:0] SCYCA22[1:0] SDLYA22[1:0] SCYCA23[1:0] SDLYA23[1:0] SCYCA24[1:0] SDLYA24[1:0] SCYCA25[1:0] SDLYA25[1:0] SCYCA26[1:0] SDLYA26[1:0] SCYCA30[1:0] SDLYA30[1:0] SCYCA31[1:0] SDLYA31[1:0] SCYCA32[1:0] SDLYA32[1:0] SCYCA33[1:0] SDLYA33[1:0] SCYCA34[1:0] SDLYA34[1:0] SCYCA35[1:0] SDLYA35[1:0] SCYCA36[1:0] SDLYA36[1:0] SCYCA40[1:0] SDLYA40[1:0] SCYCA41[1:0] SDLYA41[1:0] SCYCA42[1:0] SDLYA42[1:0] SCYCA43[1:0] SDLYA43[1:0] SCYCA44[1:0] SDLYA44[1:0] SCYCA45[1:0] SDLYA45[1:0] SCYCA46[1:0] SDLYA46[1:0] SCYCA50[1:0] SDLYA50[1:0] SCYCA51[1:0] SDLYA51[1:0] SCYCA52[1:0] SDLYA52[1:0] SCYCA53[1:0] SDLYA53[1:0] SCYCA54[1:0] SDLYA54[1:0] SCYCA55[1:0] SDLYA55[1:0] SCYCA56[1:0] SDLYA56[1:0] SCYCA60[1:0] SDLYA60[1:0] SCYCA61[1:0] SDLYA61[1:0] SCYCA62[1:0] SDLYA62[1:0] SCYCA63[1:0] SDLYA63[1:0] SCYCA64[1:0] SDLYA64[1:0] SCYCA65[1:0] SDLYA65[1:0] ILEDA00SET[3:0] ILEDA01SET[3:0] ILEDA02SET[3:0] ILEDA03SET[3:0] ILEDA04SET[3:0] ILEDA05SET[3:0] ILEDA06SET[3:0] ILEDA10SET[3:0] ILEDA11SET[3:0] ILEDA12SET[3:0] ILEDA13SET[3:0] ILEDA14SET[3:0] ILEDA15SET[3:0] ILEDA16SET[3:0] ILEDA20SET[3:0] ILEDA21SET[3:0] ILEDA22SET[3:0] ILEDA23SET[3:0] ILEDA24SET[3:0] ILEDA25SET[3:0] ILEDA26SET[3:0] ILEDA30SET[3:0] ILEDA31SET[3:0] ILEDA32SET[3:0] ILEDA33SET[3:0] ILEDA34SET[3:0] ILEDA35SET[3:0] ILEDA36SET[3:0] ILEDA40SET[3:0] ILEDA41SET[3:0] ILEDA42SET[3:0] ILEDA43SET[3:0] ILEDA44SET[3:0] ILEDA45SET[3:0] ILEDA46SET[3:0] ILEDA50SET[3:0] ILEDA51SET[3:0] ILEDA52SET[3:0] ILEDA53SET[3:0] ILEDA54SET[3:0] ILEDA55SET[3:0] ILEDA56SET[3:0] ILEDA60SET[3:0] ILEDA61SET[3:0] ILEDA62SET[3:0] ILEDA63SET[3:0] ILEDA64SET[3:0] ILEDA65SET[3:0] MATRIX W Data W W W W W W W W W W W W W W W W W W W W W W W W www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 14/39 2010.02 - Rev.A BD26502GUL Technical Note Address default 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch 3Dh 3Eh 3Fh 40h 41h 42h 43h 44h 45h 46h 47h 48h 49h 4Ah 4Bh 4Ch 4Dh 4Eh 4Fh 50h 51h 52h 53h 54h 55h 56h 57h 58h 59h 5Ah 5Bh 5Ch 5Dh 5Eh 5Fh 60h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h D7 D6 D5 D4 D3 D2 D1 D0 Block R/W W W W W W W W W W W W W W W W W W W W W W W W Remark Data for Matrix 66(DA66) Data for Matrix 70(DA70) Data for Matrix 71(DA71) Data for Matrix 72(DA72) Data for Matrix 73(DA73) Data for Matrix 74(DA74) Data for Matrix 75(DA75) Data for Matrix 76(DA76) Data for Matrix 80(DA80) Data for Matrix 81(DA81) Data for Matrix 82(DA82) Data for Matrix 83(DA83) Data for Matrix 84(DA84) Data for Matrix 85(DA85) Data for Matrix 86(DA86) Data for Matrix 90(DA90) Data for Matrix 91(DA91) Data for Matrix 92(DA92) Data for Matrix 93(DA93) Data for Matrix 94(DA94) Data for Matrix 95(DA95) Data for Matrix 96(DA96) Data for Matrix A0(DAA0) Data for Matrix A1(DAA1) Data for Matrix A2(DAA2) Data for Matrix A3(DAA3) Data for Matrix A4(DAA4) Data for Matrix A5(DAA5) Data for Matrix A6(DAA6) Data for Matrix B0(DAB0) Data for Matrix B1(DAB1) Data for Matrix B2(DAB2) Data for Matrix B3(DAB3) Data for Matrix B4(DAB4) Data for Matrix B5(DAB5) Data for Matrix B6(DAB6) Data for Matrix C0(DAC0) Data for Matrix C1(DAC1) Data for Matrix C2(DAC2) Data for Matrix C3(DAC3) Data for Matrix C4(DAC4) Data for Matrix C5(DAC5) Data for Matrix C6(DAC6) Data for Matrix D0(DAD0) Data for Matrix D1(DAD1) Data for Matrix D2(DAD2) Data for Matrix D3(DAD3) Data for Matrix D4(DAD4) SCYCA66[1:0] SDLYA66[1:0] SCYCA70[1:0] SDLYA70[1:0] SCYCA71[1:0] SDLYA71[1:0] SCYCA72[1:0] SDLYA72[1:0] SCYCA73[1:0] SDLYA73[1:0] SCYCA74[1:0] SDLYA74[1:0] SCYCA75[1:0] SDLYA75[1:0] SCYCA76[1:0] SDLYA76[1:0] SCYCA80[1:0] SDLYA80[1:0] SCYCA81[1:0] SDLYA81[1:0] SCYCA82[1:0] SDLYA82[1:0] SCYCA83[1:0] SDLYA83[1:0] SCYCA84[1:0] SDLYA84[1:0] SCYCA85[1:0] SDLYA85[1:0] SCYCA86[1:0] SDLYA86[1:0] SCYCA90[1:0] SDLYA90[1:0] SCYCA91[1:0] SDLYA91[1:0] SCYCA92[1:0] SDLYA92[1:0] SCYCA93[1:0] SDLYA93[1:0] SCYCA94[1:0] SDLYA94[1:0] SCYCA95[1:0] SDLYA95[1:0] SCYCA96[1:0] SDLYA96[1:0] SCYCAA0[1:0] SDLYAA0[1:0] SCYCAA1[1:0] SDLYAA1[1:0] SCYCAA2[1:0] SDLYAA2[1:0] SCYCAA3[1:0] SDLYAA3[1:0] SCYCAA4[1:0] SDLYAA4[1:0] SCYCAA5[1:0] SDLYAA5[1:0] SCYCAA6[1:0] SDLYAA6[1:0] SCYCAB0[1:0] SDLYAB0[1:0] SCYCAB1[1:0] SDLYAB1[1:0] SCYCAB2[1:0] SDLYAB2[1:0] SCYCAB3[1:0] SDLYAB3[1:0] SCYCAB4[1:0] SDLYAB4[1:0] SCYCAB5[1:0] SDLYAB5[1:0] SCYCAB6[1:0] SDLYAB6[1:0] SCYCAC0[1:0] SDLYAC0[1:0] SCYCAC1[1:0] SDLYAC1[1:0] SCYCAC2[1:0] SDLYAC2[1:0] SCYCAC3[1:0] SDLYAC3[1:0] SCYCAC4[1:0] SDLYAC4[1:0] SCYCAC5[1:0] SDLYAC5[1:0] SCYCAC6[1:0] SDLYAC6[1:0] SCYCAD0[1:0] SDLYAD0[1:0] SCYCAD1[1:0] SDLYAD1[1:0] SCYCAD2[1:0] SDLYAD2[1:0] SCYCAD3[1:0] SDLYAD3[1:0] SCYCAD4[1:0] SDLYAD4[1:0] ILEDA66SET[3:0] ILEDA70SET[3:0] ILEDA71SET[3:0] ILEDA72SET[3:0] ILEDA73SET[3:0] ILEDA74SET[3:0] ILEDA75SET[3:0] ILEDA76SET[3:0] ILEDA80SET[3:0] ILEDA81SET[3:0] ILEDA82SET[3:0] ILEDA83SET[3:0] ILEDA84SET[3:0] ILEDA85SET[3:0] ILEDA86SET[3:0] ILEDA90SET[3:0] ILEDA91SET[3:0] ILEDA92SET[3:0] ILEDA93SET[3:0] ILEDA94SET[3:0] ILEDA95SET[3:0] ILEDA96SET[3:0] ILEDAA0SET[3:0] ILEDAA1SET[3:0] ILEDAA2SET[3:0] ILEDAA3SET[3:0] ILEDAA4SET[3:0] ILEDAA5SET[3:0] ILEDAA6SET[3:0] ILEDAB0SET[3:0] ILEDAB1SET[3:0] ILEDAB2SET[3:0] ILEDAB3SET[3:0] ILEDAB4SET[3:0] ILEDAB5SET[3:0] ILEDAB6SET[3:0] ILEDAC0SET[3:0] ILEDAC1SET[3:0] ILEDAC2SET[3:0] ILEDAC3SET[3:0] ILEDAC4SET[3:0] ILEDAC5SET[3:0] ILEDAC6SET[3:0] ILEDAD0SET[3:0] ILEDAD1SET[3:0] ILEDAD2SET[3:0] ILEDAD3SET[3:0] ILEDAD4SET[3:0] MATRIX W Data W W W W W W W W W W W W W W W W W W W W W W W W www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 15/39 2010.02 - Rev.A BD26502GUL Technical Note Address default 61h 62h 63h 64h 65h 66h 67h 68h 69h 6Ah 6Bh 6Ch 6Dh 6Eh 6Fh 70h 71h 72h 73h 74h 75h 76h 77h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h D7 D6 D5 D4 D3 D2 D1 D0 Block R/W W W W W W W W W W W W Remark Data for Matrix D5(DAD5) Data for Matrix D6(DAD6) Data for Matrix E0(DAE0) Data for Matrix E1(DAE1) Data for Matrix E2(DAE2) Data for Matrix E3(DAE3) Data for Matrix E4(DAE4) Data for Matrix E5(DAE5) Data for Matrix E6(DAE6) Data for Matrix F0(DAF0) Data for Matrix F1(DAF1) Data for Matrix F2(DAF2) Data for Matrix F3(DAF3) Data for Matrix F4(DAF4) Data for Matrix F5(DAF5) Data for Matrix F6(DAF6) Data for Matrix G0(DAG0) Data for Matrix G1(DAG1) Data for Matrix G2(DAG2) Data for Matrix G3(DAG3) Data for Matrix G4(DAG4) Data for Matrix G5(DAG5) Data for Matrix G6(DAG6) SCYCAD5[1:0] SDLYAD5[1:0] SCYCAD6[1:0] SDLYAD6[1:0] SCYCAE0[1:0] SDLYAE0[1:0] SCYCAE1[1:0] SDLYAE1[1:0] SCYCAE2[1:0] SDLYAE2[1:0] SCYCAE3[1:0] SDLYAE3[1:0] SCYCAE4[1:0] SDLYAE4[1:0] SCYCAE5[1:0] SDLYAE5[1:0] SCYCAE6[1:0] SDLYAE6[1:0] SCYCAF0[1:0] SDLYAF0[1:0] SCYCAF1[1:0] SDLYAF1[1:0] SCYCAF2[1:0] SDLYAF2[1:0] SCYCAF3[1:0] SDLYAF3[1:0] SCYCAF4[1:0] SDLYAF4[1:0] SCYCAF5[1:0] SDLYAF5[1:0] SCYCAF6[1:0] SDLYAF6[1:0] SCYCAG0[1:0] SDLYAG0[1:0] SCYCAG1[1:0] SDLYAG1[1:0] SCYCAG2[1:0] SDLYAG2[1:0] SCYCAG3[1:0] SDLYAG3[1:0] SCYCAG4[1:0] SDLYAG4[1:0] SCYCAG5[1:0] SDLYAG5[1:0] SCYCAG6[1:0] SDLYAG6[1:0] ILEDAD5SET[3:0] ILEDAD6SET[3:0] ILEDAE0SET[3:0] ILEDAE1SET[3:0] ILEDAE2SET[3:0] ILEDAE3SET[3:0] ILEDAE4SET[3:0] ILEDAE5SET[3:0] ILEDAE6SET[3:0] ILEDAF0SET[3:0] ILEDAF1SET[3:0] ILEDAF2SET[3:0] ILEDAF3SET[3:0] ILEDAF4SET[3:0] ILEDAF5SET[3:0] ILEDAF6SET[3:0] ILEDAG0SET[3:0] ILEDAG1SET[3:0] ILEDAG2SET[3:0] ILEDAG3SET[3:0] ILEDAG4SET[3:0] ILEDAG5SET[3:0] ILEDAG6SET[3:0] MATRIX W Data W W W W W W W W W W W www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 16/39 2010.02 - Rev.A BD26502GUL B-pattern register Address default D7 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h Technical Note D6 D5 D4 D3 D2 D1 D0 Block R/W W W W W W W W W W W W W W W W W W W W W W W W Remark Data for Matrix 00(DB00) Data for Matrix 01(DB01) Data for Matrix 02(DB02) Data for Matrix 03(DB03) Data for Matrix 04(DB04) Data for Matrix 05(DB05) Data for Matrix 06(DB06) Data for Matrix 10(DB10) Data for Matrix 11(DB11) Data for Matrix 12(DB12) Data for Matrix 13(DB13) Data for Matrix 14(DB14) Data for Matrix 15(DB15) Data for Matrix 16(DB16) Data for Matrix 20(DB20) Data for Matrix 21(DB21) Data for Matrix 22(DB22) Data for Matrix 23(DB23) Data for Matrix 24(DB24) Data for Matrix 25(DB25) Data for Matrix 26(DB26) Data for Matrix 30(DB30) Data for Matrix 31(DB31) Data for Matrix 32(DB32) Data for Matrix 33(DB33) Data for Matrix 34(DB34) Data for Matrix 35(DB35) Data for Matrix 36(DB36) Data for Matrix 40(DB40) Data for Matrix 41(DB41) Data for Matrix 42(DB42) Data for Matrix 43(DB43) Data for Matrix 44(DB44) Data for Matrix 45(DB45) Data for Matrix 46(DB46) Data for Matrix 50(DB50) Data for Matrix 51(DB51) Data for Matrix 52(DB52) Data for Matrix 53(DB53) Data for Matrix 54(DB54) Data for Matrix 55(DB55) Data for Matrix 56(DB56) Data for Matrix 60(DB60) Data for Matrix 61(DB61) Data for Matrix 62(DB62) Data for Matrix 63(DB63) Data for Matrix 64(DB64) Data for Matrix 65(DB65) SCYCB00[1:0] SDLYB00[1:0] SCYCB01[1:0] SDLYB01[1:0] SCYCB02[1:0] SDLYB02[1:0] SCYCB03[1:0] SDLYB03[1:0] SCYCB04[1:0] SDLYB04[1:0] SCYCB05[1:0] SDLYB05[1:0] SCYCB06[1:0] SDLYB06[1:0] SCYCB10[1:0] SDLYB10[1:0] SCYCB11[1:0] SDLYB11[1:0] SCYCB12[1:0] SDLYB12[1:0] SCYCB13[1:0] SDLYB13[1:0] SCYCB14[1:0] SDLYB14[1:0] SCYCB15[1:0] SDLYB15[1:0] SCYCB16[1:0] SDLYB16[1:0] SCYCB20[1:0] SDLYB20[1:0] SCYCB21[1:0] SDLYB21[1:0] SCYCB22[1:0] SDLYB22[1:0] SCYCB23[1:0] SDLYB23[1:0] SCYCB24[1:0] SDLYB24[1:0] SCYCB25[1:0] SDLYB25[1:0] SCYCB26[1:0] SDLYB26[1:0] SCYCB30[1:0] SDLYB30[1:0] SCYCB31[1:0] SDLYB31[1:0] SCYCB32[1:0] SDLYB32[1:0] SCYCB33[1:0] SDLYB33[1:0] SCYCB34[1:0] SDLYB34[1:0] SCYCB35[1:0] SDLYB35[1:0] SCYCB36[1:0] SDLYB36[1:0] SCYCB40[1:0] SDLYB40[1:0] SCYCB41[1:0] SDLYB41[1:0] SCYCB42[1:0] SDLYB42[1:0] SCYCB43[1:0] SDLYB43[1:0] SCYCB44[1:0] SDLYB44[1:0] SCYCB45[1:0] SDLYB45[1:0] SCYCB46[1:0] SDLYB46[1:0] SCYCB50[1:0] SDLYB50[1:0] SCYCB51[1:0] SDLYB51[1:0] SCYCB52[1:0] SDLYB52[1:0] SCYCB53[1:0] SDLYB53[1:0] SCYCB54[1:0] SDLYB54[1:0] SCYCB55[1:0] SDLYB55[1:0] SCYCB56[1:0] SDLYB56[1:0] SCYCB60[1:0] SDLYB60[1:0] SCYCB61[1:0] SDLYB61[1:0] SCYCB62[1:0] SDLYB62[1:0] SCYCB63[1:0] SDLYB63[1:0] SCYCB64[1:0] SDLYB64[1:0] SCYCB65[1:0] SDLYB65[1:0] ILEDB00SET[3:0] ILEDB01SET[3:0] ILEDB02SET[3:0] ILEDB03SET[3:0] ILEDB04SET[3:0] ILEDB05SET[3:0] ILEDB06SET[3:0] ILEDB10SET[3:0] ILEDB11SET[3:0] ILEDB12SET[3:0] ILEDB13SET[3:0] ILEDB14SET[3:0] ILEDB15SET[3:0] ILEDB16SET[3:0] ILEDB20SET[3:0] ILEDB21SET[3:0] ILEDB22SET[3:0] ILEDB23SET[3:0] ILEDB24SET[3:0] ILEDB25SET[3:0] ILEDB26SET[3:0] ILEDB30SET[3:0] ILEDB31SET[3:0] ILEDB32SET[3:0] ILEDB33SET[3:0] ILEDB34SET[3:0] ILEDB35SET[3:0] ILEDB36SET[3:0] ILEDB40SET[3:0] ILEDB41SET[3:0] ILEDB42SET[3:0] ILEDB43SET[3:0] ILEDB44SET[3:0] ILEDB45SET[3:0] ILEDB46SET[3:0] ILEDB50SET[3:0] ILEDB51SET[3:0] ILEDB52SET[3:0] ILEDB53SET[3:0] ILEDB54SET[3:0] ILEDB55SET[3:0] ILEDB56SET[3:0] ILEDB60SET[3:0] ILEDB61SET[3:0] ILEDB62SET[3:0] ILEDB63SET[3:0] ILEDB64SET[3:0] ILEDB65SET[3:0] MATRIX W Data W W W W W W W W W W W W W W W W W W W W W W W W www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 17/39 2010.02 - Rev.A BD26502GUL Technical Note Address default 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch 3Dh 3Eh 3Fh 40h 41h 42h 43h 44h 45h 46h 47h 48h 49h 4Ah 4Bh 4Ch 4Dh 4Eh 4Fh 50h 51h 52h 53h 54h 55h 56h 57h 58h 59h 5Ah 5Bh 5Ch 5Dh 5Eh 5Fh 60h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h D7 D6 D5 D4 D3 D2 D1 D0 Block R/W W W W W W W W W W W W W W W W W W W W W W W W Remark Data for Matrix 66(DB66) Data for Matrix 70(DB70) Data for Matrix 71(DB71) Data for Matrix 72(DB72) Data for Matrix 73(DB73) Data for Matrix 74(DB74) Data for Matrix 75(DB75) Data for Matrix 76(DB76) Data for Matrix 80(DB80) Data for Matrix 81(DB81) Data for Matrix 82(DB82) Data for Matrix 83(DB83) Data for Matrix 84(DB84) Data for Matrix 85(DB85) Data for Matrix 86(DB86) Data for Matrix 90(DB90) Data for Matrix 91(DB91) Data for Matrix 92(DB92) Data for Matrix 93(DB93) Data for Matrix 94(DB94) Data for Matrix 95(DB95) Data for Matrix 96(DB96) Data for Matrix A0(DBA0) Data for Matrix A1(DBA1) Data for Matrix A2(DBA2) Data for Matrix A3(DBA3) Data for Matrix A4(DBA4) Data for Matrix A5(DBA5) Data for Matrix A6(DBA6) Data for Matrix B0(DBB0) Data for Matrix B1(DBB1) Data for Matrix B2(DBB2) Data for Matrix B3(DBB3) Data for Matrix B4(DBB4) Data for Matrix B5(DBB5) Data for Matrix B6(DBB6) Data for Matrix C0(DBC0) Data for Matrix C1(DBC1) Data for Matrix C2(DBC2) Data for Matrix C3(DBC3) Data for Matrix C4(DBC4) Data for Matrix C5(DBC5) Data for Matrix C6(DBC6) Data for Matrix D0(DBD0) Data for Matrix D1(DBD1) Data for Matrix D2(DBD2) Data for Matrix D3(DBD3) Data for Matrix D4(DBD4) SCYCB66[1:0] SDLYB66[1:0] SCYCB70[1:0] SDLYB70[1:0] SCYCB71[1:0] SDLYB71[1:0] SCYCB72[1:0] SDLYB72[1:0] SCYCB73[1:0] SDLYB73[1:0] SCYCB74[1:0] SDLYB74[1:0] SCYCB75[1:0] SDLYB75[1:0] SCYCB76[1:0] SDLYB76[1:0] SCYCB80[1:0] SDLYB80[1:0] SCYCB81[1:0] SDLYB81[1:0] SCYCB82[1:0] SDLYB82[1:0] SCYCB83[1:0] SDLYB83[1:0] SCYCB84[1:0] SDLYB84[1:0] SCYCB85[1:0] SDLYB85[1:0] SCYCB86[1:0] SDLYB86[1:0] SCYCB90[1:0] SDLYB90[1:0] SCYCB91[1:0] SDLYB91[1:0] SCYCB92[1:0] SDLYB92[1:0] SCYCB93[1:0] SDLYB93[1:0] SCYCB94[1:0] SDLYB94[1:0] SCYCB95[1:0] SDLYB95[1:0] SCYCB96[1:0] SDLYB96[1:0] SCYCBA0[1:0] SDLYBA0[1:0] SCYCBA1[1:0] SDLYBA1[1:0] SCYCBA2[1:0] SDLYBA2[1:0] SCYCBA3[1:0] SDLYBA3[1:0] SCYCBA4[1:0] SDLYBA4[1:0] SCYCBA5[1:0] SDLYBA5[1:0] SCYCBA6[1:0] SDLYBA6[1:0] SCYCBB0[1:0] SDLYBB0[1:0] SCYCBB1[1:0] SDLYBB1[1:0] SCYCBB2[1:0] SDLYBB2[1:0] SCYCBB3[1:0] SDLYBB3[1:0] SCYCBB4[1:0] SDLYBB4[1:0] SCYCBB5[1:0] SDLYBB5[1:0] SCYCBB6[1:0] SDLYBB6[1:0] SCYCBC0[1:0] SDLYBC0[1:0] SCYCBC1[1:0] SDLYBC1[1:0] SCYCBC2[1:0] SDLYBC2[1:0] SCYCBC3[1:0] SDLYBC3[1:0] SCYCBC4[1:0] SDLYBC4[1:0] SCYCBC5[1:0] SDLYBC5[1:0] SCYCBC6[1:0] SDLYBC6[1:0] SCYCBD0[1:0] SDLYBD0[1:0] SCYCBD1[1:0] SDLYBD1[1:0] SCYCBD2[1:0] SDLYBD2[1:0] SCYCBD3[1:0] SDLYBD3[1:0] SCYCBD4[1:0] SDLYBD4[1:0] ILEDB66SET[3:0] ILEDB70SET[3:0] ILEDB71SET[3:0] ILEDB72SET[3:0] ILEDB73SET[3:0] ILEDB74SET[3:0] ILEDB75SET[3:0] ILEDB76SET[3:0] ILEDB80SET[3:0] ILEDB81SET[3:0] ILEDB82SET[3:0] ILEDB83SET[3:0] ILEDB84SET[3:0] ILEDB85SET[3:0] ILEDB86SET[3:0] ILEDB90SET[3:0] ILEDB91SET[3:0] ILEDB92SET[3:0] ILEDB93SET[3:0] ILEDB94SET[3:0] ILEDB95SET[3:0] ILEDB96SET[3:0] ILEDBA0SET[3:0] ILEDBA1SET[3:0] ILEDBA2SET[3:0] ILEDBA3SET[3:0] ILEDBA4SET[3:0] ILEDBA5SET[3:0] ILEDBA6SET[3:0] ILEDBB0SET[3:0] ILEDBB1SET[3:0] ILEDBB2SET[3:0] ILEDBB3SET[3:0] ILEDBB4SET[3:0] ILEDBB5SET[3:0] ILEDBB6SET[3:0] ILEDBC0SET[3:0] ILEDBC1SET[3:0] ILEDBC2SET[3:0] ILEDBC3SET[3:0] ILEDBC4SET[3:0] ILEDBC5SET[3:0] ILEDBC6SET[3:0] ILEDBD0SET[3:0] ILEDBD1SET[3:0] ILEDBD2SET[3:0] ILEDBD3SET[3:0] ILEDBD4SET[3:0] MATRIX W Data W W W W W W W W W W W W W W W W W W W W W W W W www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 18/39 2010.02 - Rev.A BD26502GUL Address default 61h 62h 63h 64h 65h 66h 67h 68h 69h 6Ah 6Bh 6Ch 6Dh 6Eh 6Fh 70h 71h 72h 73h 74h 75h 76h 77h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h D7 D6 D5 D4 D3 D2 D1 D0 Block R/W W W W W W W W W W W MATRIX W Data W W W W W W W W W W W W Technical Note Remark Data for Matrix D5(DBD5) Data for Matrix D6(DBD6) Data for Matrix E0(DBE0) Data for Matrix E1(DBE1) Data for Matrix E2(DBE2) Data for Matrix E3(DBE3) Data for Matrix E4(DBE4) Data for Matrix E5(DBE5) Data for Matrix E6(DBE6) Data for Matrix F0(DBF0) Data for Matrix F1(DBF1) Data for Matrix F2(DBF2) Data for Matrix F3(DBF3) Data for Matrix F4(DBF4) Data for Matrix F5(DBF5) Data for Matrix F6(DBF6) Data for Matrix G0(DBG0) Data for Matrix G1(DBG1) Data for Matrix G2(DBG2) Data for Matrix G3(DBG3) Data for Matrix G4(DBG4) Data for Matrix G5(DBG5) Data for Matrix G6(DBG6) SCYCBD5[1:0] SDLYBD5[1:0] SCYCBD6[1:0] SDLYBD6[1:0] SCYCBE0[1:0] SDLYBE0[1:0] SCYCBE1[1:0] SDLYBE1[1:0] SCYCBE2[1:0] SDLYBE2[1:0] SCYCBE3[1:0] SDLYBE3[1:0] SCYCBE4[1:0] SDLYBE4[1:0] SCYCBE5[1:0] SDLYBE5[1:0] SCYCBE6[1:0] SDLYBE6[1:0] SCYCBF0[1:0] SDLYBF0[1:0] SCYCBF1[1:0] SDLYBF1[1:0] SCYCBF2[1:0] SDLYBF2[1:0] SCYCBF3[1:0] SDLYBF3[1:0] SCYCBF4[1:0] SDLYBF4[1:0] SCYCBF5[1:0] SDLYBF5[1:0] SCYCBF6[1:0] SDLYBF6[1:0] SCYCBG0[1:0] SDLYBG0[1:0] SCYCBG1[1:0] SDLYBG1[1:0] SCYCBG2[1:0] SDLYBG2[1:0] SCYCBG3[1:0] SDLYBG3[1:0] SCYCBG4[1:0] SDLYBG4[1:0] SCYCBG5[1:0] SDLYBG5[1:0] SCYCBG6[1:0] SDLYBG6[1:0] ILEDBD5SET[3:0] ILEDBD6SET[3:0] ILEDBE0SET[3:0] ILEDBE1SET[3:0] ILEDBE2SET[3:0] ILEDBE3SET[3:0] ILEDBE4SET[3:0] ILEDBE5SET[3:0] ILEDBE6SET[3:0] ILEDBF0SET[3:0] ILEDBF1SET[3:0] ILEDBF2SET[3:0] ILEDBF3SET[3:0] ILEDBF4SET[3:0] ILEDBF5SET[3:0] ILEDBF6SET[3:0] ILEDBG0SET[3:0] ILEDBG1SET[3:0] ILEDBG2SET[3:0] ILEDBG3SET[3:0] ILEDBG4SET[3:0] ILEDBG5SET[3:0] ILEDBG6SET[3:0] www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 19/39 2010.02 - Rev.A BD26502GUL ●Register Map Technical Note Address 00H < Software Reset > Address R/W Bit7 (Index) 00H W Initial value 00H - Bit6 - Bit5 - Bit4 - Bit3 - Bit2 - Bit1 - Bit0 SFTRST 0 Bit 0 : SFTRST Software Reset “0” : Reset cancel “1” : Reset(All register initializing) *SFTRST register return to 0 automatically. Address 01H Address R/W Bit7 (Index) 01H W Initial value 00H 0 Bit6 0 Bit5 0 Bit4 0 Bit3 OSCEN 0 Bit2 0 Bit1 0 Bit0 0 Bit 3 : OSCEN OSC block ON/OFF control “0” : OFF(Initial) “1” : ON This register should not change into “1 “→” 0” at the time of START (30h, D0) register =“1” setup (under lighting operation). This register must be set to “0” after LED putting out lights (“START register = 0”), and please surely stop an internal oscillation circuit. Address 11H < LED1-6 Enable > Address R/W Bit7 (Index) 11H W Initial value 00H 0 Bit6 0 Bit5 LED6ON 0 Bit4 LED5ON 0 Bit3 LED4ON 0 Bit2 LED3ON 0 Bit1 LED2ON 0 Bit0 LED1ON 0 Bit 0 : LED1ON LED1 ON/OFF setting “0” : LED1 OFF(initial) “1” : LED1 ON Bit 1 : LED2ON LED2 ON/OFF setting “0” : LED2 OFF(initial) “1” : LED2 ON Bit 2 : LED3ON LED3 ON/OFF setting “0” : LED3 OFF(initial) “1” : LED3 ON Bit 3 : LED4ON LED4 ON/OFF setting “0” : LED4 OFF(initial) “1” : LED4 ON Bit 4 : LED5ON LED5 ON/OFF setting “0” : LED5 OFF(initial) “1” : LED5 ON Bit 5 : LED6ON LED6 ON/OFF setting “0” : LED6 OFF(initial) “1” : LED6 ON * Current setting follows ILEDAXXSET[3:0] or ILEDBXXSET[3:0] register. www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 20/39 2010.02 - Rev.A BD26502GUL Address 12H < LED7-12 Enable > Address R/W Bit7 (Index) 12H W Initial value 00H 0 Technical Note Bit6 0 Bit5 LED12ON 0 Bit4 LED11ON 0 Bit3 LED10ON 0 Bit2 LED9ON 0 Bit1 LED8ON 0 Bit0 LED7ON 0 Bit 0 : LED7ON LED7 ON/OFF setting “0” : LED7 OFF(initial) “1” : LED7 ON Bit 1 : LED8ON LED8 ON/OFF setting “0” : LED8 OFF(initial) “1” : LED8 ON Bit 2 : LED9ON LED9 ON/OFF setting “0” : LED9 OFF(initial) “1” : LED9 ON Bit 3 : LED10ON LED10 ON/OFF setting “0” : LED10 OFF(initial) “1” : LED10 ON Bit 4 : LED11ON LED11 ON/OFF setting “0” : LED11 OFF(initial) “1” : LED11 ON Bit 5 : LED12ON LED12 ON/OFF setting “0” : LED12 OFF(initial) “1” : LED12 ON * Current setting follows ILEDAXXSET[3:0] or ILEDBXXSET[3:0] register. Address 13H < LED13-17 Enable > Address R/W Bit7 Bit6 (Index) 13H W Initial value 00H 0 0 Bit5 0 Bit4 LED17ON 0 Bit3 LED16ON 0 Bit2 LED15ON 0 Bit1 LED14ON 0 Bit0 LED13ON 0 Bit 0 : LED13ON LED13 ON/OFF setting “0” : LED13 OFF(initial) “1” : LED13 ON Bit 1 : LED14ON LED14 ON/OFF setting “0” : LED14 OFF(initial) “1” : LED14 ON Bit 2 : LED15ON LED15 ON/OFF setting “0” : LED15 OFF(initial) “1” : LED15 ON Bit 3 : LED16ON LED16 ON/OFF setting “0” : LED16 OFF(initial) “1” : LED16 ON Bit 4 : LED17ON LED17 ON/OFF setting “0” : LED17 OFF(initial) “1” : LED17 ON * Current setting follows ILEDAXXSET[3:0] or ILEDBXXSET[3:0] register. www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 21/39 2010.02 - Rev.A BD26502GUL Address 17H < LED14-17 TDMA Enable > Address R/W Bit7 Bit6 (Index) 17H Initial value W 0FH 0 0 Technical Note Bit5 0 Bit4 0 Bit3 LED17 TDMAON 1 Bit2 LED16 TDMAON 1 Bit1 LED15 TDMAON 1 Bit0 LED14 TDMAON 1 Bit 0 : LED14TDMAON TDMA control Enable setting for LED14 “0” : TDMA control for LED14 is OFF LED current value is set by ILEDAD0SET[3:0] or ILEDBD0SET[3:0] (it changes by the OAB [7Fh, D1] register). It becomes the setting value of ILEDAD0SET [3:0] until scroll reset is carried out by SCLRST (2Eh, D0) register =“1” after a scroll stop, under scrolling. “1” : TDMA control for LED14 is ON (initial) Bit 1 : LED15TDMAON TDMA control Enable setting for LED15 “0” : TDMA control for LED15 is OFF LED current value is set by ILEDAE0SET[3:0] or ILEDBE0SET[3:0]. (it changes by the OAB [7Fh, D1] register). It becomes the setting value of ILEDAE0SET [3:0] until scroll reset is carried out by SCLRST (2Eh, D0) register =“1” after a scroll stop, under scrolling. “1” : TDMA control for LED15 is ON (initial) Bit 2 : LED16TDMAON TDMA control Enable setting for LED16 “0” : TDMA control for LED16 is OFF LED current value is set by ILEDAF0SET[3:0] or ILEDBF0SET[3:0]. (it changes by the OAB [7Fh, D1] register). It becomes the setting value of ILEDAF0SET [3:0] until scroll reset is carried out by SCLRST (2Eh, D0) register =“1” after a scroll stop, under scrolling. “1” : TDMA control for LED16 is ON (initial) Bit 3 : LED17TDMAON TDMA control Enable setting for LED17 “0” : TDMA control for LED17 is OFF LED current value is set by ILEDAG0SET[3:0] or ILEDBG0SET[3:0]. (it changes by the OAB [7Fh, D1] register). It becomes the setting value of ILEDAG0SET [3:0] until scroll reset is carried out by SCLRST (2Eh, D0) register =“1” after a scroll stop, under scrolling. “1” : TDMA control for LED17 is ON (initial) * The setting change at the time of START (30h, D0) register =“1” of this register is prohibition. * LED, which is set to “0”(TDMA off), is put on and not controlled by SYNC terminal however SYNCON (21h,D2) register is set to “1”. * Please use this register only in the following combination. LED17TDMAON 0 0 0 0 1 LED16TDMAON 0 0 0 1 1 LED15TDMAON 0 0 1 1 1 LED14TDMAON 0 1 1 1 1 Except the above: Prohibition www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 22/39 2010.02 - Rev.A BD26502GUL Address 20H < LED1-17 PWM setting > Address R/W Bit7 Bit6 (Index) 20H W Initial value 00H 0 0 Technical Note Bit5 0 Bit4 0 Bit3 0 Bit2 0 Bit1 0 Bit0 0 PWMSET [5:0] Bit 5-0 : PWMSET[5:0] LED1-17 PWM DUTY setting “000000” : 0/63＝0%(initial) “000001” : 1/63＝1.59% ： ： “100000” : 32/63＝50.8% ： ： “111110” : 62/63＝98.4% “111111” : 63/63＝100% *Please refer to Description of operation, chapter 2 Address 21H < SYNC operation control > Address R/W Bit7 Bit6 (Index) 21H W Initial value 00H 0 0 Bit5 0 Bit4 0 Bit3 SYNCACT 0 Bit2 SYNCON 0 Bit1 CLKOUT 0 Bit0 CLKIN 0 Bit 0 : CLKIN Selection CLK for PWM control “0” : Internal OSC (initial) “1” : External CLK input Bit 1 : CLKOUT Output CLK enable “0” : CLK is not output (initial) “1” : Output selected CLK from CLKOUT pin As for CLKIN & CLKOUT, setting change is forbidden under OSCEN (01h, D3) register =“1” and also under clock input to CLKIN terminal. Bit 2 : SYNCON SYNC operation enable “0” : Disable SYNC operation (initial) “1” : SYNC pin control LED driver ON/OFF Bit 3 : SYNCACT SYNC operation setting “0” : When SYNC pin is “L”, LED drivers are ON (initial) “1” : When SYNC pin is “H”, LED drivers are ON Address 2DH < PWM, SLOPE, SCROLL ON/OFF setting > Address R/W Bit7 Bit6 Bit5 (Index) 2DH W Initial value 00H 0 0 0 Bit4 0 Bit3 0 Bit2 PWMEN 0 Bit1 SLPEN 0 Bit0 SCLEN 0 Bit 0 : SCLEN SCROLL operation ON/OFF setting “0” : SCROL operation OFF(initial value) “1” : SCROL operation ON Bit 1 : SLPEN SLOPE operation ON/OFF setting “0” : SLOPE operation OFF(initial value) “1” : SLOPE operation ON Bit 2 : PWMEN PWM control at LED1-17 ON/OFF setting “0” : PWM operation is invalid(initial value) “1” : PWM operation is valid *Please refer to Description of operation, chapter 2 www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 23/39 2010.02 - Rev.A BD26502GUL Address 2EH < Reset scroll > Address R/W Bit7 (Index) 2EH W Initial value 00H 0 Technical Note Bit6 0 Bit5 0 Bit4 0 Bit3 0 Bit2 0 Bit1 0 Bit0 SCLRST 0 Bit 0 : SCLRST Reset scroll state “0” : Not reset(initial value) “1” : Reset scroll state * SCLRST register return to 0 automatically Address 2FH < Scroll setting > Address R/W Bit7 (Index) 2FH W Initial value 00H 0 Bit6 0 Bit5 SCLSPEED [2:0] 0 Bit4 0 Bit3 UP 0 Bit2 DOWN 0 Bit1 RIGHT 0 Bit0 LEFT 0 Bit 0 : LEFT Setting the scroll operation from right to left “0” : Scroll operation OFF (initial value) “1” : Scroll operation ON Bit 1 : RIGHT Setting the scroll operation from left to right “0” : Scroll operation OFF (initial value) “1” : Scroll operation ON *When LEFT operation is valid, RIGHT setting is ignored. Bit 2 : DOWN Setting the scroll operation from top to bottom “0” : Scroll operation OFF (initial value) “1” : Scroll operation ON Bit 3 : UP Setting the scroll operation from bottom to top “0” : Scroll operation OFF (initial value) “1” : Scroll operation ON *When UP operation is valid, DOWN setting is ignored. Bit 6-4 : SCLSPEED[2:0] Setting the scroll speed “000” : 0.1s (initial value) “001” : 0.2s “010” : 0.3s “011” : 0.4s “100” : 0.5s “101” : 0.6s “110” : 0.7s “111” : 0.8s *Setting time is based on OSC frequency, and the above-mentioned shows the value under Typ (1.2MHz). *Setting time changes on CLKIN terminal input frequency at the external clock operation. Example) CLKIN input frequency=1.2MHz→”000”: 0.1sec (it is the same as the above) CLKIN input frequency=2.4MHz→”000”: 0.05sec CLKIN input frequency= 0.6MHz→”000”: 0.2sec Address 30H < LED Matrix control > Address R/W Bit7 Bit6 (Index) 30H W Initial value 00H 0 0 Bit5 0 Bit4 0 Bit3 0 Bit2 0 Bit1 0 Bit0 START 0 Bit 0 : START Lighting/turning off bit of MATRIX LED(LED1-17) “0” : MATRIX LED(LED1-17) Lights out “1” : MATRIX LED(LED1-17) Lighting, SLOPE and SCROLL sequence start www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 24/39 2010.02 - Rev.A BD26502GUL Address 31H < Matrix data clear > Address R/W Bit7 (Index) 31H W Initial value 00H 0 Technical Note Bit6 0 Bit5 0 Bit4 0 Bit3 0 Bit2 0 Bit1 CLRB 0 Bit0 CLRA 0 Bit 0 : CLRA Reset A-pattern register “0” : A-pattern register is not reset and writable(initial value) “1” : A-pattern register is reset Bit 0 : CLRB Reset B-pattern register “0” : B-pattern register is not reset and writable(initial value) “1” : B-pattern register is reset *CLRA and CLRB register return to 0 automatically. Address 7FH < Register map change > Address R/W Bit7 Bit6 (Index) 7FH W Initial value 00H 0 0 Bit5 0 Bit4 0 Bit3 0 Bit2 IAB 0 Bit1 OAB 0 Bit0 RMCG 0 Bit 0 : RMCG Change register map “0” : Control register is selected(initial value) “1” : A-pattern register or B-pattern register is selected Bit 1 : OAB Select register to output for matrix “0” : A-pattern register is selected(initial value) “1” : B-pattern register is selected Bit 2 : IAB Select register to write matrix data “0” : A-pattern register is selected(initial value) “1” : B-pattern register is selected * It is prohibition to write A-pattern data when A-pattern is displaying (OAB=0). Also, it is prohibition to write B-pattern data when B-pattern is displaying (OAB=1). Change of a display picture should be done by change of the OAB register, after updating of a non-displaying pattern register. www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 25/39 2010.02 - Rev.A BD26502GUL Address 01H-77H < A-pattern register data > Address R/W Bit7 Bit6 (Index) 01-77H W SCYCAXX [1:0] Initial value 08H 0 0 Technical Note Bit5 0 Bit4 0 Bit3 1 Bit2 0 Bit1 0 Bit0 0 SDLYAXX [1:0] ILEDAXXSET [3:0] Bit 3-0 : ILEDAXXSET[3:0] LED output current setting for A-pattern matrix data “0000” : 0.00mA “0001” : 1.33mA “0010” : 2.67mA “0011” : 4.00mA “0100” : 5.33mA “0101” : 6.67mA “0110” : 8.00mA “0111” : 9.33mA “1000” : 10.67mA(initial value) “1001” : 12.00mA “1010” : 13.33mA “1011” : 14.67mA “1100” : 16.00mA “1101” : 17.33mA “1110” : 18.67mA “1111” : 20.00mA Bit 5-4 : SDLYAXX[1:0] SLOPE delay setting for A-pattern matrix “00” : No delay(initial value) “01” : 1/4x(slope cycle time) “10” : 1/2x(slope cycle time) “11” : 3/4x(slope cycle time) Bit 7-6 : SCYCAXX[1:0] SLOPE cycle time setting for A-pattern matrix “00” : No SLOPE control(initial value) “01” : 1s(=slope cycle time) “10” : 2s(=slope cycle time) “11” : 3s(=slope cycle time) * The “XX” shows the matrix number from “00” to “G6”. Please refer 7x17 LED Matrix coordinate. *Setting time is based on OSC frequency, and the above-mentioned shows the value under Typ (1.2MHz). *Setting time changes on CLKIN terminal input frequency at the external clock operation. Example) CLKIN input frequency=1.2MHz→”01”: Slope cycle =1sec (it is the same as the above) CLKIN input frequency=2.4MHz→”01”: Slope cycle =0.5sec CLKIN input frequency=0.6MHz→”01”: Slope cycle =2sec www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 26/39 2010.02 - Rev.A BD26502GUL Address 01H-77H < B-pattern register data > Address R/W Bit7 Bit6 (Index) 01-77H W SCYCBXX[1:0] Initial value 08H 0 0 Technical Note Bit5 0 Bit4 0 Bit3 1 Bit2 0 Bit1 0 Bit0 0 SDLYBXX[1:0] ILEDBXXSET[3:0] Bit 3-0 : ILEDBXXSET[3:0] LED output current setting for B-pattern matrix data “0000” : 0.00mA “0001” : 1.33mA “0010” : 2.67mA “0011” : 4.00mA “0100” : 5.33mA “0101” : 6.67mA “0110” : 8.00mA “0111” : 9.33mA “1000” : 10.67mA(initial value) “1001” : 12.00mA “1010” : 13.33mA “1011” : 14.67mA “1100” : 16.00mA “1101” : 17.33mA “1110” : 18.67mA “1111” : 20.00mA Bit 5-4 : SDLYBXX[1:0] SLOPE delay setting for B-pattern matrix “00” : No delay(initial value) “01” : 1/4x(slope cycle time) “10” : 1/2x(slope cycle time) “11” : 3/4x(slope cycle time) Bit 7-6 : SCYCBXX[1:0] SLOPE cycle time setting for B-pattern matrix “00” : No SLOPE control(initial value) “01” : 1s(=slope cycle time) “10” : 2s(=slope cycle time) “11” : 3s(=slope cycle time) * The “XX” shows the matrix number from “00” to “G6”. Please refer 7x17 LED Matrix coordinate. *Setting time is based on OSC frequency, and the above-mentioned shows the value under Typ (1.2MHz). *Setting time changes on CLKIN terminal input frequency at the external clock operation. Example) CLKIN input frequency=1.2MHz→”01”: Slope cycle =1sec (it is the same as the above) CLKIN input frequency=2.4MHz→”01”: Slope cycle =0.5sec CLKIN input frequency=0.6MHz→”01”: Slope cycle =2sec www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 27/39 2010.02 - Rev.A BD26502GUL ●Description of operation 1. LED Matrix Technical Note 1-1. Lighting method of dot Matrix It can control 7 x 17 Matrix. V INSW SW 1 00 01 02 03 04 05 06 LED1 LED2 10 11 12 13 14 15 16 LED3 20 21 22 23 24 25 26 LED4 30 31 32 33 34 35 36 LED5 40 41 42 43 44 45 46 LED6 50 51 52 53 54 55 56 LED7 60 61 62 63 64 65 66 LED8 70 71 72 73 74 75 76 LED9 80 81 82 83 84 85 86 LED10 90 91 92 93 94 95 96 LED11 A0 A1 A2 A3 A4 A5 A6 LED12 B0 B1 B2 B3 B4 B5 B6 LED13 C0 C1 C2 C3 C4 C5 C6 LED14 D0 D1 D2 D3 D4 D5 D6 LED15 E0 E1 E2 E3 E4 E5 E6 LED16 F0 F1 F2 F3 F4 F5 F6 G0 G1 G2 G3 G4 G5 G6 LED17 T 00 SW 2 T 01 SW 3 T 02 SW 4 T 03 SW 5 T 04 SW 6 T 05 SW 7 T 06 TDMA TDMA TDMA TDMA TDMA TDMA TDMA TDMA TDMA TDMA TDMA TDMA TDMA TDMA TDMA Fig.10 7 x 17 LED Matrix coordinate The SW1 – SW7 is turned on by serial. LED is driven one by one within the ON period. SW 1 SW 2 SW 3 SW 4 SW 5 SW 6 SW 7 L ED1 ・ ・ ・ ・ ・ D A00 DA01 DA02 DA03 DA04 DA05 TDMA D A06 DA00 D A02 LED17 D AG0 DAG1 DAG2 DAG3 DAG4 D AG5 D AG6 DAG0 D AG2 D AG3 P W M period ＝ 635clk （ @ 1.2MHz 、 529.2us ） 1 /7TDMA period ＝ 680clk （ @ 1.2MHz 、 566.67us ） TDMA period ＝ 4760clk （ @ 1.2MHz 、 3.97m s ） D uty is variable 0/63 and between 1/63 and 63/63 of PW M period. Fig.11 SW timing www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. TDMA D A03 28/39 2010.02 - Rev.A BD26502GUL 1-2. LED lighting example The firefly lighting example. The following command set is the example of LED matrix firefly lighting. It can control the turn on/off time in detail by SLOPE setting registers. 1) 2) 3) 4) 5) 6) 7) 8) 9) 10) 11) 12) 13) 7FH 21H 01H 11H 12H 13H 20H 1FH 01-77H 7FH 2DH 30H 30H 00000000 00000000 00001000 00111111 00111111 00011111 00111111 00000001 xxxxxxxx 00000000 00000100 00000001 00000000 Technical Note Select control register Select internal OSC for CLK Start OSC Set LED1-6 enable Set LED7-12 enable Set LED13-17 enable Set Max Duty at Slope Select A-pattern or B-pattern register, Select A-pattern register to write matrix data Write A-pattern data Select control register, Select A-pattern register to output for matrix Set SLOPE control enable Start SLOPE sequence Lights out www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 29/39 2010.02 - Rev.A BD26502GUL 2. LED Driver Current, SLOPE and SCROLL Sequence Control 2-1. LED driver current control It can be controlled PWM Duty and DC current for LED driver current. Item (A) (B) PWM Duty DC current Control object Whole matrix Each matrix dot Control detail 0/63~63/63 (64 step) 0~20.00mA (16 step) Technical Note Setting Registers Name * PWMSET ILEDAXXSET ILEDBXXSET Bits 6 4 * The “XX” shows the matrix number from “00” to “G6”. Please refer 7x17 LED Matrix coordinate. Minimum width=5clk (A) PWM Duty Duty is variable by PWMSET[5：0] or slope control between 0/63 and 63/63. （Duty 1/63=10clk） LED Drive Internal enable signal OFF Clk (ex.1.2MHz at internal OSC) ~ ~ ~ 680clk = 1/7TDMA ~ Fig.12 LED output current timing and PWM cycle 635clk of PWM period is set in the 1/7 TDMA period (680clk). PWM is operated 63 steps of 10clk. TDMA period is 3.97s (@1.2MHz). Moreover, it has the starting waiting time of a constant current driver by 5clk(s). PWM”H” time turns into ON time after waiting 5 clk. (However, LED driver is set “OFF” compulsorily at PWM=0% setting.) 5clk wait LED Drive Internal enable signal OFF PWM = 0/63 setting 0mA PWM = 1/63 setting 5clk 1/63 = 10clk PWM = 2/63 setting 5clk 2/63 = 20clk Fig.13 LED output current timing and a PWM cycle www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 30/39 2010.02 - Rev.A BD26502GUL 2-2. SLOPE control It can be controlled Delay and SLOPE cycle time for LED driver current. Item (A) (B) Delay SLOPE cycle time Control object Each matrix dot Each matrix dot Control detail 0~3/4 x slope cycle time (4 step) 0~3sec (4 step) Technical Note Setting Registers Name * SDLYAXX SDLYBXX SCYCAXX SCYCBXX Bits 2 2 * The “XX” shows the matrix number from “00” to “G6”. Please refer 7x17 LED Matrix coordinate. PWM Duty 1/4 of SLOPE cycle time 100% 0% SLOPE 1 (A) Delay START SLOPE 2 SLOPE 3 SLOPE 4 Repeat SLOPE 1-4 Time (B) SLOPE cycle time Fig.14 SLOPE operation When SLPEN=“1” and PWMEN=SCLEN=“0”, SLOPE operation starts (like upper figure). After “Delay” time SLOPE1-4 operation repeat. Each period of SLOPE1-4 is 1/4 of SLOPE cycle time. SLOPE 1: 1 step is 1/63 of SLOPE 1 period. Duty is increased 1.587% step by step. SLOPE 2: Duty is fixed at 100%. SLOPE 3: 1 step is 1/63 of SLOPE 1 period. Duty is decreased 1.587% step by step. SLOPE 4: Duty is fixed at 0%. www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 31/39 2010.02 - Rev.A BD26502GUL 2-3. SCROLL control 2-3-1 Normal operation A-pattern data B-pattern data Technical Note LEFT scroll RIGHT scroll UP scroll DOWN scroll 2-3-2 Operation at TDMA off setting (The following is the matrix arrangement which has not assigned LED16-LED17.) A-pattern data TDMA off B-pattern data TDMA off LEFT scroll RIGHT scroll UP scroll DOWN scroll www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 32/39 2010.02 - Rev.A BD26502GUL 2-4. Relation of PWM, SLOPE and SCROLL control Register of condition and enable PWM Condition Enable Combination of command Operation 1 2 3 4 5 Do not use this combination PWMSET [5:0] PWMEN SLOPE SCYCXXX [1:0] SDLYXXX [1:0] SLPEN Technical Note SCROLL SCLSPEED [2:0] UP/DOWN/RIGHT/LEFT SCLEN PWMEN OFF ON OFF ON OFF ON OFF ON SLPEN OFF OFF ON ON OFF OFF ON ON SCLEN OFF OFF OFF OFF ON ON ON ON P W M D uty 1 00% Operation 1 0% S TA RT Tim e P W M D uty 1 00% Operation 2 D uty set at PW M SE T[5:0] （ 0/63 ～ 63/63 ） 0% S TA RT P W M D uty D elay S LO P E c y c le tim e 1 00% 0% S TA RT P W M D uty D elay S LO P E cyc le tim e D uty s et at PW M S E T[5:0] （ 0/63 ～ 63/63 ） Tim e 1 00% 0% S TA RT Tim e Tim e Operation 3 Operation 4 PWM Duty 100% 0% START Time Operation 5 www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 33/39 2010.02 - Rev.A BD26502GUL 3. Power up sequence Technical Note V BAT T VBATON1 T VBATO N2 T VBATOFF1 T VBATO FF2 T VINSW O FF VINSW T VINSW ON V IO T VIOO N=min 0.5m s T VIO O FF=m in 1m s R ESETB T RSTB=m in 0.1m s C OM MAND Inhibit Possible T RST=m in 0m s I nhibit Fig.15 Power up sequence Please take sufficient wait time for each Power/Control signal. However, if VBATTTSD(typ:175℃), the command input is not effective because of the protection operation 4. Reset There are two kinds of reset, software reset and hardware reset (1)Software reset ・All the registers are initialized by SFTRST=“1”. ・SFTRST is an automatically returned to “0”. (Auto Return 0). (2)Hardware reset ・It shifts to hardware reset by changing RESETB pin “H” → “L”. ・The condition of all the registers under hardware reset pin is returned to the Initial Value and it stops accepting all address.all LED driver turn off. ・It’s possible to release from a state of hardware reset by changing RESETB pin “L” → “H”. RESETB pin has delay circuit. It doesn’t recognize as hardware reset in “L” period under 5μs. 5. Thermal shutdown A thermal shutdown function is effective at all blocks of those other than VREF. Return to the state before detection automatically at the time of release. The thermal shutdown function is detection temperature that it works is about 175℃ Detection temperature has a hysteresis, and detection release temperature is about 150℃(Design reference value) 6. UVLO Function (VBAT Voltage Low-Voltage Detection) UVLO function is effective at all blocks of those other than VREF, and when detected, those blocks function is stopped. Return to the state before detection automatically at the time of release. www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 34/39 2010.02 - Rev.A BD26502GUL Technical Note 7. I/O When the RESETB pin is Low, the input buffers (SDA and SCL) are disabling for the Low consumption power. VBAT VIO SCL (SDA) EN RESETB=L, Output “H” Level Shift LOGIC RESETB Fig.16 Input disabling by RESETB 8. Standard Clock Input and Output It is possible to carry out synchronous operation of two or more ICs using the input-and-output function of a standard clock. CLKOUT Register : CLKOUT CLKIN PMOS TDMA Switch LED Matrix OSC SEL Controller LED Register : CLKIN SYNC Driver Register: SYNCON Fig.17 I/O part equivalent circuit diagram ・When a clock is supplied from the exterior Inputting an external standard clock from CLKIN and setting register CLKIN=1, IC operates with the clock inputted from CLKIN as a standard clock. ・When the built-in oscillation circuit of one IC is used When a clock cannot be supplied from the exterior, it is possible to synchronize between ICs by the connection as the following figure. When a clock is strung IC1 IC2 IC3 OSC OSC OSC CLKIN CLKOUT CLKIN CLKOUT CLKIN CLKOUT When a clock is supplied from IC1 IC1 IC2 IC3 OSC OSC OSC CLKIN CLKOUT CLKIN CLKOUT CLKIN CLKOUT Fig.18 It is an example of application for the usage of two or more. www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 35/39 2010.02 - Rev.A BD26502GUL 9. External ON/OFF Synchronization (SYNC Terminal) Lighting of LED that synchronized with the external signal is possible. By setting H/L of SYNC terminal, LED drivers output is set ON/OFF. It’s asynchronous operation with the internal TDMA control. CLKOUT Technical Note Register : CLKOUT CLKIN PMOS TDMA Switch LED Matrix OSC SEL Controller LED Register : CLKIN SYNC Driver Register : SYNCON Fig.19 I/O part equivalent circuit diagram 10. About terminal processing of the function which is not used Please set up a test terminal and the unused terminal as the following table. Especially, if an input terminal is not fixed, it may occur the unstable state of a device and the unexpected internal current. Terminal name SYNC CLKIN CLKOUT TEST1 – TEST5 TESTO DO LED Terminal SW Terminal Processing GND Short GND Short Open GND Short Open Open GND Short VINSW Short The input terminal The input terminal The output terminal The input terminal for a test The output terminal for a test The output terminal In order to avoid an unfixed state. (A register setup in connection with LED terminal that is not used is forbidden.) In order to avoid an unfixed state. (A register setup in connection with SW terminal that is not used is forbidden.) Reason www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 36/39 2010.02 - Rev.A BD26502GUL ●PCB pattern of the Power dissipation measuring board Technical Note 1st layer(component) 2nd layer 3rd layer 4th layer 5th layer 6th layer 7th layer 8th layer(solder) www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 37/39 2010.02 - Rev.A BD26502GUL Technical Note ●Notes for use (1) Absolute Maximum Ratings An excess in the absolute maximum ratings, such as supply voltage, temperature range of operating conditions, etc., can break down devices, thus making impossible to identify breaking mode such as a short circuit or an open circuit. If any special mode exceeding the absolute maximum ratings is assumed, consideration should be given to take physical safety measures including the use of fuses, etc. (2) Power supply and ground line Design PCB pattern to provide low impedance for the wiring between the power supply and the ground lines. Pay attention to the interference by common impedance of layout pattern when there are plural power supplies and ground lines. Especially, when there are ground pattern for small signal and ground pattern for large current included the external circuits, please separate each ground pattern. Furthermore, for all power supply pins to ICs, mount a capacitor between the power supply and the ground pin. At the same time, in order to use a capacitor, thoroughly check to be sure the characteristics of the capacitor to be used present no problem including the occurrence of capacity dropout at a low temperature, thus determining the constant. (3) Ground voltage Make setting of the potential of the ground pin so that it will be maintained at the minimum in any operating state. Furthermore, check to be sure no pins are at a potential lower than the ground voltage including an actual electric transient. (4) Short circuit between pins and erroneous mounting In order to mount ICs on a set PCB, pay thorough attention to the direction and offset of the ICs. Erroneous mounting can break down the ICs. Furthermore, if a short circuit occurs due to foreign matters entering between pins or between the pin and the power supply or the ground pin, the ICs can break down. (5) Operation in strong electromagnetic field Be noted that using ICs in the strong electromagnetic field can malfunction them. (6) Input pins In terms of the construction of IC, parasitic elements are inevitably formed in relation to potential. The operation of the parasitic element can cause interference with circuit operation, thus resulting in a malfunction and then breakdown of the input pin. Therefore, pay thorough attention not to handle the input pins, such as to apply to the input pins a voltage lower than the ground respectively, so that any parasitic element will operate. Furthermore, do not apply a voltage to the input pins when no power supply voltage is applied to the IC. In addition, even if the power supply voltage is applied, apply to the input pins a voltage lower than the power supply voltage or within the guaranteed value of electrical characteristics. (7) External capacitor In order to use a ceramic capacitor as the external capacitor, determine the constant with consideration given to a degradation in the nominal capacitance due to DC bias and changes in the capacitance due to temperature, etc. (8) Thermal shutdown circuit (TSD) This LSI builds in a thermal shutdown (TSD) circuit. When junction temperatures become detection temperature or higher, the thermal shutdown circuit operates and turns a switch OFF. The thermal shutdown circuit, which is aimed at isolating the LSI from thermal runaway as much as possible, is not aimed at the protection or guarantee of the LSI. Therefore, do not continuously use the LSI with this circuit operating or use the LSI assuming its operation. (9) Thermal design Perform thermal design in which there are adequate margins by taking into account the permissible dissipation (Pd) in actual states of use. (10) About the pin for the test, the un-use pin Prevent a problem from being in the pin for the test and the un-use pin under the state of actual use. Please refer to a function manual and an application notebook. And, as for the pin that doesn't specially have an explanation, ask our company person in charge. (11) About the rush current For ICs with more than one power supply, it is possible that rush current may flow instantaneously due to the internal powering sequence and delays. Therefore, give special consideration to power coupling capacitance, power wiring, width of ground wiring, and routing of wiring. (12) About the function description or application note or more. The function description and the application notebook are the design materials to design a set. So, the contents of the materials aren't always guaranteed. Please design application by having fully examination and evaluation include the external elements. www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 38/39 2010.02 - Rev.A BD26502GUL ●Ordering part number Technical Note B D 2 Part No. 6 5 0 2 G U L - E 2 Part No. Package GUL : VCSP50L4 Packaging and forming specification E2: Embossed tape and reel VCSP50L4 (BD26502GUL) 1PIN MARK 4.10±0.05 0.1±0.05 0.55MAX Tape Quantity Direction of feed S 0.3±0.05 Embossed carrier tape 2500pcs E2 The direction is the 1pin of product is at the upper left when you hold 4.10±0.05 ( reel on the left hand and you pull out the tape on the right hand ) 62-φ0.25±0.05 0.05 A B H G F E D C B A 0.06 S A B (φ0.15)INDEX POST 1 2 34567 8 P=0.5×7 0.3±0.05 P=0.5×7 1pin Direction of feed (Unit : mm) Reel ∗ Order quantity needs to be multiple of the minimum quantity. www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 39/39 2010.02 - Rev.A Notice Notes No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM Co.,Ltd. The content specified herein is subject to change for improvement without notice. The content specified herein is for the purpose of introducing ROHM's products (hereinafter "Products"). If you wish to use any such Product, please be sure to refer to the specifications, which can be obtained from ROHM upon request. Examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the Products. The peripheral conditions must be taken into account when designing circuits for mass production. Great care was taken in ensuring the accuracy of the information specified in this document. However, should you incur any damage arising from any inaccuracy or misprint of such information, ROHM shall bear no responsibility for such damage. The technical information specified herein is intended only to show the typical functions of and examples of application circuits for the Products. ROHM does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or other rights held by ROHM and other parties. ROHM shall bear no responsibility whatsoever for any dispute arising from the use of such technical information. The Products specified in this document are intended to be used with general-use electronic equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices). The Products specified in this document are not designed to be radiation tolerant. While ROHM always makes efforts to enhance the quality and reliability of its Products, a Product may fail or malfunction for a variety of reasons. Please be sure to implement in your equipment using the Products safety measures to guard against the possibility of physical injury, fire or any other damage caused in the event of the failure of any Product, such as derating, redundancy, fire control and fail-safe designs. ROHM shall bear no responsibility whatsoever for your use of any Product outside of the prescribed scope or not in accordance with the instruction manual. The Products are not designed or manufactured to be used with any equipment, device or system which requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of human injury (such as a medical instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuelcontroller or other safety device). ROHM shall bear no responsibility in any way for use of any of the Products for the above special purposes. If a Product is intended to be used for any such special purpose, please contact a ROHM sales representative before purchasing. If you intend to export or ship overseas any Product or technology specified herein that may be controlled under the Foreign Exchange and the Foreign Trade Law, you will be required to obtain a license or permit under the Law. Thank you for your accessing to ROHM product informations. More detail product informations and catalogs are available, please contact us. ROHM Customer Support System http://www.rohm.com/contact/ www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. R1010A