Datasheet
Sound Processors for Home Theater Systems
7.1ch Sound Processor for High-Quality Audio
with Built-in Micro-step Volume
BD34704KS2
Key Specifications
General description
The BD34704KS2 is an 8ch independent volume system
realized high-quality sound by improved specification of
op-amp and optimized layout of the element.The system
is designed to allow 7.1ch surround system application.
Micro-step volume can reduce the switching pop noise
during volume attenuation, so a high quality audio
system could be achieved.
This IC is available 12ch single-end input selectors to
maximum 3 zones. And also available 2 system multi
input selector.
Total harmonic distortion:
Maximum output voltage:
Output noise voltage:
Residual output noise voltage:
Cross-talk between channels:
Cross-talk between selectors:
Package
SQFP-T80C
0.0004%(Typ)
4.2Vrms(Typ)
1.2μVrms(Typ)
1.0μVrms(Typ)
-105dB(Typ)
-105dB(Typ)
W(Typ) x D(Typ) x H(Max)
16.00mm x 16.00mm x 1.60mm
Features
12ch input selectors
(It is extendable to up to 18 in case of no use other
functions such as Multi input, REC output and SUB
output)
Micro-step volume can reduce the switching pop
noise during volume attenuation
Zone 3 is supported
2ch sub-volume for zone output that is available for
independent control with a micro step function
2-wire serial bus control, corresponding to 3.3/5V
SQFP-T80C
Applications
Suitable for the AV receivers, home theater systems,
etc
Typical Application Circuit
Figure 1. Application Circuit
○Product structure：Silicon monolithic integrated circuit
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58 INL1
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47 INR6
46 INL7
45 INR7
44 INL8
43 INR8
42 INL9
41 INR9
OUTSL 15
OUTSR 16
OUTSBL 17
OUTSBR 18
OUTPL 19
OUTPR 20
48 INL6
50 INL5
49 INR5
52 INL4
51 INR4
53 INR3
55 INR2
54 INL3
56 INL2
OUTC 14
N.C. 13
OUTSW 12
N.C. 11
OUTFR 10
N.C. 9
OUTFL 8
VEE2 7
N.C. 6
VEE1 5
57 INR1
59 GND
CL 2
VCC 3
DGND 4
60 SBRIN
DA 1
BD34704KS2
Datasheet
Pin Configuration
Figure 2. Pin Configuration
TSZ02201-0C2C0E100210-1-2
2015.2.25 Rev.002
Datasheet
BD34704KS2
Description of terminal
Terminal
Number
Symbol
Data and latch input terminal
41
INR9(SBRIN2)
Rch input terminal 9
Clock input terminal
42
INL9(SBLIN2)
Lch input terminal 9
Positive power supply terminal
43
INR8
Rch input terminal 8
DGND
Digital ground terminal
44
INL8
Lch input terminal 8
5
VEE1
Negative power supply terminal 1
45
INR7
Rch input terminal 7
6
N.C.
No connect
46
INL7
Lch input terminal 7
7
VEE2
Negative power supply terminal 2
47
INR6
Rch input terminal 6
8
OUTFL
FLch Output terminal
48
INL6
Lch input terminal 6
9
N.C.
No connect
49
INR5
Rch input terminal 5
10
OUTFR
FRch Output terminal
50
INL5
Lch input terminal 5
11
N.C.
No connect
51
INR4
Rch input terminal 4
12
OUTSW
SWch Output terminal
52
INL4
Lch input terminal 4
13
N.C.
No connect
53
INR3
Rch input terminal 3
14
OUTC
Cch Output terminal
54
INL3
Lch input terminal 3
15
OUTSL
SLch Output terminal
55
INR2
Rch input terminal 2
16
OUTSR
SRch Output terminal
56
INL2
Lch input terminal 2
17
OUTSBL
SBLch Output terminal
57
INR1
Rch input terminal 1
18
OUTSBR
SBRch Output terminal
58
INL1
Lch input terminal 1
19
OUTPL
Lch PRE Output terminal
59
GND
Analog ground terminal
20
OUTPR
Rch PRE Output terminal
60
SBRIN
SBRch DSP input terminal
21
GND
Analog ground terminal
61
SBLIN
SBLch DSP input terminal
22
GND
Analog ground terminal
62
SRIN
SRch DSP input terminal
23
GND
Analog ground terminal
63
SLIN
SLch DSP input terminal
24
GND
Analog ground terminal
64
CIN
Cch DSP input terminal
25
GND
Analog ground terminal
65
SWIN
SWch DSP input terminal
26
GND
Analog ground terminal
66
FRIN
FRch DSP input terminal
27
GND
Analog ground terminal
67
FLIN
FLch DSP input terminal
28
SUBR
Rch SUB Output terminal
68
FRIN3
FRch DSP input terminal 3
29
SUBL
Lch SUB Output terminal
69
FLIN3
FLch DSP input terminal 3
30
RECR
Rch REC Output terminal
70
GND
Analog ground terminal
31
RECL
Lch REC Output terminal
71
ADCR
Rch ADC Output terminal
32
GND
Analog ground terminal
72
ADCL
Lch ADC Output terminal
33
INR12(FRIN2)
Rch input terminal 12
73
GND
Analog ground terminal
34
INL12(FLIN2)
Lch input terminal 12
74
GND
Analog ground terminal
35
INR11(CIN2)
Rch input terminal 11
75
GND
Analog ground terminal
36
INL11(SWIN2)
Lch input terminal 11
76
GND
Analog ground terminal
37
INR10(SRIN)
Rch input terminal 10
77
GND
Analog ground terminal
38
INL10(SLIN2)
Lch input terminal 10
78
GND
Analog ground terminal
39
GND
Analog ground terminal
79
GND
Analog ground terminal
40
N.C.
No connect
80
CHIP
Chip select terminal
Terminal
Number
Symbol
1
DA
2
CL
3
VCC
4
Function
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Function
TSZ02201-0C2C0E100210-1-2
2015.2.25 Rev.002
Datasheet
BD34704KS2
Block Diagram
Figure 3. Block Diagram
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Datasheet
BD34704KS2
Absolute Maximum Ratings
Item
Symbol
Rating
Unit
Positive power supply
VCC
+7.75
(Note1)
V
Negative power supply
VEE
-7.75
(Note1)
V
Power dissipation
Pd
1.75
(Note2)
W
Input voltage
Vin
Operating temperature
Topr
Storage temperature
Tastg
(Note1)
(Note2)
(Note3)
Caution:
VEE-0.2 ~ VCC+0.2
-40 ~ +85
(Note3)
-55 ~ +150
V
°C
°C
The maximum voltage that can be applied based on GND.
Derating at 14.0mW/°C for operating above Ta≥25°C (mounted on 70×70×1.6mm ROHM standard board)
If it is within the operating voltage range, circuit functions and operation are guaranteed within this
operating temperature.
Operating the IC over the absolute maximum ratings may damage the IC. The damage can
either be a short circuit between pins or an open circuit between pins and the internal circuitry. Therefore,
it is important to consider circuit protection measures, such as adding a fuse, in case the IC is operated
over the absolute maximum ratings.
Operating Condition
Item
Symbol
Rating
Positive power supply
VCC
+6.5 ~ +7.5
Negative power supply
VEE
-6.5 ~ -7.5
(Note4)
(Note5)
Unit
(Note4,5)
(Note4,5)
V
V
Applying voltage based on GND.
Within the operating temperature range, basic circuit function and operation are guaranteed within this operation
voltage range. But please confirm the setting of the constants, temperature, etc. Please take note that
electrical characteristics other than defined values cannot be guaranteed, however original function will retain.
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Datasheet
BD34704KS2
Electrical characteristic
Unless otherwise specified, Ta=25°C, VCC=7V, VEE=-7V, f=1kHz, Vin=1Vrms, RL=10kΩ,
Stereo input selector(MAIN, SUB1, SUB2)=IN1, Mode selector(FL, FRch)=MAIN,
Mode selector(SW, C, SL, SRch)=MULTI, Mode selector(SBL, SBRch)=MULTI, SB OUTSEL=SB,
Input Att=0dB, Input gain=0dB, Volume=0dB.
Item
TOTAL
Symbol
Limit
Min
Typ
Max
Unit
Conditions
Positive circuit current
Iqp
-
32
45
mA
No signal
Negative circuit current
Iqn
-45
-32
-
mA
No signal
Output voltage gain
Gv
-1.5
0
1.5
dB
Channel balance
CB
-0.5
0
0.5
dB
Total harmonic distortion
+ Noise
THD
-
0.0004
0.02
%
Maximum output voltage
Vom
3.8
4.2
-
Vrms
Output noise voltage *
Vno
-
1.2
10
µVrms
Residual output noise
voltage *
Vnor
-
1
8
µVrms
Cross-talk between
channels *
CT
-
-105
-80
dB
Cross-talk between
selectors *
CS
-
-105
-80
dB
Input impedance
Rin
70
100
130
kΩ
8, 10, 12, 14~18 pin
output
C Channel reference,
8, 10, 12, 14~18 pin
output
BW=400~30kHz
8, 10, 12, 14~18 pin
output
THD=1%,
VOLUME=+10dB
8, 10, 12, 14~18 pin
output
Rg=0Ω, BW=IHF-A
8, 10, 12, 14~18 pin
output
Volume=Mute,
Rg=0Ω, BW=IHF-A
8, 10, 12, 14~18 pin
output
Rg=0Ω, BW=IHF-A
8, 10 pin output
Rg=0Ω, BW=IHF-A
8, 10, 12, 14~18 pin
output
28~31, 33~38, 41~58
60~69 pin input
VOLUME
Maximum attenuation *
ATTmax
-
-115
-100
dB
Volume=Mute, BW=IHF-A
REC
OUT
Total harmonic distortion
THDR
-
0.0005
0.02
%
BW=400~30kHz,
RL=6.8kΩ
28~31 pin output
PRE
OUT
Output impedance
Ron
520
800
1080
Ω
19, 20 pin output
※VP-9690(Average value detection, effective value display) filter by Panasonic is used for * measurement.
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Datasheet
BD34704KS2
Typical Performance Curve(s)
50
40
20
Volume Gain[dB]
Consumption Current[mA]
30
10
0
Operational
range
-10
-20
-30
-40
-50
0
1
2
3
4
5
6
7
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
0
-2
10
8
100
1000
10000
100000
VCC(+)/VEE(-)[V]
Frequency[Hz]
Figure 5. Volume Gain vs. Input Frequency
(32dB to 0 dB setting)
2
0
-2
-4
-6
-8
-10
-12
-14
-16
-18
-20
-22
-24
-26
-28
-30
-32
-34
Volume Gain[dB]
Volume Gain[dB]
Figure 4. Circuit Currents vs. Circuit Voltage
10
100
1000
10000
100000
10
100
1000
10000
100000
Frequency[Hz]
Frequency[Hz]
Figure 6. Volume Gain vs. Input Frequency
(0dB to -32 dB setting)
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-30
-32
-34
-36
-38
-40
-42
-44
-46
-48
-50
-52
-54
-56
-58
-60
-62
-64
-66
Figure 7. Volume Gain vs. Input Frequency
(-32dB to -64 dB setting)
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Datasheet
-60
-62
-64
-66
-68
-70
-72
-74
-76
-78
-80
-82
-84
-86
-88
-90
-92
-94
-96
-98
1.0000
0.1000
10kHz
100Hz
THD+N[%]
Volume Gain[dB]
BD34704KS2
1 kHz
0.0100
0.0010
10
100
1000
10000
0.0001
0.001
100000
Frequency[Hz]
0.010
0.100
1.00 0
10.000
Input Voltage[Vrms]
Figure 8. Volume Gain vs. Input Frequency
(-64dB to -95 dB setting)
Figure 9. THD + N vs. Input Voltage
(Note) The measurement results of Figure 4 to Figure 8 used by 80kHz LPF.
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Datasheet
BD34704KS2
Specifications for Control Signal
(4) Timing of control signal
Data is read at the rising edge of clock.
Latch is read at the falling edge of clock. Data on the latest 16bit is taken inside the IC.
Ensure to set DA and CL to LOW after Latch.
1byte=16bit
CL
( CLOCK）
tsu
90%
90%
twc
10%
thd
DA
DATA
LATCH
90%
twd
ts
90%
DATA
th
90%
10%
10%
tsd
thd
tsl
90%
twh
10%
90%
twc
90%
DATA
10%
thl
10%
90%
twl
LATCH
Figure 10. The timing definition of the control signal
Item
Symbol
Clock width
Data width
Latch width
Low hold width
Data setup time (DATA→CLK)
Data hold time (CLK→DATA)
Latch setup time (CLK→LATCH)
Latch hold time (DATA→LATCH)
Latch Low setup time
Latch Low hold time
twc
twd
twl
twh
tsd
thd
tsl
thl
ts
th
Limit
Typ
-
Min
1.0
1.0
1.0
1.0
0.5
0.5
0.5
0.5
0.5
0.5
Max
-
Unit
µsec
µsec
µsec
µsec
µsec
µsec
µsec
µsec
µsec
µsec
(2) Voltage of control signal (CL, DA, CHIP)
Limit
Item
High input voltage
Low input voltage
(3) Basic Structure of Control Data
←Input Direction
D15 D14 D13 D12 D11
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Conditions
VCC=+6.5 to +7.5V
VEE=-6.5 to -7.5V
D10
D9
Data
D8
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D7
Min
Typ
Max
( Pin A and VEE > Pin B, the P-N junction operates as a parasitic diode.
When VEE > Pin B, the P-N junction operates as a parasitic transistor.
Parasitic diodes inevitably occur in the structure of the IC. The operation of parasitic diodes can result in mutual
interference among circuits, operational faults, or physical damage. Therefore, conditions that cause these diodes to
operate, such as applying a voltage lower than the VEE voltage to an input pin (and thus to the P substrate) should
be avoided.
Resistor
Transistor(NPN)
Pin A
Pin B
Pin B
B
C
E
Pin A
B C
+
+
+
P
N P P+
P N
P
P
N
N
N
N
N
N
Parasitic
E
Elements
Parasitic
P Substrate
P Substrate
Elements
Parasitic
Elements
VEE
Parasitic
Elements
VEE
VEE
N Region
close- by
VEE
Figure 19. Example of monolithic IC structure
13. Ceramic Capacitor
When using a ceramic capacitor, determine the dielectric constant considering the change of capacitance with
temperature and the decrease in nominal capacitance due to DC bias and others.
14.
About power ON/OFF
1. At power ON/OFF, a pop sound will be generated and, therefore, use MUTE on the set.
2. When turning on power supplies, VEE and VCC should be powered on simultaneously or VEE first; then
followed by VCC.(tdelay should be VEE=
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