BD3500FVM

TECHNICAL NOTE High-performance Regulator IC Series for PCs Ultra Low Dropout Linear Regulator Controllers for PC Chipsets BD3504FVM, BD3500FVM, BD3501FVM, BD3502FVM ●Description The BD3500/01/02/04FVM is an ultra-low dropout linear regulator controller for chipset that can achieve ultra-low voltage input to ultra-low voltage output. By using N-MOSFET for external power transistor, the controller can be used at ultra-low I/O voltage difference up to voltage difference generated by ON resistance. In addition, because best suited power transistor can be chosen in accord with the output current, downsizing and cost reduction of the set can be achieved. Because by reducing the I/O voltage difference, large current output is achieved and conversion loss can be reduced, switching power supply can be replaced. BD3500/01/02/04FVM does not need any choke coil, diode for rectification and power transistor which are required for switching power supply, total cost of the set can be reduced and compact size can be achieved for the set. Using external resistors, optional output from 0.65V to 2.5V can be set. In addition, since voltage output start-up time can be adjusted by using the NRCS terminal, it is possible to flexibly meet the power supply sequence of the set. ●Features 1) Reduced rush current by NRCS 2) Built-in driver for external Nch h transistor 3) Adoption of MSOP8 package: 2.9 x 4.0 x 0.9 (mm) 4) Built-in timer latch short protection circuit 5) Built-in low input maloperation prevention circuit 6) Output voltage variable type 7) Built-in overheat protection circuit ●Applications Mobile PC, desktop PC, digital home appliances ●Line up Parameter Output Voltage NRCS (Soft start) Timer latch short protection circuit VIN UVLO External FET GATE Drive Current BD3500FVM 1.8V (Fix) ○ (Independent Setting) BD3501FVM 1.5V (Fix) ○ (Independent Setting) BD3502FVM 1.2V (Fix) ○ (Independent Setting) BD3504FVM Variable(0.65～2.5V) ○ (Same Timer Latch) ○ (Independent Setting) ○ (Independent Setting) ○ (Independent Setting) ○ (Same NRCS) Hysterisis +1/-3mA Hysterisis +1/-3mA Hysterisis +1/-3mA Detected at start-up only (set by external resistor) +3/-3mA Oct. 2008 ●ABSOLUTE MAXIMUM RATINGS (Ta=25℃) ◎BD3500/01/02FVM Parameter Input Voltage Drain Voltage (VIN) Enable Input Voltage Power Dissipation Operating Temperature Range Storage Temperature Range Maximum Junction Temperature *1 However, not exceeding Pd. *2 Pd derating at 3.5mW/℃ for temperature above Ta=25℃ Symbol VCC VIN Ven Pd Topr Tstg Tjmax Limit 7 *1 7 7 437.5 *2 -10～+100 -55～+150 +150 Unit V V V mW ℃ ℃ ℃ ◎BD3504FVM Parameter Supply Voltage Drain Voltage Enable Input Voltage Power dissipation Operating temperature range Storage temperature range Maximum Junction Temperature *3 However, not exceeding Pd. *4 Pd derating at 3.5mW/℃ for temperature above Ta=25℃ Symbol VCC VD Ven Pd Topr Tstg Tjmax Limit 7 *3 7 7 437.5 *4 -10～+100 -55～+150 +150 Unit V V V mW ℃ ℃ ℃ ●RECOMMENDED OPERATING CONDITIONS ◎BD3500/01/02FVM Parameter Symbol Supply Voltage VCC Drain Voltage(VIN) VIN Enable Input Voltage Ven Capacitor on NRCS Terminal CNRCS Capacitor on SCP Terminal CSCP ★ No radiation-resistant design is adopted for the present product. MIN 4.5 Vo×1.15 -0.3 0.001 0.001 MAX 5.5 5.5 5.5 1 1 Unit V V V uF uF ◎BD3504FVM Parameter Supply Voltage Drain Voltage Enable Input Voltage Capacitor in NRCS pin Output Voltage Symbol VCC VD Ven CNRCS VOUT MIN 4.5 0.65 -0.3 0.001 0.65 MAX 5.5 5.5 5.5 1 2.5 Unit V V V uF V ★ No radiation-resistant design is adopted for the present product. 2/16 ●ELECTRICAL CHARACTERISTICS (unless otherwise noted, Ta=25℃ VCC=5V Vin=3.3V Ven=3V) ◎BD3500FVM/BD3501FVM/BD3502FVM Standard Value Parameter Symbol Unit Condition MIN TYP MAX Bias Current ICC 0.8 1.6 mA Shut Down Mode Current IST 0 10 uA Ven=0V Output Voltage 1 Vo1 1.782 1.800 1.818 V Io=50mA (BD3500FVM) Output Voltage 1 Vo1 1.485 1.500 1.515 V Io=50mA (BD3501FVM) Output Voltage 1 Vo1 1.188 1.200 1.212 V Io=50mA (BD3502FVM) Output Voltage 2 Vcc=4.5V to 5.5V ,Io=0 to 3A Vo2 1.746 1.800 1.854 V (BD3500FVM) Ta=-10℃ to 100℃(※) Output Voltage 2 Vcc=4.5V to 5.5V ,Io=0 to 3A Vo2 1.455 1.500 1.545 V (BD3501FVM) Ta=-10℃ to 100℃(※) Output Voltage 2 Vcc=4.5V to 5.5V ,Io=0 to 3A Vo2 1.164 1.200 1.236 V (BD3502FVM) Ta=-10℃ to 100℃(※) Line Regulation Reg.l 0.1 0.5 %/V VCC=4.5V to 5.5V Load Regulation Reg.L 0.5 10 mV Io=0 to 3A [Enable] High Level Enable Input Enhi 2 Vcc V Voltage Low Level Enable Input Enlow -0.3 0.8 V Voltage Enable Pin Input Current Ien 7 10 uA Ven=3V [NRCS] Vnrcs=0.5V,VCC=4.5V to 5.5V NRCS Charge Current Inrcs 14 20 26 uA Ta=-10℃ to 100℃ (※) NRCS Standby Voltage Vnrcs 0 50 mV Ven=0V [Voltage Feed Back] VFB Input Bias Current IFB 0.7 1.2 mA Ven=3V VFB Standby Current FBSTB 150 mA Ven=0V,VFB=1V [Output MOSFET Driver] MOSFET Driver Source IGSO 0.5 1 1.5 mA VFB=Vo-0.1V,G=Vo+1V Current MOSFET Driver Sink IGSI 2 3 4 mA VFB=Vo+0.1V,G=Vo+1V Current [UVLO] VCC UVLO VccUVLO 4.2 4.35 4.5 V Vcc:Sweep up VCC UVLO Hysteresis Vcchys 100 160 220 mV Vcc:Sweep down VIN UVLO VINUVLO Vo×1.05 Vo×1.1 Vo×1.15 V VIN:Sweep up VIN UVLO Hysteresis VINhys 100 160 220 mV VIN:Sweep down [SCP] VSCP=0.5V,VCC=4.5V to 5.5V SCP Charge Current Iscpch 14 20 26 uA Ta=-10℃ to 100℃ (※) SCP Discharge Current IscpDi 0.5 mA VSCP=0.5V SCP Threshold Voltage Vscpth 1.2 1.3 1.4 V Short Detect Voltage Vscp Vo×0.6 Vo×0.7 Vo×0.8 V SCP Stand-by Voltage VSTB 0 50 mV (※) Design Guarantee 3/16 ●ELECTRICAL CHARACTERISTICS (unless otherwise noted, Ta=25℃ VCC=5V VIN=3.3V Ven=3V. R1=R1'=∞Ω, R2=R2'=0Ω) ◎BD3504FVM Standard Value Parameter Symbol Unit Condition MIN TYP MAX Bias Current ICC 0.85 1.7 mA Shut Down Mode Current IST 0 10 uA Ven=0V Feed Back Voltage 1 VFB1 0.643 0.650 0.657 V Io=50mA Vcc=4.5V to 5.5V , Feed Back Voltage 2 VFB2 0.630 0.650 0.670 V Ta=-10℃ to 100℃(※) R1=R1'=3.9kΩ, Output Voltage Vo 1.20 V R2=R2'=3.3KΩ Line Regulation Reg.l 0.1 0.5 %/V VCC=4.5V to 5.5V Load Regulation Reg.L 0.5 10 mV Io=0 to 3A [Enable] High Level Enable Input Enhi 2 Vcc V Voltage Low Level Enable Input Enlow -0.3 0.8 V Voltage Enable pin Input Current Ien 7 10 uA Ven=3V [Voltage Feed Back] VFB Input Bias Current IFB 80 nA [Source Voltage] VS Input Bias Current ISBIAS 1.2 2.4 mA VS Standby Current ISSTB 150 mA VS=1V Ven=0V [Output MOSFET Driver] MOSFET Driver Source IGSO 2 3 4 mA VFB=0.6V,VGATE=2.5V Current MOSFET Driver Sink Current IGSI 2 3 4 mA VFB=0.7V,VGATE=2.5V [UVLO] VCC UVLO VccUVLO 4.20 4.35 4.50 V Vcc:Sweep up VCC UVLO Hysterisis Vcchys 100 160 220 mV Vcc:Sweep down VD UVLO VDUVLO Vo×0.6 Vo×0.7 Vo×0.8 V VD:Sweep up [Drain Voltage Sensing] VD Input bias Current Ivd 0 nA [NRCS/SCP] NRCS Charge Current Inrcs 14 20 26 uA VNRCS=0.5V SCP Charge Current Iscpch 14 20 26 uA VNRCS=0.5V SCP Discharge Current IscpDi 0.3 mA VNRCS=0.5V SCP Threshold Voltage Vscp 1.2 1.3 1.4 V Short Detect Voltage Voscp Vo×0.3 Vo×0.35 Vo×0.4 V NRCS Stand-by Voltage VSTB 50 mV (※) Design Guarantee 4/16 ●Reference Data 1.40 1.20 1.00 1.800 1.795 1.790 Vo(V) 4.7 4.9 5.1 VCC(V) 5.3 5.5 0.80 1.00 ICC(mA) I(uA) 0.80 0.60 0.40 0.20 0.00 -60 0.60 1.785 1.780 0.40 0.20 1.775 1.770 -10 15 40 Ta( ℃) 65 90 -10 40 Ta( ℃) 90 140 0.00 4.5 Fig.1 Ta-ISTB 300 250 200 150 100 50 0 Fig.2 ICC-VCC Fig.3 Ta-Vo 12 11 10 IEN(uA) IS(mA) 21.5 21 20.5 ISCP(uA) 0 0.2 0.4 0.6 0.8 Vout(mV) 1 1.2 9 8 7 6 25 50 75 100 Ta( ℃) 125 150 20 19.5 19 18.5 -60 -10 40 Ta( ℃) 90 140 Fig.4 Ta-IEN 1.26 1.255 1.25 Fig.5 VS Discharge Current Fig.6 Ta-ISCP VCC VCC Vo(V) VBG(V) VIN 1.245 1.24 1.235 1.23 -60 VIN EN EN VOUT (1.075V 出力) -10 40 Ta( ℃) 90 140 VOUT (1.075V 出力) Fig.7 Ta-Vo Fig.8 Input Sequence 1 EN Fig 9. Input Sequence 2 VIN VCC VIN VOUT (1.075V 出力) VIN EN EN VOUT (1.075V 出力) VOUT IOUT (1A/div) Fig.10 Input Sequence 3 Vcc Fig.11 Input Sequence 4 (Only BD3504FVM) Fig.12 Transient Response 0→3A(0.6A／μs)ΔＶ=30mV 5/16 VOUT (1.075V 出力) VOUT (BD3502FVM) VOUT (BD3502FVM) IOUT (1A/div) IOUT (1A/div) IOUT (1A/div) Fig.13 Transient Response 3→0A(0.6A/μs)ΔV=20mＶ Fig.14 Transient Response 0→3A(0.6A/μs)ΔV=21mV Fig.15 Transient Response 3→0A(0.6A/μs) ΔV=17mV VOUT (BD3501FVM) VOUT (BD3501FVM) VOUT (BD3500FVM) IOUT (1A/div) IOUT (1A/div) IOUT (1A/div) Fig.16 Transient Response 0→3A(0.6A/μs) ΔV=42mＶ Fig.17 Transient Response 3→0A(0.6A/μs) ΔV=27mＶ Fig.18 Transient Response 0→3A(0.6A/μs) ΔV=44mＶ VOUT (BD3500FVM) VOUT (1.05V 出力) VOUT (1.05V 出力) IOUT (1A/div) IOUT (1A/div) IOUT Fig.19 Transient Response 3→0A(0.6A/μs) ΔV=26mＶ Fig.20 Transient Response 0→3A(0.6A/μs) ΔV=44mＶ Fig.21 Transient Response 3→0A(0.6A/μs) ΔV=23mＶ 6/16 ●BLOCK DIAGRAM ◎BD3500FVM/BD3501FVM/BD3502FVM VCC VCC 4 1 NRCS NRCS Enable EN 8 Reference Block UVLO1 VIN UVLO2 5 VREF VIN VREF VREF TSD SCP UVLO1 UVLO2 G 7 VFB 6 Vo Thermal Protection TSD VREF SCP 3 SCP 2 GND ◎BD3504FVM VCC VCC 4 VD UVLO2 R2’ VIN Enable EN 3 UVLO1 Reference Block NRCS 0.65V 0.65V VD UVLO LATCH 8 UVLO1 EN VREF R1’ G 7 TSD SCP UVLO1 UVLO2 EN VS 6 R2 5 SCP VFB R1 Vo Thermal Protection TSD 0.65V SCP NRCS NRCS 1 2 NRCS GND 7/16 ◎BD3500FVM/BD3501FVM/BD3502FVM ●PIN CONFIGRATION ●PIN FUNCTION Pin No. PIN NAME PIN FUNCTION NRCS GND SCP VCC 1 2 3 4 8 7 6 5 1 EN 2 G 3 4 5 VIN 6 7 8 NRCS GND SCP VCC VIN VFB G EN (Non Rush Current on Start up) time setup Ground pin Timer latch setup for Short Circuit Protection Power Source Drain Voltage Sense Output Voltage Feedback MOSFET Driver Output Enable VFB ◎BD3504FVM ●PIN CONFIGRATION ●PIN FUNCTION PIN Pin No. NAME 1 8 7 6 5 VD G NRCS PIN FUNCTION NRCS (Non Rush Current on Start up) time setup. Timer latch setup for Short Circuit Protection operating time set up Pin. Ground Pin Enable Pin Power Source Output Voltage Feedback Source Voltage Pin MOSFET Driver Output Drain Voltage Sense NRCS GND EN VCC 1 2 3 4 2 3 4 5 6 7 8 GND EN VCC VFB VS G VD VS VFB 8/16 ●Pin Function ・VCC BD3500/01/02/04FVM has an independent power input pin for an internal circuit operation of IC. N-MOSFET. The voltage used of VCC terminal is 5.0V and maximum current is 1.7 mA. This is used for bias of IC internal circuit and external It is recommended to connect a bypass capacitor of 0.1 μF or so to VCC pin. ・EN With an input of 2.0 volts or higher, the EN terminal turns to “High” level and VOUT is outputted. At 0.8V or lower, it detects “Low” level and VOUT is turned OFF and simultaneously, the discharge circuit inside the VS terminal is activated and lowers output voltage (150 mA (Min) when VFB//VS=1V and VEN=0V). ・VIN(BD3500/01/02FVM) The VIN terminal is a drain voltage detection terminal of external N-MOSFET. In the event that the VIN terminal is lower than 1.1 times the output set voltage, output is turned OFF to prevent low-input maloperation. ・VD(BD3504FVM only) The VD terminal is a drain voltage detection terminal of external N-MOSFET. prevent low-input maloperation. equation: In the event that drain voltage (VIN) is low, output voltage is turned OFF to The reset voltage (VDUVLO) of drain voltage low-input maloperation prevention circuit is determined by the following VDUVLO=VFB×0.7× R1’+R2 R1’ In the event that the maloperation prevention set resistance at the time of low-input drain voltage is set to a resistance value same as output voltage set resistor (R1 = R1’, R2 = R2’), low-input maloperation prevention (UVLO) is reset when drain voltage (VIN) reaches 70% of the output voltage. the startup of the EN terminal. ・VFB(BD3504FVM only) The VFB terminal is a terminal to decide output voltage and is determined by the following equation: UVLO detects only at VOUT=VFB× R1’+R2 R1’ VFB is controlled to achieve 0.65 V (typ.). ・NRCS terminal he NRCS terminal is a constant current output terminal, and operates as  Soft-Start ... during start-up SCP-Delay ... after start-up (BD3504FVM only). How to set Soft-Start of NRCS terminal The output voltage startup time (TNRCS) is determined by the time when the NRCS terminal reaches VFB (0.65V). During start-up, the NRCS terminal serves as a constant current source (INRCS) of 20 uA (Typ.) output, and charges capacitor (CNRCS) externally connected. reference voltage (0.65V) when the NRCS terminal reaches 0.65V, output voltage (VOUT) is fixed. By changing over to internal How to set NRCS terminal short protection Delay (BD3504FVM only) BD3504FVM has short protection (SCP) activated when output voltage becomes VOUT x 0.35 (typ.) or lower. activated until latching takes place (TSCP) is determined by the following equation: Tscp = CNRCS × Voscp ÷ Iscp When short protection is activated, the NRCS terminal provides 20 uA (typ.) constant current output (lscp), and charges the capacitor (CNRCS) externally connected. When the NRCS terminal reaches 1.3V (Voscp), latch operation is carried out and output voltage is turned OFF. The time when short protection is ・SCP(BD3500/01/02FVM) BD3500/01/02FVM has short protection (SCP) activated when output becomes 70% or lower than the set voltage. until latching takes place (TSCP) is determined by the following equation: Tscp = CNRCS × Voscp ÷ Iscp When short protection is activated, the NRCS terminal provides 20 uA (typ.) constant current output (lscp), and charges the capacitor (CNRCS) externally connected. When the NRCS terminal reaches 1.3V (Voscp), latch operation is carried out and output voltage is turned OFF. ・VFB//VS (BD3500FVM/BD3501FVM/BD3502FVM//BD3504FVM) VFB//VS terminal is a source voltage detection terminal of external N-MOSFET. VFB//VS terminal has the internal discharge circuit activated to lower output The time when short protection is activated voltage when EN becomes a Low level or various protection circuits (TSD, SCP, UVLO) are activated. ・G G terminal is a gate drive terminal of external N-MOSFET. Because the output voltage range of G terminal is up to 5V (VCC), it is necessary to use N-MOSFET whose threshold is lower than “5V-VOUT.” In addition, by incorporating a RC snubber circuit to the G terminal, phase allowance of loop gain can be increased and the terminal can accommodate ceramic capacitors. 9/16 ●APPLICATION CIRCUIT Ven 1 C3 2 3 C2 4 Vcc C1 5 7 6 C5 + 8 C4 VIN R2’ 1 C3 2 3 Ven 4 Vcc C1 5 R1 7 6 R2 C4 + 8 R1’ C2 VIN ●Directions for pattern layout of PCB ・Because a VIN input capacitor causes impedance to drop, mount it as close to the VIN terminal as possible and use thick wiring patterns. In the event that it causes the wire to come in contact with the inner-layer ground plane, use a plurality of through holes. ・Because the NRCS terminal is analog I/O, take care to noise. In particular, high-frequency noise of GND may cause IC maloperation through capacitors. It is recommended to connect GND of NRCS capacitor to IC GND terminal at one point. ・The VFB terminal is an output voltage sense line. Effects of wiring impedance can be ignored by sensing the output voltage from the load side, but increased sense wiring causes VFB to be susceptible to noise, to which care must be taken. ・Because the GND terminal is GND to be used in analog circuit inside BD3501/02/04FVM, connect it at one point to inner-layer GND of substrate by as short pattern as possible. Arrange a bypass capacitor across VCC and GND as close as possible so that a loop can be minimized. ・The G terminal is a terminal for gate drive. If long wiring is inevitable, increase the pattern width and lower impedance. ・Heat generated in the output transistor can be calculated by: (VIN - VOUT) × Io(Max) Design heat generation not to exceed the guarantee temperature of transistor. ・Connect the output capacitor with thick short wiring so that the impedance is lowered. Connect capacitor GND to inner-layer GND plane by a plurality of through holes. 10/16 ●Evaluation Board (BD3500/01/02FVM) ■ BD350XFVM Evaluation Board Circuit VCC 8 S1 3 1 C2 VCC C1 2 GND C3 U1 BD350XFVM EN SCP G NRCS VFB 4 VCC 6 C5 VIN 5 C4 7 U2 VOUT VIN ■ BD350XFVM Evaluation Board Application Components Part No Value Company Parts Name U1 U2 C1 C2 Part No NMOS 1uF 0.01uF Value ROHM ROHM ROHM ROHM Company BD3500/01/02FVM RTW060N03 MCH184CN105KK Parts Name C3 C4 C5 0.01uF 10uF 220uF ROHM ROHM SANYO,etc MCH218CN106K 2R5TPE220MF ■ BD350XFVM Evaluation Board Layout Silk Screen TOP Layer Bottom Layer ●Evaluation Board (BD3504FVM) ■ BD3504FVM Evaluation Board Circuit GND U1 BD3504FVM VCC 3 S1 1 C2 VCC C1 4 VD 8 VTTS R2’ C3 VIN ■ BD3504FVM Evaluation Board Application Components Part No Value Company Parts Name EN NRCS G VS VCC VFB 7 R1’ U2 6 C4 U1 U2 R1 R1’ R2 Part No NMOS 3.9K 3.3K 3.9K Value ROHM ROHM ROHM ROHM ROHM Company BD35304FVM RTW060N03 MCR03EZPF3901 MCR03EZPF3301 MCR03EZPF3901 Parts Name VOUT 5 R2 2 GND R1 ■ BD3504FVM Evaluation Board Layout Silk Screen TOP Layer R2’ C1 C2 C3 C4 3.3K 1uF 0.01uF 10uF 220uF ROHM ROHM ROHM ROHM SANYO,etc MCR03EZPF3301 MCH184CN105KK MCH185CN103KK MCH218CN106KP 2R5TPE220MF Bottom Layer 11/16 ●I/O EQUIVALENCE CIRCUIT ◎BD3500FVM/BD3501FVM/BD3502FVM Vcc Vcc Vcc VI Vcc Vcc Vcc NRCS SCP Vcc Vcc EN Vcc Vcc VFB GATE ◎BD3504FVM Vcc Vcc NRCS VD Vs Vcc Vcc Vcc EN Vcc GATE VFB 12/16 ●NOTE FOR USE 1.Absolute maximum ratings For the present product, thoroughgoing quality control is carried out, but in the event that applied voltage, working temperature range, and other absolute maximum rating are exceeded, the present product may be destroyed. be taken, such as fuses, etc. 2.GND potential Bring the GND terminal potential to the minimum potential in any operating condition. 3.Thermal design Consider allowable loss (Pd) under actual working condition and carry out thermal design with sufficient margin provided. 4.Terminal-to-terminal short-circuit and erroneous mounting When the present IC is mounted to a printed circuit board, take utmost care to direction of IC and displacement. mounted erroneously, IC may be destroyed. 5.Operation in strong electromagnetic field The use of the present IC in the strong electromagnetic field may result in maloperation, to which care must be taken. 6.Built-in thermal shutdown protection circuit The present IC incorporates a thermal shutdown protection circuit (TSD circuit). has a -15°C (standard value) hysteresis width. brought to the OFF state. The working temperature is 175°C (standard value) and When the IC chip temperature rises and the TSD circuit operates, the output terminal is Consequently, never attempt to continuously use the IC after this outputs or output and power-GND, the IC may be destroyed. In the event that the IC is In the event of short-circuit caused by foreign matter that enters in a clearance between Because it is unable to identify the short mode, open mode, etc., if any special mode is assumed, which exceeds the absolute maximum rating, physical safety measures are requested to The built-in thermal shutdown protection circuit (TSD circuit) is first and foremost intended for interrupt IC from thermal runaway, and is not intended to protect and warrant the IC. 7.Capacitor across output and GND circuit is activated or to use the circuit with the activation of the circuit premised. In the event a large capacitor is connected across output and GND, when Vcc and VIN are short-circuited with 0V or GND for some kind of reasons, current charged in the capacitor flows into the output and may destroy the IC. output and GND. 8.Inspection by set substrate In the event a capacitor is connected to a pin with low impedance at the time of inspection with a set substrate, there is a fear of applying stress to the IC. Therefore, be sure to discharge electricity for every process. As electrostatic measures, provide grounding in the assembly process, and take utmost care in transportation and storage. 9.IC terminal input The present IC is a monolithic IC and has a P substrate and P isolation between elements. With this P layer and N layer of each element, PN junction is formed, and when the potential relation is GND>terminal A>terminal B, PN junction works as a diode, and terminal B>GND terminal A, PN junction operates as a parasitic transistor. The parasitic element is inevitably formed because of the IC construction. The operation of the parasitic element gives rise to mutual Consequently, take utmost care not to use the IC to interference between circuits and results in malfunction, and eventually, breakdown. + Use a capacitor smaller than 1000 μF between Furthermore, when the set substrate is connected to a jig in the inspection process, be sure to turn OFF power supply to connect the jig and be sure to turn OFF power supply to remove the jig. operate the parasitic element such as applying voltage lower than GND (P substrate) to the input terminal. Resistor (PIN A) (PIN B) C NPN Transistor Structure (NPN) B E (PIN A) Parasitic diode GND N P+ N N P substrate N Parasitic diode GND Parasitic diode N P substrate GND P P+ P+ N N P P+ GND (PIN B) C B E GND Nearby other device Parasitic diode 13/16 10.Output capacitor (C5) Connect the output capacitor between Vo1, Vo2 terminals and GND terminal without fail in order to stabilize output voltage. The output capacitor has a role to compensate for the phase of loop gain and to reduce output voltage fluctuation when load is rapidly changed. When there is an insufficient capacity value, there is a possibility to cause oscillation, and when the equivalent serial resistance (ESR) of the capacitors is large, output voltage fluctuation is increased when load is rapidly changed. temperature and load conditions. About 220 μF high-performance electrolytic capacitors are recommended, but this greatly depends on the gate capacity of external MOSFET and mutual conductance (gm), In addition, when only ceramic capacitors with low ESR are used, or various capacitors are connected in Thoroughgoing confirmation at series, the total phase allowance of loop gain becomes not sufficient, and oscillation may result. application temperature and under load range conditions is requested. 11.Input capacitor setting method (C1, C4) The input capacitor plays a part to lower output impedance of a power supply connected to input terminals (Vcc, VIN). oscillation and degraded ripple rejection characteristics. When output impedance of this power supply increases, the input voltages (Vcc, VIN) become unstable and there is a possibility of giving rise to The use of capacitors of about 10 μF with low ESR, which provide less capacity value changes caused by temperature changes, is recommended, but since input capacitor greatly depends on characteristics of the power supply used for input, substrate wiring pattern, and MOSFET gate-drain capacity, thoroughgoing confirmation under the application temperature, load range, and M-MOSFET conditions is requested. 12.NRCS terminal capacitor setting method (C3) To the present IC, there mounted is a function (Non Rush Current on Start-up: NRCS) to prevent rush current from VIN to load and output capacitor via Vo at the output voltage start-up. NRCS terminal. When the EN terminal is reset from Hi or UVLO, constant current is allowed to flow from the In By this current, voltage generated at the NRCS terminal becomes the reference voltage and output voltage is started. order to stabilize the NRCS set time, it is recommended to use a capacitor (B special) with less capacity value change caused by temperature change. 13.SCP terminal capacitor setting method (C2) The present IC incorporates a timer-latch type short-circuit protection circuit in order to prevent MOSFET from being destroyed by abnormal current when output terminal is short-circuited (operates at the time of NRCS, too). output setting voltage, IC judges that the output is short-circuited. When the output terminal voltage drops 30% from When the voltage When the In order to stabilize the In such event, constant current begins to flow. generated in the SCP terminal reaches 1.3V (Typ) by this current, the gate terminal is brought to the Low level. SCP function is not used, short-circuit the SCP terminal to the GND terminal. latch type protection circuit operates. and VIN terminal of MOSFET. 14.Input terminals (VCC, VIN, EN) In the present IC, N terminal, VIN terminal, and VCC terminal have an independent construction. SCP setting time, a capacitor (B special) with less capacity value change caused by temperature changes is recommended. In addition, when the output terminal is short-circuited, the MOSFET gate voltage reaches the Vcc voltage and the large current that meets MOSFET characteristics flows to the output while the timer When the current capacity of VIN terminal power supply lacks, the Vin terminal voltage lowers and In such event, connect a limiting resistor across drain terminal the UVLO circuit operates, and the latch operation may not be finished. In addition, in order to prevent They begin to start output malfunction at the time of low input, the UVLO function is equipped with the VIN terminal and the VCC terminal. voltage when all the terminals reach threshold voltage without depending on the input order of input terminals. 15.Maximum output current (maximum load) The maximum output current capacity of the power supply which is composed by the use of the present IC depends on the external FET. Consequently, confirm the characteristics of the power required for the set to be used, choose the external FET. 16.Operating ranges If it is within the operating ranges, certain circuit functions and operations are warranted in the working ambient temperature range. characteristic values within these ranges. 17.Allowable loss Pd With respect to the allowable loss, the thermal derating characteristics are shown in the Exhibit, which we hope would be used as a good-rule-of-thumb. loss. 18.The use in the strong electromagnetic field may sometimes cause malfunction, to which care must be taken. 19.In the event that load containing a large inductance component is connected to the output terminal, and generation of back-EMF at the start-up and when output is turned OFF is assumed, it is requested to insert a protection diode. 19. In the event that load containing a large inductance component is connected to the output terminal, and generation of back-EMF at the start-up and when output is turned OFF is assumed, it is requested to insert a protection diode. 20.We are certain that examples of applied circuit diagrams are recommendable, but you are requested to thoroughly confirm the characteristics before using the IC. In addition, when the IC is used with the external circuit changed, decide the IC with sufficient margin provided while consideration is being given not only to static characteristics but also variations of external parts and our IC including transient characteristics. (Example) OUTPUT PIN Should the IC be used in such a manner to exceed the allowable loss, reduction of current capacity due to chip You are strongly urged to use the IC within the allowable temperature rise, and other degraded properties inherent to the IC would result. With respect to characteristic values, it is unable to warrant standard values of electric characteristics but there are no sudden variations in 14/16 ●POWER DISSIPATION [mW] 500 437.5mW Without heat sink. θj-a=286℃/W 400 Power Dissipation [Pd] 300 200 100℃ 100 0 0 25 50 75 100 125 150 [℃] Ambient Temperature [Ta] ●Ordering part number B ・BD3504 ・BD3502 ・BD3501 ・BD3500 D 3 5 0 4 F V M ― T R Part Number Package Type ・FVM : MSOP8 TR : Embossed carrier tape ●Package specification MSOP8 Tape Quantity 2.9 ± 0.1 Embossed carrier tape 3000pcs TR (The direction is the 1pin of product is at the upper light when you hold reel on the left hand and you pull out the tape on the right hand) 4.0 ± 0.2 8 5 2.8 ± 0.1 1 4 0.475 0.9Max. 0.75 ± 0.05 0.08 ± 0.05 0.22 0.65 +0.05 −0.04 0.29 ± 0.15 0.6 ± 0.2 Direction of feed 0.145 +0.05 −0.03 0.08 M 0.08 S XX X X XXX XX X X XXX XX X X XXX XX X X XX XX X X XXX 1Pin Reel Direction of feed (Unit:mm) ※When you order , please order in times the amount of package quantity. 15/16 16/16 Catalog No.08T439A '08.10 ROHM © Appendix Notes No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM CO.,LTD. The content specified herein is subject to change for improvement without notice. The content specified herein is for the purpose of introducing ROHM's products (hereinafter "Products"). If you wish to use any such Product, please be sure to refer to the specifications, which can be obtained from ROHM upon request. Examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the Products. The peripheral conditions must be taken into account when designing circuits for mass production. Great care was taken in ensuring the accuracy of the information specified in this document. However, should you incur any damage arising from any inaccuracy or misprint of such information, ROHM shall bear no responsibility for such damage. The technical information specified herein is intended only to show the typical functions of and examples of application circuits for the Products. ROHM does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or other rights held by ROHM and other parties. ROHM shall bear no responsibility whatsoever for any dispute arising from the use of such technical information. The Products specified in this document are intended to be used with general-use electronic equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices). The Products are not designed to be radiation tolerant. While ROHM always makes efforts to enhance the quality and reliability of its Products, a Product may fail or malfunction for a variety of reasons. Please be sure to implement in your equipment using the Products safety measures to guard against the possibility of physical injury, fire or any other damage caused in the event of the failure of any Product, such as derating, redundancy, fire control and fail-safe designs. ROHM shall bear no responsibility whatsoever for your use of any Product outside of the prescribed scope or not in accordance with the instruction manual. The Products are not designed or manufactured to be used with any equipment, device or system which requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of human injury (such as a medical instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuel-controller or other safety device). ROHM shall bear no responsibility in any way for use of any of the Products for the above special purposes. If a Product is intended to be used for any such special purpose, please contact a ROHM sales representative before purchasing. If you intend to export or ship overseas any Product or technology specified herein that may be controlled under the Foreign Exchange and the Foreign Trade Law, you will be required to obtain a license or permit under the Law. Thank you for your accessing to ROHM product informations. More detail product informations and catalogs are available, please contact your nearest sales office. ROHM Customer Support System www.rohm.com Copyright © 2008 ROHM CO.,LTD. THE AMERICAS / EUROPE / ASIA / JAPAN Contact us : webmaster@ rohm.co. jp 21 Saiin Mizosaki-cho, Ukyo-ku, Kyoto 615-8585, Japan TEL : +81-75-311-2121 FAX : +81-75-315-0172 Appendix1-Rev3.0