Datasheet
0.7V to VCC-1V, 3A 1ch
Ultra-Low Dropout Linear Regulator
BD3512MUV
Key Specifications
IN Input Voltage Range:
VCC Input Voltage Range:
Output Voltage Range:
Output Current:
ON-Resistance:
Standby Current:
Operating Temperature:
General Description
BD3512MUV is an ultra-low dropout linear chipset
regulator, which operates at a very low input supply. It
offers ideal performance in low input to output voltage
applications. The input-to-output voltage difference is
minimized by using a built-in N-Channel power
MOSFET with a maximum ON-Resistance of
RON=100mΩ. By lowering the dropout voltage, the
regulator achieves high output current of up to
IOUTMAX=3.0A, thereby, reducing conversion loss, making
it comparable to a switching regulator and its power
transistor, choke coil, and rectifier diode constituents. It
is a low-cost design and is available in significantly
downsized package profiles. An external resistor sets
the output voltage which ranges from 0.65V to 2.7V,
while the NRCS (soft start) function enables a controlled
output voltage ramp-up, which can be programmed to
anything the power supply sequence is required.
Package
0.7V to VCC-1V
4.3V to 5.5V
0.65V to 2.7V
3.0A (Max)
65mΩ(Typ)
0μA (Typ)
-10°C to +100°C
W(Typ) x D(Typ) x H(Max)
Features
Incorporates High-Precision Reference Voltage
Circuit (0.65V±1%)
Built-in VCC Undervoltage Lockout Circuit
(VCC=3.80V)
NRCS (Soft-start) Function Reduces the
Magnitude of In-rush Current
Built-in N-Channel MOSFET
Built-in Current Limit Circuit (3.0A min)
Built-in Thermal Shutdown (TSD) Circuit (Timer
latch)
Tracking Function
VQFN020V4040
4.00mm x 4.00mm x 1.00mm
Applications
Notebook and Desktop computers, LCD-TV, DVD,
Digital appliances
Typical Application Circuit and Block Diagram
VCC
C1
VCC
8
6
UVLO2
VIN
UVLOLATCH
9
VCC
EN
7
VCC
EN
UVLO1
Reference
Block
VD
Current
Limit
CL
UVLO1
IN
10
VREF
X 0.7
IN
11
12
R2
C2
13
VCC
VREF
R1
NRCS
OUT
14
NRCS x 0.3
VREF x 0.4
FB
SCP/TSD
LATCH
EN
UVLO1
TSD
SCP
LATCH
CL
UVLO1
UVLO2
TSD
SCP
15
OUT
16
17
R2
EN
CFB
C3
18
2
CSCP
19
FB
20
CNRCS
R1
POWER
GOOD
NRCS
NRCS
EN/UVLO
5
○Product structure：Silicon monolithic integrated circuit
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© 2015 ROHM Co., Ltd. All rights reserved.
TSZ22111・14・001
VDD
3
PGDLY
1
4
GND
PG
○This product has no designed protection against radioactive rays
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BD3512MUV
Pin Configuration
Pin Descriptions
TOP VIEW
OUT2 OUT1
15
14
IN5
IN4
IN3
13
12
11
OUT3 16
OUT 4
17
OUT 5
10 IN2
9
IN1
18
8
VD
FB 19
7
EN
20
6
VCC
FIN
NRCS
1
2
3
4
GND1 SCP PGDLY PG
5
VDD
Pin No.
1
Pin Name
GND1
2
SCP
3
PGDLY
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
PG
VDD
VCC
EN
VD
IN1
IN2
IN3
IN4
IN5
OUT1
OUT 2
OUT 3
OUT 4
OUT 5
FB
20
NRCS
bottom
FIN
PIN Function
Ground pin 1
SCP delay time setting capacitor
connection pin
PGOOD delay setting
capacitor connection pin
Power good pin
Power supply pin
Power supply pin
Enable input pin
IN input voltage detect pin
Input voltage pin 1
Input voltage pin 2
Input voltage pin 3
Input voltage pin 4
Input voltage pin 5
Output voltage pin 1
Output voltage pin 2
Output voltage pin 3
Output voltage pin 4
Output voltage pin 5
Reference voltage feedback pin
In-rush current protection (NRCS)
capacitor connection pin
Connected to heat sink and GND
(Note) Please short N.C to the GND line.
Description of Blocks
1. AMP
This is an error amplifier, which compares the reference voltage (0.65V) to FB voltage to drive the output N-Channel FET.
Frequency optimization aids in attaining rapid transient response, and to support the use of ceramic capacitors on the
output. AMP output voltage ranges from GND to VCC. When EN is OFF, or when UVLO is active, output goes LOW and
the output of the N-Channel FET switches to OFF state.
2. EN
The EN block controls the ON and OFF state of the regulator via the EN logic input pin. During OFF state, circuit voltage
stabilizes at 0μA which minimizes the current consumption during standby mode. The FET is switched ON to enable the
discharge of NRCS and OUT, thereby draining the excess charge and preventing the load side of an IC from
malfunctioning. Since there is no electrical connection required (e.g. between the VCC pin and the ESD prevention
diode), module operation is independent of the input sequence.
3. UVLO
To prevent malfunctions that can occur during sudden decrease in VCC, the UVLO circuit switches the output to OFF
state, and (like the EN block) discharges NRCS and OUT. Once the UVLO threshold voltage (TYP3.80V) is reached, the
power-ON reset is triggered and the output is restored.
4. CURRENT LIMIT
During ON state, it monitors the output current of the IC against the current limit value. When the output current exceeds
this value, this block lowers the output current to protect the load of the IC. When it overcomes the overcurrent state,
output voltage is restored to allowable value.
5. NRCS (Non Rush Current on Start-up)
The soft start function is enabled by connecting an external capacitor between the NRCS pin and ground. Output
ramp-up can be set to any period up to the time the NRCS pin reaches V FB (0.65V). During startup, the NRCS pin serves
as a constant current source about 20μA (TYP) to charge the external capacitor. Capacitors with low susceptibility
(0.001µF to 1µF) to temperature are recommended, in order to assure a stable soft-start time.
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BD3512MUV
Description of Blocks –continued
6. TSD (Thermal Shut down)
The shutdown (TSD) circuit is automatically latched OFF when the chip temperature exceeds the threshold temperature
after the programmed time period elapses, thus protecting the IC against “thermal runaway” and heat damage. Since the
TSD circuit is designed only to shut down the IC in the occurrence of extreme heat, it is important that the Tj(max)
parameter should not be exceeded in the thermal design, in order to avoid potential problems with the TSD.
7. IN
The IN line acts as the major current supply line, and is connected to the output N-Channel FET drain. Since there is no
electrical connection (such as between the VCC pin and the ESD protection diode) required, IN operates independent of
the input sequence. However, since an output N-Channel FET body diode exists between IN and OUT, a VIN-VOUT
electric (diode) connection is present. Therefore, when output is switched ON or OFF, reverse current may flow from
OUT to IN.
8. PGOOD
It determines the status of the output voltage. This is an open-drain pin, which is connected to VCC pin through the
pull-up resistance (100kΩ or so). When the output voltage ranges from VOUT x 0.9 to VOUT x 1.1(TYP), the status is high.
Absolute Maximum Ratings (Ta=25°C)
Parameter
Input Voltage 1
Input Voltage 2
Input Voltage 3
Input Voltage 4
Maximum Output Current
Enable Input Voltage
PGOOD Input Voltage
Power Dissipation 1
Power Dissipation 2
Power Dissipation 3
Power Dissipation 4
Operating Temperature Range
Storage Temperature Range
Maximum Junction Temperature
Symbol
Limit
Unit
VCC
VIN
VDD
VVD
IOUT
VEN
6.0 (Note 1)
6.0 (Note 1)
6.0 (Note 1)
1
3 (Note 1)
6.0
6.0
0.34 (Note 2)
0.70 (Note 3)
2.21 (Note 4)
3.56 (Note 5)
-10 to +100
-55 to +125
+150
V
V
V
V
A
V
V
W
W
W
W
°C
°C
°C
VPGOOD
Pd1
Pd2
Pd3
Pd4
Topr
Tstg
Tjmax
(Note 1) Should not exceed Pd.
(Note 2) Derating in done 2.7mV/°C for operating above Ta ≥ 25°C no heat sink
(Note 3) Derating in done 5.6mV/°C for operating above Ta ≥ 25°C
PCB size:74.2mm x 74.2mm x 1.6mm when mounted on a 1-layer glass epoxy board(copper foil area : 10.29mm2)
(Note 4) Derating in done 17.7mV/°C for operating above Ta ≥ 25°C
PCB size:74.2mm x 74.2mm x 1.6mm when mounted on a 4-layer glass epoxy board(copper foil area : front and reverse 10.29mm 2 , 2nd and 3rd
5505mm2)
(Note 5) Derating in done 28.5mV/°C for operating above Ta ≥ 25°C
PCB size:74.2mm x 74.2mm x 1.6mm when mounted on a 4-layer glass epoxy board(copper foil area : each 5505mm 2)
Caution: Operating the IC over the absolute maximum ratings may damage the IC. The damage can either be a short circuit between pins or an open circuit
between pins and the internal circuitry. Therefore, it is important to consider circuit protection measures, such as adding a fuse, in case the IC is operated over
the absolute maximum ratings.
Recommended Operating Conditions (Ta=25°C)
Parameter
Input Voltage 1
Input Voltage 2
Input Voltage 3
Output Voltage Setting Range
Enable Input Voltage
Symbol
VCC
VIN
VDD
VOUT
VEN
Min
4.3
0.7
4.5
VFB
-0.3
Max
5.5
VCC-1 (Note 6)
5.5
2.7
+5.5
Unit
V
V
V
V
V
(Note 6) VCC and IN do not have to be implemented in the order listed.
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BD3512MUV
Electrical Characteristics
(Unless otherwise specified, Ta=25°C, VCC=5V, VEN=3V, VIN=1.7V, R1=3.9kΩ, R2=3.3kΩ)
Parameter
ICC
IST
IOUT
Min
3.0
Limit
Typ
1.4
0
-
Max
2.2
10
-
Tcvo
-
0.01
-
%/°C
VFB1
0.643
0.650
0.657
V
VFB2
0.637
0.650
0.663
V
Reg.l1
Reg.l2
Reg.L
dVo
IDEN
1
0.1
0.1
0.5
65
-
0.5
0.5
10
100
-
%/V
%/V
mV
mV
mA
VENHI
2
-
-
V
VENLOW
-0.2
-
+0.8
V
IEN
-
6
10
µA
IFB
-100
0
+100
nA
INRCS
VSTB
14
-
20
0
26
50
µA
mV
VCCUVLO
3.5
3.8
4.1
V
VCCHYS
100
160
220
mV
Symbol
Circuit Current
VCC Shutdown Mode Current
Maximum Output Current
Output Voltage Temperature
Coefficient
Feedback Voltage 1
Feedback Voltage 2
Line Regulation 1
Line Regulation 2
Load Regulation
Minimum dropout voltage
Standby Discharge Current
[ENABLE]
Enable Pin
Input Voltage High
Enable Pin
Input Voltage Low
Enable Input Bias Current
[FEEDBACK]
Feedback Pin Bias Current
[NRCS]
NRCS Charge Current
NRCS Standby Voltage
[UVLO]
VCC Undervoltage Lockout
Threshold Voltage
VCC Undervoltage Lockout
Hysteresis Voltage
VD Undervoltage Lockout
Threshold Voltage
[SCP]
SCP Startup Voltage
SCP Threshold Voltage
SCP Charge Current
SCP Standby Voltage
[PGOOD]
VDUVLO
VREF x 0.6 VREF x 0.7 VREF x 0.8
VOUTSCP VOUT x 0.3 VOUT x 0.4 VOUT x 0.5
VSCPTH
1.05
1.15
1.25
ISCP
1.4
2
2.6
VSCPSTBY
50
Low-side Threshold Voltage
VTHPGL
High-side Threshold Voltage
VTHPGH
PGDLY Charge Current
Ron
IPGDLY
RPG
VOUT x
0.87
VOUT x
1.07
1.4
-
Unit
mA
µA
A
V
V
VOUT x 1.1 VOUT x 1.13
V
2.6
-
VEN=0V
IOUT=0A to 3A
Tj=-10°C to +100°C
VCC=4.3V to 5.5V
VIN=1.5V to 3.3V
IOUT=0A to 3A
IOUT=1A,VIN=1.2V
VEN=0V, VOUT=1V
VEN=3V
VNRCS=0.5V
VEN=0V
VCC: Sweep-up
VCC: Sweep-down
VD: Sweep-up
V
V
µA
mV
VOUT x 0.9 VOUT x 0.93
2.0
0.1
Conditions
µA
kΩ
(Note)
(Note) PGOOD delay time is determined using the formula below:
t PGDLY
CpF 1.23
sec
IPGDLY A
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BD3512MUV
Typical Waveforms
VOUT
VOUT
50mV/div
50mV/div
IOUT
1A/div
IOUT
1A/div
3.0A
IOUT=0A to 3A/3µsec
3.0A
t(10µsec/div)
IOUT=0A to 3A/3µsec
Figure 2. Transient Response
(0A to 3A)
COUT=100μF
Figure 1. Transient Response
(0A to 3A)
COUT=22μF, CFB=1000pF
VOUT
VOUT
50mV/div
50mV/div
IOUT
1A/div
IOUT
1A/div
t(4µsec/div)
3.0A
IOUT=0A to 3A/3µsec
t(4µsec/div)
IOUT=3A to 0A/3µsec
t(40µsec/div)
Figure 4. Transient Response
(3A to 0A)
COUT=22μF, CFB=1000pF
Figure 3. Transient Response
(0A to 3A)
COUT=100μF, CFB=1000pF
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BD3512MUV
Typical Waveforms – continued
VOUT
VOUT
50mV/div
50mV/div
IOUT
IOUT
1A/div
3.0A
IOUT=3A to 0A/3µsec
1A/div
3.0A
IOUT=3A to 0A/3µsec
t(100µsec/div)
t(100µsec/div)
Figure 6. Transient Response
(3A to 0A)
COUT=100μF, CFB=1000pF
Figure 5. Transient Response
(3A to 0A)
COUT=100μF
VEN
VEN
2V/div
2V/div
VNRCS
VNRCS
1V/div
1V/div
VOUT
VOUT
500mV/div
500mV/div
t(100µsec/div)
t(2msec/div)
Figure 7. Waveform at Output Start
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Figure 8. Waveform at Output OFF
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BD3512MUV
Typical Waveforms – continued
VCC
VCC
5V/div
5V/div
VEN
VEN
2V/div
2V/div
VIN
VIN
2V/div
2V/div
VOUT
VOUT
1V/div
1V/div
VCC to VIN to VEN
VIN to VCC to VEN
Figure 10. Input Sequence
Figure 9. Input Sequence
VCC
VCC
5V/div
5V/div
VEN
VEN
2V/div
2V/div
VIN
VIN
2V/div
2V/div
VOUT
VOUT
1V/div
1V/div
VCC to VEN to VIN
VEN to VCC to VIN
Figure 11. Input Sequence
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Figure 12. Input Sequence
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BD3512MUV
Typical Waveforms – continued
VCC
VCC
VEN
VEN
VIN
VIN
VOUT
VOUT
VEN to VIN to VCC
VIN to VEN to VCC
Figure 13. Input Sequence
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Figure 14. Input Sequence
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BD3512MUV
Typical Performance Curves
1.23
2.0
1.9
1.8
Circuit Current : ICC (mA)
Output Voltage : VOUT (V)
1.22
1.21
1.20
1.19
1.7
1.6
1.5
1.4
1.3
1.2
1.18
1.1
1.0
1.17
-50
-25
0
25
50
75
100
125
150
-50
-25
Temperature : Ta [°C]
25
50
75
100
125
150
Temperature : Ta [°C]
Figure 16. Circuit Current vs Temperature
Figure 15. Output Voltage vs Temperature
5.0
50
4.5
45
4.0
40
3.5
35
IINSTB [µA]
ISTB [µA]
0
3.0
2.5
30
25
2.0
20
1.5
15
1.0
10
0.5
5
0
0.0
-50
-25
0
25
50
75
100
125
150
-50
0
25
50
75
100
125
150
Temperature : Ta [°C]
Temperature : Ta [°C]
Figure 18. IINSTB vs Temperature
Figure 17. ISTB vs Temperature
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BD3512MUV
Typical Performance Curves – continued
10
Enable Input Bias Current : IEN (µA)
NRCS Charge Current : INRCS (µA)
24
22
20
18
16
14
9
8
7
6
5
4
3
2
1
0
12
-50
-25
0
25
50
75
100
125
150
-50
-25
Temperature : Ta [°C]
70
70
ON-Resistance : RON [mΩ]
ON-Resistance : RON [mΩ]
80
60
50
40
30
20
100
125
150
20
-50
-25
0
25
50
75
100
125
150
Temperature : Ta [°C]
Temperature : Ta [°C]
Figure 21. ON-Resistance vs Temperature
(VCC=5V/VOUT=1.2V)
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150
30
0
75
125
40
0
50
100
50
10
25
75
60
10
0
50
Figure 20. Enable Input Bias Current vs Temperature
80
-25
25
Temperature : Ta [°C]
Figure 19. NRCS Charge Current vs Temperature
-50
0
Figure 22. ON-Resistance vs Temperature
(VCC=5V/VOUT=1.5V)
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BD3512MUV
Typical Performance Curves – continued
50
ON-Resistance : RON [mΩ]
VOUT=2.5V
45
VOUT=1.8V
VOUT=1.7V
VOUT=1.5V
VOUT=1.2V
40
35
3
5
7
Supply Voltage : VCC [V]
Figure 23. ON-Resistance vs Supply Voltage
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BD3512MUV
Timing Chart
EN ON/OFF
IN
VCC
EN
0.65V(typ)
NRCS
Startup
VOUT x 0.9V(typ)
OUT
60µs(typ)
(typ@ C=100pF)
t
PGOOD
VCC ON/OFF
IN
UVLO
Hysteresis
VCC
EN
0.65V(typ)
NRCS
Startup
VOUT x 0.9V(typ)
OUT
60us (typ@100pF)
t
PGOOD
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BD3512MUV
Timing Chart – continued
IN ON
IN
VD=VREF x 0.7(typ)
UVLO (latch)
VD
(detect in VD)
VCC
EN
0.65V(typ)
NRCS
VOUT x 0.9V (typ)
OUT
60µs(typ@ C=100pF)
PGOOD
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BD3512MUV
Application Information
1. Evaluation Board
■ BD3512MUV Evaluation Board Schematic
C9
1
VO
RLD
U2
VO_S
1
JPF2
17
JPF1
VIN
11
12
IN3
13
IN4
14
U1
IN2
OUT3
IN1
OUT4
18
R18
19
20
EN
R9
1
VCC
VD
R8
7
R7
C7
1
6
VDD
1
1
H
SW1
L
VCC
VDD
C5
1
GND1 GND2
PGDLY
1
1
1
VINS
8
C6
C3
C2
SGND
JP9
9
5
4
1
PG
PGDLY
NRCS
C20
VCC
3
R19
NRCS
EN
FB
SCP
1
2
FB
VD
OUT5
C18
RF2
10
JP18
U3
CF
1
1
VCC
IN5
C14
16
INV
C12
R14
15
RF2
OUT1
RF1
OUT2
1
C11
C16
GND1
INF
C15
C10
1
PG
JP4B
SCP
R4
1
VPG
JP4
VCC
■ BD3512MUV Evaluation Board Standard Component List
Component
Rating
Manufacturer
Product Name
Component
Rating
Manufacturer
Product Name
U1
C2
100pF
ROHM
MURATA
BD3512MUV
CRM1882C1H101JA01
R8
R9
3.9kΩ
3.3kΩ
ROHM
ROHM
MCR03EZPF3901
MCR03EZPF3301
C3
R4
100pF
100kΩ
MURATA
ROHM
CRM1882C1H101JA01
MCR03EZPF1003
C9
C16
10µF
22µF
KYOCERA
KYOCERA
CM21B106M06A
CM316B226M06A
C5
C6
0.1µF
1µF
KYOCERA
KYOCERA
CM05104K10A
CM105B105K06A
R18
R19
3.3kΩ
3.9kΩ
ROHM
ROHM
MCR03EZPF3301
MCR03EZPF3901
R7
0Ω
-
Jumper
V20
0.01µF
MURATA
GRM188B11H102KA01
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BD3512MUV
■ BD3512MUV Evaluation Board Layout
Silk Screen (Top)
Silk Screen (Bottom)
TOP Layer
Middle Layer_2
Bottom Layer
Middle Layer_1
2. Recommended Circuit Example
Vo (1.2V/3A)
C9
C16
CFB
15
14
13
12
VIN
11
16
10
17
9
18
8
19
7
R18
R9
R8
VEN
R19
C20
20
6
C6
1
2
3
C2
4
C3
VCC
5
R4
VDD
C5
VPGOOD
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R18/R19
Recommended
Value
3.3kΩ/3.9kΩ
R4
100kΩ
This is the pull-up resistance for open-drain pin. It is recommended to set the value about
100kΩ.
C16
22µF
To assure output voltage stability, please be certain that OUT1 to OUT5 pins and the GND
pins are connected. Output capacitors play a role in loop gain phase compensation and in
mitigating output fluctuation during rapid changes in load level. Insufficient capacitance
may cause oscillation, while high equivalent series reisistance (ESR) will exacerbate
output voltage fluctuation under rapid load change conditions. While a 22µF ceramic
capacitor is recommended, actual stability is highly dependent on temperature and load
conditions. Also, note that connecting different types of capacitors in series may result in
insufficient total phase compensation, thus causing oscillation. Please confirm operation
across a variety of temperature and load conditions.
C6/C5
1µF/0.1µF
Input capacitors reduce the output impedance of the voltage supply source connected to
the (VCC,VDD) input pins. If the impedance of this power supply were to increase, input
voltage (VCC,VDD) could become unstable, leading to oscillation or lowering ripple rejection
function. While a low-ESR 1µF/0.1µF capacitor with minimal susceptibility to temperature
is recommended, stability is highly dependent on the input power supply characteristics
and the substrate wiring pattern. Please confirm operation across a variety of temperature
and load conditions.
C9
10µF
Input capacitors reduce the output impedance of the voltage supply source connected to
the (IN) input pins. If the impedance of this power supply were to increase, input voltage
(VIN) could become unstable, leading to oscillation or lowering ripple rejection function.
While a low-ESR 10µF capacitor with minimal susceptibility to temperature is
recommended, stability is highly dependent on the input power supply characteristics and
the substrate wiring pattern. Please confirm operation across a variety of temperature and
load conditions.
C20
0.01µF
The Non-Rush Current on Startup (NRCS) function is built into the IC to prevent rush
current from going through the load (IN to OUT) and affects output capacitors at power
supply start-up. Constant current comes from the NRCS pin when EN is HIGH or when
the UVLO function is deactivated. The temporary reference voltage is proportional to time,
due to the current charge of the NRCS pin capacitor, and output voltage start-up is
proportional to this reference voltage. Capacitors with low susceptibility to temperature
are recommended to ensure a stable soft-start time.
CFB
1000pF
This component is employed when the C16 capacitor causes, or may cause, oscillation. It
provides more precise internal phase compensation.
Component
Programming Notes and Precautions
IC output voltage can be set by the formula VFB X (R18+R19)/R19 using the values for the
internal reference output voltage (VFB) and the output voltage resistors (R18, R19). Select
resistance values that will avoid the impact of the FB bias current (±100nA). The
recommended total resistance value is 10KΩ.
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BD3512MUV
3. Heat Loss
In thermal design, consider the temperature range wherein the IC is guaranteed to operate and apply appropriate
margins. The temperature conditions that need to be considered are listed below:
(1) Ambient temperature (Ta) should not be higher than 100°C.
(2) Chip junction temperature (Tj) should not be higher than 150°C.
The chip’s junction temperature can be determined as follows:
① Calculation based on ambient temperature (Ta)
Tj Ta j a W
θj-a:VQFN020V4040 367.6°C/W IC only
2
178.6°C/W 1-layer board(copper foil area : 10.29mm )
2
2
56.6°C/W 4-layer board(copper foil area : front and reverse 10.29mm , 2nd and 3rd 5505mm )
2)
4-layer
board(copper
foil
area
:
each
5505mm
35.1°C/W
Substrate size: 74.2 x 74.2 x 1.6mm3 (substrate with thermal via)
It is recommended to layout multiple VIAs, for heat radiation, in the GND pattern of reverse (of IC) when there is the
GND pattern in the inner layer (in using multi-layer substrate). This package is so small (size: 4.0mm x 4.0mm) to layout
the VIA at the bottom of IC. Spreading the pattern and increasing the number of VIA, as shown in the figure below,
enable to achieve most heat radiation characteristics. It is recommended that the size and number of VIA are designed
suitable for the actual application (see figure below).
Most heat loss in BD3512MUV occurs at the output N-Channel FET. Power loss is determined by multiplying the total
VIN-VOUT voltage by the output current. Be sure to confirm the system input-to-output voltage and the output current
conditions in relation to the heat dissipation characteristics of the IN and OUT in the design. Considering that heat
dissipation may vary substantially depending on the substrate employed (due to the power package incorporated in the
BD3512MUV) make certain to factor conditions such as substrate size into the thermal design.
Power consumption (W) =
Input voltage (VIN)- Output voltage (VOUT) (VOUT ≈ VREF)
x IOUT(Ave)
For instance, VIN=1.5V, VOUT=1.25V, IOUT(Ave) = 3A,
Power consumption W 1.5 V 1.25 V 3.0 A
0.75 W
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BD3512MUV
Power Dissipation
Power Dissipation:Pd [W]
4.0
①3.56W
① 4 layers (Copper foil area : 5505mm2)
copper foil in each layers.
θj-a=35.1°C/W
② 4 layers (Copper foil area front and reverse : 10.29mm2、
2nd and 3rd : 5505mm2)
θj-a=56.6°C/W
③ 1 layer (Copper foil area : 10.29m2)
θj-a=178.6°C/W
④ IC only.
θj-a=367.6°C/W
3.0
②2.21W
2.0
1.0
③0.70W
④0.34W
0
0
25
50
75
100 105 125
150
Ambient temperature:Ta [°C]
I/O Equivalent Circuits
VCC
1kΩ
IN1
1kΩ
NRCS
1kΩ
PGOOD
1kΩ
IN2
1kΩ
IN3
IN4
1kΩ
IN5
VCC
VCC
1kΩ
OUT1
EN
1kΩ
FB
400kΩ
OUT2
OUT3
OUT4
OUT5
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BD3512MUV
Operational Notes
1.
Reverse Connection of Power Supply
Connecting the power supply in reverse polarity can damage the IC. Take precautions against reverse polarity when
connecting the power supply, such as mounting an external diode between the power supply and the IC’s power
supply pins.
2.
Power Supply Lines
Design the PCB layout pattern to provide low impedance supply lines. Separate the ground and supply lines of the
digital and analog blocks to prevent noise in the ground and supply lines of the digital block from affecting the analog
block. Furthermore, connect a capacitor to ground at all power supply pins. Consider the effect of temperature and
aging on the capacitance value when using electrolytic capacitors.
3.
Ground Voltage
Ensure that no pins are at a voltage below that of the ground pin at any time, even during transient condition.
4.
Ground Wiring Pattern
When using both small-signal and large-current ground traces, the two ground traces should be routed separately but
connected to a single ground at the reference point of the application board to avoid fluctuations in the small-signal
ground caused by large currents. Also ensure that the ground traces of external components do not cause variations
on the ground voltage. The ground lines must be as short and thick as possible to reduce line impedance.
5.
Thermal Consideration
Should by any chance the power dissipation rating be exceeded the rise in temperature of the chip may result in
deterioration of the properties of the chip. In case of exceeding this absolute maximum rating, increase the board size
and copper area to prevent exceeding the Pd rating.
6.
Recommended Operating Conditions
These conditions represent a range within which the expected characteristics of the IC can be approximately
obtained. The electrical characteristics are guaranteed under the conditions of each parameter.
7.
Inrush Current
When power is first supplied to the IC, it is possible that the internal logic may be unstable and inrush current may
flow instantaneously due to the internal powering sequence and delays, especially if the IC has more than one power
supply. Therefore, give special consideration to power coupling capacitance, power wiring, width of ground wiring,
and routing of connections.
8.
Operation Under Strong Electromagnetic Field
Operating the IC in the presence of a strong electromagnetic field may cause the IC to malfunction.
9.
Testing on Application Boards
When testing the IC on an application board, connecting a capacitor directly to a low-impedance output pin may
subject the IC to stress. Always discharge capacitors completely after each process or step. The IC’s power supply
should always be turned off completely before connecting or removing it from the test setup during the inspection
process. To prevent damage from static discharge, ground the IC during assembly and use similar precautions during
transport and storage.
10. Inter-pin Short and Mounting Errors
Ensure that the direction and position are correct when mounting the IC on the PCB. Incorrect mounting may result in
damaging the IC. Avoid nearby pins being shorted to each other especially to ground, power supply and output pin.
Inter-pin shorts could be due to many reasons such as metal particles, water droplets (in very humid environment)
and unintentional solder bridge deposited in between pins during assembly to name a few.
11. Unused Input Pins
Input pins of an IC are often connected to the gate of a MOS transistor. The gate has extremely high impedance and
extremely low capacitance. If left unconnected, the electric field from the outside can easily charge it. The small
charge acquired in this way is enough to produce a significant effect on the conduction through the transistor and
cause unexpected operation of the IC. So unless otherwise specified, unused input pins should be connected to the
power supply or ground line.
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BD3512MUV
Operational Notes – continued
12. Regarding the Input Pin of the IC
This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them
isolated. P-N junctions are formed at the intersection of the P layers with the N layers of other elements, creating a
parasitic diode or transistor. For example (refer to figure below):
When GND > Pin A and GND > Pin B, the P-N junction operates as a parasitic diode.
When GND > Pin B, the P-N junction operates as a parasitic transistor.
Parasitic diodes inevitably occur in the structure of the IC. The operation of parasitic diodes can result in mutual
interference among circuits, operational faults, or physical damage. Therefore, conditions that cause these diodes to
operate, such as applying a voltage lower than the GND voltage to an input pin (and thus to the P substrate) should
be avoided.
Resistor
Transistor (NPN)
Pin A
Pin B
E
Pin A
N
P+
P
N
N
P+
N
Pin B
B
C
N
Parasitic
Elements
P+
N P
N
P+
B
N
C
E
Parasitic
Elements
P Substrate
P Substrate
GND
GND
Parasitic
Elements
GND
Parasitic
Elements
GND
N Region
close-by
Figure 24. Example of monolithic IC structure
13. Area of Safe Operation (ASO)
Operate the IC such that the output voltage, output current, and power dissipation are all within the Area of Safe
Operation (ASO).
14. Thermal Shutdown Circuit(TSD)
This IC has a built-in thermal shutdown circuit that prevents heat damage to the IC. Normal operation should always
be within the IC’s power dissipation rating. If however the rating is exceeded for a continued period, the junction
temperature (Tj) will rise which will activate the TSD circuit that will turn OFF all output pins. The IC should be
powered down and turned ON again to resume normal operation because the TSD circuit keeps the outputs at the
OFF state even if the TJ falls below the TSD threshold.
Note that the TSD circuit operates in a situation that exceeds the absolute maximum ratings and therefore, under no
circumstances, should the TSD circuit be used in a set design or for any purpose other than protecting the IC from
heat damage.
TSD on Temperature [°C] (typ)
BD3512MUV
175
15. Output Pin
In the event that load containing a large inductance component is connected to the output terminal, and generation of
back-EMF at the start-up and when output is turned OFF is assumed, it is requested to insert a protection diode.
(Example)
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BD3512MUV
Ordering Information
B
D
3
5
1
2
Part Number
M
U
V
-
Package
MUV: VQFN020V4040
E2
Packaging and forming specification
E2: Emboss tape reel opposite draw-out side: 1 pin
Marking Diagram
VQFN020V4040 (TOP VIEW)
Part Number Marking
D 3 5 1 2
LOT Number
1PIN MARK
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BD3512MUV
Physical Dimension, Tape and Reel Information
Package Name
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BD3512MUV
Revision History
Date
Revision
02.Nov.2015
001
Changes
New Release
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Datasheet
Notice
Precaution on using ROHM Products
1.
Our Products are designed and manufactured for application in ordinary electronic equipments (such as AV equipment,
OA equipment, telecommunication equipment, home electronic appliances, amusement equipment, etc.). If you
(Note 1)
, transport
intend to use our Products in devices requiring extremely high reliability (such as medical equipment
equipment, traffic equipment, aircraft/spacecraft, nuclear power controllers, fuel controllers, car equipment including car
accessories, safety devices, etc.) and whose malfunction or failure may cause loss of human life, bodily injury or
serious damage to property (“Specific Applications”), please consult with the ROHM sales representative in advance.
Unless otherwise agreed in writing by ROHM in advance, ROHM shall not be in any way responsible or liable for any
damages, expenses or losses incurred by you or third parties arising from the use of any ROHM’s Products for Specific
Applications.
(Note1) Medical Equipment Classification of the Specific Applications
JAPAN
USA
EU
CHINA
CLASSⅢ
CLASSⅡb
CLASSⅢ
CLASSⅢ
CLASSⅣ
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ROHM designs and manufactures its Products subject to strict quality control system. However, semiconductor
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4.
The Products are not subject to radiation-proof design.
5.
Please verify and confirm characteristics of the final or mounted products in using the Products.
6.
In particular, if a transient load (a large amount of load applied in a short period of time, such as pulse. is applied,
confirmation of performance characteristics after on-board mounting is strongly recommended. Avoid applying power
exceeding normal rated power; exceeding the power rating under steady-state loading condition may negatively affect
product performance and reliability.
7.
De-rate Power Dissipation depending on ambient temperature. When used in sealed area, confirm that it is the use in
the range that does not exceed the maximum junction temperature.
8.
Confirm that operation temperature is within the specified range described in the product specification.
9.
ROHM shall not be in any way responsible or liable for failure induced under deviant condition from what is defined in
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Precaution for Mounting / Circuit board design
1.
When a highly active halogenous (chlorine, bromine, etc.) flux is used, the residue of flux may negatively affect product
performance and reliability.
2.
In principle, the reflow soldering method must be used on a surface-mount products, the flow soldering method must
be used on a through hole mount products. If the flow soldering method is preferred on a surface-mount products,
please consult with the ROHM representative in advance.
For details, please refer to ROHM Mounting specification
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Precautions Regarding Application Examples and External Circuits
1.
If change is made to the constant of an external circuit, please allow a sufficient margin considering variations of the
characteristics of the Products and external components, including transient characteristics, as well as static
characteristics.
2.
You agree that application notes, reference designs, and associated data and information contained in this document
are presented only as guidance for Products use. Therefore, in case you use such information, you are solely
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incurred by you or third parties arising from the use of such information.
Precaution for Electrostatic
This Product is electrostatic sensitive product, which may be damaged due to electrostatic discharge. Please take proper
caution in your manufacturing process and storage so that voltage exceeding the Products maximum rating will not be
applied to Products. Please take special care under dry condition (e.g. Grounding of human body / equipment / solder iron,
isolation from charged objects, setting of Ionizer, friction prevention and temperature / humidity control).
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1.
Product performance and soldered connections may deteriorate if the Products are stored in the places where:
[a] the Products are exposed to sea winds or corrosive gases, including Cl2, H2S, NH3, SO2, and NO2
[b] the temperature or humidity exceeds those recommended by ROHM
[c] the Products are exposed to direct sunshine or condensation
[d] the Products are exposed to high Electrostatic
2.
Even under ROHM recommended storage condition, solderability of products out of recommended storage time period
may be degraded. It is strongly recommended to confirm solderability before using Products of which storage time is
exceeding the recommended storage time period.
3.
Store / transport cartons in the correct direction, which is indicated on a carton with a symbol. Otherwise bent leads
may occur due to excessive stress applied when dropping of a carton.
4.
Use Products within the specified time after opening a humidity barrier bag. Baking is required before using Products of
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