Datasheet
Power Management IC for Automotive Microcontroller
Buck-Boost Switching Regulator + LDO +
Step-down Switching Regulator + Reset +
Watch Dog Timer
BD39001EKV-C
General Description
Key Specifications
BD39001EKV-C is a power management IC with
buck-boost switching regulator controller (DC / DC1),
secondary step-down switching regulator (DC / DC2),
LDO, reset and WDT.
The BD39001EKV-C includes protection circuits, such
as Under voltage, Over voltage, Over current and TSD.
Input voltage range
4.0 V to 30 V
(Startup voltage needs to be above 4.5V.)
Output voltage
Buck-Boost DC / DC1 FB Voltage
0.8 V
Secondary DC / DC2
3.3 V
Secondary LDO
5.0 V
Reference voltage accuracy
Buck-Boost DC / DC1 FB Voltage
±2 %
Secondary DC / DC2
±2 %
Secondary LDO
±2 %
Oscillation frequency
200 to 550 kHz
Max output current
Secondary Buck DC / DC2
900 mA
Secondary LDO
600 mA
Stand-by Current
0 μA (Typ)
Operating temperature range
-40 °C to 125 °C
AEC-Q100 Qualified
■
■
■
Features
AEC-Q100 Qualified(Note 1)
Automatically controlled buck-boost switching
regulator with 40 V rated VCC, DC / DC2 and LDO
input
3.3 V fixed output secondary step-down switching
regulator with built-in FET
5 V fixed output secondary LDO
Configurable Sequence control
Over Current protection
DC / DC1: Adjustable voltage with external resistors
DC / DC2: Integrated
LDO: Integrated
Over voltage / Under voltage detection
Reset for LDO and DC / DC2
Window Watchdog Timer
HTQFP48V package
(Note 1: Grade 1)
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
Package
W (Typ) × D (Typ) × H (Max)
9.00 mm × 9.00 mm × 1.00 mm
HTQFP48V
Applications
Microcontroller for Automotive
■
Typical Application Circuit
Simplified Circuit1
Simplified Circuit2
VCC
EN1
VO1
RT
VDD
FB1
OUTL
VO1
VO1
VS2
FB2
SW2
VO3
VS3
CT
RT
VL
VDD
FB1
VO2
VO2
PGND1
SS2
VS2
FB2
SW2
COMP2
VO3
VO1
EN3
VO2
PGND2
EN2
VO3
VS3
CT
VO3
EN3
SEQ2
RST2#
SEQ2
SEQ3
RST3#
SEQ3
RST3#
ENWD
RSTWD#
ENWD
RSTWD#
CLK
PG1
CLK
RTW
PG2
RTW
PG3
SEL_UVLO
SEL_UVLO
VO1
OUTL
COMP1
PGND2
EN2
OUTH
SS1
PGND1
SS2
CL
VERG
VL
SS1
COMP2
VO1
EN1
OUTH
COMP1
VO2
VCC
CL
VREG
GND
Buck-Boost Switching Regulator
+ Secondary Switching Regulator
+ Secondary LDO
○Product structure: Silicon monolithic integrated circuit
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© 2014 ROHM Co., Ltd. All rights reserved.
TSZ22111・14・001
RST2#
PG1
PG2
GND
PG3
Buck Switching Regulator
+ Secondary Switching Regulator
+ Secondary LDO
○This product is not designed for protection against radioactive rays
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BD39001EKV-C
Pin Configuration
25 EN1
27 VREG
26 T4
28 SS1
30 FB1
29 COMP1
31 RT
33 RST2#
32 GND
34 RST3#
36 CT
35 RSTWD#
(TOP VIEW)
COMP2
12
13
SS2
SEL_UVLO 48
10
FB2
11
14
PGND2
VDD
T3 47
PGND2
OUTL
15
9
16
PG1 46
NC
PG2 45
7
PGND1
8
17
SW2
NC
PG3 44
SW2
VL
18
6
19
SEQ2 43
NC
SEQ3 42
4
NC
5
20
VS2
OUTH
EN2 41
VS2
NC
21
3
22
EN3 40
VS3
ENWD 39
1
CL
2
VCC
23
NC
24
CLK 38
VO3
RTW 37
Pin Description
Pin No.
Symbol
Function
Pin No.
Symbol
Function
1
2
VO3
5 V Output
N.C.
Not connected
25
EN1
Output ON / OFF
26
T4 (Note 1)
Test pin
3
VS3
Supply Voltage Input for LDO
27
VREG
Internal power supply
4
5
VS2
Supply Voltage Input for DC / DC2
28
SS1
Soft start time setting for DC / DC1
VS2
Supply Voltage Input for DC / DC2
29
COMP1
Error-amp output for DC / DC1
6
N.C.
Not connected
30
FB1
Feedback for DC / DC1
7
SW2
DC / DC2 SW pin
31
RT
Frequency setting
8
SW2
DC / DC2 SW pin
32
GND
Ground
9
N.C.
Not connected
33
RST2#
Reset Output for DC / DC2
10
PGND2
Power Ground
34
RST3#
Reset Output for LDO
11
PGND2
Power Ground
35
RSTWD#
Reset Output for WDT
12
SS2
Soft start time setting for DC / DC2
36
CT
Reset Delay
13
COMP2
Error-amp output for DC / DC2
37
RTW
Frequency setting for WDT
14
FB2
Feedback for DC / DC2
38
CLK
Clock input
15
VDD
N-channel MOSFET drive supply
39
ENWD
WDT ON / OFF
16
OUTL
N-channel MOSFET drive
40
EN3
Output ON / OFF for LDO
17
PGND1
Power Ground
41
EN2
Output ON / OFF for DC / DC2
18
N.C.
Not connected
42
SEQ3
Sequence setting for LDO
19
VL
Pch FET gate clamp for DC / DC1
43
SEQ2
Sequence setting for DC / DC2
20
N.C.
Not connected
44
PG3
Power good output for LDO
21
OUTH
N-channel MOSFET drive
45
PG2
Power good output for DC / DC2
22
N.C.
46
PG1
Power good output for DC / DC1
23
CL
Not connected
Overcurrent detection setting
for DC / DC1
Supply Voltage Input
47
T3 (Note 1)
Test pin
48
SEL_UVLO
Select Pin for VCC UVLO
24
VCC
(Note 1)
Short with GND
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BD39001EKV-C
Block Diagram
VCC
SEL_UVLO
EN1
UVLO
VREG
CL
OCP
INTERNAL
REGULATOR
OCP1
VREG
RT
OSC
VREG
SLOPE
VREG
SS1
OUTH
PWM
_BUCK
DC/DC1
VREG
VL
PWM
_BOOST
SOFT
START1
DRIVER1
VREG
VCC
ERR
_BOOST
VREG
FB1
VCC
VREG
VREG
ERR
_BUCK
VDD
REG
VS3OVP
OCP1
OUTL
PG1
PGND1
VREG
COMP1
PGOOD1
(LVD/OVD)
VS2
VS2
DC/DC2
OCP2
VREG
SS2
CUR
CMOP
SOFT
START2
VS2
VREG
VREG
FB2
VREG
SLOPE
PWM2
ERR2
SW2
DRIVER2
OCP2
COMP2
OVD2
VREG
VREG
EN2
LVD2
LVD
PGND2
PG2
OVD
OVD2
VS3
LDO
AMP3
VO3
INTERNAL
REGULATOR
VS3OVP
LDOREG
LDOREG
LVD2
VREG
LDOREG
EN3
CT
VREG
OVP
LVD3
RESET
VO3
RST2#
RST3#
LVD3
LVD
PG3
OVD
RSTWD#
VREG
WATCHDOG
TIMER
VREG
PG1
PG1
PG2
PG2
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PG3
PG3
LDO_REG
LVD2
SEQ2
LVD3
SEQ3
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VREG
FOSCW
ENWD
RTW CLK
GND
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23.Mar.2017 Rev.002
BD39001EKV-C
Absolute Maximum Ratings
Parameter
Symbol
Limits
Unit
VCC Voltage
(Note 1)
VCC
40
V
VS2 Voltage
(Note 1)
VS2
40
V
VS3 Voltage
(Note 1)
VS3
40
V
CL Voltage
VCL
VCC
V
EN1 Voltage
VEN1
VCC
V
VREG Voltage
VREG
7
V
VDD Voltage
VDD
7
V
VSS1, VSS2
VREG
V
RST2#, RST3#, RSTWD#
VRST2#, VRST3#, VRSTWD#
7
V
CLK, RTW, CT, ENWD
VCLK, VRTW, VCT, VENWD
7
V
VPG1, VPG2, VPG3
7
V
VEN2, VEN3
VREG
V
VSEQ2, VSEQ3
7
V
Pd
5.00
W
Tstg
-55 to +150
°C
Tjmax
150
°C
SS1, SS2 Voltage
PG1, PG2, PG3
EN2, EN3
SEQ2, SEQ3
Power Dissipation
(Note 2)
Storage Temperature Range
Junction Temperature
(Note 1) Pd should not be exceeded.
(Note 2) If mounted on a standard ROHM 4 layer PCB (copper foil area: 70 mm × 70 mm) (Standard ROHM PCB size: 70mm × 70 mm ×1.6mm)
Reduce by 9.6 mW / °C (Ta ≥ 25 °C)
Caution: Operating the IC over the absolute maximum ratings may damage the IC. The damage can either be a short circuit between pins or an open
circuit between pins and the internal circuitry. Therefore, it is important to consider circuit protection measures, such as adding a fuse, in case the
IC is operated over the absolute maximum ratings.
Recommended Operating Rating
Maximum ratings
Parameter
Symbol
Unit
Min
Max
VCC (Buck Boost mode)
4 (Note 1)
30
V
VCC (Buck mode)
6
30
V
VS2
5
10
V
VS3
5
10
V
FOSC
200
550
kHz
WDT Oscillation Frequency
FOSCW
50
250
kHz
OUTH Current Ability
IOUTH
-
1.5
A
OUTL Current Ability
IOUTL
-
1.5
A
SW2 Current Ability
ISW2
-
900 (Note 2)
mA
VO3 Current Ability
IVO3
-
600 (Note 2)
mA
Operating Temperature Range
Topr
-40
+125
°C
Voltage Power Supply
Oscillation Frequency
(Note 1) Initial startup is over 4.5 V
(Note 2) Pd should not be exceeded.
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BD39001EKV-C
Electrical Characteristic
(Unless otherwise specified: -40 °C ≤ Ta ≤ +125 °C, 4 V ≤ VCC ≤ 30 V, 5 V ≤ VS2 ≤ 10 V, 5 V ≤ VS3 ≤ 10 V)
Limits
Parameter
Symbol
Unit
Min
Typ
Max
Condition
All
Standby Current 1
ISTB1
-
0
10
μA
Ta = 25 °C
Standby Current 2
ISTB2
-
-
30
μA
Ta = 125 °C
Circuit Current
IVCC
5
8
12
mA
RRT = 33 kΩ, VFB1 = 1.0 V
Oscillation Frequency
FOSC
315
350
385
kHz
RRT = 33 kΩ
VREG Output Voltage
VREG
3.0
3.5
4.0
V
VDD Output Voltage
VDD
4.5
5
5.5
V
VCC = 12 V
VUVLOVCC1
3.30
3.60
3.90
V
SEL_UVLO = OPEN
UVLO_VCC Release Voltage 1
VUVVCCRE1
3.50
4.00
4.50
V
SEL_UVLO = OPEN
UVLO_VCC Hysteresis Voltage 1
VUVVCCHYS1
200
400
600
mV
SEL_UVLO = OPEN
UVLO_VCC Detection Voltage 2
VUVLOVCC2
5.27
5.58
5.89
V
SEL_UVLO = GND
UVLO_VCC Release Voltage 2
VUVVCCRE2
5.35
5.67
6.0
V
SEL_UVLO = GND
UVLO_VCC Hysteresis Voltage 2
VUVVCCHYS2
50
75
-
mV
SEL_UVLO = GND
EN1 L Voltage
VEN1L
-
-
0.5
V
EN1 H Voltage
VEN1H
2.5
-
-
V
EN1 Input Resistance
REN1
180
375
570
kΩ
SEL_UVLO Threshold
VSEL_UVLO
-
VREG / 2
-
V
SEL_UVLO Output Current
ISEL_UVLO
5
14
23
μA
VSEL_UVLO = 0V
VREF08
0.784
0.800
0.816
V
FB1 = COMP1
FB1 Input Bias Current
IFB1
-1
0
+1
μA
VFB1 = 0.8 V
Soft Start Quick Charge Current
ISS0
55
110
165
μA
Soft Start Charge Current
ISS1
5
10
15
μA
Soft Start selected Voltage
VSS0
0.3
1.5
V
Soft Start End Voltage 1
VSS1
-
-
V
Soft Start Cramp Voltage
VSSCL1
2.2
0.7
VSS0+
VREF08
2.8
3.3
V
SS1 = OPEN
VL
8
10
12
V
VCC ≥ 12 V, VCC - VVL
Hi - Side OUTH ON - Resistance
RONHH
-
1.7
-
Ω
VCC = 12 V, OUTH - VCC
Lo - Side OUTH ON - Resistance1
RONHL1
-
3
-
Ω
VCC = 12 V, OUTH - VL
Lo - Side OUTH ON - Resistance2
RONHL2
-
-
30
Ω
VCC = 4 V, OUTH - PGND
Hi - Side OUTL ON - Resistance
RONLH
-
18
-
Ω
VCC = 12 V
Lo - Side OUTL ON - Resistance
RONLL
-
22
-
Ω
VCC = 12 V
Over current detection CL voltage (Low)
VCL_L
86
100
114
mV
VCC - VCL, VCC = 12 V
Over current detection CL voltage (High)
VCL_H
172
200
228
mV
VCC - VCL, VCC = 12 V
TON
-
92
-
%
UVLO_VCC Detection Voltage 1
DC / DC1
VEN1 = 5 V
(Buck - Boost DC / DC Controller)
FB1 Voltage
VCC - VL Voltage
Maximum ON Duty (OUTL)
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FOSC = 550 kHz
TSZ02201-0T3T0AM00120-1-2
23.Mar.2017 Rev.002
BD39001EKV-C
Electrical Characteristic
(Unless otherwise specified: -40 °C ≤ Ta ≤ +125 °C, 4 V ≤ VCC ≤ 30 V, 5 V ≤ VS2 ≤ 10 V, 5 V ≤ VS3 ≤ 10 V)
Limits
Parameter
Symbol
Unit
Condition
Min
Typ
Max
VO2
3.23
3.30
3.37
V
Under voltage detection voltage
VRST2
3.00
3.07
3.14
V
Under voltage hysteresis voltage
VRSTH2
20
-
80
mV
ISS2
5
10
15
μA
Soft Start end voltage 2
VSS2
0.6
0.8
1.0
V
SW2 ON - Resistance H
RONH2
-
0.3
0.6
Ω
SW2 ON - Resistance L
RONL2
-
0.3
0.6
Ω
EN2 L Voltage
VEN2L
-
-
0.6
V
EN2 H Voltage
VEN2H
1.0
-
-
V
IEN2
4
8
12
μA
UVLO_VS2 Detection Voltage
VUVLOVS2
3.5
3.9
4.3
V
UVLO_VS2 Hysteresis Voltage
VUVVS2HYS
0.2
0.35
0.5
V
VO3
4.90
5.00
5.10
V
Drop Voltage
ΔVO3
-
-
0.6
V
Under voltage detection voltage
VRST3
4.50
4.625
4.75
V
Under voltage hysteresis voltage
VCC UVLO - LDO LVD
difference voltage
EN3 L Voltage
VRSTH3
30
-
150
mV
ΔVLVD3
0.7
0.9
1.5
V
VEN3L
-
-
0.6
V
EN3 H Voltage
VEN3H
1.0
-
-
V
IEN3
4
8
12
μA
UVLO_VS3 Detection Voltage
VUVLOVS3
3.5
3.9
4.3
V
UVLO_VS3 Hysteresis Voltage
VUVVS3HYS
0.2
0.35
0.5
V
VOVVS
12.5
14
15.5
V
Reset Delay Time
tRST
30
56
160
ms
Reset L Voltage 1
VRSTL1
-
-
0.25
V
VO3 = 1.0 V, IRST = 100 μA
Reset L Voltage 2
VRSTL2
-
-
0.4
V
IRST = 1 mA
tPHL
-
-
5
µs
RST# pull up resistance 4.7 kΩ
FOSCW
75
100
125
kHz
512
FOSCW
6655
FOSCW
128
FOSCW
517
FOSCW
6675
FOSCW
133
FOSCW
DC / DC2
(Secondary DC / DC)
Output Voltage 2
Soft Start Charge Current
EN2 Charge Current
LDO
VSS2 = 0.2 V
VEN2 = 0.2 V
(5.0 V Output LDO)
Output Voltage 3
EN3 Charge Current
VS3 Over voltage detection voltage
6.0 V ≤ VS3 ≤ 10 V,
5 mA ≤ IVO3 ≤ 600 mA
VS3 = 4.65 V, IVO3 = 600 mA
VUVLOVVCC2 - VRST3
VEN3 = 0.2 V
RST2#, RST3#, RSTWD#
Reset Response Time
WDT Oscillation Frequency
CCT = 0.47 μF
RTW = 51 kΩ
WDT Reset Time
tWRES
507
FOSCW
6635
FOSCW
123
FOSCW
CLK L Voltage
VCLKL
-
-
0.8
V
CLK H Voltage
VCLKH
2.0
-
-
V
ENWD L Voltage
VENWDL
-
-
0.8
V
ENWD H Voltage
VENWDH
2.0
-
-
V
RSTWD ON Resistance
RRSTWD
50
100
200
Ω
IRSTWD = 100 μA
ICLK
10
22
55
μA
VCLK = 5 V
ENWD Input Current
IENWD
5
11
28
μA
VENWD = 5 V
RST Leak Current
ILRST
-
-
10
μA
VRST = 5V
ILRSTWD
-
-
10
μA
VRSTWD = 5V
CLK FAST NG Threshold
tWF
CLK SLOW NG Threshold
tWS
CLK Input Current
RSTWD Leak Current
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s
s
s
TSZ02201-0T3T0AM00120-1-2
23.Mar.2017 Rev.002
BD39001EKV-C
Electrical Characteristic
(Unless otherwise specified: -40 °C ≤ Ta ≤ +125 °C, 4 V ≤ VCC ≤ 30 V, 5 V ≤ VS2 ≤ 10 V, 5 V ≤ VS3 ≤ 10 V)
Parameter
Symbol
Limits
Unit
Condition
Min
Typ
Max
0.5
1.0
2.0
kΩ
0.62
0.67
0.72
V
VFB1 Voltage
PG1, PG2, PG3
PG ON - Resistance
PG1 Under Voltage Detection voltage
RPG1
RPG2
RPG3
VLVPG1
PG1 Under Voltage Hysteresis
VLVPH1
20
-
100
mV
VFB1 Voltage
PG1 Over Voltage Detection Voltage
VOVPG1
0.88
0.94
1.00
V
VFB1 Voltage
PG1 Over Voltage Hysteresis
VOVPH1
20
-
100
mV
VFB1 Voltage
PG2 Under Voltage Detection Voltage
VLVPG2
3.00
3.07
3.14
V
VFB2 Voltage
PG2 Under Voltage Hysteresis
VLVPH2
20
-
80
mV
VFB2 Voltage
PG2 Over Voltage Detection Voltage
VOVPG2
3.45
3.53
3.60
V
VFB2 Voltage
PG2 Over Voltage Hysteresis
VOVPH2
20
-
80
mV
VFB2 Voltage
PG3 Under Voltage Detection Voltage
VLVPG3
4.50
4.625
4.75
V
VO3 Voltage
PG3 Under Voltage Hysteresis
VLVPH3
30
-
150
mV
VO3 Voltage
PG3 Over Voltage Detection Voltage
VOVPG3
5.25
5.38
5.50
V
VO3 Voltage
PG3 Over Voltage Hysteresis
VOVPH3
30
-
150
mV
VO3 Voltage
ILPG
-
-
10
μA
VPG = 5V
SEQ2 ON Resistance
RSEQ2
0.5
1.0
2.0
kΩ
ISEQ2 = 100 μA
SEQ3 ON Resistance
RSEQ3
0.5
1.0
2.0
kΩ
ISEQ3 = 100 μA
SEQ Leak Current
ILSEQ
-
-
10
μA
VSEQ = 5V
PG Leak Current
SEQ 2, SEQ 3
Reset response time (tPHL)
VCC
UVLO
VRST2
FB2
VO3
VRST3
RST2#
RST2#
tPHL ≤ 5µs
RST3#
tPHL ≤ 5µs
RST2#
tPHL ≤ 5µs
RST3#
UVLO, RST# Delay time
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RST3#
FB2, RST2# Delay time
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tPHL ≤ 5µs
VO3, RST3# Delay time
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23.Mar.2017 Rev.002
BD39001EKV-C
Typical Performance Curves
10
12.00
11.00
Circuit Current: IVCC [mA]
Stundby Current: Istb [μA]
8
6
4
10.00
9.00
8.00
7.00
2
6.00
0
5.00
-40
-10
20
50
80
Ambient Temperature: Ta [°C]
110
-40
Figure 1. Standby Current vs. Temperature
Figure 2. Circuit Current vs. Temperature
3.37
0.810
3.35
Output Voltage2: VO2 [V]
0.805
FB1 Voltage 1: VREF08 [V]
-10
20
50
80
110
Ambient Temperature: Ta [°C]
0.800
0.795
0.790
0.785
3.33
3.31
3.29
3.27
3.25
3.23
0.780
-40
-40
-10
20
50
80
110
Ambient Temperature: Ta [°C]
Figure 3. FB1 Voltage vs. Temperature
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TSZ22111・15・001
-10
20
50
80
110
Ambient Temperature: Ta [°C]
Figure 4. Output Voltage2 vs. Temperature
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BD39001EKV-C
Typical Performance Curves
5.1
385
5.1
Frequency: FOSC [kHz]
Output Voltage3: V O3 [V]
375
5.0
5.0
365
355
345
335
325
4.9
315
-40
-10
20
50
80
Ambient Temperature: Ta [°C]
110
-40
Figure 5. Output Voltage3 vs. Temperature
110
Figure 6. Frequency vs. Temperature
2.5
125
115
EN1 Threshold: VEN1 [V]
WDT Frequency: FOSCW [kHz]
-10
20
50
80
Ambient Temperature: Ta [°C]
105
95
2.0
1.5
1.0
85
0.5
75
-40
-10
20
50
80
Ambient Temperature: Ta [°C]
-40
110
Figure 7. WDT Frequency vs. Temperature
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20
50
80
Ambient Temperature: Ta [°C]
110
Figure 8. EN1 Threshold vs. Temperature
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Typical Performance Curves
VCC UVLO Threshold Voltage2: VUVLOVCC2 [V]
VCC UVLO Threshold Voltage1: VUVLOVCC1 [V]
3.9
3.8
3.7
3.6
3.5
3.4
5.77
5.72
5.67
5.62
5.57
5.52
5.47
5.42
5.37
3.3
-40
-10
20
50
80
Ambient Temperature: Ta [°C]
-40
110
Figure 9. VCC UVLO Threshold Voltage1
vs. Temperature
Figure 10. VCC UVLO Threshold Voltage2
vs. Temperature
3.14
4.8
3.12
Under Voltage Detection3: V RST3 [V]
Under Voltage Detection2: V RST2 [V]
-10
20
50
80
110
Ambient Temperature: Ta [°C]
3.1
3.08
3.06
3.04
3.02
3
4.7
4.7
4.6
4.6
4.5
-40
-10
20
50
80
110
Ambient Temperature: Ta [°C]
-40
Figure 11. Under Voltage Detection2
vs. Temperature
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20
50
80
Ambient Temperature: Ta [°C]
110
Figure 12. Under Voltage Detection3
vs. Temperature
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Typical Performance Curves
2.5
4.5
OUTH Low RON1 RONHL1 [Ω]
OUTH High RON RONHH [Ω]
4
2.0
1.5
1.0
3.5
3
2.5
2
0.5
-40
-10
20
50
80
Ambient Temperature: Ta [°C]
1.5
110
-40
110
Figure 14. OUTH Low RON1 vs. Temperature
21
26.0
20
25.0
OUTL Low RON: RONLL [Ω]
OUTL High RON: VONLH [Ω]
Figure 13. OUTH High RON vs. Temperature
-10
20
50
80
Ambient Temperature: Ta [°C]
19
18
17
16
24.0
23.0
22.0
21.0
15
20.0
-40
-10
20
50
80
Ambient Temperature: Ta [°C]
110
-40
Figure 15. OUTL High RON vs. Temperature
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20
50
80
110
Ambient Temperature: Ta [°C]
Figure 16. OUTL Low RON vs. Temperature
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0.6
0.6
0.5
0.5
SW2 Low RON: RONL2 [Ω]
SW2 High RON: RONH2 [Ω]
Typical Performance Curves
0.4
0.3
0.2
0.4
0.3
0.2
0.1
0.1
-40
-10
20
50
80
Ambient Temperature: Ta [°C]
110
-40
Figure 17. SW2 High RON vs. Temperature
-10
20
50
80
Ambient Temperature: Ta [°C]
110
Figure 18. SW2 Low RON vs. Temperature
6
25
-40℃
125℃
OUTL Voltage: VOUTL [V]
OUTH Voltage: VOUTH [V]
5
25℃
20
15
10
4
3
2
-40℃
5
1
25℃
125℃
0
0
0
5
10
15
20
VCC Voltage: VCC[V]
25
30
Figure 19. OUTH Voltage vs. VCC
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5
10
15
20
VCC Voltage: VCC[V]
25
30
Figure 20. OUTL Voltage vs. VCC
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Description of Blocks
■
Under Voltage Lockout circuit (VCC_UVLO)
This is a Low Voltage Error Prevention Circuit.
In case of SEL_UVLO = OPEN, if the VCC drops below 3.6 V (Typ), the VCC_UVLO is activated and the output circuit
shuts down. In case of SEL_UVLO = GND, if the VCC drops below 5.58 V (Typ), the VCC_UVLO is activated and the
output circuit shuts down. When Vcc power supply off, Vcc voltage drop down low enough and make UVLO detect
function, then the voltage of OUTH is same as VCC and OUTL is same as VDD.
■
Thermal Shut Down (TSD)
The TSD protects the device from overheating.
If the chip temperature (Tj) reaches 175 °C (Typ), the circuit shuts down
■
Oscillation Frequency (OSC)
The oscillator frequency is fixed by RT pull-down resistance value. Switching frequency of DC / DC1 and DC / DC2 are
as same as OSC, but with a 180 °C difference in phase angle.
Over Voltage Detection (OVD)
If DC / DC1, DC / DC2 and LDO output voltage exceed OVD, each PGOOD Pin turns Low.
DC / DC1 OVD monitors FB1 voltage, DC / DC2 OVD monitors FB2 voltage and LDO OVD monitors VO3 voltage.
PGOOD pin is an open drain output. And the pull up resistor should be connected to PGOOD for using this function.
Low Voltage Detection (LVD)
If DC / DC1, DC / DC2 and LDO output voltage below LVD, each PGOOD Pin turns Low.
DC / DC1 LVD monitors FB1 voltage, DC / DC2 LVD monitors FB2 voltage and LDO LVD monitors VO3 voltage.
PGOOD pin is an open drain output, and the pull up resistor should be connected to PGOOD for using this function.
■
Under Voltage Lockout (VS_UVLO)
VS_UVLO prevents Error function at low VS voltage.
If the VS2 or VS3 drops below 3.9 V (Typ), the VS_UVLO is activated and the DC / DC2 or LDO is turned off.
■
Over Current Protection (OCP1_L, OCP1_H)
DC / DC1 has two levels over current protection with different control system as shown below.
1) OCP1 low level operations
In case the voltage between VCC and CL exceeds 100 mV (Typ), OCP1 (low level operation) is activated and the
switching pulse width of OUTH and the switching pulse width of OUTL are limited. Also, if this pulse limited status
continues during 256 clock times where the FB1 pin voltage drops below the under voltage detection level, the SS1
pin capacitor is discharged and the output is turned OFF during 8192 clock times.
During the 8192 clock in which the output is turned OFF, the logic of OUTH and OUTL pin changes as follows;
OUTH = H and OUTL = H. After the 8192 clock the chip returns to normal operations and the SS1 pin is recharged.
The clk is the same frequency as OSC.
2) OCP1 high level operations
In case the inter VCC - CL pin voltage exceeds 200 mV (Typ), the chip goes into OCP1 high level operations, the
SS1 pin capacitor is discharged and the output is turned OFF for 8192 clk. During the 8192 clock in which the
output is turned OFF, the logic of OUTH and OUTL pin changes as follows; OUTH = H and OUTL = H. After the
8192 clock the chip returns to normal operations and the SS1 pin is recharged. clk and OSC has the same
frequency.
VCC UVLO
RELEASE
OCP LOW LEVEL OPERATION
VCC UVLO
DETECTION
VCC
OVP
LVP
OCP HIGH LEVEL
OPERATION
OCP LOW LEVEL OPERATION
CL
LVP RELEASE
FB1
VO1
ISW
PG1
DISCHARGE SS
DISCHARGE SS
SS1
VCC VOLTAGE
256clk
8192clk
8192clk
OUTH
VDD VOLTAGE
OUTL
OUTPUT PULSE
IS LIMITED
VREG
OUTH=High,OUTL=High
FIXED BY LOGIC
NORMAL OPERATION
OUTH=High,OUTL=High
FIXED BY LOGIC
NORMAL OPERATION
Figure 21. Timing chart for DC / DC1 protection
VDD
VDD UVLO DETECTION
VDD UVLO RELEASE
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・DC / DC2
If output current of SW2 exceeds OCP, SW2 ON duty is limited and the output voltage is lowered.
If FB2 voltage is below SCP and after 256 clk, DC / DC2 is turned off. After 256 clk, DC / DC2 return to normal
operation. The clk is the same frequency as OSC.
DCDC2 OFF
Restart
VO2
SCP delay time
256clk
FB2
SCP delay time
256clk
SCP Level
SCP is release
SCP protection time
256clk
SW2
SW pulse is
limited
SW pulse is
limited
OCP Level
IL2
SS2
Figure 22. DC / DC2 Over current protection
・If the output current of LDO exceed OCP, the output current is limited and the output voltage is lowered.
(fold-back OCP)
■
Over Voltage Protection (VS3 OVP)
・In case the VS3 voltage exceeds 14 V (Typ), the chip goes into VS3 OVP, the SS1 capacitor is discharged and the
output is turned OFF for 8192 clock. During the 8192 clock in which the output is turned OFF, the logic of OUTH and
OUTL changes as follows; OUTH = H and OUTL = H. After the 8192 clock the chip returns to normal operations and
the SS1 is recharged. The clk is the same frequency as OSC.
VCC
14V
VO1 x
VS3
(=VO1)
0.94
V
0.8
8192clk
VO1 x
0.67
V
0.8
PG1
SS1
Discharge SS
OUTH
OUTL
OUTH=H,OUTL=H
fix to logic
Normal operation
EN2
EN3
All numerical values are Typical.
Figure 23. VS3 Over voltage protection
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RST#, RSTWD# pin
In case of ENWD = L, RSTWD# voltage is pull up voltage.
In case of ENWD = H, WDT operation starts. If WDT is in abnormal condition, RSTWD# outputs ‘L’.
If VO2 or VO3 voltage is below the LVD, reset voltage (RST#) output is low.
If both of VO2 and VO3 exceed the reset release voltage, CT is charged. After tPOR, reset voltage outputs high.
VO2 abnormal
detection
RST2#
VS2 UVLO
EN2
VO3 abnormal
detection
RST3#
VS3 UVLO
EN3
VCC UVLO
TSD
RSTWD#
WDT abnormal
detection
ENWD
Figure 24. RST#, RSTWD# Logic Circuit
LVD release
LVD detect
LVD detect
VO2
(DCDC2 Output)
LVD release
LVD release
LVD detect
VO3
(LDO Output)
1.5V
1.5V
Reset release(0.8V)
CT
LVD detect
VO3=1.0V
1.5V
Reset release(0.8V)
tPOR
Reset release(0.8V)
tRST
RST2#
tPOR
tRST
RST3#
Figure 25. RST2#, RST3# Timing Chart
VO2
(DCDC2 Output)
LVD release
LVD detect
LVD release
LVD detect
LVD release
LVD detect
VO3
(LDO Output)
LVD release
LVD detect
1.5V
Reset
release
CT
0.8V
0.2V
Reset
release
1.5V
0V
tRST
RST2#
tRST
RST3#
Figure 26. Timing chart (detection of LVD between reset)
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Oscillator for Watch Dog Timer (FOSCW)
This block creates a reference frequency of the Watch Dog Timer. The oscillation frequency is determined by the RTW
resistance. The oscillation frequency can be set in the range of 50 kHz to 250 kHz.
WATCH DOG TIMER
Microcontroller (μC) operation is monitored with CLK pin. Window watch dog timer is included to enhance the
assurance of the system. WDT starts operating when ENWD becomes high. CLK pin voltage must be Low when
ENWD switches to High.
WDT monitors both edges of CLK pin (rising edge and falling edge). If width of both edges are shorter than Fast NG or
longer than Slow NG, RSTWD turns low for a WDT reset time (tWRES). Since the width of Fast NG and Slow NG depends
on a number of FOSCW, Fast NG and Slow NG are variable by frequency of FOSCW. If FOSCW is unusual (ex. RTW is short
to ground), RSTWD turns low. In case of using RSTWD, pull-up resister is needed because RSTWD is an open drain.
ENWD=Low
FOSCW Error detection
Standby
MODE
FOSCW ERR
Detect
“RSTWD=Low”
ENWD=Low
FOSCW Error detection
ENWD=Low
ENWD=High
“RSTWD=High”
Nomal
MODE
“RSTWD=High”
Fast NG or Slow NG detection
RSTWD Low range > tWRES
μC error not detect
(Fast NG, Slow NG not detect)
μC ERR
Detect
“RSTWD=Low”
RSTWD Low range < tWRES
Figure 27. Witch Dog Timer State Change Diagram (WDT FSM)
(2)
WDT_FSM
Stop
Standby (1)
Normal (2)
(3)
(2)
(3)
(2)
(1)
(2)
(4)
(3)
(2)
(1)
UVLO
VCC
VREG
VO2
(5)
(5)
ENWD
Slow NG
ｔWRES
ｔWRES
ｔWRES
In case of pull up to 5V LDO
RSTWD#
Fast NG
Fast NG
CLK
WDT_CLK
(1): Standby Mode, (2): Normal Mode, (3): Microcontroller Error Detect, (4): OSC_WDT Error Detect (See Figure 27 WDT FSM)
(5): When ENWD is changed Low to High, it is necessary that CLK is Low.
Figure 28. WDT Timing Chart
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External Components Selection
VO1
RFB1B
RFB1C
CFB1
RFB1A
FB1
VCC
CCO1A
CCO1B
RCLA
CL
COMP1
RCO1
CVCCA
CCL
RCLB
CVCCB
CVL
VL
PGND2
OUTH
M1
L1
D1B
SW1
OUTL
COMP2
D1A
CVO1
VO1
M2
RCO2
CCO2
VS2
CVS2
VDD
CVDD
SW2
L2
CVO2
PGND1
VO2
Figure 29. Application Example 1
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(1)
Buck mode (VCC>>VO1)
In case the input voltage is high compared to the output voltage, the
chip will go into buck mode, resulting OUTH to repeatedly switch
between H and L and that the OUTL will go to L (= OFF).
This operation is the same as that of standard step-down switching
regulators.
Shown below are the OUTH and OUTL waveforms on the right.
ON duty of PMOS (Dpon), VCC and VO1 are shown in the following
equation.
𝑉𝑐𝑐 × 𝐷𝑝𝑜𝑛 = 𝑉𝑂1
OUTH
switching
OUTL
Low
IL1
(eq. 1)
Figure 30
(2) Buck-Boost mode (VCC ≈ VO1)
In case the input voltage is close to the output voltage, the chip will go into buck-boost mode, resulting both the OUTH
and OUTL to repeatedly switch between H and L. Concerning the OUTH, OUTL timing, the chip internally controls
where the following sequence is upheld; when OUTH: H L, OUTL: H L.
Shown below are the OUTH and OUTL waveforms.
①
②
VCC > VO1
VCC < VO1
OUTH
switching
OUTH
switching
OUTL
switching
OUTL
switching
IL1
IL1
Figure 31
Figure 32
*The timing excludes the SW delay
The relationship between ON duty of PMOS (Dpon), ON duty of NMOS (Dnon), VCC and VO1 is shown in the following equation.
𝑉𝑐𝑐 ×𝐷𝑝𝑜𝑛
(1−𝐷𝑛𝑜𝑛 )
= 𝑉𝑂1
(eq. 2)
The calculation formula of Dpon and Dnon are shown in page 20.
(3) Boost mode (VCC VO1
∆𝐼𝐿1 =
(𝑉𝐶𝐶 − 𝑉𝑂1 ) × 𝑉𝑂1
𝐿1 × 𝑉𝐶𝐶 × 𝑓
∆𝐼𝐿1 =
(𝑉𝐶𝐶 − 𝑉𝑂1 ) × 𝐷𝑝𝑜𝑛
𝐿1 × 𝑓
Boost mode
VCC < VO1
∆𝐼𝐿1 =
(𝑉𝑂1 − 𝑉𝐶𝐶 ) × 𝐷𝑛𝑜𝑓𝑓
𝐿1 × 𝑓
̅̅̅̅
𝐼𝐿1 =
̅̅̅̅
𝐼𝐿1 = 𝐼𝑂1
∆𝐼𝐿1 =
(𝑉𝑂1 − 𝑉𝐶𝐶 ) × 𝑉𝐶𝐶
𝐿1 × 𝑉𝑂1 × 𝑓
𝐼𝑂1
𝐷𝑛𝑜𝑓𝑓
_
ΔIL: Ripple current, I L: Average coil current, f: Oscillating frequency
Dpon:
Dnoff:
PMOS ON 𝑑𝑢𝑡𝑦 = 𝑉𝑂1 × 𝐷𝑥 (1 + 𝐴) / (𝑉𝐶𝐶 + 𝐴 × 𝑉𝑂1 )
= 2.13 × 𝑉𝑂1 / (𝑉𝐶𝐶 + 1.5 × 𝑉𝑂1 )
NMOS OFF 𝑑𝑢𝑡𝑦 = (1 + 𝐴) × 𝐷𝑥 – 𝐴 × 𝐷𝑝𝑜𝑛
= 2.13 − 1.5 × 𝐷𝑝𝑜𝑛
(𝑇𝑦𝑝)
(𝑇𝑦𝑝)
・DC / DC1 (at Buck)
∆𝐼𝐿1 =
(𝑉𝐶𝐶(𝑀𝐴𝑋) − 𝑉𝑂1 ) × 𝑉𝑂1
𝑉𝐶𝐶(𝑀𝐴𝑋) × 𝑓𝑆𝑊 × 𝐿1
(VCC (MAX): Maximum input voltage, ΔIL1: Inductor ripple current, VO1: Output voltage 1, fSW: Oscillating frequency)
・DC / DC2 (at Boost)
∆𝐼𝐿2 =
(𝑉𝑆2(𝑀𝐴𝑋) − 𝑉𝑂2 ) × 𝑉𝑂2
𝑉𝑆2(𝑀𝐴𝑋) × 𝑓𝑆𝑊 × 𝐿2
(VS2 (MAX): Maximum input voltage, ΔIL2: Inductor ripple current, VO2: Output voltage 2, fSW: Oscillating frequency)
An output current in excess of the coil current rating will cause magnetic saturation to the coil and decrease efficiency.
The following equation shows the peak current ILMAX assuming the efficiency as η.
It is recommended to secure sufficient margin to ensure that the peak current does not exceed the coil current rating.
𝐼𝐿𝑀𝐴𝑋 =
1
η
(𝐼̅𝐿 +
Δ𝐼𝐿
)
2
Use low resistance (DCR, ACR) coils to minimize coil loss and increase efficiency.
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When load current is low, DC / DC1 operates discontinuously so set ΔIL in a way it operates continuously (IL1 keeps
continuously flowing).
The condition of continuous operation is shown in the following equation.
・DC / DC1
𝐼𝑂1 >
(𝑉𝐶𝐶 − 𝑉𝑂1 ) × 𝑉𝑂1
2 × 𝑉𝐶𝐶 × 𝑓𝑆𝑊 × 𝐿1
(IO1: Load current)
SW1
SW1
IO1
ΔIL1
IO1
Figure 36. Continuous operation
Figure 37. Discontinuous operation
IOLIMIT
IO1
Figure 38. Over current detection
Shielded type inductor (closed magnetic circuit) is recommended. Open magnetic circuit type inductor can be used for low
cost applications if noise is not of concern. But in this case, there is magnetic field radiation between the parts and thus
keep enough spacing between the parts.
For ferrite core inductor type, please note that magnetic saturation may occur. Saturation needs to be avoided at all times.
Precautions must be taken into account on the given provisions of the current rating because it differs according to each
manufacturer.
Please confirm the rated current at the maximum ambient temperature of the application to the coil manufacturer.
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2.
Setting the output capacitor CVO1, CVO2 value (DC / DC1, DC / DC 2)
The maximum output current is limited by the over current protect operation current as shown in below equation.
𝛥𝐼𝐿
2
𝐼𝑂(𝑀𝐴𝑋) = 𝐼𝐿𝐼𝑀𝐼𝑇(𝑀𝐼𝑁) −
IO (MAX): Maximum output current, ILIMIT (MIN): Minimum over current protect operation level (0.9 A) (1ch is external set)
When the ΔIL is low, the Inductor core loss (iron loss), the loss due to ESR of the output capacitor and the ΔVPP will
become low. ΔVPP is expressed as follows:
Buck mode
𝛥𝑉𝑃𝑃 = 𝛥𝐼𝐿 × 𝑅𝐸𝑆𝑅 +
∆𝐼𝐿
8 × 𝐶𝑉𝑂 × 𝑓𝑆𝑊
Boost mode
𝛥𝑉𝑃𝑃 = 𝐼𝐿𝑀𝐴𝑋 × 𝑅𝐸𝑆𝑅 +
𝐶𝑉𝑂
𝐼𝑂
𝑉𝑂 − 𝑉𝐶𝐶
×
× 𝑓𝑆𝑊
𝑉𝑂
(ESR: Output capacitor equivalence series resistance, CO: Output capacitor volume)
By using small ESR capacitor, ΔVPP voltage level can be lowered. The benefit of ceramics capacitor is low ESR and small
form factor.
The frequency characteristic of ESR from the datasheet of the manufacturer should be confirmed. Choose the ceramic
capacitor which exhibits low ESR in the switching frequency range that is used On the other hand, DC biasing
characteristics of the ceramic capacitor is significant so it needs to be carefully examined. For the voltage rating of the
ceramic capacitor, twice or more than the maximum output voltage is usually required. By selecting these high voltages
rating, it is possible to reduce the influence of DC bias characteristics. Moreover, in order to maintain good temperature
characteristics, the one with the characteristic of X7R or better, is recommended.
Because the voltage rating of ceramic capacitor is low, the selection becomes difficult in the application with high output
voltage. In that case, select electrolytic capacitor.
When using electrolytic capacitors, the voltage rating should be 1.2 times or more than the output voltage. Electrolytic
capacitors have a high voltage rating, large capacity, small amount of DC biasing characteristic, and are generally
inexpensive. Because typical failure mode is OPEN, it is effective to use electrolytic capacitor for applications where high
reliability is required such as automotive. On the other hand, disadvantages are relatively high ESR and capacitance value
drop at low temperatures. In this case, please take note that ΔVPP may increase at low temperature conditions. Moreover,
consider the lifetime characteristic of this capacitor.
When it comes to the capacitance CO, the value needs to be less than the value calculated by the equations below.
・DC / DC 1
𝐶𝑂1 (𝑀𝐴𝑋) =
0.5 𝑚𝑠 × (𝐼𝐿1𝑖𝑚𝑖𝑡 (𝑀𝐼𝑁) − 𝐼𝑂1 (𝑀𝐴𝑋) )
𝑉𝑂1
・DC / DC 2
𝐶𝑂2 (𝑀𝐴𝑋) =
0.4 𝑚𝑠 × (𝐼𝐿2𝑖𝑚𝑖𝑡 (𝑀𝐼𝑁) − 𝐼𝑂2 (𝑀𝐴𝑋)
𝑉𝑂2
(ILIMIT (MIN): Minimum over current protect operation current (1ch is external set). 2ch = 0.9 A.
Soft start Min time DC / DC1: 0.5 ms, DC / DC2: 0.4 ms, Soft start setting refer to page 34)
Boot failure may occur if the capacitance value exceeds the limits explained above. If the capacitance value is extremely
large, over-current protection may be activated by the inrush current at startup, and the output may not start.
Please confirm this on the actual circuit.
Capacitance values are critical parameter to determine the LC oscillation frequency. Transient response and loop stability
are dependent on the CVO. Please select after confirming the setting of the phase compensation circuit.
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3.
Setting the input capacitor CVCCA / CVCCB, CVS2 value (VCC, VS2)
Input capacitors reduce the power output impedance that is connected to VCC. Two types of capacitors are needed for
input capacitor, i.e., decoupling capacitor CVCCB and bulk capacitor CVCCA. The decoupling capacitors of VCC and VS2
need to be 1 μF to 10 μF ceramics. More than 22 µF are necessary for the bulk capacitor of VCC. The ceramic
capacitors are most effective when placed as close to VCC and VS2 as possible. At VCC, the ceramic capacitors need
to be placed between VCC and GND and close to PMOS and the ground of schottky barrier diode. At VS2, the ceramic
capacitor needs to be placed between VS2 and GND. Voltage rating is recommended to be more than 1.2 times the
maximum input voltage and twice the normal input voltage.
The bulk capacitor prevents line voltage drop and serves as a backup power supply to maintain the input voltage. The
low ESR electrolytic capacitor with large capacitance is suitable for the bulk capacitor. It is necessary to select the
capacitance value which best fits to each application. In case impedance of input side is high such as long wiring
between the power supply and VCC, input voltage gets unstable when output impedance of the power supply
increases resulting in oscillation or degraded ripple rejection characteristics. Large capacitor is needed in this case. It
is necessary to verify that the output does not turn off in the event of Vcc drop due to transient in the actual circuit.
Make sure not to exceed the rated ripple current of the capacitor in this case. The RMS of the input ripple current can
be obtained from the following equation.
・DC / DC 1
VCC
𝐼𝐶𝑉𝐶𝐶𝐵 (𝑅𝑀𝑆) = 𝐼𝑂1 ×
√𝑉𝑂1 (𝑉𝐶𝐶 − 𝑉𝑂1 )
𝑉𝐶𝐶
CVCCB
OUTH
L1
(ICVCCB (RMS): Input ripple current RMS value)
VO1
CVO1
Figure 39. VCC pin
・DC / DC 2
𝐼𝐶𝑉𝑆2 (𝑅𝑀𝑆) = 𝐼𝑂2
VS2
√𝑉𝑂2 (𝑉𝑆2 − 𝑉𝑂2 )
×
𝑉𝑆2
VS2
(ICVS2 (RMS): Input ripple current RMS value)
CVS2
SW2
L2
VO2
CVO2
Figure 40. VS2 pin
In automotive and other applications requiring high reliability, it is recommended that capacitors are connected in parallel
to reduce the risk of electrolytic capacitors drying out. In case of ceramic capacitors, it is recommended make it two in
series and two in parallel structures to reduce the risk of destruction due to short circuit event. Currently capacitors
containing two in series or two in parallel in one package are available in the market so please contact suppliers.
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4.
Setting the input capacitor CVS3 value
Place a capacitor which is greater than 0.1 µF between VS3 and GND. Select the capacitor considering filter circuit for
power supply and VS3. Since the capacitance value is dependent on the board layout and pattern, secure enough margin
when selecting the capacitor. Capacitors that have good voltage and temperature characteristics are recommended.
5.
Setting the output capacitor CVREG value
Place a capacitor between the VREG pin and GND to avoid oscillation. 0.47 μF or greater capacitance is recommended.
CVREG can be electrolytic capacitor or ceramic capacitor. Secure the capacitance of 0.47 μF or greater in the voltage and
temperature range in actual operating conditions. The change in capacitance value by temperature may cause oscillation.
Select the capacitors which have good temperature characteristics (X7R or better), good DC bias characteristics with high
voltage rating. In case significant voltage swing and load transient are expected, make sure to carry out thorough
evaluation before making a decision on the capacitance value.
6.
Setting the output capacitor CVDD value
Place a capacitor between VDD and GND. The capacitance needs to be 0.01 µF or greater (OUTL = open) and1 µF or
greater (OUTL in use). CVDD can be electrolytic or ceramic. Secure high enough capacitance in the voltage and
temperature range in actual operating conditions. The change in capacitance value by temperature may cause oscillation.
Select the capacitors which have good temperature characteristics (X7R or better), good DC bias characteristics with high
voltage rating. In case significant voltage swing and load transient are expected, make sure to carry out thorough
evaluation before making a decision on the capacitance value.
7.
Setting the internal drive circuit supply capacitor CVL value
Add the capacitor greater than 0.1 µF between VCC and VL. Select the capacitor considering the filter circuit for power
supply and VL. Since the capacitance value is dependent on the board layout and pattern, secure enough margin when
selecting the capacitor.
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8.
Setting output voltage (VO1)
VO2 and VO3 are fixed output while VO1 is adjustable.
VO1 output voltage is determined by the following equation.
𝑉𝑂1 = 0.8 ×
𝑅𝐹𝐵1𝐴 + 𝑅𝐹𝐵1𝐵
𝑅𝐹𝐵1𝐴
Please set feedback resistor RFB1A below 30 kΩ to reduce the error margin by the bias current. In addition, since power
efficiency is reduced when RFB1A + RFB1B is small, please set the current flowing through the feedback resistor small
enough as compared to the output current IO1.
9.
Selection of the MOSFET (M1, M2)
In case of Buck-Boost DC / DC, DC / DC1 needs 2 external MOSFET (PMOS = M1 and NMOS = M2). In case of Buck DC
/ DC, DC / DC1 needs 1 external MOSFET (PMOS). Key parameters in choosing MOSFET are voltage and current rating.
VCC
M1
L1
D1B
Vo
D1A
M2
Figure 41. Select MOSFET
(ⅰ) PMOS
o Vds maximum rating > VCC
o Vgs maximum rating > Lower value of 13 V or VCC
* The voltage between VCC - VL is kept at 10 V (Typ), 12 V (Max).
VL become 0 V when VCC become less than 10.3 V (Typ)
o Allowable current > coil peak current ILMAX
* A value above the over current protection setting is recommended.
* Choosing a low ON Resistance FET results in high efficiency.
(ⅱ) NMOS
o Vds maximum rating > VO
o Vgs maximum rating > VDD
o Allowable current > Coil peak current ILMAX
* A value above the over current protection setting is recommended.
* Choosing a low ON Resistance FET results in high efficiency.
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10. Selection of the schottky barrier diode
The diode D1A needs to be low Vf and fast Trr. Key parameters in the diode selection are average rectified current and DC
reverse voltage. Average rectified current IF (AVG) can be obtained from the following equation:
𝐼𝐹 (𝐴𝑉𝐺) = I𝑂1 (𝑀𝐴𝑋) ×
𝑉𝐶𝐶 (𝑀𝐴𝑋) − 𝑉𝑂1
𝑉𝐶𝐶 (𝑀𝐴𝑋)
(IF (AVG): Average rectified current)
The absolute maximum rating of the average rectified current in D1A needs to be 1.2 times or greater than the IF (AVG).
The absolute maximum rating of the DC reverse voltage in D1A needs to be 1.2 times or greater than the maximum input
voltage.
The DIA and DIB’s diode power loss can be obtained by the following equation:
𝑃𝐷1𝐴 = 𝐼𝑜1 (𝑀𝐴𝑋) ×
𝑉𝐶𝐶 (𝑀𝐴𝑋) − 𝑉𝑂1
𝑉𝐶𝐶 (𝑀𝐴𝑋)
× 𝑉𝐹
𝑃𝐷1𝐵 = 𝐼𝑜1 (𝑀𝐴𝑋) × 𝑉𝐹
(VF: Forward voltage of IO1 (MAX))
Selecting D1A and D1B diode that have low forward voltage and fast reverse recovery time will help achieve a high
efficiency. Select a diode with 0.6 V or lower forward voltage. The use of the diode greater than 0.6 V forward voltage may
cause inner element destruction so care has to be taken. The reverse recovery time of the schottky barrier diode is so
short and thus its switching loss is ignorable. If the diode needs to withstand the event of output short-circuit, absolute
maximum ratings and power dissipation need to be even higher. The maximum rated current needs to be approximately
1.5 times of the over current detection value. The D1A and D1B’s diode power loss at the event of output short-circuit can
be obtained by the following equation.
𝑃𝐷𝑖 (𝑆𝐻𝑂𝑅𝑇) = 𝐼𝐿𝐼𝑀𝐼 𝑇 (𝑀𝐴𝑋) × 𝑉𝐹
(ILIMIT (MAX): VO1 Maximum over current protect operation current)
11. Setting the oscillation frequency (DC / DC1, DC / DC2)
The internal oscillation frequency can be set by changing the resistance value connected to RT pin. Frequency can be set
in the range of 250 kHz to 550 kHz. The following table shows the resistance value and its corresponding oscillation
frequency. Switching may stop if the oscillation frequency is set outside of the recommended frequency range and thus
normal operation is not guaranteed in such case.
OSCILLATING FREQUENCY: FOSC [kHz]
RRT vs FOSC
600
500
400
RRT [kΩ]
FOSC [kHz]
20
564
27
424
33
350
39
298
47
250
56
211
68
175
300
200
100
0
0
20
40
60
80
OSCILLATING FREQUENCY SETTING
RESISTANCE: RRT [kΩ]
Figure 42. RT resistance vs. oscillation frequency
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*The oscillation frequency graph is typical. A certain
variation exists in actual usage.
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12. Setting the phase compensation circuit (DC / DC1)
Circuit stability and transient response characteristics are determined by phase compensation. In order to get negative
feedback stability, set phase lag when gain 1 (0 dB) equal to or less than 135 ˚ (greater than 45 ˚ phase margin).
Good frequency response can be realized by setting higher zero crossing frequency fc (frequency at 0 dB gain) of the
total gain. However, speed and stability are in trade-off relationship. Moreover, DC / DC converter application is sampled
by switching frequency and the gain of the switching frequency needs to be suppressed. In order to do so, zero crossing
frequency needs to be set equal to or lower than 1 / 10 of the switching frequency.
To improve the responsiveness, switching frequency needs to be raised. It is recommended to draw a Bode plot using
the transfer function of control loop in order to get a frequency response necessary. Please confirm the frequency
characteristics of the total gain by combining the below three transfer functions.
𝐺𝐿𝐶 =
𝑠
2𝜋 × 𝑓𝐸𝑆𝑅
1+
1+
𝐺𝐹𝐵1 =
𝐺𝑃𝑊𝑀 =
･･･ (a)
2
𝑠
𝑠
)
+(
𝑄 ×2𝜋 × 𝑓𝐿𝐶
2𝜋 × 𝑓𝐿𝐶
𝑠
𝑠
)×(1 +
)
2𝜋 × 𝑓𝑍1
2𝜋 × 𝑓𝑍2
𝑠
𝑠
)×(1+
)
×𝑅𝐹𝐵1𝐵 ×𝐶𝐶𝑂1𝐴 ×(1+
2𝜋 × 𝑓𝑃1
2𝜋 × 𝑓𝑃2
(1 +
𝑠
･･･ (b)
𝑉𝐶𝐶
･･･ (c)
∆𝑉𝑅𝐴𝑀𝑃
(GLC: transfer function of LC resonance, GFB: transfer function of phase compensation,
GPWM: transfer function of PWM, ΔVRAMP: 0.4 V, Q: LC quality factor)
Since DC / DC1 of the BD39001EKV-C is voltage mode, it is possible to add 2-pole and 2-zero compensation as follows.
The frequency of zero and pole is determined by the following equations:
DCR
SW1
L1
VO1
D1
ESR
CVO1
RFB1C
CCO1B
CCO1A RCO1
RFB1B
RVO1
CFB1
COMP1
FB1
ERRAMP
VREF
RFB1A
Figure 43. Phase compensation circuit (DC / DC1)
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𝑓𝐿𝐶 =
𝑓𝐸𝑆𝑅 =
𝑓𝑍1 =
𝑓𝑍2 =
𝑓𝑃1 =
1
𝑅𝑉𝑂1 +𝐷𝐶𝑅+ 𝑅𝑂𝑁
2π
√𝐿1 ×𝐶
𝑉𝑂1
･･･ (d)
(𝑅𝑉𝑂1 +𝐸𝑆𝑅)
1
･･･ (e)
2π ×ESR ×𝐶𝑉𝑂1
1
･･･ (f)
2π ×𝑅𝐶𝑂1 ×𝐶𝐶𝑂1𝐴
1
･･･ (g)
2π × (𝑅𝐹𝐵1𝐵 +𝑅𝐹𝐵1𝐶 ) ×𝐶𝐹𝐵1
𝐶𝐶𝑂1𝐴 +𝐶𝐶𝑂1𝐵
･･･ (h)
2π × 𝑅𝐶𝑂1 ×𝐶𝐶𝑂1𝐴 × 𝐶𝐶01𝐵
f𝑃2 = 2𝜋×𝑅
1
･･･ (i)
𝐹𝐵1𝐶 ×𝐶𝐹𝐵1
(DCR: Inductor DC resistance, RO: Load resistance, RON: MOS FET ON resistance)
The frequency characteristics are optimized by placing pole and zero at most appropriate frequencies. The estimate is as
follows.
0.2 × 𝑓𝐿𝐶 ≤ 𝑓𝑍1 ≤ 𝑓𝐿𝐶
･･･ (j)
0.5 × 𝑓𝐿𝐶 ≤ 𝑓𝑍2 ≤ 𝑓𝐿𝐶 × 2
･･･ (k)
𝑓𝑃1 ≈ 𝑓𝐶 × 5 = 𝑓𝑆𝑊 × 0.5
･･･ (l)
𝑓𝑃2 ≈ 𝑓𝐸𝑆𝑅
･･･ (m)
(fc: Zero cross frequency、fSW: DCDC1 switching frequency)
The phase compensation set as explained can cancel out the second order lag (-180 ˚) caused by LC resonance.
If fESR is positioned higher than DC / DC switching frequency such as using low ESR ceramic for output cap, fP2 is not
necessary.
If LC filter Q (quality factor) is high, the gain has peak and phase rotates too fast resulting in not enough phase margin. In
such case, set fZ1 and fZ2 as close to fLC as possible. Q (quality factor) is calculated by following equation:
Q=
√𝐿1 ×𝐶𝑉𝑂1 × 𝑅𝑉𝑂1 (𝑅𝑉𝑂1 +𝐸𝑆𝑅)
･･･ (n)
𝐿1+𝐶𝑉𝑂1 × 𝑅𝑉𝑂1 ×𝐸𝑆𝑅
𝐶𝑉𝑂1
≈ 𝑅𝑉𝑂1 × √
･･･ (o)
𝐿1
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13. Phase compensation circuit (DC / DC2)
DC / DC2 is current mode control and is 2-pole and 1-zero system. It has two poles formed by error amp and output load
and one zero added by phase compensation. The appropriate pole point and zero point placement results in good
transient response and stability. Generic Bode plot of DC / DC converters is shown below. At point (a), gain starts falling
due to the pole formed by output impedance of error amp and C CO2 capacitance. After that, in order to cancel out the
pole formed by output load, insert zero formed by RCO2 and CCO2 and offset the fluctuation of gain and phase before
reaching out to point (b).
(a)
A
Gain [dB]
GBW (b)
0
F[kHz]
FCRS
PHASE[deg]
0
-90°
-90
Phase margin
-180°
-180
F[kHz]
Figure 44. Phase compensation level
External component values are determined in this way. The R CO2 determines the cross over frequency FCRS, i.e., the
frequency at which DC / DC total gain falls down to 0 dB. When FCRS is set high, good transient response is expected
but stability is sacrificed on the other hand. When F CRS is set low, good stability is expected but transient response is
sacrificed on the other hand.
In this example, component value is set in a way F CRS is 1 / 5 to 1 / 10 of the switching frequency.
(i) RCO2 for Phase compensation
Phase compensation resistor RCMP can be obtained by the following equation.
𝑅𝐶𝑂2 =
2𝜋 × 𝑉𝑂2 × 𝐹𝐶𝑅𝑆 × 𝐶𝑉𝑂2
0.8 × 𝐺𝑁𝑃 × 𝐺𝑀𝐴
(Ω)
VO2: Output voltage, FCRS: Cross over frequency, CVO2: Output capacitor, VFB2: Feedback reference voltage (0.8 V (Typ)),
GMP: Current sense gain (16.7 A / V (Typ)), GMA: Error amp trans-conductance (220 uA / V (Typ))
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(ii) CCO2 for Phase compensation
Phase compensation capacitor CCO2 can be obtained by the following equation.
𝐶𝐶𝑂2 =
𝑉𝑂2 × 𝐶𝑉𝑂2
(F)
𝐼𝑂2 × 𝑅𝐶𝑂2
L2
DCR
SW2
VO2
CVO2
RVO2
CFB2
RFB2B
COMP2
FB2
RCO2
RFB2A
ERRAMP
0.8V
CCO2
Figure 45. Phase compensation circuit (DC / DC2)
However these are simple equation and thus adjustment of the value using the actual product may be necessary for
optimization. Also compensation characteristics are influenced by PCB layout and load conditions and thus thorough
evaluation using the production intent unit is recommended.
14. Phase compensation circuit (DC / DC1, DC / DC2)
The way to start designing phase compensation circuit is as explained. Create a Bode plot and check if targeted frequency
characteristics are met. The frequency characteristics pretty much fluctuate depending on PCB layout, type of
components used and operating conditions. For instance, using electrolytic capacitor for output stability may cause the
shift of LC resonance resulting in oscillation due to the capacitance drop at low temp and relevant ESR increase. For
phase compensation, temperature compensating type capacitor is recommended. Make sure to check stability and
responsiveness in actual product.
Frequency characteristics are checked by gain phase analyzer or FRA. Ask each vendor for measurement method. Even
you such measurement equipment is unavailable, phase margin can be estimated from transient load response. Monitor
how the output waveform fluctuates when changing from no load to maximum load. If the output fluctuation is significant,
response time is slow. If the ringing is frequent, phase margin is not enough. Twice or less ringing is appropriate. The
phase margin however cannot be quantified in this check method.
Output load
Maximum load
0
Phase margin: little
Output voltage
Phase margin: good
t
Figure 46. Load response
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15. Phase compensation circuit (LDO3)
VO3 pin capacitor
The capacitor must be added between VO3 pin and GND in order to stop from having it Oscillated and the recommended
Capacitance value is more than 10uF. In accordance to graph shown in below, either Electrolytic or Ceramic Capacitor can
be used. Please ensure to select the Capacitor higher than 10uF in the range of voltage and temperature to be used at.
There is possibility of oscillation when capacitance value changes due to change of temperature. When selecting a
ceramic capacitor, X7R or higher is recommended which is good in temperature characteristic and has excellent DC bias
characteristic. In case significant voltage swing and load transient are expected, make sure to carry out thorough
evaluation before making a decision on the capacitance value.
○Condition
VCC = 12 V
VS3 = 6.5 V
0 mA ≤ IO3 ≤ 600 mA
10 µF ≤ CVO3 ≤ 100 µF
CVO3 VS. RESR
100
RESR[Ω]
10
1
0.1
0.01
10
22
33
47
68
100
CVO3[uF]
Figure 47. Output capacitor value CVO3 vs Output capacitor RESR
VO3
CVO3
RESR
IO3
Figure 48. Output capacitor and ESR measurement circuit
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16. Over Current Protection (OCP) Function (DCDC1)
Once coil current that flows through OCP sensing resistor R CL exceeds OCP detection level, OCP starts functioning. The
setting method is shown below.
Selecting OCP sensing resistor - RCL
In the state of OCP detection, the relation of coil current-IL (OCP), load current-IO (OCP) and current sensing resistor-RCL are
shown in the following form. The VCC value that used to calculate IL (OCP) is the minimum or the maximum value of VCC,
whichever can finally generate the maximum IL (OCP) value.
BUCK MODE
BUCK-BOOST MODE
BOOST MODE
VCC ≥ 1.333 × Vo
1.333 × Vo > VCC ≥ 0.625 × Vo
VCC < 0.625 × Vo
𝑅𝐶𝐿 =
0.1
𝐼𝐿(𝑂𝐶𝑃)
𝐼𝐿(𝑂𝐶𝑃) = 𝐼𝑂(𝑂𝐶𝑃) +
∆𝐼𝐿
2
(𝑉𝐶𝐶 − 𝑉𝑜) × 𝑉𝑜
∆𝐼𝐿 =
𝑉𝐶𝐶 × 𝑓𝑠𝑤 × 𝐿
𝐼𝐿(𝑂𝐶𝑃) =
𝑉𝑜 × 𝐼𝑂(𝑂𝐶𝑃) ∆𝐼𝐿
+
𝑉𝐶𝐶 × 𝜂
2
VCC > Vo
(𝑉𝐶𝐶 − 𝑉𝑜) × 𝐷𝑝𝑜𝑛
∆𝐼𝐿 =
𝐿 × 𝑓𝑠𝑤
(𝑉𝐶𝐶 − 𝑉𝑜) × 2.13 × 𝑉𝑜
=
𝐿 × 𝑓𝑠𝑤 × (𝑉𝐶𝐶 + 1.5 × 𝑉𝑜)
VCC < Vo
(𝑉𝑜 − 𝑉𝐶𝐶) × 𝐷𝑛𝑜𝑓𝑓
𝐿 × 𝑓𝑠𝑤
(𝑉𝑜 − 𝑉𝐶𝐶) × 2.13 × 𝑉𝐶𝐶
=
𝐿 × 𝑓𝑠𝑤 × (𝑉𝐶𝐶 + 1.5 × 𝑉𝑜)
∆𝐼𝐿 =
∆𝐼𝐿 =
(𝑉𝑜 − 𝑉𝐶𝐶) × 𝑉𝐶𝐶
𝑉𝑜 × 𝐿 × 𝑓𝑠𝑤
VCC: minimum or maximum voltage of VCC, VO: output voltage, fSW: switching frequency, L: inductance value
η: efficiency (It is necessary to measure on real board, as an reference:80%~90%)
In Figure 49 (BUCK-BOOST MODE) and Figure 50 (BUCK MODE), the reason of OCPH detection were considered
Schottky diode break down and SW1 short to GND.
VCC
VCC
RCL
RCL
M1
M1
L1
SW2 D1B
L1
Vo
SW1
D1A
M2
D1A
CVO1
CVO1
Figure 50. BUCK Mode OCPH Detection
Figure 49. BUCK-BOOST Mode OCPH Detection
①
Vo
SW1
BUCK DCDC Application
When PchFET ON, once coil current × OCP sensing resistor RCL exceed VCCCL-CL voltage (100mV Typ), OCPL
detection start working. In the condition of OCPL detect, on pulse width of PchFET be fixed, output voltage Vo
decreases. If FB voltage lower than SCP detection level and continue 256clks, PchFET OFF, COMP and SS are
discharged forcibly. After 8192clks, IC turn back to normal operation and SS be recharged again. (Figure 51) In addition,
If VCCCL-CL voltage decrease to less than 100mV (Typ) within 256 clks, IC turns back to normal operation immediately.
(Figure 52) Additionally, when VCCCL-CL voltage exceeds 200mV (Typ), OCPH detection start working, meanwhile
PchFET OFF, COMP and SS are discharged forcibly. After 8192clks, IC turn back to normal operation and SS be
recharged.
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Io
Io
OCPL detection
VCC-CL=100mV
IL
IL
Vo
Vo
0.8V
FB
SCP
detection
SCP
detection
FB
256clk
PGOOD
Under
256clk
PGOOD
8192clk
SS
SS
COMP
COMP
Figure 52. OCPL Detection
Figure 51. OCPL Detection・Release
②
OCPL detection
VCC-CL=100mV
BUCK-BOOST DCDC Application
In BUCK-BOOST DCDC Application, OCPL and OCPH function waves are as same as BUCK DCDC Application. (Refer
to Figure 21) However, an exception rarely occurs - load current over OCPL detect current in a moment and turn to
normal level within 256clks, but SS still be discharged. Please refer to the detail in the following section.
Once OCPL detected, Vo voltage decreases at first. Then Vo have the trend of increasing output voltage that been set
as target output t in advance, so that DCDC come into BUCK-BOOST MODE and COMP voltage rise up. Finally, ON
pulse width of NchFET is extended. Because coil current increases is depending on several essential factor (Input and
output, frequency condition, load applying waveform, reply properties), the following 2 phenomenon related to OCPL is
rarely occurs and could be automatically recover after Vo drop to 0V.
(1) VCCCL-CL voltage exceeds 200mV within OCPL 256clks’ on pulse width limitation period.
(2) Even if load current decreases after OCPL detected, coil current keep increasing and an OCPL detection state
won’t stop until SS discharged.
The setting resistance of the OCP is from 1.2 times to 1.5 times of the rush current. Please check on application
board.
(2)
(1)
Load current decrease
Io
Io
OCPH detection
VCC-CL=200mV
OCPL detection
VCC-CL=100mV
IL
IL
OCPL detection
VCC-CL=100mV
Vo
Vo
FB
PGOOD
0.8V
SCP
detection
FB
Under
256clk
SS
PGOOD
8192clk
SS
SCP
detection
256clk
8192clk
COMP
COMP
Figure 53. OCPH Detection・Release
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Figure 54. OCPL Detection・Release
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17. Provision of Capacitor connected to CL terminal
The capacitor (CCL) and resistor (RCLB) connected to CL pin are the CR noise filter for preventing OCP error detection.
For the constant setting of filter, since noise depends on
circuit and board pattern, there is no fixed rule. But, please
try reducing cut-off frequency of CR filter without
deteriorating ON pulse waveform that requires detecting
current sense.
Pulse width≈ (VO1 / VCC) × (1 / FOSC)
(The rough estimate setting is RCLB = 10kΩ, CCL = 0.1µF)
CCL
CL
RCLA
VCC
RCLB
OUTH
Figure 55. CL pin filter circuit
18. Soft Start setting
The soft start function is necessary to prevent inrush of coil current and output voltage overshoot at start up.
Setting of soft start time is shown in the following equation.
・DC / DC1
𝑇𝑆𝑆1 =
𝑉𝑆𝑆0 × 𝐶𝑆𝑆1 𝑉𝑅𝐸𝐹08 × 𝐶𝑆𝑆1
+
≥ 0.5𝑚𝑠
𝐼𝑆𝑆0
𝐼𝑆𝑆1
In addition, Please take SS1 discharge time (TSS1DIS) into account, when start up this IC with VCC_UVLO function or EN
pin. If SS1 is not finish discharge, it is possible that this IC can't do re-start.
𝑇𝑆𝑆1𝑑𝑖𝑠 ≥ 𝐶𝑆𝑆1 × 2.2 × 103
(For example: If 𝐶𝑠𝑠1 = 33𝑛𝐹, 𝑇𝑆𝑆1𝑑𝑖𝑠 = 72.6𝜇𝑠)
・DC / DC2
𝑇𝑆𝑆2 =
𝑉𝑆𝑆2 × 𝐶𝑆𝑆2
≥ 0.4𝑚𝑠
𝐼𝑆𝑆2
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19. Setting the CT power on reset time
Power reset setting time can be set by the capacitor connected to CT
Capacitance can be chosen from 0.01 μF to 1 μF range or have CT terminal OPEN.
If setting is made out of its range, chattering may occur at Reset output.
CT operation is changed by the time of error detection. See page 15, Figure 26 for detail.
(1) CT pin starts 0 V
Power ON Reset Time: tPOR[ms]
CT vs tPOR
200
CCT [μF]
0.001
tPOR [ms]
0.167
180
0.0082
1.09
160
0.01
1.62
140
0.022
3.46
120
0.033
5.24
100
0.047
7.64
80
0.068
10.8
60
40
20
0.1
16
0.22
36.2
0.47
76.8
1
159
0
0
0.25
0.5
0.75
1
POR SETTING CAPACITOR:
CCT[μF]
Figure 56. Power ON Reset time1 (VCT = 0 V to 0.8 V(Typ))
𝑡 = 𝐶𝑉/𝐼
(C: CT pin capacitance value, V: Reset release voltage 0.8V, I: Charge current value 5µA)
(2) CT pin starts 0.2 V
Power ON Reset Time: tRST[ms]
CCT vs tRST
200
180
160
140
120
100
80
60
40
20
0
0
0.25
0.5
0.75
CCT [μF]
0.001
tRST [ms]
0.16
0.0082
0.826
0.01
1.452
0.022
2.51
0.033
3.93
0.047
5.82
0.068
7.9
0.1
14.12
0.22
26.7
0.47
57.2
1
114.4
1
POR SETTING CAPACITOR:
CCT[μF]
Figure 57. Power ON Reset time2 (VCT = 0.2 V (Typ) to 0.8 V(Typ))
𝑡 = 𝐶(𝑉1 − 𝑉2 )/𝐼
(C: CT pin capacitance value, V1: Reset release voltage 0.8V, V2: CT pin voltage 0.2V, I: Charge current value 5µA)
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20. Setting the WDT oscillation frequency
WDT oscillation frequency can be set by resistance value connected to RTW. Possible setting range is 50 kHz to 250 kHz and the
relation between resistance value and oscillation frequency is decided as shown below.
It is possible that the WDT stops at outside these range and its operation is not guaranteed.
WDTOSCILLATING FREQUENCY: FOSCW [kHz]
RRTW vs FOSCW
450
400
350
300
250
200
150
100
50
RRTW [kΩ]
FOSCW [kHz]
18
22
27
33
47
51
62
75
82
100
120
268
221
182
151
108
100
83
69
64
53
45
0
0
40
80
120
160
OSCILLATING FREQUENCY SETTING
RESISTANCE: RRTW [kΩ]
*This oscillation frequency graph is typical value
Tolerance needs to be put into consideration.
Figure 58. WDT oscillation frequency characteristics
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21. Recommend value of external pull - up resistance
VREG
PG pin ON resistance (PPUPG)
Min = 0.5 kΩ, Typ = 1.0 kΩ, Max = 2.0 kΩ
VO3
RPUPG
RPUPG
PG
PG
RPG
RPG
𝑅𝑃𝐺
𝑅𝑃𝐺 +𝑅𝑃𝑈𝑃𝐺
× 𝑉𝑂3 > 𝑉𝑃𝐺
(V)
Please set the Resistance value considering H threshold of
PG pin.
Figure 59
22. Provision of EN1 pull -up resistance
Because "H" threshold of EN1 is Min 2.5 V, please design as the below equation is able to work.
𝑅𝐸𝑁1𝐵
VCC
𝑅𝐸𝑁1𝐵 +𝑅𝐸𝑁1𝐴
× 𝑉𝐶𝐶 > 2.5
(V)
REN1A
EN
(188 kΩ ≤ REN1B ≤ 750 kΩ)
REN1B
Figure 60
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Application Examples
*There are many factors (Board layout, variation of the part, etc.) that can affect the characteristics.
Please verify and confirm using practical applications.
*No connection (N.C) pin should not be connected to any other lines.
*Be sure to connect the TEST pin to ground.
* If EN1 pin is connected to VCC pin, please insert resistance between the pins.
CVCCA
REN1A
CVCCB
VCC
EN1
VREG
power gnd
CVREG
VO1
RFB1C
CSS1
CFB1
CCO1A
RFB1A
CCL
CVL
RCLA
RCLB
OUTH
RT
RRT
RFB1B
CL
M1
VL
SS1
VDD
FB1
OUTL
L1
VCDD
D1A
power gnd
CVO1A
M2
CCO1B
RCO1
VO1
D1B
CVO1B
power gnd
COMP1
PGND1
power gnd
VO2
CSS2
SS2
VS2
CVS2
FB2
SW2
L2
power gnd
VO2
CVO2
power gnd
COMP2
PGND2
RCO2
CCO2
VO1
power gnd
EN2
VO3
VO3
CVO3
VS3
CT
CVS3
power gnd
RRTW
power gnd
CCT
RRST2
RRST3
RRSTW
RPUPG1
RPUPG2
RPUPG3
EN3
SEQ2
RST2#
SEQ3
RST3#
ENWD
RSTWD#
CLK
PG1
RTW
PG2
SEL_UVLO
PG3
GND
Figure 61. Application Example 2 (DC / DC1 Buck - Boost)
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Application Examples
*There are many factors (Board layout, variation of the part, etc.) that can affect the characteristics.
Please verify and confirm using practical applications.
*No connection (N.C) pin should not be connected to any other lines.
*Be sure to connect the TEST pin to ground.
* If EN1 pin is connected to VCC pin, please insert resistance between the pins.
REN1A
CVCCA
VCC
CVCCB
EN1
CL
VERG
power gnd
CVL
CCL
RCLA
RCLB
OUTH
M1
CVREG
RT
VO1
RFB1C
RFB1B
CSS1
CFB1
CCO1A
RFB1A
VL
RRT
SS1
VDD
FB1
OUTL
L1
CVDD
D1A
CCO1B
RCO1
VO1
D1B
CVO1B
CVO1A
power gnd
COMP1
PGND1
power gnd
VO2
CSS2
SS2
VS2
FB2
SW2
CVS2
L2
VO2
power gnd
CVO2
power gnd
COMP2
PGND2
RCO2
CCO2
VO1
VO3
power gnd
EN2
VO3
CVO3
VS3
CT
CVS3
power gnd
power gnd
CCT
RRST2
RRST3
RRSTW
RPUPG1
RPUPG2
RPUPG3
EN3
SEQ2
RST2#
SEQ3
RST3#
ENWD
RSTWD#
CLK
PG1
RTW
PG2
RRTW
SEL_UVLO
PG3
GND
Figure 62. Application Example 3 (DC / DC1 Buck)
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Example of Constant Setting (DC / DC1 Buck Mode)
Name
IC
-
Value
-
Parts No.
BD39001EKV-C
Size Code
10 × 10 mm
Maker
ROHM
REN1A
150
kΩ
MCR03
1608
ROHM
RRT
33
kΩ
MCR03
1608
ROHM
RFB1A
10
kΩ
MCR03
1608
ROHM
RFB1B
68
kΩ
MCR03
1608
ROHM
RFB1C
1.6
kΩ
MCR03
1608
ROHM
At Buck-Boost: 0.1 kΩ
RCO1
36
kΩ
MCR03
1608
ROHM
At Buck-Boost: 4.7 kΩ
RCO2
20
kΩ
MCR03
1608
ROHM
RRTW
51
kΩ
MCR03
1608
ROHM
RCLA
110
mΩ
MCR10
2012
ROHM
RCLB
10
kΩ
MCR03
1608
ROHM
RRST2
10
kΩ
MCR03
1608
ROHM
RRST3
10
kΩ
MCR03
1608
ROHM
RRSTW
10
kΩ
MCR03
1608
ROHM
RPUPG1
10
kΩ
MCR03
1608
ROHM
RPUPG2
10
kΩ
MCR03
1608
ROHM
RPUPG3
10
kΩ
MCR03
1608
ROHM
Electrolytic capacitor
GCM
GCM
GCM
GCM
GCM
GCM
GCM
GCM
GCM
GCM
GCM
GCM
Hybrid capacitor
GCM
Hybrid capacitor
GCM
GCM
CLF12577NIT-470M-D
CLF6045NIT-100M-D
RB050L-40DD
RB050L-40DD
RSD046P05FRA
RSD080N06FRA
1608
1608
1608
1608
1608
1608
1608
1608
1608
1608
1608
1608
2012
3216
1608
12.5 × 12.8 mm
6 × 6.3 mm
2.6 × 5.0 mm
2.6 × 5.0 mm
6.5 × 9.5 mm
6.5 × 9.5 mm
murata
murata
murata
murata
murata
murata
murata
murata
murata
murata
murata
murata
murata
murata
murata
TDK
TDK
ROHM
ROHM
ROHM
ROHM
CVCCA
CVCCB
CVREG
CVDD
CSS1
CFB1
CSS2
CCO1A
CCO1B
CCO2
CVS3
CCL
CVL
CVO1A
CVO1B
CVS2
CVO2
CVO3
CCT
L1
L2
D1A
D1B
M1
M2
47
µF
2.2
µF
1
µF
0.1
µF
0.033
µF
820
pF
0.047
µF
2200
pF
33
pF
2200
pF
1
µF
0.1
µF
0.1
µF
100
µF
OPEN
4.7
µF
100
µF
10
µF
0.1
µF
47
µH
10
µH
SBD
SBD
pchFET
nchFET
Note
At Buck-Boost: 1 µF
At Buck-Boost: 2200 pF
At Buck-Boost: 47000 pF
At Buck-Boost: 100 pF
At Buck-Boost: 47 μF
At Buck-Boost: 44 μF
Only Buck-Boost
Only Buck-Boost
Notes for pattern layout of PCB
1)
2)
3)
4)
5)
6)
Design the wirings shown in bold line as short as possible.
Place the input ceramic capacitor CVCCB as close to M1 as possible.
Place the RRT and RRTW as close to GND pin as possible.
Place the RFB1A and RFB1B as close to FB1 pin as possible and provide the shortest wiring from FB1 pin.
Place the RFB1A, RFB1B and FB2 as far away from L1 and L2 as possible.
Separate power GND and signal GND so that SW noise doesn’t affect the signal GND.
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Sequence function
DC / DC2 and LDO output sequence can be set with EN2, EN3, SEQ2 and SEQ3 pin.
Ex. 1) EN2, EN3, SEQ2 and SEQ3 pins are open
DC / DC1→LDO and DC / DC2 start at once.
LVD2 Release Voltage = Under voltage detection voltage (VRST2) + Under voltage hysteresis voltage (VRSTH2).
LVD3 Release Voltage = Under voltage detection voltage (VRST3) + Under voltage hysteresis voltage (VRSTH3).
EN2
DC / DC2
VCC_UVLO
VCC
150Ω
VS_UVLO
Soft Start（SS1）
VO1(Buck-Boost DC / DC)
EN3
LDO
150Ω
EN2
SEQ2
LVD2
Release voltage
VO2(Secondary DC / DC2)
1kΩ
LVD2
（DC / DC2)
1kΩ
LVD3
（LDO)
EN3
VO3(Secondary LDO)
SEQ3
LVD3
Release voltage
ｔRST
CPOR
RST2#
RST3#
Figure 63. Start sequence example 1
Ex. 2) Condenser connects to EN pin
VCC
EN1
EN2
150Ω
CEN2
SS1
DC / DC2
Soft Start
EN3
VS_UVLO
LDO
VO1(VS2, VS3)
150Ω
EN2
SEQ2
Soft Start
SS2
VO2
LVD2
（DC / DC2)
1kΩ
LVD3
（LDO)
LVD2 Release voltage
SEQ3
EN3
VO3
1kΩ
LVD3 Release voltage
CT
RST
ｔRST
Figure 64. Start sequence example 2
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Power Dissipation
Maximum Junction Temperature Tj is 150 °C. If the junction temperature reaches 175 °C or higher, the circuit will be shut
down. Please make sure that the junction temperature must not exceed 150C at all time.
For thermal design, be sure to operate the IC within the following conditions.
(Since the temperatures described hereunder are all guaranteed temperatures, take margin into account.)
1. Ambient temperature Ta is less than 125 °C.
2. Tj is less than 150 °C.
Temperature Tj can be calculated by two ways as below.
1. To obtain Tj from the IC surface temperature Tc in actual use
𝑇𝑗 = 𝑇𝐶 + 𝜃𝑗𝑐 × 𝑃𝑇𝑂𝑇𝐴𝐿
2. To obtain Tj from the ambient temperature Ta
𝑇𝑗 = 𝑇𝑎 + 𝜃𝑗𝑎 × 𝑃𝑇𝑂𝑇𝐴𝐿
The heat loss of the IC (PTOTAL) is calculated by the equation below.
𝑃𝑇𝑂𝑇𝐴𝐿 = 𝑃1 + 𝑃2 + 𝑃3
・DC / DC1
𝑃1 = 𝑉𝐶𝐶 × 𝐼𝐶𝐶
・DC / DC2
𝑉𝑂2
𝑉𝑆2 − 𝑉𝑂2
𝑃2 = {𝑅𝑜𝑛𝐻2 × 𝐼𝑂2 2 × (
)} + {𝑅𝑜𝑛𝐿2 × 𝐼𝑂2 2 ×
}
𝑉𝑆2
𝑉𝑆2 – 𝑇𝑜𝑓𝑓2)
𝑓
+ {𝑉𝑓 × 𝐼𝑂2 × (𝑇𝑜𝑓𝑓2 × 𝑓)} + (𝑇𝑟2 × 𝑉𝑆2 × 𝐼𝑂2 × )
2
+(𝑇𝑓2 × 𝑉𝑆2 × 𝐼𝑂2 × 𝑓/2)
・LDO
𝑃3 = (𝑉𝑆3 – 𝑉𝑂3 ) × 𝐼𝑂3 + 𝑉𝑆3 × 𝐼𝐶𝐶3
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・DC / DC2
OUTH2
VS2
OUTL2
OUTH2
Tr
SW2
①
VIN
OUTL2
SW wave
PGND1
③
GND
④
②
⑤
Figure 65. SW2 wave and circuit
①The loss of ON Duty
𝑅𝑜𝑛𝐻2 × 𝐼𝑂2 × 𝐼𝑂2 ×
②The loss of OFF Duty
③The loss of OFF / OFF
𝑅𝑜𝑛𝐿2 × 𝐼𝑂2 × 𝐼𝑂2 ×
𝑉𝑂2
𝑉𝑆2
𝑉𝑆2 − 𝑉𝑂2
𝑉𝑆2 – Toff2 × f
Vf × 𝐼𝑂2 × (Toff2 × f)
𝑓
④The loss of Tr2
Tr2 × 𝑉𝑆2 × 𝐼𝑂2 ×
⑤The loss of Tf2
Tf2 × 𝑉𝑆2 × 𝐼𝑂2 × 2
2
𝑓
RONH2: ON resistor of internal Pch-PowTr
RONL2: ON resistor of internal Nch-PowTr
VO1: DC / DC1 output voltage
VO2: DC / DC2 output voltage
VO3: LDO output voltage
VCC: Input voltage (VS2 = VO1, VS3 = VO1)
Io2: DC / DC2 output current
Io3: LDO output current
IVCC: circuit current (see page 5)
ICC3: VS3 circuit current (About 1mA)
Vf: Internal Nch-PowTr’s body diode (About 1.3 V)
Tr2: Switching rise time (About15 ns)
Tf2: Switching fall time (About15 ns)
Toff2: DC / DC2 dead time (About 65 ns)
f: Oscillation frequency
See the thermal derating characteristics (Figure 66) if the device used over the ambient temperature Ta = 25 °C.
The characteristics of IC largely depend on temperature, and IC must be used at maximum junction temperature (Tjmax) or
lower. Even if the ambient temperature is 25 °C, there is a possibility junction temperature gets high as consequence of input
voltage and load current. IC must be used within power dissipation Pd.
Thermal resistance value θja is varied by the number of the layer and copper foil area of the PCB.
See Figure 66 for the thermal design.
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Thermal Derating Characteristics
Power Dissipation : Pd （W)
6
IC mounted on ROHM standard board
・Board size: 70 mm × 70 mm × 1.6 mm
・PCB and back metal are connected by soldering
④5.00 W
5
①1 layer board 70 × 70 × 1.6 mm (copper foil area 0 mm × 0 mm)
②2 layer board 70 × 70 × 1.6 mm (copper foil 15 mm × 15 mm)
③2 layer board 70 × 70 × 1.6 mm (copper foil 70 mm × 70 mm)
④4 layer board 70 × 70 × 1.6 mm (copper foil 70 mm × 70 mm)
③3.60 W
4
3
Board①: θja = 89.3 °C / W
Board②: θja = 69.4 °C / W
Board③: θja = 34.7 °C / W
Board④: θja = 25.0 °C / W
②1.80 W
2
①1.40 W
1
0
0
25
50
75
100
125
150
Ambient Temperature: Ta(℃)
Figure 66. Package data of HTQFP48V (Reference data)
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I / O Equivalence Circuit
1. VO3
3. VS3
4, 5. VS2
VS2
VS3
VS3
VO3
LDO
Circuit
GND
DC/DC2
Circuit
GND
GND
7, 8. SW2
10, 11. PGND2
12. SS2
VREG
VS2
PGND2
SS2
SW2
GND
PGND2
GND
13. COMP2
14. FB2
VREG
VREG
COMP2
FB2
GND
GND
15. VDD
VCC
VDD
16. OUTL
PGND1
17. PGND1
19. VL
VCC
VDD
PGND1
VL
DC / DC1
Driver Circuit
OUTL
GND
PGND1
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PGND1
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I / O Equivalence Circuit
21. OUTH
23. CL
VCC
OUTH
24. VCC
VCC
VCC
CL
CL
GND
GND
VL
PGND1
25. EN1
26. T4
27. VREG
VCC
VCC
VREG
EN1
VREG
T4
GND
GND
GND
28. SS1
VCC
29. COMP1
30. FB1
VREG
VREG
COMP1
FB1
GND
GND
SS1
GND
31. RT
33, 34
RST2#, RST3#
35. RSTWD#
VREG
RST2#
RST3#
RSTWD
GND
GND
RT
GND
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I / O Equivalence Circuit
36. CT
LDO_PREREG
37. RTW
38. CLK
VREG
VREG
CLK
RTW
GND
GND
GND
39. ENWD
VREG
ENWD
GND
40. EN3
VREG
VREG
EN3
EN2
GND
GND
42, 43, 44, 45, 46
SEQ3, SEQ2, PG3, PG2, PG1
PG1
PG2
PG3
SEQ2
SEQ3
GND
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41. EN2
47. T3
48. SEL_UVLO
VREG
VREG
T3
SEL_UVLO
GND
GND
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Operational Notes
1.
Reverse Connection of Power Supply
Connecting the power supply in reverse polarity can damage the IC. Please make sure to have protection against
reverse polarity, such as putting an external diode between the power supply and the IC’s power supply pins.
2.
Power Supply Lines
Power supply line must be low impedance on the PCB. The power supply of digital and analog must be separated
(even if the electrical potentials are the same) to prevent analog circuit from having digital noise by common
impedance of line pattern (ground line must be designed in the same way)
Furthermore, connect a capacitor to ground at all power supply pins. Consider the effect of temperature and aging on
the capacitance value when using electrolytic capacitors.
3.
Ground Voltage
Ensure that ground pin must have the lowest electrical potential at all time even during transient condition.
4.
Ground Wiring Pattern
When using both small-signal and large-current ground traces, the two ground traces should be routed separately, but
connected to a single ground at the reference point of the application board to avoid fluctuations in the small-signal
ground voltage caused by large currents. Also ensure that the ground traces of external components do not cause
variations on the ground voltage. The ground lines must be as short and thick as possible to reduce line impedance.
5.
Thermal Consideration
Should by any chance the power dissipation rating be exceeded, the rise in temperature of the chip may result in
deterioration of the properties of the chip. The absolute maximum rating of the Pd is specified at the condition of
70mm x 70mm x 1.6mm glass epoxy board. In case of exceeding this absolute maximum rating, increase the board
size or copper area to prevent the IC from exceeding the Pd rating.
6.
Recommended Operating Conditions
These conditions represent a range within which the specified characteristics can be approximately obtained. The
electrical characteristics are guaranteed under the specified conditions.
7.
Inrush Current
When power is first supplied to the IC, it is possible that the internal logic may be unstable and inrush current may flow
instantaneously due to the internal powering sequence and delays, especially if the IC has more than one power supply.
Therefore, give special consideration to power coupling capacitance, power wiring, width of ground wiring, and routing
of connections.
8.
Testing on Application Boards
When testing the IC on an application board, connecting a capacitor directly to a low-impedance output pin may subject
the IC to stress. Always discharge capacitors completely after each process or step. The IC’s power supply should
always be turned off completely before connecting or removing it from the test setup during the inspection process. To
protect IC from static discharge damage, ground the IC during assembly and use similar precautions during transport
and storage.
9.
Inter-pin Short and Mounting Errors
Ensure that the direction and position are correct when mounting the IC on the PCB. Incorrect mounting may result in
damaging the IC. Avoid nearby pins being shorted to each other especially to ground, power supply and output pin.
Make sure that there is nothing between the pins, such as no metal particles, no water droplets (in very humid
environment) and unintentional solder bridge deposited.
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10.
Unused Input Pins
Input pins of an IC are often connected to the gate of a MOS transistor. The gate has extremely high impedance and
extremely low capacitance. If input pins left unconnected, the electric field from the outside can easily charge it. The
small charge acquired in this way is enough to produce a significant effect on the conduction through the transistor and
cause unexpected operation of the IC. So unless otherwise specified, unused input pins should be connected to the
power supply or ground line.
11. Regarding the Input Pin of the IC
This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them
isolated. P-N junctions are formed at the intersection of the P layers with the N layers of other elements, creating a
parasitic diode or transistor. For example (refer to figure below):
When GND > Pin A and GND > Pin B, the P-N junction operates as a parasitic diode.
When GND > Pin B, the P-N junction operates as a parasitic transistor.
Parasitic diodes inevitably occur in the structure of the IC. The operation of parasitic diodes can result in mutual
interference among circuits, operational faults, or physical damage. Therefore, conditions that cause these diodes to
operate, such as applying a voltage lower than the GND voltage to an input pin (and thus to the P substrate) should be
avoided.
Resistor
Transistor (NPN)
Pin A
Pin B
C
E
Pin A
N
P+
P
N
N
P+
N
Pin B
B
Parasitic
Elements
N
P+
N P
N
P+
B
N
C
E
Parasitic
Elements
P Substrate
P Substrate
GND
GND
Parasitic
Elements
Parasitic
Elements
GND
GND
N Region
close-by
In the construction of this IC, P-N junctions are inevitably formed creating parasitic diodes or transistors. The operation
of these parasitic elements can result in mutual interference among circuits, operational faults, or physical damage.
Therefore, conditions which cause these parasitic elements to operate, such as applying a voltage to an input pin lower
than the ground voltage should be avoided. Furthermore, do not apply a voltage to the input pins when no power
supply voltage is applied to the IC. Even if the power supply voltage is applied, make sure that the input pins have
voltages within the values specified in the electrical characteristics of this IC.
12.
Ceramic Capacitor
When using a ceramic capacitor, determine the dielectric constant with the consideration of the capacitance charge
with temperature and the decrease in nominal capacitance due to DC bias and others.
13. Thermal Shutdown Circuit (TSD)
This IC has a built-in thermal shutdown circuit that prevents heat damage to the IC. Normal operation should always be
within the IC’s power dissipation rating. If however the rating is exceeded for a continued period of time, the junction
temperature (Tj) rises, and TSD activated, which turns off all output pins. When the Tj falls below the TSD threshold,
the circuits are automatically restored to normal operation.
Note that the TSD circuit operates in a situation that exceeds the absolute maximum ratings. Under no circumstances,
TSD circuit should not be used for any purpose other than protecting the IC from exceeding the maximum rating.
14. Over Current Protection Circuit (OCP)
This IC incorporates an integrated overcurrent protection circuit that is activated when the load is shorted. This
protection circuit is designed to avoid IC damaged from sudden and unexpected incidents, so should not be used in
applications characterized by continuous operation or transitioning of the protection circuit.
15. Power input at shutdown
If VCC starts up in rapid period of time at shutdown (EN1 = OFF), VREG voltage may be output, which causes the IC to
malfunction. Therefore, set the VCC rise time at 40V/ms or shorter.
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16. Reverse Polarity and Surge voltage
If the VCC and pin potential are reversed, internal circuit or element may be damaged (example: VCC is shorted to
GND while external capacitor changed) Putting diode for reverse protection in series of VCC or putting bypass diode
between VCC is recommended.
Bypass Diode
Reverse Polarity Diode
VCC
VO1
GND
If the VS2 and pin potential are reversed, internal circuit or element may be damaged (example: VCC is shorted to
GND while external capacitor changed) Putting diode for reverse protection in series of VCC or putting bypass diode
between VCC is recommended.
Bypass Diode
VS2
VO2
GND
If the VS3 and pin potential are reversed, internal circuit or element may be damaged (example: VCC is shorted to
GND while external capacitor changed) Putting diode for reverse protection in series of VCC or putting bypass diode
between VCC is recommended
Bypass Diode
VS3
VS2
VO3
GND
Applying positive surge to the VCC
If there is apossibility a surge exceeding the rating be applied to VCC, please put a power zener diode between VCC
and GND.
VCC
GND
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Applying negative surge to the VCC
If there is a possibility VCC gets lower than GND, please put a schottky diode between VCC and GND.
VCC
GND
Protection Diode
If there is a possibility large inductive load is connected to the output pin (VO2 or VO3) resulting in back-EMF at time
of startup and shutdown, a protection diode should be placed as shown in the figure below.
VS2
or
VS3
VO2
or
VO3
GND
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Physical Dimension, Tape and Reel Information
Package Name
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HTQFP48V
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Ordering Information
B
D
3
9
0
Part Number
0
1
E
K
Package
EKV: HTQFP48V
V
-
For in-vehicle
C
E2
Packaging and forming specification
E2: Embossed tape and reel
Marking Diagram
HTQFP48V (TOP VIEW)
Part Number Marking
BD39001
LOT Number
1PIN MARK
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Revision History
Date
Revision
2014.02.12
001
New Release
002
P.6: at Electrical Characteristic, add four item.
(CLK Input Current, ENWD Input Current,
RST Leak Current and RSTWD Leak Current )
P.32 to 33: add “16. Over Current Protection Function“.
P.34: at 18. Soft Start Setting, add the discharge time of SS1.
The other: It revises errors.
2017.03.23
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Notice
Precaution on using ROHM Products
1.
(Note 1)
If you intend to use our Products in devices requiring extremely high reliability (such as medical equipment
,
aircraft/spacecraft, nuclear power controllers, etc.) and whose malfunction or failure may cause loss of human life,
bodily injury or serious damage to property (“Specific Applications”), please consult with the ROHM sales
representative in advance. Unless otherwise agreed in writing by ROHM in advance, ROHM shall not be in any way
responsible or liable for any damages, expenses or losses incurred by you or third parties arising from the use of any
ROHM’s Products for Specific Applications.
(Note1) Medical Equipment Classification of the Specific Applications
JAPAN
USA
EU
CHINA
CLASSⅢ
CLASSⅡb
CLASSⅢ
CLASSⅢ
CLASSⅣ
CLASSⅢ
2.
ROHM designs and manufactures its Products subject to strict quality control system. However, semiconductor
products can fail or malfunction at a certain rate. Please be sure to implement, at your own responsibilities, adequate
safety measures including but not limited to fail-safe design against the physical injury, damage to any property, which
a failure or malfunction of our Products may cause. The following are examples of safety measures:
[a] Installation of protection circuits or other protective devices to improve system safety
[b] Installation of redundant circuits to reduce the impact of single or multiple circuit failure
3.
Our Products are not designed under any special or extraordinary environments or conditions, as exemplified below.
Accordingly, ROHM shall not be in any way responsible or liable for any damages, expenses or losses arising from the
use of any ROHM’s Products under any special or extraordinary environments or conditions. If you intend to use our
Products under any special or extraordinary environments or conditions (as exemplified below), your independent
verification and confirmation of product performance, reliability, etc, prior to use, must be necessary:
[a] Use of our Products in any types of liquid, including water, oils, chemicals, and organic solvents
[b] Use of our Products outdoors or in places where the Products are exposed to direct sunlight or dust
[c] Use of our Products in places where the Products are exposed to sea wind or corrosive gases, including Cl2,
H2S, NH3, SO2, and NO2
[d] Use of our Products in places where the Products are exposed to static electricity or electromagnetic waves
[e] Use of our Products in proximity to heat-producing components, plastic cords, or other flammable items
[f] Sealing or coating our Products with resin or other coating materials
[g] Use of our Products without cleaning residue of flux (even if you use no-clean type fluxes, cleaning residue of
flux is recommended); or Washing our Products by using water or water-soluble cleaning agents for cleaning
residue after soldering
[h] Use of the Products in places subject to dew condensation
4.
The Products are not subject to radiation-proof design.
5.
Please verify and confirm characteristics of the final or mounted products in using the Products.
6.
In particular, if a transient load (a large amount of load applied in a short period of time, such as pulse. is applied,
confirmation of performance characteristics after on-board mounting is strongly recommended. Avoid applying power
exceeding normal rated power; exceeding the power rating under steady-state loading condition may negatively affect
product performance and reliability.
7.
De-rate Power Dissipation depending on ambient temperature. When used in sealed area, confirm that it is the use in
the range that does not exceed the maximum junction temperature.
8.
Confirm that operation temperature is within the specified range described in the product specification.
9.
ROHM shall not be in any way responsible or liable for failure induced under deviant condition from what is defined in
this document.
Precaution for Mounting / Circuit board design
1.
When a highly active halogenous (chlorine, bromine, etc.) flux is used, the residue of flux may negatively affect product
performance and reliability.
2.
In principle, the reflow soldering method must be used on a surface-mount products, the flow soldering method must
be used on a through hole mount products. If the flow soldering method is preferred on a surface-mount products,
please consult with the ROHM representative in advance.
For details, please refer to ROHM Mounting specification
Notice-PAA-E
© 2015 ROHM Co., Ltd. All rights reserved.
Rev.003
Precautions Regarding Application Examples and External Circuits
1.
If change is made to the constant of an external circuit, please allow a sufficient margin considering variations of the
characteristics of the Products and external components, including transient characteristics, as well as static
characteristics.
2.
You agree that application notes, reference designs, and associated data and information contained in this document
are presented only as guidance for Products use. Therefore, in case you use such information, you are solely
responsible for it and you must exercise your own independent verification and judgment in the use of such information
contained in this document. ROHM shall not be in any way responsible or liable for any damages, expenses or losses
incurred by you or third parties arising from the use of such information.
Precaution for Electrostatic
This Product is electrostatic sensitive product, which may be damaged due to electrostatic discharge. Please take proper
caution in your manufacturing process and storage so that voltage exceeding the Products maximum rating will not be
applied to Products. Please take special care under dry condition (e.g. Grounding of human body / equipment / solder iron,
isolation from charged objects, setting of Ionizer, friction prevention and temperature / humidity control).
Precaution for Storage / Transportation
1.
Product performance and soldered connections may deteriorate if the Products are stored in the places where:
[a] the Products are exposed to sea winds or corrosive gases, including Cl2, H2S, NH3, SO2, and NO2
[b] the temperature or humidity exceeds those recommended by ROHM
[c] the Products are exposed to direct sunshine or condensation
[d] the Products are exposed to high Electrostatic
2.
Even under ROHM recommended storage condition, solderability of products out of recommended storage time period
may be degraded. It is strongly recommended to confirm solderability before using Products of which storage time is
exceeding the recommended storage time period.
3.
Store / transport cartons in the correct direction, which is indicated on a carton with a symbol. Otherwise bent leads
may occur due to excessive stress applied when dropping of a carton.
4.
Use Products within the specified time after opening a humidity barrier bag. Baking is required before using Products of
which storage time is exceeding the recommended storage time period.
Precaution for Product Label
A two-dimensional barcode printed on ROHM Products label is for ROHM’s internal use only.
Precaution for Disposition
When disposing Products please dispose them properly using an authorized industry waste company.
Precaution for Foreign Exchange and Foreign Trade act
Since concerned goods might be fallen under listed items of export control prescribed by Foreign exchange and Foreign
trade act, please consult with ROHM in case of export.
Precaution Regarding Intellectual Property Rights
1.
All information and data including but not limited to application example contained in this document is for reference
only. ROHM does not warrant that foregoing information or data will not infringe any intellectual property rights or any
other rights of any third party regarding such information or data.
2.
ROHM shall not have any obligations where the claims, actions or demands arising from the combination of the
Products with other articles such as components, circuits, systems or external equipment (including software).
3.
No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of ROHM or any
third parties with respect to the Products or the information contained in this document. Provided, however, that ROHM
will not assert its intellectual property rights or other rights against you or your customers to the extent necessary to
manufacture or sell products containing the Products, subject to the terms and conditions herein.
Other Precaution
1.
This document may not be reprinted or reproduced, in whole or in part, without prior written consent of ROHM.
2.
The Products may not be disassembled, converted, modified, reproduced or otherwise changed without prior written
consent of ROHM.
3.
In no event shall you use in any way whatsoever the Products and the related technical information contained in the
Products or this document for any military purposes, including but not limited to, the development of mass-destruction
weapons.
4.
The proper names of companies or products described in this document are trademarks or registered trademarks of
ROHM, its affiliated companies or third parties.
Notice-PAA-E
© 2015 ROHM Co., Ltd. All rights reserved.
Rev.003
Datasheet
General Precaution
1. Before you use our Pro ducts, you are requested to care fully read this document and fully understand its contents.
ROHM shall n ot be in an y way responsible or liabl e for fa ilure, malfunction or acci dent arising from the use of a ny
ROHM’s Products against warning, caution or note contained in this document.
2. All information contained in this docume nt is current as of the issuing date and subj ect to change without any prior
notice. Before purchasing or using ROHM’s Products, please confirm the la test information with a ROHM sale s
representative.
3.
The information contained in this doc ument is provi ded on an “as is” basis and ROHM does not warrant that all
information contained in this document is accurate an d/or error-free. ROHM shall not be in an y way responsible or
liable for an y damages, expenses or losses incurred b y you or third parties resulting from inaccur acy or errors of or
concerning such information.
Notice – WE
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Rev.001
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