Datasheet
LDO Regulators with Watchdog Timer and Voltage Detector
550 mA Output LDO Regulator
with WDT and Voltage Detector
BD4271xxx-C Series
General Description
Key Specifications
AEC-Q100 qualified (Note 1)
Functional Safety Supportive Automotive Products
Qualified for Automotive Applications
Wide Temperature Range (Tj):
-40 °C to +150 °C
Wide Operating Input Range:
-0.3 V to +45 V
Low Quiescent Current:
75 µA (Typ)
Output Load Current:
550 mA
Output Voltage:
5.0 V (Typ) ± 2 %
Reset Detection Voltage Accuracy:
4.53 V to 4.77 V
4.65 V (Typ)
◼ Enable input
◼ Over Current Protection (OCP)
◼ Thermal Shutdown (TSD)
BD4271xxx-C Series are automotive voltage regulators
with watchdog timer and offers the output current of 550
mA while limiting the quiescent current low. A logical
“HIGH” at the CTL pin enables the LDO regulator and
“LOW” disables the LDO regulator and keeps current
consumption low.
A reset signal is generated for an output voltage V O of
Typ 4.65 V.
The reset delay time and watchdog time (WDT) can be
programmed by the external capacitor.
◼
◼
◼
◼
◼
◼
◼
◼
◼
(Note1: Grade 1)
Features
◼
◼
◼
◼
Low ESR ceramic capacitors applicable for output
Low drop voltage: PDMOS output transistor
Power on and under-voltage reset
Programmable reset delay and watchdog time by
external capacitor
Packages
◼ HFP: HRP7
◼ FP2: TO263-7
◼ EFJ: HTSOP-J8
W (Typ) x D (Typ) x H (Max)
9.395 mm x 10.540 mm x 2.005 mm
10.00 mm x 14.95 mm x 4.50 mm
4.9 mm x 6.0 mm x 1.0 mm
Applications
◼ Onboard Vehicle Device
(Engine ECU, Body-control, Car Stereos, Satellite
Navigation System, etc.)
HRP7
TO263-7
HTSOP-J8
Typical Application Circuit
CIN ≥ 0.1 µF, CCT = 0.001 µF to 10 µF, CO ≥ 6 µF
VCC
CTL
CIN
〇Product structure : Silicon integrated circuit
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TSZ22111・14・001
RO
GND
CT
CLK
CCT
VO
CO
〇This product has no designed protection against radioactive rays.
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BD4271xxx-C Series
Pin Configurations (BD4271HFP-C, BD4271FP2-C)
TO263-7
(TOP VIEW)
HRP7
(TOP VIEW)
FIN
FIN
1 2 3 4 5 6 7
1 2 3 4 5 6 7
Pin Description (BD4271HFP-C, BD4271FP2-C)
Pin No.
Pin Name
Function
1
VCC
Input
2
CTL
Output control
3
RO
Reset output
4
GND
5
CT
6
CLK
Input CLK from Microcomputer
7
VO
Output
FIN
GND
Ground
Ground
Setting Reset Delay Time and WDT time
Pin Configuration (BD4271EFJ-C)
HTSOP-J8
(TOP VIEW)
8
1
7
2
EXP-PAD
3
6
5
4
Pin Description (BD4271EFJ-C)
Pin No.
Pin Name
Function
1
VCC
Input
2
CTL
Output control
3
N.C
No Connection(Note 1)
4
RO
Reset output
5
GND
Ground
6
CLK
Input CLK from Microcomputer
7
CT
Setting Reset Delay Time and WDT time
8
VO
Output
EXP-PAD
EXP-PAD
No Connection(Note 2)
(Note 1) This pin is not connected to the chip. It can keep open or it’s also possible to connect to GND.
If Pin No.3 is shorted to GND, Pin No.3 will be adjacent to Pin No.2 CTL and Pin No.4 RO on the board layout.
If adjacent pins are expected to be shorted, please confirm if there is any problem with the actual application.
(Note 2) It is recommended to connect the EXP-PAD to the GND pattern to improve heat dissipation.
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BD4271xxx-C Series
Block Diagram
VCC
VO
TSD
Error
Amplifier
CTL
OCP
Reference
VO
CT
RO
Control
Reference
UVLO
CLK
GND
Block Descriptions
Block Name
Function
TSD
Thermal shutdown protection
Reference
Reference voltage
OCP
Over current protection
The OCP protects the device from damage caused by over current.
UVLO
Under voltage lock out
The UVLO prevents malfunction of the reset block in case of very low
output voltage.
Error Amplifier
Error amplifier
Control
RESET + WDT time control
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TSZ22111・15・001
Description of Blocks
The TSD protects the device from overheating.
If the chip temperature (Tj) reaches ca. 175 °C (Typ),
the output is turned off.
The Reference generates the Reference Voltage.
The Error Amplifier amplifies the difference between the feedback
voltage of the output voltage and the reference voltage.
The reset delay time and watchdog time can be programmed.
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BD4271xxx-C Series
Absolute Maximum Ratings
Parameter
Symbol
Ratings
Unit
Supply Voltage
VCC
-0.3 to +45.0
V
Output Control Voltage
VCTL
-0.3 to +45.0
V
RO Voltage
VRO
-0.3 to +7.0 (≤ VO + 0.3)
V
Output Voltage
VO
-0.3 to +7.0
V
VCLK
-0.3 to VO + 0.3
V
Junction Temperature Range
Tj
-40 to +150
°C
Storage Temperature Range
Tstg
-55 to +150
°C
Tjmax
+150
°C
CLK Voltage
Maximum Junction Temperature
Caution:
Exceeding the absolute maximum rating for supply voltage, operating temperature or other parameters can result in damages to or
destruction of the chip. In this event it also becomes impossible to determine the cause of the damage (e.g. short circuit, open circuit, etc.).
Therefore, if any special mode is being considered with values expected to exceed the absolute maximum ratings,
implementing physical safety measures, such as adding fuses, should be considered.
Recommended Operating Conditions
Parameter
Symbol
Min
Max
Unit
Supply Voltage (IO ≤ 300 mA)
VCC
5.5
45.0
V
Supply Voltage (IO ≤ 550 mA)
VCC
6.0
45.0
V
Output Control Voltage
VCTL
0
45.0
V
Start -Up Voltage (Note 1)
VCC
3.0
－
V
Output Current
IO
0
550
mA
Operating Ratings Temperature
Ta
-40
+125
°C
(Note 1)
When IO = 0 mA.
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BD4271xxx-C Series
Thermal Resistance(Note 1)
Parameter
Symbol
Thermal Resistance (Typ)
Unit
1s (Note 3)
2s2p (Note 4)
θJA
96.0
22.0
°C/W
ΨJT
6
2
°C/W
HRP7
Junction to Ambient
Junction to Top Characterization Parameter
(Note 2)
TO263-7
Junction to Ambient
Junction to Top Characterization Parameter
θJA
80.7
20.3
°C/W
(Note 2)
ΨJT
8
2
°C/W
θJA
131.7
33.0
°C/W
(Note 2)
ΨJT
12
5
°C/W
HTSOP-J8
Junction to Ambient
Junction to Top Characterization Parameter
(Note 1) Based on JESD51-2A (Still-Air)
(Note 2) The thermal characterization parameter to report the difference between junction temperature and the temperature at the top center of the outside
surface of the component package.
(Note 3) Using a PCB board based on JESD51-3.
(Note 4) Using a PCB board based on JESD51-5, 7.
Layer Number of
Measurement Board
Single
Material
Board Size
FR-4
114.3 mm x 76.2 mm x 1.57 mmt
Top
Copper Pattern
Thickness
Footprints and Traces
70 μm
Layer Number of
Measurement Board
4 Layers
Material
Board Size
FR-4
114.3 mm x 76.2 mm x 1.6 mmt
Top
2 Internal Layers
Thermal Via(Note 5)
Pitch
Diameter
1.20 mm
Φ0.30 mm
Bottom
Copper Pattern
Thickness
Copper Pattern
Thickness
Copper Pattern
Thickness
Footprints and Traces
70 μm
74.2 mm x 74.2 mm
35 μm
74.2 mm x 74.2 mm
70 μm
(Note 5) This thermal via connects with the copper pattern of all layers.
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BD4271xxx-C Series
Electrical Characteristics (LDO)
(Unless otherwise specified, Tj = -40 °C to +150 °C, VCC = 13.5 V, VCTL = 5 V, IO = 0 mA, the typical value is defined
at Tj = +25 °C)
Parameter
Symbol
Limit
Min
Typ
Max
Unit
Conditions
Circuit Current
ICC
－
75
150
μA
Standby Current
IST
－
2.0
9.0
μA
Output Voltage
VO
4.90
5.00
5.10
V
Output Voltage
VO
4.90
5.00
5.10
V
Dropout Voltage
ΔVd
－
0.2
0.5
V
Ripple Rejection
R.R.
－
60
－
dB
Line Regulation
Reg.I
-30
－
30
mV
8 V ≤ VCC ≤ 16 V
Load Regulation
Reg.L
－
10
40
mV
10 mA ≤ IO ≤ 300 mA
TSD
－
175
－
°C
Tj at TSD ON
Over Current Protection
IO
550
－
－
mA
CTL ON Mode Voltage
VthH
2.7
－
－
V
Active Mode
CTL OFF Mode Voltage
VthL
－
－
0.8
V
Off Mode
CTL Input Current
ICTL
－
15
30
µA
VCTL = 5 V
Thermal Shutdown
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IO = 0 mA
VCTL = 0 V
Tj ≤ 125 °C
6 V ≤ VCC ≤ 40 V
0 mA ≤ IO ≤ 300 mA
8 V ≤ VCC ≤ 26 V
IO ≤ 550 mA
VCC = 4.75 V
IO = 300 mA
f = 120 Hz, ein = 1 Vrms
IO = 100 mA
TSZ02201-0G9G0AN00610-1-2
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BD4271xxx-C Series
Electrical Characteristics (Reset, WDT Function)
(Unless otherwise specified, Tj = -40 °C to +150 °C, VCC = 13.5 V, VCTL = 5 V, IO = 0 mA, the typical value is defined
at Tj = +25 °C)
Parameter
Symbol
Limit
Unit
Conditions
Min
Typ
Max
VRT
4.53
4.65
4.77
V
－
VRHYS
25
60
100
mV
－
Reset Pull-up Resistance
RRO
18
30
46
kΩ
－
Reset Low Voltage
VRO
－
－
0.4
V
－
CT Upper-side Threshold
VCT_H
－
1.80
－
V
－
CT Lower-side Threshold
VCT_L
－
0.45
－
V
－
CT Charge Current
ICT_C
－
16
－
μA
VCT = 0.15 V
CT Discharge Current
ICT_D
－
3
－
μA
VCT = 1.35 V
td
8
11.5
16
ms
CCT = 0.1 μF (Note 1)
WDT Monitor Time
tWH
30
45
66
ms
CCT = 0.1 μF (Note 1)
WDT Reset Time
tWL
5
9
15
ms
CCT = 0.1 μF (Note 1)
CLK Input High Level Voltage
VHCLK
VO
x 0.8
－
VO
V
CLK Input Low Level Voltage
VLCLK
0
－
VO
x 0.3
V
CLK is pulled down inside the IC
when CLK open.
CLK Input Current
ICLK
1.5
5
15
μA
VCLK = 5 V
CLK Input Pulse Width
tPCLK
3
－
－
μs
Minimum Operation Voltage
VOPR
1
－
－
V
Reset Detection Voltage
Reset Detection Hysteresis
Delay Time L→H
(Note 1)
RO < 0.5 V
td, tWH, and tWL can be varied by changing the CT capacitance value. (0.001 μF to 10 μF available)
td1 (ms) ≈ td (the Delay Time at 0.1 μF) x CCT (μF) / 0.1
for example: when CCT = 1 μF, 80 ms ≤ td ≤ 160 ms
tWH1 (ms) ≈ tWH (the WDT Monitor Time at 0.1 μF) x CCT (μF) / 0.1
for example: when CCT = 1 μF, 300 ms ≤ td ≤ 660 ms
tWL1 (ms) ≈ tWL (the WDT Reset Time at 0.1 μF) x CCT (μF) / 0.1
for example: when CCT = 1 μF, 50 ms ≤ td ≤ 150 ms
td2 (ms) ≈ td (the Delay Time at 0.1 μF) x CCT (μF) / 0.1 ± 0.1
for example: when CCT = 0.01 μF, 0.7 ms ≤ td ≤ 1.7 ms
tWH2 (ms) ≈ tWH (the WDT Monitor Time at 0.1 μF) x CCT (μF) / 0.1 ± 0.1
for example: when CCT = 0.01 μF, 2.9 ms ≤ td ≤ 6.7 ms
tWL2 (ms) ≈ tWL (the WDT Reset Time at 0.1 μF) x CCT (μF) / 0.1 ± 0.1
for example: when CCT = 0.01 μF, 0.4 ms ≤ td ≤ 1.6 ms
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CT Capacitor: 0.1 μF ≤ CCT ≤ 10 μF
CT Capacitor: 0.1 μF ≤ CCT ≤ 10 μF
CT Capacitor: 0.1 μF ≤ CCT ≤ 10 μF
CT Capacitor: 0.001 μF ≤ CCT < 0.1 μF
CT Capacitor: 0.001 μF ≤ CCT < 0.1 μF
CT Capacitor: 0.001 μF ≤ CCT < 0.1 μF
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30.Mar.2023 Rev.004
BD4271xxx-C Series
6
6
5
5
Output Voltage : VO [V]
Output Voltage : VO [V]
Typical Performance Curves (Unless otherwise specified, Tj = 25 °C, VCC = 13.5 V, VCTL = 5 V)
4
3
2
Tj = -40 ℃
Tj = 25 ℃
Tj = 125 ℃
1
4
3
2
Tj = -40 ℃
Tj = 25 ℃
Tj = 125 ℃
1
0
0
0
10
20
30
40
50
0
2
Supply Voltage : VCC [V]
4
6
8
10
Supply Voltage : VCC [V]
Figure 1. Output Voltage vs Supply Voltage
(RL = 25 Ω)
Figure 2. Output Voltage vs Supply Voltage
(RL = 25 Ω)
5.2
1500
Tj = -40 °C
Tj = 25 °C
1200
Tj = 150 °C
Circuit Current : ICC [μA]
Output Voltage : VO [V]
5.1
5.0
4.9
4.8
900
600
300
0
-40
0
40
80
120
160
10
20
30
40
50
Supply Voltage : VCC [V]
Junction Temperature : Tj [℃]
Figure 3. Output Voltage vs Junction Temperature
(RL = 1 kΩ)
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Figure 4. Circuit Current vs Supply Voltage
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BD4271xxx-C Series
150
150
130
120
Circuit Current :ICC [μA]
Circuit Current :ICC [μA]
Typical Performance Curves - continued
110
90
90
60
30
70
0
50
-40
0
40
80
120
Junction Temperature : Tj [℃]
0
160
100
200
300
400
500
600
Output Current : IO [mA]
Figure 6. Circuit Current vs Output Current
Figure 5. Circuit Current vs Junction Temperature
6
1200
5
4
Output Current : IO [mA]
Output Voltage: VO [V]
Tj = -40 °C
Tj = 25 °C
Tj = 150 °C
3
2
1100
1000
900
1
0
800
0
200
400
600
800
1000
1200
-40
40
80
120
160
Junction Temperature : Tj [℃]
Output Current : IO [mA]
Figure 8. Output Current vs Junction
Temperature
Figure 7. Output Voltage vs. Output Current
(Over Current Protection)
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BD4271xxx-C Series
Typical Performance Curves - continued
600
6
Tj = -40 °C
Tj = 25 °C
Tj = 150 °C
5
400
Output Voltage:VO [V]
Dropout Voltage : ΔVd [mV]
500
300
200
4
3
2
1
100
0
0
0
100
200
300
400
100
500
120
160
180
Junction Temperature : Tj [℃]
Output Current : IO [mA]
Figure 10. Output Voltage vs Junction Temperature
(Thermal Shutdown)
Figure 9. Dropout Voltage vs Output Current
(VCC = 4.75 V)
5
6
5
4
CTL Voltage : VCTL [V]
Output Voltage : VO [V]
140
4
3
2
Tj = -40 °C
1
3
CTL ON
CTL OFF
2
1
Tj = 25 °C
Tj = 150 °C
0
0
1
2
3
4
0
5
-40
CTL Voltage : VCTL [V]
40
80
120
160
Junction Temperature : Tj [℃]
Figure 12. CTL Voltage vs Junction Temperature
Figure 11. Output Voltage vs CTL Voltage
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BD4271xxx-C Series
Typical Performance Curves - continued
30
4.9
Reset Detection Voltage : VRT [V]
CTL Current : ICTL [μA]
25
20
15
10
5
0
-40
0
40
80
120
4.8
VRT++VVRHY
VRT
RHYS
VRT
VRT
4.7
4.6
4.5
4.4
160
-40
Junction Temperature : Tj [℃]
40
80
120
160
Junction Temperature : Tj [℃]
Figure 14. Reset Detection Voltage vs
Junction Temperature
Figure 13. CTL Current vs Junction Temperature
6
6
Tj = -40 °C
Tj = 25 °C
Tj = 150 °C
Tj = -40 °C
Tj = 25 °C
Tj = 150 °C
5
Reset Voltage : VRO [V]
5
Reset Voltage : VRO [V]
0
4
3
2
4
3
2
1
1
0
0
0.0
1.0
2.0
3.0
4.0
5.0
6.0
Output Voltage : VO [V]
4.5
4.6
4.7
4.8
Output Voltage : VO [V]
Figure 15. RO Voltage vs Output Voltage
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4.4
Figure 16. RO Voltage vs Output Voltage
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BD4271xxx-C Series
Typical Performance Curves - continued
2.4
20
2.0
12
CT Voltage : VCT [V]
CT Current : ICT [μA]
16
ICTICT_C
charge
ICTICT_D
discharge
8
1.6
VCT_H
VCTH
1.2
VCT_L
VCTL
0.8
4
0.4
0
0.0
-40
0
40
80
120
160
-40
0
40
80
120
160
Junction Temperature : Tj [℃]
Junction Temperature : Tj [℃]
Figure 17. CT Current vs Junction Temperature
Figure 18. CT Voltage vs Junction Temperature
16
10000
Delay Time L→H : td [ms]
Delay Time L→H : td [ms]
1000
14
12
10
100
10
1
0.1
8
-40
0
40
80
120
160
Junction Temperature : Tj [℃]
0.01
0.1
1
10
CT Capacitance : CCT [μF]
Figure 19. Delay Time L→H vs Junction Temperature
(CCT = 0.1 µF)
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0.01
0.001
Figure 20. Delay Time L→H vs CT Capacitance
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BD4271xxx-C Series
Typical Performance Curves - continued
70
10000
1000
Watchdog Time : tWH, tWL [ms]
Watchdog Time : tWH, tWL [ms]
60
50
40
tWH
tWH
30
tWL
tWL
20
10
0
-40
0
40
80
120
160
10
1
tWH
tWH
tWL
tWL
0.1
0.01
0.001
0.01
0.1
1
10
CT Capacitance : CCT [μF]
Junction Temperature : Tj [℃]
Figure 22. Watchdog Time vs CT Capacitance
Figure 21. Watchdog Time vs Junction Temperature
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BD4271xxx-C Series
Measurement Circuit
FIN
FIN
VCC
CTL
RO
GND
CT
CLK
VCC
VO
CTL
RO
FIN
GND
CT
CLK
VO
VCC
CTL
RO
GND
CT
CLK
VO
IO
V
0.1µF
0.1µF
10µF
A
0.1µF
Measurement setup for Figure 1,2,3,10.
0.1µF
CTL
RO
GND
CT
CLK
VO
VCC
CTL
RO
GND
0.1µF
10µF
Measurement setup for Figure 7,8.
CT
RO
GND
Measurement setup for Figure 6.
CLK
VO
VCC
CTL
RO
CLK
VO
CT
CLK
VO
V
0.1µF
0.1µF
10µF
Measurement setup for Figure 9.
0.1µF
VCC
CTL
RO
GND
10µF
Measurement setup for Figure 11,12,13.
FIN
CT
GND
A
IO
0.1µF
FIN
CTL
10µF
FIN
V
VCC
0.1µF
FIN
A
0.1µF
0.1µF
Measurement setup for Figure 4,5.
FIN
VCC
10µF
FIN
CT
CLK
VCC
VO
CTL
RO
GND
CT
CLK
VO
V
V A
V
0.1µF
0.1µF
10µF
Measurement setup for Figure 14,15,16.
0.1µF
0.1µF
Hz
Hz
10µF
Measurement setup for Figure 17,18.
0.1µF
0.1µF
10µF
Measurement setup for Figure 19,20,21,22.
Figure 23. Measurement Circuit
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BD4271xxx-C Series
Timing Chart
1.
When supply voltage VCC is ON ↔ OFF (Not to input CLK voltage VCLK when output voltage VO = Low)
VCC
13.5V
0V
VCTL
5V
VthH
VRO
td tWH tWL
≒Vo
VCT
VCT_H
VCT_L
VCLK
0V
VO
VRHYS
5V
VRT
Figure 24. Timing Chart 1
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Timing Chart – continued
2.
When output control voltage VCTL is ON ↔ OFF (Not to input CLK voltage VCLK when output voltage VO = Low)
VCC
13.5V
VCTL
5V
VthH
VthL
0V
VRO
td twH twL
≒Vo
VCT
VCT_H
VCT_L
VCLK
0V
VO
VRHYS
VRT
5V
Figure 25. Timing Chart 2
The Delay Time ( td ) is estimated roughly by following calculation.
t d [s] ≈
VCT_H [V] × CCT [F]
ICT_C [A]
Basically, verify the Delay Time ( td ) by the ratio of the value at CCT = 0.1 μF specified in datasheet and the actual CCT
capacitance used to calculate.
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BD4271xxx-C Series
Timing Chart – continued
3.
When WDT threshold Voltage VCLK is ON ↔ OFF
VCC
13.5V
VCTL
5V
VthH
VRO
td twH twL
≒Vo
VCT
VCT_H
VCT_L
VCLK
tPCLK
5V
0V
VO
VRHYS
5V
VRT
Figure 26. Timing Chart 3
The WDT Monitor Time ( tWH ) and the WDT Reset Time ( tWL ) is estimated roughly by following calculation.
t WH [s] ≈
|VCT_H − VCT_L |[V] × CCT [F]
ICT_D [A]
t WL [s] ≈
|VCT_L − VCT_H |[V] × CCT [F]
ICT_C [A]
Basically, verify the WDT Monitor Time ( tWH ) and the WDT Reset Time ( tWL ) by the ratio of the value at CCT = 0.1 μF
specified in datasheet and the actual CCT capacitance used to calculate
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BD4271xxx-C Series
Disable WDT behavior
VCC
VO
CTL
RO
CIN
CO
RCT
CT_SW
CLK
GND
CT
CCT
Figure 27. Application Circuit
VO
5V
CT_SW
CT_SW
OFF
CT_SW
ON
CT_SW
OFF
VCT
Vo
VCT_H
VCT_L
VRO
twH
twL
Figure 28. Timing Chart 4
By pulling up the CT pin to the VO pin and keeping CT voltage above V CT_H, RO switching and WDT behavior are disabled.
However, if under voltage reset is detected with the CT pin pulled up to the VO pin, the circuit that rapidly discharges the CCT
electron will operate and current will flow into the CT pin. Therefore, when pulling up the CT pin to the VO pin, the pull up
resister must be required between the VO pin and the CT pin for limiting current.
Recommended pull up resistance: 10 kΩ ~ 200 kΩ
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BD4271xxx-C Series
Selection of Components Externally Connected
・VCC pin capacitor
Insert capacitors with a capacitance of 0.1 μF or higher between the VCC and GND pin. We recommend using ceramic
capacitor generally featuring good high frequency characteristic. When selecting a ceramic capacitor, please be
consider about temperature and DC-biasing characteristics. Place capacitors closest possible to VCC-GND pin. When
input impedance is high, e.g. in case there is distance from battery, line voltage drop needs to be prevented by large
capacitor. Choose the capacitance according to the line impedance between the power smoothing circuit and the VCC
pin. Selection of the capacitance also depends on the applications. Verify the application and allow sufficient margins
in the design. We recommend using a capacitor with excellent voltage and temperature characteristics.
・Output pin capacitor
In order to prevent oscillation, a capacitor needs to be placed between the output pin and GND pin. We recommend
using a ceramic capacitor with a capacitance of 6 μF or higher. In selecting the capacitor, ensure that the capacitance
of 6 μF or higher is maintained at the intended applied voltage and temperature range. Due to changes in temperature
the capacitor's capacitance can fluctuate possibly resulting in oscillation.
In actual applications the stable operating range is influenced by the PCB impedance, input supply impedance and
load impedance. Therefore verification of the final operating environment is needed. When selecting a ceramic
capacitor, we recommend using X7R or better components with excellent temperature and DC-biasing characteristics
and high voltage tolerance.
In case of the transient input voltage and the load current fluctuation, output voltage may fluctuate. In case this
fluctuation can be problematic for the application, connect low ESR capacitor (capacitance > 6 μF, ESR < 1 Ω) in
paralleled to large capacitor with a capacitance of 13 μF or higher and ESR of 5 Ω or lower. Electrolytic and tantalum
capacitors can be used as large capacitor. When selecting an electrolytic capacitor, please consider about increasing
ESR and decreasing capacitance at cold temperature.
Place the capacitor closest possible to output pin.
6
Unstable Available Area
5
ESR [Ω]
4
3
Stable Available Area
2
1
0
1
10
100
1000
Output Capacitance : CO [μF]
Figure 29. Output Capacitance ESR Available Area
-40 °C ≤ Tj ≤ +150 °C, 6 V ≤ VCC ≤ 45 V, VCTL = 5 V, IO = 0 mA to 550 mA
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BD4271xxx-C Series
Power Dissipation
◼
HRP7
10
Power Dissipation: Pd[W]
8
(2) 5.7 W
6
4
2
(1) 1.3 W
0
0
25
50
75
100
125
150
Ambient Temperature: Ta [°C]
Figure 30. HRP7 Package Data
◼
TO263-7
10
8
Power Dissipation: Pd[W]
IC mounted on ROHM standard board based on JEDEC.
(1) : 1-layer PCB
(Copper foil area on the reverse side of PCB: 0 mm x 0 mm)
Board material: FR4
Board size: 114.3 mm x 76.2 mm x 1.57 mmt
Mount condition: PCB and exposed pad are soldered.
Top copper foil: ROHM recommended
footprint + wiring to measure, 2 oz. copper.
(2) : 4-layer PCB
(2 inner layers and Copper foil area on the reverse side of PCB:
74.2 mm x 74.2 mm)
Board material: FR4
Board size: 114.3 mm x 76.2 mm x 1.60 mmt
Mount condition: PCB and exposed pad are soldered.
Top copper foil: ROHM recommended
footprint + wiring to measure, 2 oz. copper.
2 inner layers copper foil area of PCB:
74.2 mm x 74.2 mm, 1 oz. copper.
Copper foil area on the reverse side of PCB:
74.2 mm x 74.2 mm, 2 oz. copper.
Condition (1): θJA = 96.0 °C/W, ΨJT (top center) = 6 °C/W
Condition (2): θJA = 22.0 °C/W, ΨJT (top center) = 2 °C/W
(2) 6.16 W
6
4
(1) 1.55 W
2
0
0
25
50
75
100
125
Ambient Temperature: Ta [°C]
Figure 31. TO263-7 Package Data
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150
IC mounted on ROHM standard board based on JEDEC.
(1) : 1-layer PCB
(Copper foil area on the reverse side of PCB: 0 mm x 0 mm)
Board material: FR4
Board size: 114.3 mm x 76.2 mm x 1.57 mmt
Mount condition: PCB and exposed pad are soldered.
Top copper foil: ROHM recommended
footprint + wiring to measure, 2 oz. copper.
(2) : 4-layer PCB
(2 inner layers and Copper foil area on the reverse side of PCB:
74.2 mm x 74.2 mm)
Board material: FR4
Board size: 114.3 mm x 76.2 mm x 1.60 mmt
Mount condition: PCB and exposed pad are soldered.
Top copper foil: ROHM recommended
footprint + wiring to measure, 2 oz. copper.
2 inner layers copper foil area of PCB:
74.2 mm x 74.2 mm, 1 oz. copper.
Copper foil area on the reverse side of PCB:
74.2 mm x 74.2 mm, 2 oz. copper.
Condition (1): θJA = 80.7 °C/W, ΨJT (top center) = 8 °C/W
Condition (2): θJA = 20.3 °C/W, ΨJT (top center) = 2 °C/W
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BD4271xxx-C Series
Power Dissipation – continued
◼
HTSOP-J8
5
(2) 3.79 W
Power Dissipation: Pd[W]
4
3
2
(1) 0.95W
1
0
0
25
50
75
100
125
150
Ambient Temperature: Ta [°C]
Figure 32. HTSOP-J8 Package Data
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IC mounted on ROHM standard board based on JEDEC.
(1) : 1-layer PCB
(Copper foil area on the reverse side of PCB: 0 mm x 0 mm)
Board material: FR4
Board size: 114.3 mm x 76.2 mm x 1.57 mmt
Mount condition: PCB and exposed pad are soldered.
Top copper foil: ROHM recommended
footprint + wiring to measure, 2 oz. copper.
(2) : 4-layer PCB
(2 inner layers and Copper foil area on the reverse side of PCB:
74.2 mm x 74.2 mm)
Board material: FR4
Board size: 114.3 mm x 76.2 mm x 1.60 mmt
Mount condition: PCB and exposed pad are soldered.
Top copper foil: ROHM recommended
footprint + wiring to measure, 2 oz. copper.
2 inner layers copper foil area of PCB:
74.2 mm x 74.2 mm, 1 oz. copper.
Copper foil area on the reverse side of PCB:
74.2 mm x 74.2 mm, 2 oz. copper.
Condition (1): θJA = 131.7 °C/W, ΨJT (top center) = 12 °C/W
Condition (2): θJA = 33 °C/W, ΨJT (top center) = 5 °C/W
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BD4271xxx-C Series
Thermal Design
This product exposes a frame on the back side of the package for thermal efficiency improvement.
Within this IC, the power consumption is decided by the dropout voltage condition, the load current and the circuit current.
Refer to power dissipation curves illustrated in Figure 30, 31 and 32 when using the IC in an environment of Ta ≥ 25 °C. Even
if the ambient temperature Ta is at 25 °C, depending on the input voltage and the load current, chip junction temperature can
be very high. Consider the design to be Tj ≤ Tjmax = 150 °C in all possible operating temperature range.
Should by any condition the maximum junction temperature Tjmax = 150 °C rating be exceeded by the temperature increase
of the chip, it may result in deterioration of the properties of the chip. The thermal impedance in this specification is based on
recommended PCB and measurement condition by JEDEC standard. Verify the application and allow sufficient margins in
the thermal design by the following method is used to calculate the junction temperature Tj.
Tj can be calculated by either of the two following methods.
1. The following method is used to calculate the junction temperature Tj.
Tj = Ta + PC × θJA
Tj
Ta
PC
θJA
: Junction Temperature
: Ambient Temperature
: Power Consumption
: Thermal Impedance (Junction to Ambient)
2. The following method is also used to calculate the junction temperature Tj.
Tj = TT + PC × ΨJT
Tj
TT
PC
ΨJT
: Junction Temperature
: Top Center of Case’s (mold) Temperature
: Power Consumption
: Thermal Impedance (Junction to Top Center of Case)
The following method is used to calculate the power consumption P C (W).
PC = (VCC - VO) × IO + VCC × ICC
PC
VCC
VO
IO
ICC
: Power Consumption
: Supply Voltage
: Output Voltage
: Load Current
: Circuit Current
・Calculation Example
If VCC = 13.5 V, VO = 5.0 V, IO = 200 mA, ICC = 85 μA, the power consumption PC can be calculated as follows:
PC = (VCC - VO) × IO + VCC × ICC
= (13.5 V – 5.0 V) × 200 mA + 13.5 V × 85 μA
= 1.7 W
At the ambient temperature Ta = 85 °C, the thermal impedance (Junction to Ambient) θJA = 22.0 °C/W (4-layer PCB),
Tj = Ta + PC × θJA
= 85 °C + 1.7 W × 22.0 °C/W
= 122.4 °C
When operating the IC, the top center of case’s (mold) temperature TT = 100 °C, ΨJT = 6 °C/W (1-layer PCB),
Tj = TT + PC × ΨJT
= 100 °C + 1.7 W × 6 °C/W
= 110.2 °C
For optimum thermal performance, it is recommended to expand the copper foil area of the board, increasing the layer and
thermal via between thermal land pad.
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BD4271xxx-C Series
Application Examples
・Applying positive surge to the VCC
If the possibility exists that surges higher than 45 V will be applied to the VCC, a Zener Diode should be placed between
the VCC and GND as shown in the figure below.
VCC
VO
GND
・Applying negative surge to the VCC
If the possibility exists that negative surges lower than the GND are applied to the VCC, a Shottky Diode should be place
between the VCC and GND as shown in the figure below.
VCC
VO
GND
・Implementing a Protection Diode
If the possibility exists that a large inductive load is connected to the output pin resulting in back-EMF at time of startup
and shutdown, a protection diode should be placed as shown in the figure below.
VCC
VO
GND
・Reverse Polarity Diode
In some applications, the VCC and the VO potential might be reversed, possibly resulting in circuit internal damage or
damage to the elements. For example, the accumulated charge in the output pin capacitor flowing backward from the VO
to the VCC when the VCC shorts to the GND. In order to minimize the damage in such case, use a capacitor with a
capacitance less than 1000 μF. Also by inserting a reverse polarity diode in series to the VCC, it can prevent reverse current
from reverse battery connection or the case. When the point A is short-circuited GND, if there may be any possible case
point B is short-circuited to GND, we also recommend using a bypass diode between the VCC and the VO.
Bypass Diode
Reverse Polarity Diode
A
VCC
B
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VO
GND
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BD4271xxx-C Series
I/O Equivalence Circuits (Note 1)
VCC
CTL
VCC
CTL
340 kΩ
IC
IC
RO
5 kΩ
370 kΩ
370 kΩ
140 kΩ
140 kΩ
CT
VO
VO
VO
30 kΩ
1 kΩ
0.1 kΩ
RO
CT
50 kΩ
CLK
VO
VO
VO
VCC
VO
50 kΩ
CLK
10 kΩ
1550 kΩ
Reset
IC
Block
1000 kΩ
525 kΩ
(Note 1) Resistance value is Typical.
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BD4271xxx-C Series
Operational Notes
1.
Reverse Connection of Power Supply
Connecting the power supply in reverse polarity can damage the IC. Take precautions against reverse polarity when
connecting the power supply, such as mounting an external diode between the power supply and the IC’s power supply
terminals.
2.
Power Supply Lines
Design the PCB layout pattern to provide low impedance supply lines. Separate the ground and supply lines of the
digital and analog blocks to prevent noise in the ground and supply lines of the digital block from affecting the analog
block. Furthermore, connect a capacitor to ground at all power supply pins. Consider the effect of temperature and
aging on the capacitance value when using electrolytic capacitors.
3.
Ground Voltage
Ensure that no pins are at a voltage below that of the ground pin at any time, even during transient condition.
4.
Ground Wiring Pattern
When using both small-signal and large-current ground traces, the two ground traces should be routed separately but
connected to a single ground at the reference point of the application board to avoid fluctuations in the small-signal
ground caused by large currents. Also ensure that the ground traces of external components do not cause variations
on the ground voltage. The ground lines must be as short and thick as possible to reduce line impedance.
5.
Thermal Consideration
The power dissipation under actual operating conditions should be taken into consideration and a sufficient margin
should be allowed for in the thermal design. On the reverse side of the package this product has an exposed heat pad
for improving the heat dissipation. Use both the front and reverse side of the PCB to increase the heat dissipation
pattern as far as possible. The amount of heat generated depends on the voltage difference across the input and output,
load current, and bias current. Therefore, when actually using the chip, ensure that the generated heat does not exceed
the Pd rating.
Should by any condition the maximum junction temperature Tjmax = 150 °C rating be exceeded by the temperature
increase of the chip, it may result in deterioration of the properties of the chip. The thermal impedance in this
specification is based on recommended PCB and measurement condition by JEDEC standard. Verify the application
and allow sufficient margins in the thermal design.
6.
Recommended Operating Conditions
These conditions represent a range within which the expected characteristics of the IC can be approximately obtained.
The electrical characteristics are guaranteed under the conditions of each parameter.
7.
Rush Current
When power is first supplied to the IC, it is possible that the internal logic may be unstable and inrush current may flow
instantaneously due to the internal powering sequence and delays, especially if the IC has more than one power supply.
Therefore, give special consideration to power coupling capacitance, power wiring, width of ground wiring, and routing
of connections.
8.
Testing on Application Boards
When testing the IC on an application board, connecting a capacitor directly to a low-impedance output pin may subject
the IC to stress. Always discharge capacitors completely after each process or step. The IC’s power supply should
always be turned off completely before connecting or removing it from the test setup during the inspection process. To
prevent damage from static discharge, ground the IC during assembly and use similar precautions during transport and
storage.
9.
Inter-pin Short and Mounting Errors
Ensure that the direction and position are correct when mounting the IC on the PCB. Incorrect mounting may result in
damaging the IC. Avoid nearby pins being shorted to each other especially to ground, power supply and output pin.
Inter-pin shorts could be due to many reasons such as metal particles, water droplets (in very humid environment) and
unintentional solder bridge deposited in between pins during assembly to name a few.
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BD4271xxx-C Series
Operational Notes – continued
10.
Unused Input Terminals
Input terminals of an IC are often connected to the gate of a MOS transistor. The gate has extremely high impedance
and extremely low capacitance. If left unconnected, the electric field from the outside can easily charge it. The small
charge acquired in this way is enough to produce a significant effect on the conduction through the transistor and
cause unexpected operation of the IC. So unless otherwise specified, unused input terminals should be connected to
the power supply or ground line.
11.
Regarding the Input Pin of the IC
This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them
isolated. P/N junctions are formed at the intersection of these P layers with the N layers of other elements to create
a variety of parasitic elements.
For example, in case a resistor and a transistor are connected to the pins as shown in the figure below then:
○ The P/N junction functions as a parasitic diode when the GND > pin A for the resistor, or the GND > pin B for the
transistor.
○ Also, when the GND > pin B for the transistor (NPN), the parasitic diode described above combines with the N layer
of the other adjacent elements to operate as a parasitic NPN transistor.
Parasitic diodes inevitably occur in the structure of the IC. Their operation can result in mutual interference between
circuits and can cause malfunctions and, in turn, physical damage to or destruction of the chip. Therefore do not
employ any method in which parasitic diodes can operate such as applying a voltage to an input pin that is lower than
the (P substrate) GND.
Resistor
Transistor (NPN)
Pin A
Pin B
C
E
Pin A
N
P+
P
N
N
P+
N
Parasitic
Elements
N
P+
N P
N
P+
B
N
C
E
Parasitic
Elements
P Substrate
P Substrate
GND
Parasitic
Elements
Pin B
B
GND
Parasitic
Elements
GND
GND
N Region
close-by
12.
Ceramic Capacitor
When using a ceramic capacitor, determine the dielectric constant considering the change of capacitance with
temperature and the decrease in nominal capacitance due to DC bias and others.
13.
Thermal Shutdown Circuit (TSD)
This IC incorporates and integrated thermal shutdown circuit to prevent heat damage to the IC. Normal operation
should be within the power dissipation rating, if however the rating is exceeded for a continued period, the junction
temperature (Tj) will rise and the TSD circuit will be activated and turn all output pins OFF. After the Tj falls below the
TSD threshold the circuits are automatically restored to normal operation.
Note that the TSD circuit operates in a situation that exceeds the absolute maximum ratings and therefore, under no
circumstances, should the TSD circuit be used in a set design or for any purpose other than protecting the IC from
heat damage.
14.
Over Current Protection Circuit (OCP)
This IC incorporates an integrated overcurrent protection circuit that is activated when the load is shorted. This
protection circuit is effective in preventing damage due to sudden and unexpected incidents. However, the IC should
not be used in applications characterized by continuous operation or transitioning of the protection circuit.
15.
Functional Safety
“ISO 26262 Process Compliant to Support ASIL-*”
A product that has been developed based on an ISO 26262 design process compliant to the ASIL level described in
the datasheet.
“Safety Mechanism is Implemented to Support Functional Safety (ASIL-*)”
A product that has implemented safety mechanism to meet ASIL level requirements described in the datasheet.
“Functional Safety Supportive Automotive Products”
A product that has been developed for automotive use and is capable of supporting safety analysis with regard to the
functional safety.
Note: “ASIL-*” is stands for the ratings of “ASIL-A”, “-B”, “-C” or “-D” specified by each product's datasheet.
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BD4271xxx-C Series
Ordering Information
B
D
4
2
7
1
Part Number
x
x
x
Package
HFP: HRP7
FP2: TO263-7
EFJ: HTSOP-J8
-
C x x
Product Rank
C: for Automotive
Packaging and forming specification
TR: Embossed tape and reel
E2: Embossed tape and reel
Marking Diagram
HRP7 (TOP VIEW)
TO263-7 (TOP VIEW)
Part Number Marking
Part Number Marking
LOT Number
LOT Number
Pin 1 Mark
Pin 1
HTSOP-J8 (TOP VIEW)
Part Number Marking
LOT Number
Pin 1 Mark
Part Number Marking
Package
Orderable Part Number
HRP7
BD4271HFP-CTR
BD4271
TO263-7
BD4271FP2-CE2
HTSOP-J8
BD4271EFJ-CE2
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BD4271xxx-C Series
Physical Dimension, Tape and Reel Information
Package Name
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HRP7
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BD4271xxx-C Series
Physical Dimension, Tape and Reel Information – continued
Package Name
TO263-7
< Tape and Reel Information >
Tape
Embossed carrier tape
Quantity
500pcs
Direction of feed
E2
The direction is the pin 1 of product is at the lower left when you hold
reel on the left hand and you pull out the tape on the right hand
Reel
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Direction of feed
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30.Mar.2023 Rev.004
BD4271xxx-C Series
Physical Dimension and Packing Information – continued
Package Name
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HTSOP-J8
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BD4271xxx-C Series
Revision History
Date
Revision
Mar.30.2016
001
New Release.
Jun.21.2016
002
TO263-7 PKG added.
Thermal resistance format updated.
003
Subtitle correction.
Symbol correction “Reset Detection Hysteresis”.
Symbol correction “CT Upper-side Threshold”.
Symbol correction “CT Lower-side Threshold”.
Symbol correction “CT Charge Current”.
Symbol correction “CT Discharge Current”.
Formula correction “WDT Monitor Time”.
Formula correction “WDT Reset Time”.
Graph title correction Figure 13.
Vertical axis label and Graph title correction Figure 14.
Legend correction Figure 17.
Legend correction Figure 18.
Vertical axis label and Graph title correction Figure 19.
Vertical axis label and Graph title correction Figure 20.
HTSOP-J8 PKG added.
004
Add Key Specifications “Functional Safety Supportive Automotive Products”
Electrical Characteristics parameter correction. “CLK Input High Level Voltage”.
Electrical Characteristics parameter correction. “CLK Input Low Level Voltage”.
Data correction Figure 11.
Add Operational Notes “15. Functional Safety”.
Mar.25.2021
Mar.30.2023
Changes
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Notice
Precaution on using ROHM Products
1.
If you intend to use our Products in devices requiring extremely high reliability (such as medical equipment (Note 1),
aircraft/spacecraft, nuclear power controllers, etc.) and whose malfunction or failure may cause loss of human life,
bodily injury or serious damage to property (“Specific Applications”), please consult with the ROHM sales
representative in advance. Unless otherwise agreed in writing by ROHM in advance, ROHM shall not be in any way
responsible or liable for any damages, expenses or losses incurred by you or third parties arising from the use of any
ROHM’s Products for Specific Applications.
(Note1) Medical Equipment Classification of the Specific Applications
JAPAN
USA
EU
CHINA
CLASSⅢ
CLASSⅡb
CLASSⅢ
CLASSⅢ
CLASSⅣ
CLASSⅢ
2.
ROHM designs and manufactures its Products subject to strict quality control system. However, semiconductor
products can fail or malfunction at a certain rate. Please be sure to implement, at your own responsibilities, adequate
safety measures including but not limited to fail-safe design against the physical injury, damage to any property, which
a failure or malfunction of our Products may cause. The following are examples of safety measures:
[a] Installation of protection circuits or other protective devices to improve system safety
[b] Installation of redundant circuits to reduce the impact of single or multiple circuit failure
3.
Our Products are not designed under any special or extraordinary environments or conditions, as exemplified below.
Accordingly, ROHM shall not be in any way responsible or liable for any damages, expenses or losses arising from the
use of any ROHM’s Products under any special or extraordinary environments or conditions. If you intend to use our
Products under any special or extraordinary environments or conditions (as exemplified below), your independent
verification and confirmation of product performance, reliability, etc, prior to use, must be necessary:
[a] Use of our Products in any types of liquid, including water, oils, chemicals, and organic solvents
[b] Use of our Products outdoors or in places where the Products are exposed to direct sunlight or dust
[c] Use of our Products in places where the Products are exposed to sea wind or corrosive gases, including Cl2,
H2S, NH3, SO2, and NO2
[d] Use of our Products in places where the Products are exposed to static electricity or electromagnetic waves
[e] Use of our Products in proximity to heat-producing components, plastic cords, or other flammable items
[f] Sealing or coating our Products with resin or other coating materials
[g] Use of our Products without cleaning residue of flux (Exclude cases where no-clean type fluxes is used.
However, recommend sufficiently about the residue.); or Washing our Products by using water or water-soluble
cleaning agents for cleaning residue after soldering
[h] Use of the Products in places subject to dew condensation
4.
The Products are not subject to radiation-proof design.
5.
Please verify and confirm characteristics of the final or mounted products in using the Products.
6.
In particular, if a transient load (a large amount of load applied in a short period of time, such as pulse, is applied,
confirmation of performance characteristics after on-board mounting is strongly recommended. Avoid applying power
exceeding normal rated power; exceeding the power rating under steady-state loading condition may negatively affect
product performance and reliability.
7.
De-rate Power Dissipation depending on ambient temperature. When used in sealed area, confirm that it is the use in
the range that does not exceed the maximum junction temperature.
8.
Confirm that operation temperature is within the specified range described in the product specification.
9.
ROHM shall not be in any way responsible or liable for failure induced under deviant condition from what is defined in
this document.
Precaution for Mounting / Circuit board design
1.
When a highly active halogenous (chlorine, bromine, etc.) flux is used, the residue of flux may negatively affect product
performance and reliability.
2.
In principle, the reflow soldering method must be used on a surface-mount products, the flow soldering method must
be used on a through hole mount products. If the flow soldering method is preferred on a surface-mount products,
please consult with the ROHM representative in advance.
For details, please refer to ROHM Mounting specification
Notice-PAA-E
© 2015 ROHM Co., Ltd. All rights reserved.
Rev.004
Precautions Regarding Application Examples and External Circuits
1.
If change is made to the constant of an external circuit, please allow a sufficient margin considering variations of the
characteristics of the Products and external components, including transient characteristics, as well as static
characteristics.
2.
You agree that application notes, reference designs, and associated data and information contained in this document
are presented only as guidance for Products use. Therefore, in case you use such information, you are solely
responsible for it and you must exercise your own independent verification and judgment in the use of such information
contained in this document. ROHM shall not be in any way responsible or liable for any damages, expenses or losses
incurred by you or third parties arising from the use of such information.
Precaution for Electrostatic
This Product is electrostatic sensitive product, which may be damaged due to electrostatic discharge. Please take proper
caution in your manufacturing process and storage so that voltage exceeding the Products maximum rating will not be
applied to Products. Please take special care under dry condition (e.g. Grounding of human body / equipment / solder iron,
isolation from charged objects, setting of Ionizer, friction prevention and temperature / humidity control).
Precaution for Storage / Transportation
1.
Product performance and soldered connections may deteriorate if the Products are stored in the places where:
[a] the Products are exposed to sea winds or corrosive gases, including Cl 2, H2S, NH3, SO2, and NO2
[b] the temperature or humidity exceeds those recommended by ROHM
[c] the Products are exposed to direct sunshine or condensation
[d] the Products are exposed to high Electrostatic
2.
Even under ROHM recommended storage condition, solderability of products out of recommended storage time period
may be degraded. It is strongly recommended to confirm solderability before using Products of which storage time is
exceeding the recommended storage time period.
3.
Store / transport cartons in the correct direction, which is indicated on a carton with a symbol. Otherwise bent leads
may occur due to excessive stress applied when dropping of a carton.
4.
Use Products within the specified time after opening a humidity barrier bag. Baking is required before using Products of
which storage time is exceeding the recommended storage time period.
Precaution for Product Label
A two-dimensional barcode printed on ROHM Products label is for ROHM’s internal use only.
Precaution for Disposition
When disposing Products please dispose them properly using an authorized industry waste company.
Precaution for Foreign Exchange and Foreign Trade act
Since concerned goods might be fallen under listed items of export control prescribed by Foreign exchange and Foreign
trade act, please consult with ROHM in case of export.
Precaution Regarding Intellectual Property Rights
1.
All information and data including but not limited to application example contained in this document is for reference
only. ROHM does not warrant that foregoing information or data will not infringe any intellectual property rights or any
other rights of any third party regarding such information or data.
2.
ROHM shall not have any obligations where the claims, actions or demands arising from the combination of the
Products with other articles such as components, circuits, systems or external equipment (including software).
3.
No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of ROHM or any
third parties with respect to the Products or the information contained in this document. Provided, however, that ROHM
will not assert its intellectual property rights or other rights against you or your customers to the extent necessary to
manufacture or sell products containing the Products, subject to the terms and conditions herein.
Other Precaution
1.
This document may not be reprinted or reproduced, in whole or in part, without prior written consent of ROHM.
2.
The Products may not be disassembled, converted, modified, reproduced or otherwise changed without prior written
consent of ROHM.
3.
In no event shall you use in any way whatsoever the Products and the related technical information contained in the
Products or this document for any military purposes, including but not limited to, the development of mass-destruction
weapons.
4.
The proper names of companies or products described in this document are trademarks or registered trademarks of
ROHM, its affiliated companies or third parties.
Notice-PAA-E
© 2015 ROHM Co., Ltd. All rights reserved.
Rev.004
Datasheet
General Precaution
1. Before you use our Products, you are requested to carefully read this document and fully understand its contents.
ROHM shall not be in any way responsible or liable for failure, malfunction or accident arising from the use of any
ROHM’s Products against warning, caution or note contained in this document.
2. All information contained in this document is current as of the issuing date and subject to change without any prior
notice. Before purchasing or using ROHM’s Products, please confirm the latest information with a ROHM sales
representative.
3.
The information contained in this document is provided on an “as is” basis and ROHM does not warrant that all
information contained in this document is accurate and/or error-free. ROHM shall not be in any way responsible or
liable for an y damages, expenses or losses incurred b y you or third parties resulting from inaccuracy or errors of or
concerning such information.
Notice – WE
© 2015 ROHM Co., Ltd. All rights reserved.
Rev.001
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