System Power Supply ICs for CCD Camera of Mobile Phones
Power Supply for CCD Camera Module
BD6029GU
No.10033EAT01
●Description BD6029GU is system power supply LSI for CCD camera that supplies all voltage sources for CCD camera. This IC has Step up DC/DC converter and LDO for CCD sensor, Inverted DC/DC converter for CCD sensor, Series Regulators for DSP 3ch, CCD I/O 1ch and V-driver 1ch. Each output voltage has an adjustable to the register, and this IC can correspond to various CCD modules. A necessary power supply for CCD camera is integrated into 1chip, and it contributes to space saving. BD6029GU achieves compact size with the chip size package. ●Features 1) The BD6029GU is equipped with all voltage sources for CCD camera. 2) Each output has an adjustable voltage, and hence this IC can correspond to various CCD modules. 3) The BD6029GU has 3ch voltage regulators which have adjustable voltage for DSP, and hence BD6029GU can correspond to various DSP chip sets. 4) The BD6029GU has other 2ch voltage regulators for CCD I/O and V-driver. 2 5) The BD6029GU is controlled by I C BUS format. 6) The BD6029GU employs 4.35mm2 chip size package, so this IC achieves compact size. ●Functions 1) Step up DC/DC converter and LDO for CCD sensor (+15V/+14.5V/+13V) 2) Inverted DC/DC converter for CCD sensor (-8V/-7.5V/-7V) 3) 5ch Series Regulator REG1 : 1.2V/1.8V, Iomax=150mA REG2 : 2.7V/3.0V/3.3V, Iomax=150mA REG5 : 1.8V/3.0V, Iomax=150mA REG6 : 3.0V/3.1V/3.2V/3.3V, Iomax=200mA REGA: 1.8V/3.0V/3.3, Iomax=150mA 2 4) Correspondence to I C BUS format 5) Thermal shutdown (Auto-reset type) 6) VCSP85H4 small package (chip size package) ●Absolute Maximum Ratings (Ta=25°C) Parameter Maximum Applied voltage 1 Maximum Applied Voltage 2 Maximum Applied Voltage 3 Maximum Applied Voltage 4 Power Dissipation Operating Temperature Range Storage Temperature Range
(Note 1) (Note 2) (Note 3) (Note 4) (Note 5)
Symbol VMAX1 VMAX2 VMAX3 VMAX4 Pd Topr Tstg
Ratings 20 18 -13.5 6 1925 -30 ~ +85 -55 ~ +125
Unit V V V V mW °C °C
(Note 1) SW，VPLUS1，VPLUS2 pin (Note 2) VDD3 pin (Note 3) VDD4 pin (Note 4) Except Note1~Note3 pin (Note 5) Power dissipation deleting is 15.4mW/ oC, when it’s used in over 25 oC. (It’s deleting is on the board that is ROHM’s standard)
●Recommended Operating Conditions (VBAT≥VIO, Ta=-30~85 °C) Parameter Symbol VBAT input voltage VIO pin voltage VBAT VIO
Limits 2.7 ~ 5.5 1.62 ~ 3.3
Unit V V
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1/19
2010.03 - Rev.A
BD6029GU
Technical Note
●Electrical Characteristics (Unless otherwise specified, Ta=25°C, VBAT=3.6V, VIO=1.8V/3.0V) Limits Parameter Symbol Unit Condition Min. Typ. Max. Circuit Current VBAT Circuit current 1 VBAT Circuit current 2 VBAT Circuit current 3 VBAT Circuit current 4 VBAT Circuit current 5 VBAT Circuit current 6 VBAT Circuit current 7 VBAT Circuit current 8 SWREG3 (Step up DC/DC) VoPD1 VoPD2 VoPD3 IoPD EffPD foscPD VsatPD OvPD OcPD VoND1 VoND2 VoND3 IoND EffND foscND OvND OcND ROFFN 0.8 18.0 1.0 -8.4 -7.9 -7.4 0.8 -10.5 1.0 0.5 17.0 16.5 14.5 (80) 1.0 200 18.5 1.25 -8.0 -7.5 -7.0 (75) 1.0 -10.0 1.25 1.0 60 1.2 400 19.0 1.5 -7.6 -7.1 -6.6 100 1.2 -9.5 1.5 1.5 V V V mA % MHz mV V A V V V mA % MHz V A kΩ Io=100mA Io=100mA Io=100mA
(Note 6)
IBAT1 IBAT2 IBAT3 IBAT4 IBAT5 IBAT6 IBAT7 IBAT8
-
0.1 0.5 90 90 90 90 90 9
3.0 3.0 135 135 135 135 135 14
μA μA μA μA μA μA μA mA
RST=0V, VIO=0V RST=0V REG1:ON, Io=0mA REG2:ON, Io=0mA REG5:ON, Io=0mA REG6:ON, Io=0mA REGA:ON, Io=0mA SWREG3:ON,REG3:ON, SWREG4:ON, Io=0mA Io=60mA Io=60mA Io=60mA
(Note 6)
Output voltage 1 Output voltage 2 Output voltage 3 Output current Efficiency Oscillator frequency SW saturation voltage Over voltage protection Over current protection SWREG4 (Inverted DC/DC) Output voltage 1 Output voltage 2 Output voltage 3 Output current Efficiency Oscillator frequency Over voltage protection Over current protection Electric discharge resister at OFF
Io=60mA Iin=200mA
(Note 6)
Io=100mA
(Note 6)
(Note 6) The power efficiency changes with the fluctuation of external parts and the board mounting condition.
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2/19
2010.03 - Rev.A
BD6029GU
Technical Note
●Electrical Characteristics (Unless otherwise specified, Ta=25°C, VBAT=3.6V, VIO=1.8V/3.0V) Limits Parameter Symbol Unit Condition Min. Typ. Max. REG1 (1.2V/1.8V LDO) Vo11 Vo12 Io1 ∆Vo11 ∆Vo12 RR1 Ilim01 ROFF1 Vo21 Vo22 Vo23 Io2 Vsat2 ∆Vo21 ∆Vo22 RR2 Ilim02 ROFF2 Vo31 Vo32 Vo33 Vsat3 ∆Vo31 ∆Vo32 ∆Vo33 RR3 Ilim03 ROFF3 1.140 1.746 2.619 2.910 3.201 14.05 14.55 12.55 0.5 1.20 1.80 10 10 65 200 1.0 2.70 3.00 3.30 0.2 10 10 60 200 1.0 14.5 15.0 13.0 0.32 20 10 ±100 100 1.0 1.260 1.854 150 60 60 400 1.5 2.781 3.090 3.399 150 0.3 60 60 400 1.5 14.95 15.45 13.45 0.5 80 60 3 1.5 V V mA mV mV dB mA kΩ V V V mA V mV mV dB mA kΩ V V V V mV mV Io=60mA Io=60mA Io=60mA VPLUS2=11V, Io=60mA Io=1～60mA VPLUS2=16.5～17.5V, Io=60mA Io=150mA Io=150mA Io=150mA Vo=2.7V VBAT=2.5V, Io=150mA, Vo=2.7V Io=1~150mA, Vo=2.7V VBAT=3.4~4.5V, Io=50mA, Vo=2.7V f=100Hz, Vin=200mVp-p, Vo=2.7V Io=50mA, BW=20Hz~20kHz Vo=0V Io=150mA Io=150mA Vo=1.8V Io=1~150mA, Vo=1.8V VBAT=3.2~4.5V, Io=100mA, Vo=1.8V f=100Hz, Vin=200mVp-p, Vo=1.2V Io=50mA, BW=20Hz~20kHz Vo=0V Output voltage 1 Output voltage 2 Output current Load stability Input stability Ripple rejection ratio Current over load limiter Discharge resister at OFF REG2 (2.7V/3.0V/3.3V LDO) Output voltage 1 Output voltage 2 Output voltage 3 Output current I/O voltage difference Load stability Input stability Ripple rejection ratio Current over load limiter Discharge resister at OFF REG3 (15V/14.5V/13V LDO) Output voltage 1 Output voltage 2 Output voltage 3 I/O voltage difference Load stability Input stability Output voltage temperature fluctuation rate Output ripple voltage Current over load limiter Discharge resister at OFF
(Note 7) BW: Band width
ppm/°C Ta=-30℃～85℃, Io=60mA mVp-p Io=60mA, BW=20Hz～80kHz(Note 7) mA kΩ Vo=0V
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3/19
2010.03 - Rev.A
BD6029GU
Technical Note
●Electrical Characteristics (Unless otherwise specified, Ta=25°C, VBAT=3.6V, VIO=1.8V/3.0V) Limits Parameter Symbol Unit Condition Min. Typ. Max. REG5 (1.8V/3.0V LDO) Vo51 Vo52 Io5 Vsat5 ∆Vo51 ∆Vo52 RR5 Ilim05 ROFF5 Vo61 Vo62 Vo63 Vo64 Io6 Vsat6 ∆Vo61 ∆Vo62 RR6 Ilim06 ROFF6 VoA1 VoA2 VoA3 IoA VsatA ΔVoA1 ΔVoA2 RRA Ilim0A ROFFA VIL VIH Vhys VOL li 1.746 2.910 2.910 3.007 3.104 3.201 1.746 2.910 3.201 -0.3 0.75VIO 0.05VIO 0 -10 1.80 3.00 0.2 10 10 65 200 1.0 3.00 3.10 3.20 3.30 0.2 10 10 60 250 1.0 1.80 3.00 3.30 0.2 10 10 65 200 1.0 1.854 3.090 150 0.3 60 60 400 1.5 3.090 3.193 3.296 3.399 200 0.3 60 60 500 1.5 1.854 3.090 3.399 150 0.3 60 60 400 1.5 0.25VIO VIO+0.3 0.30 10 V V mA V mV mV dB mA kΩ V V V V mA V mV mV dB mA kΩ V V V mA V mV mV dB mA kΩ V V V V μA input voltage between 0.1 VIO and 0.9 VIO Io=150mA Io=150mA Io=150mA Vo=1.8V VBAT=2.5V, Io=150mA, Vo=3.0V Io=1~150mA, Vo=1.8V VBAT=3.4~4.5V, Io=150mA, Vo=1.8V f=100Hz, Vin=200mVp-p, Vo=1.8V Io=50mA, BW=20Hz~20kHz Vo=0V Io=200mA Io=200mA Io=200mA Io=200mA Vo=3.0V VBAT=2.5V, Io=200mA, Vo=3.0V Io=1~200mA, Vo=3.0V VBAT=3.4~4.5V, Io=200mA, Vo=3.0V f=100Hz, Vin=200mVp-p, Vo=3.0V Io=50mA, BW=20Hz~20kHz Vo=0V Io=150mA Io=150mA Vo=1.8V VBAT=2.5V, Io=150mA, Vo=3.0V Io=1~150mA, Vo=1.8V VBAT=3.3~4.5V, Io=80mA, Vo=1.8V f=100Hz, Vin=200mVp-p, Vo=1.8V Io=50mA, BW=20Hz~20kHz Vo=0V Output voltage 1 Output voltage 2 Output current I/O voltage difference Load stability Input stability Ripple rejection ratio Current over load limiter Discharge resister at OFF REG6 (3.0V/3.1V/3.2V/3.3V LDO) Output voltage 1 Output voltage 2 Output voltage 3 Output voltage 4 Output current I/O voltage difference Load stability Input stability Ripple rejection ratio Current over load limiter Discharge resister at OFF REGA (1.8V/3.0V/3.3V LDO) Output voltage 1 Output voltage 2 Output voltage 3 Output current I/O voltage difference Load stability Input stability Ripple rejection ratio Current over load limiter Discharge resister at OFF I2C Input (RST, SDA, SCL) LOW level input voltage HIGH level input voltage Hysteresis of Schmitt trigger input LOW level output voltage (SDA) at 3mA sink current Input current each I/O pin
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4/19
2010.03 - Rev.A
BD6029GU
●Power Dissipation (On the ROHM’s standard board)
2 1.8 1.6
Technical Note
1925mW
Power Dissipation Pd （W)
1.4 1.2 1 0.8 0.6 0.4 0.2 0 0 25 50 75 100 125 150
Ta(℃)
Fig.1 Power Dissipation Information of the ROHM’s standard board Material : glass-epoxy Size : 50mm×58mm×1.75mm (8 Layer) Pattern of the board : Refer to P.18
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5/19
2010.03 - Rev.A
BD6029GU
●Block Diagram / Application Circuit example
Battery 1μF(6.3V) F F
Technical Note
RB521S-30
2.2μF(6.3V)
1μF(25V)
10μH
MONR2
MONR1
GNDPS
VPLUS1
VBAT1 VBAT2 VBAT3 VBAT4 VBAT5 VBAT6 VBAT7 R
0.08Ω
VPLUS2
GNDP
SW
Current Sense
Over Voltage Limit
Q
+
-
Driver
15V / 14.5V /13V Iomax=60mA
REG3
VDD3 1μF(16V)
REG1
1.2V / 1.8V Iomax=150mA
S
VDD1 1μF(6.3V)
T2 Control
+
T3
OSC
T1
+
2.7V / 3.0V / 3.3V Iomax=150mA
REG2
VDD2 1μF(6.3V)
SWREG3
+
-
Feed Back
REG5
1.8V / 3.0V Iomax=150mA
VDD5 1μF(6.3V)
T4
VREF 0.1μF(6.3V)
VREF
1.8V / 3.0V / 3.3V Iomax=150mA
REGA
AVDD 1μF(6.3V)
VIO
3.0V / 3.1V / 3.2V / 3.3V Iomax=200mA
REG6
VDD6 1μF(6.3V)
CCD Camera Module
MVDD1 RST MVDD2
CONT CPU
SDA
IC
2
SWREG4
Current Sense
VBATN2 VBATN1
0.08Ω
SCL
-
+
OSC TESTO1 TESTO2 TESTI1 TESTI2
SENSN1 SENSN2
2.2μF(6.3V)
+
-
Control
R S
TRSW Q
Driver
QS5U26
Over Voltage Limit
+
4.7μH 1μF(16V)
TSD
+
VDD4 -8V / -7.5V / -7V Iomax=100mA
GND1
GND2
GND3
GND4
GND5
GND6
Pin Connection
T1~T4, TESTI1, TESTI2 TEST01, TEST02, MVDD1, MVDD2 Output of unused LDO MONR1-MONR2 short MVDD1-MVDD2 short
GND7
: GND short : Open : Open
Fig.2 Block Diagram / Application Circuit example
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6/19
2010.03 - Rev.A
BD6029GU
●Pin Configuration ［Bottom View］
Technical Note
H
T4
VDD3
VPLUS1
GNDP
MONR2
SW
GND6
T3
G
TESTI1
TESTI2
VPLUS2
GNDPS
MONR1
VBAT5
TESTO2
AVDD
F
RST
VIO
VBAT4
VDD5
E
GND7
SDA
VREF
GND5
D
VDD2
SCL
VBAT3
VDD1
C
VBAT6
VBAT7
VBAT2
VDD6
B
MVDD2
MVDD1
VBATN1
SENSN2
VBAT1
GND3
TESTO1
GND4
A
T1 1
GND1 2
VBATN2 3
SENSN1 4
TRSW 5
GND2 6
VDD4 7
T2 8
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7/19
2010.03 - Rev.A
BD6029GU
●Package Outline VCSP85H4 (BU6029GU)
Technical Note
(unit:mm)
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8/19
2010.03 - Rev.A
BD6029GU
●Pin Functions No Pin No Pin Name I/O O I I I O I I I I I I O O O O O O O O O O I I I I I I O O Input Level VIO VIO VIO ESD Diode For For Power GND GND GND GND GND GND GND GND VBAT GND GND GND VBAT GND VBAT GND VBAT GND VIO GND VIO GND VIO GND VBAT VBAT VBAT VBAT VBAT VBAT VBAT GND VBAT GND VBAT GND VBAT GND VBAT GND GND GND VPLUS2 GND VBAT GND VBAT GND VBAT GND VBAT GND VBAT GND VBAT GND VBAT GND VBAT GND VBAT GND VIO GND VIO GND VBAT GND VBAT GND VBAT GND VBAT GND VBAT GND GND Functions
Technical Note
Initial Conditions 0V output Stop operating 0V output 0V output 0V output 0V output 0V output 0V output Stop operating 0V output
1 B5 VBAT1 2 C7 VBAT2 3 D7 VBAT3 4 F7 VBAT4 5 G6 VBAT5 6 C1 VBAT6 7 C2 VBAT7 8 A1 T1 9 A8 T2 10 H8 T3 11 H1 T4 12 E7 VREF 13 F2 VIO 14 F1 RST 15 E2 SDA 16 D2 SCL 17 A2 GND1 18 A6 GND2 19 B6 GND3 20 B8 GND4 21 E8 GND5 22 H7 GND6 23 E1 GND7 24 H6 SW 25 H5 MONR2 26 G5 MONR1 27 H4 GNDP 28 G4 GNDPS 29 H3 VPLUS1 30 G3 VPLUS2 31 H2 VDD3 32 D8 VDD1 33 D1 VDD2 34 F8 VDD5 35 G8 AVDD 36 C8 VDD6 37 B2 MVDD1 38 B1 MVDD2 39 B7 TESTO1 40 G7 TESTO2 41 G1 TESTI1 42 G2 TESTI2 43 A3 VBATN2 44 B3 VBATN1 45 A4 SENSN1 46 B4 SENSN2 47 A5 TRSW 48 A7 VDD4 Total: 48Pin
Battery is connected Battery is connected Battery is connected Battery is connected Battery is connected Battery is connected Battery is connected Test pin Test pin Test pin Test pin Reference voltage output Power supply for logic Reset input I2C data input I2C clock input Ground Ground Ground Ground Ground Ground Ground SWREG3 coil switching pin SWREG3 current sense pin SWREG3 current sense pin SWREG3 current sense pin SWREG3 current sense pin SWREG3 boost voltage feedback pin Power supply input for REG3 (15.5V/14.5V/13V LDO) REG3 (15.5V/14.5V/13V LDO) output pin REG1 (1.2V/1.8V LDO) output pin REG2 (2.7V/3.0V/3.3V LDO) output pin REG5 (1.8V/3.0V LDO) output pin REGA (1.8V/3.0V/3.3V LDO) output pin REG6 (3.0V/3.1V/3.2V/3.3V LDO) output pin NC NC Test pin Test pin Test pin Test pin Battery is connected (SWREG4 current sense) Battery is connected (SWREG4 current sense) SWREG4 current sense pin SWREG4 current sense pin SWREG4 switching Tr. drive pin SWREG4 (-8V/-7.5V/-7V) output pin
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9/19
2010.03 - Rev.A
BD6029GU
●I2C BUS format 2 The writing/reading operation is based on the I C slave standard. ◦ Slave address A7 A6 0 0
Technical Note
A5 0
A4 1
A3 0
A2 0
A1 1
R/W 1/0
◦ Bit Transfer SCL transfers 1-bit data during H. SCL cannot change signal of SDA during H at the time of bit transfer. If SDA changes while SCL is H, START conditions or STOP conditions will occur and it will be interpreted as a control signal.
SDA
SCL data line Stable; data valid change of data allowed
◦ START and STOP condition 2 When SDA and SCL are H, data is not transferred on the I C- bus. This condition indicates, if SDA changes from H to L while SCL has been H, it will become START (S) conditions, and an access start, if SDA changes from L to H while SCL has been H, it will become STOP (P) conditions and an access end.
SDA
SCL
S START condition
P STOP condition
◦ Acknowledge It transfers data 8 bits each after the occurrence of START condition. A transmitter opens SDA after transfer 8bits data, and a receiver returns the acknowledge signal by setting SDA to L.
DATA OUTPUT BY TRANSMITTER not acknowledge DATA OUTPUT BY RECEIVER acknowledge SCL S START condition 1 2 8 clock pulse for acknowledgement 9
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10/19
2010.03 - Rev.A
BD6029GU
Technical Note
◦ Writing protocol A register address is transferred by the next 1 byte that transferred the slave address and the write-in command. The 3rd byte writes data in the internal register written in by the 2nd byte, and after 4th byte or, the increment of register address is carried out automatically. However, when a register address turns into the last address(07h), it is set to 00h by the next transmission. After the transmission end, the increment of the address is carried out.
*1 S X X X X X X X 0 A A7 A6 A5 A4 A3 A2 A1 A0 A D7 D6 D5 D4 D3 D2 D1 D0 A slave address R/W=0(write) from master to slave from slave to master register address DATA register address increment A=acknowledge(SDA LOW) A=not acknowledge(SDA HIGH) S=START condition P=STOP condition *1: Write Timing *1 D7 D6 D5 D4 D3 D2 D1 D0 A P DATA register address increment
◦ Reading protocol It reads from the next byte after writing a slave address and R/W bit. The register to read considers as the following address accessed at the end, and the data of the address that carried out the increment is read after it. If an address turns into the last address(07h), the next byte will read out 00h. After the transmission end, the increment of the address is carried out.
SXXXX XXX slave address R/W=1(read) 1 A D7 D6 D5 D4 D3 D2 D1 D0 A DATA register address increment A=acknowledge(SDA LOW) A=not acknowledge(SDA HIGH) S=START condition P=STOP condition D7 D6 D5 D4 D3 D2 D1 D0 A P DATA register address increment
from master to slave from slave to master
◦ Multiple reading protocols After specifying an internal address, it reads by repeated START condition and changing the data transfer direction. The data of the address that carried out the increment is read after it. If an address turns into the last address, the next byte will read out 00h. After the transmission end, the increment of the address is carried out.
S X X X X X X X 0 A A7 A6 A5 A4 A3 A2 A1 A0 A Sr X X X X X X X 1 A slave address R/W=0(write) register address slave address R/W=1(read)
D7 D6 D5 D4 D3D2 D1D0 A DATA register address increment from master to slave from slave to master
D7D6 D5D4D3D2D1D0 A P DATA register address increment A=acknowledge(SDA LOW) A=not acknowledge(SDA HIGH) S=START condition P=STOP condition Sr=repeated START condition
As for reading protocol and multiple reading protocols, please do A(not acknowledge) after doing the final reading operation. It stops with read when ending by A(acknowledge), and SDA stops in the state of Low when the reading data of that time is 0. However, this state returns usually when SCL is moved, data is read, and A(not acknowledge) is done.
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11/19
2010.03 - Rev.A
BD6029GU
●Timing Diagram
Technical Note
SDA t BUF
tf t LOW SCL t HD;STA t HD;DAT tr
t SU;DAT
tf
t HD;STA
tr t SP
S
t SU;STA t HIGH Sr
t SU;STO P S
●Electrical Characteristics (Unless otherwise specified, Ta=25oC, VBAT=3.6V, VIO=1.8V/3.0V) Standard-mode Fast-mode Parameter Symbol Min. Typ. Max. Min. Typ. Max. I2C BUS format
Unit
SCL clock frequency LOW period of the SCL clock HIGH period of the SCL clock Hold time (repeated) START condition After this period, the first clock is generated Set-up time for a repeated START condition Data hold time Data set-up time Set-up time for STOP condition Bus free time between a STOP and START condition
fSCL tLOW tHIGH tHD;STA tSU;STA tHD;DAT tSU;DAT tSU;STO tBUF
0 4.7 4.0 4.0 4.7 0 250 4.0 4.7
-
100 3.45 -
0 1.3 0.6 0.6 0.6 0 100 0.6 1.3
-
400 0.9 -
kHz μs μs μs μs μs ns μs μs
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12/19
2010.03 - Rev.A
BD6029GU
●Register List
b15 b14 b13 b12 Address 8bit A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1
Technical Note
b0 Function
Register data D4 D3 D2 D1 D0
00h
0
0
0
0
0
0
0
0
-
-
-
-
-
-
-
SFTRST Software reset
01h
0
0
0
0
0
0
0
1
-
REGAPD REG6PD REG5PD REG3 VSEL1 REGA VSEL1 REG3 VSEL0 REGA VSEL0 -
SWREG4 REG3PD REG2PD REG1PD Power down PD REG2 VSEL1 REG6 VSEL1 REG2 VSEL0 REG6 VSEL0 REG1 VSEL1 REG5 VSEL1 REG1 VSEL0 REG5 VSEL0 Output Voltage Setting 1 Output Voltage Setting 2 (reserved)
02h
0
0
0
0
0
0
1
0
SWREG4 SWREG4 VSEL1 VSEL0 -
03h
0
0
0
0
0
0
1
1
04h
0
0
0
0
0
1
0
0
-
-
05h
0
0
0
0
0
1
0
1
-
-
-
-
-
-
-
-
(reserved)
06h
0
0
0
0
0
1
1
0
-
-
-
-
-
-
-
-
(reserved)
07h
0
0
0
0
0
1
1
1
reserved
for TEST
08h
0
0
0
0
1
0
0
0
reserved
for TEST
●Register Map
Address 00h BIT D7 D6 D5 D4 D3 D2 D1 D0 Name SFTRST Initial 0 Function 0 Reset cancel 1 Reset
Address 01h BIT D7 D6 D5 D4 D3 D2 D1 D0 Name REGAPD REG6PD REG5PD SWREG4PD REG3PD REG2PD REG1PD Initial 0 0 0 0 0 0 0 Function 0 REGA power OFF REG6 power OFF REG5 power OFF SWREG4 power OFF REG3 power OFF REG2 power OFF REG1 power OFF 1 REGA power ON REG6 power ON REG5 power ON SWREG4 power ON REG3 power ON REG2 power ON REG1 power ON
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13/19
2010.03 - Rev.A
BD6029GU
Address 02h BIT D7 D6 D5 D4 D3 D2 D1 D0 Name SWREG4VSEL1 SWREG4VSEL0 REG3VSEL1 REG3VSEL0 REG2VSEL1 REG2VSEL0 REG1VSEL1 REG1VSEL0 Initial 0 0 0 0 0 0 0 0 Function 0 SWREG4VSEL1 0 0 1 1 REG3VSEL1 0 0 1 1 REG2VSEL1 0 0 1 1 REG1VSEL1 0 0 1 1 SWREG4VSEL0 0 1 0 1 REG3VSEL0 0 1 0 1 REG2VSEL0 0 1 0 1 REG1VSEL0 0 1 0 1 1
Technical Note
SWREG4 output -8V -7.5V -7V -(prohibition of use) REG3 output 14.5V 15V 13V -(prohibition of use) REG2 output 3.3V -(prohibition of use) 3.0V 2.7V REG1 output 1.8V 1.2V 1.2V
Address 03h BIT D7 D6 D5 D4 D3 D2 D1 D0 Name REGAVSEL1 REGAVSEL0 REG6VSEL1 REG6VSEL0 REG5VSEL1 REG5VSEL0 Initial 0 0 0 0 0 0 Function 0 REGAVSEL1 0 0 1 1 REG6VSEL1 0 0 1 1 REG5VSEL1 0 0 1 1 REGAVSEL0 0 1 0 1 REG6VSEL0 0 1 0 1 REG5VSEL0 0 1 0 1 1 REGA output 3.3V -(prohibition of use) 3.0V 1.8V REG6 output 3.3V 3.1V 3.0V 3.2V REG5 output 3.0V -(prohibition of use) 1.8V 1.8V
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14/19
2010.03 - Rev.A
BD6029GU
●Explanation for Operate
Technical Note
1. Reset There are two kinds of reset, Software reset and Hardware reset. (1) Software reset ◦ It shifts to software reset with changing a register (SFTRST) setting “0” → “1”. ◦ I The register is returned to the initials value under the state of Soft Reset, and it stops accepting all address except for SFTRST. ◦ I It’s possible to release from a state of Soft Reset by setting register “1” → “0”. (2) Hardware reset ◦ I It shifts to hard reset by changing RST pin “H” → “L”. ◦ I The condition of all registers under Hardware Reset pin is returned to the initial value, and it stops accepting all address. ◦ I It’s possible to release from a state of hardware reset by setting register “L” → “H”. (3) Reset Sequence ◦ I When hardware reset was done during software reset, Software reset is canceled when hard reset is canceled. (Because the initial value of Soft Reset is “0” ) 2. Thermal shutdown The blocks which thermal shutdown function is effective in SWREG3 (Step up DC/DC converter) SWREG4 (Inverted DC/DC converter) REG1 REG2 REG3 REG5 REG6 REGA A thermal shutdown function works in about 175 oC. (Design reference value)
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15/19
2010.03 - Rev.A
BD6029GU
Technical Note
3. Sequencer block The sequencer block does the power control (like VREF is turned on → SWREG3 is turned on → REG3 is turned on) on the following condition corresponding to resister condition and output voltage of each block. Block VREF SWREG3 REG3 SWREG4 REG1 REG2 REG5 REG6 REGA POWER ON Condition Any one of REG3PD to REGAPD = H REG3PD = H and VREF ≥ 1.1V REG3PD = H and VPLUS2 ≥ 8V SWREG4PD = H, VDD3 ≥ 8V and VREF ≥ 1.1V REG1PD = H and VREF ≥ 1.1V REG2PD = H and VREF ≥ 1.1V REG5PD = H and VREF ≥ 1.1V REG6PD = H and VREF ≥ 1.1V REGAPD = H and VREF ≥ 1.1V
REG3PD SWREG4PD
POWER OFF Condition REG3PD to REGAPD = all L REG3PD=L REG3PD=L SWREG4PD=L REG1PD=L REG2PD=L REG5PD=L REG6PD=L REGAPD=L
REG5PD REG6PD REGAPD
REG1PD
REG2PD
VREF VREF>1.1[V]
SWREG3
SWREG4
VPLUS2>8[V]
REG3 VDD3>8[V] VDD3 VDD4
REG1
REG2
REG5
REG6
REGA
VDD1
VDD2
VDD5
VDD6
AVDD
When a thermal shutdown hangs, the whole block except for VREF turns off the power. When it reverts from the thermal shutdown, it starts from the sequence after VREF ON in the above pattern. The start of SWREG4 (CCD negative power supply) requires the rise-up of REG3 (CCD positive power supply). This requirement is valid for the reversion from the thermal shutdown and the short circuit. Detection voltage of VREF’s rise-up is 1.1V when static output is 1.2V. As shown in the former page description, VREF receives a turning on instruction blocked either each and beginsrise up. Therefore, it is necessary to consider the block started up first at the rise time of VREF.
L DO ON
VREF output
95% up
LDO output Worst 5ms
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16/19
2010.03 - Rev.A
BD6029GU
Technical Note
4. I2C BUS Operation when a signal beyond fSCL=400kHz is input cannot be guaranteed, because this LSI doesn’t correspond to the H/S(High Speed) mode of the I2C BUS format. When it uses on the serial-bus-system which the F/S(Fast Speed) mode was mixed in with the H/S mode, please connect it and remove a connection by using the mutual connection bridge from the H/S mode section to F/S mode section or in that reverse direction. However, an optional input signal never spreads to the logic part of IC, because it stops the operation of the input buffer of SDA and SCL at RST pin=L.
At RST=L, output ”H” fixed
SCL (SDA)
Level shifter EN Logic
RST
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17/19
2010.03 - Rev.A
BD6029GU
●PCB Pattern of the Power Dissipation Measuring Board
Technical Note
1st layer(component)
2nd layer
3rd layer
4th layer
5th layer
6th layer
7th layer
8th layer(solder)
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18/19
2010.03 - Rev.A
BD6029GU
●Ordering part number
Technical Note
B
D
6
Part No.
0
2
9
G
U
-
E
2
Part No.
Package GU: VCSP85H4
Packaging and forming specification E2: Embossed tape and reel
VCSP85H4 (BD6029GU)
1PIN MARK
4.35±0.05
Tape Quantity
0.25±0.1 1.0MAX
Embossed carrier tape 2500pcs E2
The direction is the 1pin of product is at the upper left when you hold
4.35±0.05
Direction of feed
S
0.425±0.05
( reel on the left hand and you pull out the tape on the right hand
)
48-φ0.3±0.05 0.05 A B
H G F E D C B A
0.06 S A B
(φ0.15)INDEX POST
P=0.5×7
1 234567 8
0.425±0.05
P=0.5×7
1pin
Direction of feed
(Unit : mm)
Reel
∗ Order quantity needs to be multiple of the minimum quantity.
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19/19
2010.03 - Rev.A
Notice
Notes
No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM Co.,Ltd. The content specified herein is subject to change for improvement without notice. The content specified herein is for the purpose of introducing ROHM's products (hereinafter "Products"). If you wish to use any such Product, please be sure to refer to the specifications, which can be obtained from ROHM upon request. Examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the Products. The peripheral conditions must be taken into account when designing circuits for mass production. Great care was taken in ensuring the accuracy of the information specified in this document. However, should you incur any damage arising from any inaccuracy or misprint of such information, ROHM shall bear no responsibility for such damage. The technical information specified herein is intended only to show the typical functions of and examples of application circuits for the Products. ROHM does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or other rights held by ROHM and other parties. ROHM shall bear no responsibility whatsoever for any dispute arising from the use of such technical information. The Products specified in this document are intended to be used with general-use electronic equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices). The Products specified in this document are not designed to be radiation tolerant. While ROHM always makes efforts to enhance the quality and reliability of its Products, a Product may fail or malfunction for a variety of reasons. Please be sure to implement in your equipment using the Products safety measures to guard against the possibility of physical injury, fire or any other damage caused in the event of the failure of any Product, such as derating, redundancy, fire control and fail-safe designs. ROHM shall bear no responsibility whatsoever for your use of any Product outside of the prescribed scope or not in accordance with the instruction manual. The Products are not designed or manufactured to be used with any equipment, device or system which requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of human injury (such as a medical instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuel-controller or other safety device). ROHM shall bear no responsibility in any way for use of any of the Products for the above special purposes. If a Product is intended to be used for any such special purpose, please contact a ROHM sales representative before purchasing. If you intend to export or ship overseas any Product or technology specified herein that may be controlled under the Foreign Exchange and the Foreign Trade Law, you will be required to obtain a license or permit under the Law.
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