Datasheet
320mA LED Camera Flash Driver
With I2C Compatible Interface
BD6164GUT
●Key Specifications
Operating power supply voltage range: 2.7V to 4.5V
Quiescent Current:
1μA (Typ.)
Switching Frequency:
4.0MHz(Typ.)
Operating temperature range:
-30℃ to +85℃
●General Description
The BD6164GUT is 320mA Flash LED driver with
Synchronous rectification step up DC/DC converter that
can drive 1 Flash LED.
2
It is possible to choice flash and torch current by I C I/F.
●Package
W(Typ.)
D(Typ.)
H (Max.)
●Features
Current regulation for LED
Flash LED Current driver
(260mA,280mA,300mA,320mA)
Assist Light Function LED Current driver
(52mA, 72mA)
High efficiency : 85%
(LED current 300mA, VBAT=3.6V, LED Vf=3.6V,
4MHz mode,Ta=25 oC)
I2C Control I/F
Synchronous rectification step-up DC/DC converter
High switching frequency 4MHz
Over Voltage Protection (OVP)
In-rush current prevention (Soft Start)
Over Current Protection (OCP)
Under Voltage Lockout (UVLO)
Over Temperature Protection (OTP)
Short-Circuit Fault detection (SCF)
VCSP60N1
1.10mm x 1.50mm x 0.675mm
●Applications
Torch light and flash for camera of mobile phone
Internal generated power supply
●Pn Configuration
●Typical Application Circuit and Block Diagram
BOTTOM VIEW
C
SCL
SDA
1.0µH
Battery
2.2µF
SW
B LEDOUT
VOUT
A
SW
GND
1
2
VOUT
2 x 1.5µF
BD6164GUT
SDA
LEDOUT
Flash LED
SCL
GND
○Product structure:Silicon monolithic integrated circuit
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Datasheet
BD6164GUT
●Absolute Maximum Ratings (Ta=25oC)
Parameter
Symbol
Rating
Unit
V
Maximum terminal voltage1*1
VMAX1
7
*2
VMAX2
4.5
Maximum terminal voltage2
Power dissipation
V
*3
Pd
550
mW
Operating temperature range
Topr
-30 to +85
o
C
Storage temperature range
Tstg
-55 to +150
o
C
*1 for SW, VOUT, LEDOUT
*2 for SCL, SDA
*3 This value will be acquired from a sample device, mounted on a PCB by ROHM. The temperature indicates the dissipation: 6.0 mW/ oC (from Ta>25 oC)
o
o
●Recommended Operating Ratings (Ta=-30 C to 85 C)
Parameter
Supply voltage
Symbol
Rating
Unit
Vin
2.7 to 4.5
V
●Electrical Characteristics
o
o
(Unless otherwise noted, Ta = -30 C to+85 C, Vin=2.7V to 4.5V)
Symbol
Min.
Typ.
Max.
Units
Low Bus voltage1
VthL1
-
-
0.1
V
High Bus voltage1
VthH1
1.71
-
-
V
High level Input current
IinH1
-
-
2
μA
SCL,SDA=1.8V
Low level Input current
IinL1
-2
-
-
μA
SCL,SDA=0.0V
Quiescent current (shutdown)
Iq,shdwn
-
1
5
μA
Quiescent current (stand by)
Iq,standby
-
3
9
μA
Iflash
-7
0
7
%
Shut down
(SDA/SCL = 0V)
Stand by mode
(SDA/SCL pull-up)
*2
Parameter
Conditions
2
I C control terminals SDA/SCL
LED driver
LED current accuracy
LED current accuracy INL
INL
-1
0
1
LSB
LED current accuracy DNL
DNL
-1
0
1
LSB
Current source saturation
voltage
Vsat
-
0.2
0.35
V
@Flash mode, LED
current=300mA,VOUT=4.0V
Inductor current limit
Icoil
0.65
0.8
0.95
A
*1
Over voltage limit
Vovp
4.9
5.1
5.3
V
VOUT terminal
Output voltage range
Vorng
-
-
4.7
V
VOUT terminal
VOUT terminal
Under voltage lockout
Vuvlo
2.3
2.4
2.5
V
UVLO hysteresis
Vhys
0.05
0.1
0.15
V
Switching frequency
Fsw
3.7
4.0
4.3
MHz
@4MHz mode
*1 This parameter is tested with DC measurement
*2 In mass production, measured in the setting that register ‘ASSISTCUR’=0,’ MODE’=0
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Datasheet
BD6164GUT
●Pin Descriptions
No.
Pin Name
In/Out
Functions
A1
SW
In
Switching terminal
Ground
A2
GND
-
B1
LEDOUT
Out
B2
VOUT
Out
C1
SCL
In
I2C clock signal in I2C mode
C2
SDA
In/Out
I2C data signal in I2C mode
LED current source. Connect to the anode of the Flash LED.
Boost output. Connect output bypass capacitor very close to this
pin. Vin is internally connected here.
●Block Diagram
1.0uH
VBAT
2.2uF
2x1.5uF
VOUT
SW
LEDOUT
UVLO
OVP
DC-DC
Control
SCF
2
IC
SCL
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GND
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Datasheet
BD6164GUT
●CPU I/F
The I2C I/F provides access to the Flash LED driver control registers.
● I2C BUS format
The writing/reading operation is based on the I2C slave standard.
◦ Slave address (60h/61h, including R/W bit)
A7
0
A6
1
A5
1
A4
0
A3
0
A2
0
A1
0
R/W
1/0
◦ Bit Transfer
Data is transferred when SCL=H. SCL cannot change signal of SDA during H at the time of bit transfer. If SDA changes
while SCL has been H, START conditions or STOP conditions will occur and it will be interpreted as a control signal.
SDA
SCL
data line
Stable; data valid
change of
data
allowed
Figure 1. I2C SDA/SCL basic waveform
◦ START and STOP condition
2
When SDA and SCL are both H, data is not transferred on the I C- bus. This condition indicates, if SDA changes from H to
L while SCL has been H, it will become START (S) conditions, and an access start, if SDA changes from L to H while SCL
has been H, it will become STOP (P) conditions and an access end.
SDA
SCL
S
P
START condition
STOP condition
Figure 2. I2C Start/Stop condition waveform
◦ Acknowledge
It transfers date 8 bits each after the occurrence of START condition. A transmitter opens SDA after transfer 8bits date, and
a receiver returns the acknowledge signal by setting SDA to L.
DATA OUTPUT
BY TRANSMITTER
not acknowledge
DATA OUTPUT
BY RECEIVER
acknowledge
SCL
1
2
8
9
S
clock pulse for
acknowledgement
START condition
Figure 3. I2C Acknowledge waveform
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Datasheet
BD6164GUT
◦ Writing protocol
A register address is transferred by the next 1 byte that transferred the slave address and the write-in command. The 3rd
byte writes data in the internal register written in by the 2nd byte, and after 4th byte or, the increment of register address is
carried out automatically. However, when a register address turns into the last address(07h), it is set to 00h by the next
transmission. After the transmission end, the increment of the address is carried out.
* 1
S X X X X X X X 0 A A7 A6 A5 A4 A3 A2 A1 A0 A D7 D6 D5 D4 D3 D2 D1 D0 A
slave address
register address
* 1
D7 D6 D5 D4 D3 D2 D1 D0 A P
DATA
DATA
R/W=0(write)
register address
increment
register address
increment
A=acknowledge(SDA LOW)
A=not acknowledge(SDA HIGH)
S=START condition
P=STOP condition
*1: Write Timing
from master to slave
from slave to master
Figure 4. I2C Write protocol
◦ Reading protocol
It reads from the next byte after writing a slave address and R/W bit. The register to read considers as the following
address accessed at the end, and the data of the address that carried out the increment is read after it. If an address turns
into the last address(07h), the next byte will read out 00h. After the transmission end, the increment of the address is
carried out.
S X X X X X X X
1 A D7 D6 D5 D4 D3 D2 D1 D0 A
slave address
D7 D6 D5 D4 D3 D2 D1 D0 A P
DATA
DATA
register address
increment
register address
increment
R/W=1(read)
A=acknowledge(SDA LOW)
A=not acknowledge(SDA HIGH)
S=START condition
P=STOP condition
from master to slave
from slave to master
Figure 5. I2C Read protocol
◦ Multiple reading protocols
After specifying an internal address, it reads by repeated START condition and changing the data transfer direction. The
data of the address that carried out the increment is read after it. If an address turns into the last address, the next byte will
read out 00h. After the transmission end, the increment of the address is carried out.
S X X X X X X X 0 A A7 A6 A5 A4 A3 A2 A1 A0 A Sr X X X X X X X 1 A
slave address
register address
slave address
R/W=0(write)
R/W=1(read)
D7 D6 D5 D4 D3D2 D1D0 A
DATA
D7D6 D5D4D3D2D1D0 A P
DATA
register address
increment
register address
increment
A=acknowledge(SDA LOW)
A=not acknowledge(SDA HIGH)
S=START condition
P=STOP condition
Sr=repeated START condition
from master to slave
from slave to master
Figure 6. I2C Multiple read protocol
As for reading protocol and multiple reading protocols, please do A(not acknowledge) after doing the final reading
operation. It stops with read when ending by A(acknowledge), and SDA stops in the state of Low when the reading data of
that time is 0. However, this state returns usually when SCL is moved, data is read, and A(not acknowledge)is done.
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Datasheet
BD6164GUT
● Timing diagram
SDA
tf
t LOW
t SU;DAT
t BUF
tr
tf
t HD;STA
tr
t SP
SCL
S
t HD;STA
t SU;STO
t SU;STA
t HD;DAT
S
P
Sr
t HIGH
Figure 7. I2C timing diagram
● Electrical Characteristics (Unless otherwise specified, Ta=25oC, VTH,H1=1.8V / VTH,L1=0V)
Parameter
Symbol
Spec
Min.
Typ.
Max.
Unit
SCL clock frequency
fSCL
0
-
400
kHz
Rise/fall times SDA/SCL
tf / tf
-
-
300
ns
LOW period of the SCL clock
tLOW
1.3
-
-
μs
HIGH period of the SCL clock
Hold time (repeated) START condition
Hold time for a repeated START condition
Set-up time for a repeated START condition
tHIGH
0.6
-
-
μs
tHD;STA
0.6
-
-
μs
tSU;STA
0.6
-
-
μs
Data hold time
tHD;DAT
0.1
-
0.9
μs
Data set-up time
tSU;DAT
100
-
-
ns
Set-up time for STOP condition
Bus free time between a STOP
and START condition
tSU;STO
0.6
-
-
μs
tBUF
1.3
-
-
μs
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Datasheet
BD6164GUT
●Register description
Register map
Name
Addr
R/W
Reset
INFO
00h
R
01010011b
MAN [3:0]
MODEL[3:0]
VER
01h
R
00000000b
TEST[3:0]
VERSION[3:0]
CUR
02h
R/W
10100000b
MOD
03h
R/W
00000100b
R
R
LEDON
MODE
INT
04h
R
00000000b
OVP
SCF
OTP
R
D[7:0]
FLASHCUR[1:0]
ASSISTCUR
R
R
R
R
R
TIMER[3:0]
R
R
R
R
R=reserved
Address ”00h”, Design information register
1)
Model ID number INFO[3:0]:
MODEL
0000
to
1111
Function
Model id (03h)
2) Manufacturer ID number INFO[7:4]:
MAN
0000
to
1111
Function
Manufacturer id (05h)
Address ”01h”, Version control register
1)
Version register VER[3:0]
VERSION[3:0]
0000
to
1111
Function
Version register
2) Test register VER[7:4] (reserved)
TEST[3:0]
0000
to
1111
Function
Reserved
Address ”02h”, Current setting
1)
Flash current CUR[7:6]
FLASHCUR[1:0]
Flash current
00
260mA
01
280mA
10
300mA
11
320mA
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Datasheet
BD6164GUT
2)
Assist Light Function current CUR[5]
ASSISTCUR
Assist light current
0
52mA
1
72mA
Default
*
Address ”03h”, LED driver mode setting and timer setting
1)
2)
LED setting MOD[5]
LEDON
LED
Default
0
OFF
*
1
ON
Mode setting MOD[4]
MODE
Driver state
Default
0
Assist Light
*
1
Flash
Changing MOD[5:4] from 10 to 01, will indicate both a mode change (Assistant to Flash) and a LED deactivation. Please note
that in this particular case, the mode change will trigger a flash sequence before it will deactivate the LED. To activate a Flash
or Assistant, we recommend 00 to 11 (for Flash) 00 to10 (for Assistant), and 10 to 11 (for switching Assistant to Flash).
BD6164GUT does not support switching to assistant light mode during a flash sequence.
To deactivate Flash or Assistant, we recommend to writing 00.
3)
Flash timer setting MOD[3:0] (only available in flash mode)
TIMER[3:0]
0000
tFlash
0001
60ms
30ms
0010
90ms
0011
120ms
0100
150ms
0101
180ms
0110
210ms
0111
240ms
1000
270ms
1001
300ms
1010
330ms
1011
360ms
1100
390ms
1101
420ms
1110
450ms
1111
480ms
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Datasheet
BD6164GUT
Address ”04h”, Interrupt register
1)
Over Voltage protection INT[7]
OVP
2)
Status
Default
0
OK
*
1
Fault
Short Circuit Fault INT[6]:
SCF
Status
Default
0
OK
*
1
Fault
3) Over Temperature Protection INT[5]:
OTP
Status
Default
0
OK
*
1
Fault
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BD6164GUT
●Functional Description
1.
Start up sequence
After waking up from sleep-mode, the LED current is ramped up and down in a controlled way in order to avoid massive
inrush current and proper initialization of the current regulation loop. The maximum current (320mA) should be reached
within 0.6-1.0ms. Since this process is controlled by the oscillator, the minimum no. of clock cycles (1MHz+7.5%) is 645
(worst-case).
1) Flash mode
MOD[7:0]:
Internal LED mode
2
0011 xxxxb*1
0000 0000b
ramp-up flash
Initialize
OFF
00xx xxxxb*
trampup*4
trampdown*4
16us*N
N steps
OFF
ramp-down
tFLASH
*3
tstep*N
tInd(~300us)
LED current
0mA
10.3mA
0.25V
0.25V
≈VBAT
VOUT
≈VBAT
tStp(16us)
LEDOUT
0V
0V
*1: MOD indicates the programmed flash time
*2: MOD[5:4] is reset (LED off) when timer is expired or by S/W (during LED flash, no new flash is accepted)
*3: N=programmed flash current / Istep (= ILED,max/(2K-1)=10.3mA, K=5 bits)
*4: tramp-up= tinitialize + N*Tstep. (Tstep= Trmp,max/(2K-1)=496us/31=16us, K=5 bits). tramp-down= (N+1)*Tstep
*5: In case that the system goes to transparency mode during ramp down phase, the system does not start boost up.
Figure 8. Ramp-up/down (Flash)
2) Assist Light mode
MOD[7:0]
0000 0000b*1
1
0000 0000b
0010 0000b*
ramp-up
Internal LED mode
initialize
OFF
trampup*2
assist Light
Optional
ramp-down
OFF
trampdown*2
72mA
LED current
VOUT
0mA
10.3mA
0mA
≈VBAT
≈VBAT
0.56V
VLEDOUT
52mA
0.56V
0V
0V
*1: In Assist Light mode, the LED is enabled until register ASSIST is reset by S/W or when a flash command is issued
*2: tramp-up= tinitialize + N*16us (N=4..6, 1st step=initialize), tramp-down = N*16us (N=5..7, to zero)
*3: In case that the system goes to transparency mode during ramp down phase, the system does not start boost up.
Figure 9. Ramp-up/down (Assistant light)
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BD6164GUT
2. Internal power supply
BD6164GUT has no separate supply for the internal circuitry generally known as “Vdd”. The internal circuitry of the chip is
supplied directly from the output voltage (VOUT). During battery-insertion, the VOUT node ramps up to battery voltage level
(PMOS switch is ON initially). When the main system is switched on (i.e. by H/W button), the I2C terminals are pulled-up,
which initializes the LED flash driver control core, after which it is goes into sleep mode, listening for I2C commands to be
activated. As soon as an I2C wake-up call from the main system is detected, the internal circuitry is enabled and the LED
flash driver goes into operational mode (see also item 6 on the next page).
L
SW
VOUT
LEDOUT
Initially LOW
Cont rol
Initially LOW
2
I C I/F and Digital control
GND
SDA
SCL
Any I2C ‘write command’ activates the internal blocks of the BD6164GUT, in order to be ready for LED activation. However,
if the write command is not immediately followed by a flash or assistant light command, please apply a read command to
ensure the IC is going back to low-current standby mode.
Figure 10. Internal power supply
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BD6164GUT
3. Over Temperature Protection (OTP)
BD6164GUT has an over-temperature protection function (Thermal shut down). When the die-temperature over 150
degrees, a shutdown-sequence is started:
1)
Set OTP interrupt
2)
Shutdown DCDC and LED driver.
3)
Wait for the die-temperature to drop below 130 degrees and the interrupt to be cleared by S/W (register read) before
allowing new LED activity.
4. Over Voltage Protection (OVP)
In order to prevent damage to the chip, Over Voltage Protection (OVP) detection is implemented. When the output voltage
exceeds 5.3V, a shut-down sequence is started:
1)
Set OVP interrupt
2)
Stop the switching of the DCDC and go to stand by mode and the register “LEDON” turns to ‘0’
3)
Then OVP register is written as ‘1’. This register is to be cleared by being read by S/W.
5. Short Circuit Fault detection (SCF)
After LED driver had started, BD6164GUT detects the LEDOUT voltage. If the voltage is under (1.2)V, the following actions
are taken:
1)
Set SCF interrupt
2)
Shutdown DCDC and LED driver.
3)
Wait for the SCF register to be cleared by S/W (register read) before allowing new LED activity.
6. Under-Voltage Lock Out
In this system, the under-voltage lockout function is performing a self-test by monitoring the voltage on the VOUT node
just before starting up the step-up DCDC converter. This ensures that any LED activity is blocked when the battery
voltage is too low. During boost up, the system is not able to accurately detect the battery voltage (no separate VBAT pin
on the chip), so the UVLO is disabled. In case of an under voltage situation, there is no need to set an interrupt register.
7. The DCDC mode.
The DCDC boost converter has three operational modes*1 that provide the supply voltage for the LED driver:
1)
4MHz PWM switching mode: when boost-up ratio is high enough to ensure a correct and stable current regulation
loop (VBAT 12.5%
Low boost up
No PWM switching
No boost up
Dutycyle > 12.5%
Ramp-down*VHR