BD64008MUV-E2

Datasheet System Motor Driver BD64008MUV General Description Key Specifications This is a system motor driver with integrated 2ch H-bridge driver (Parallel is for exclusive use), 2ch buck switching regulator (SWREG) with built-in Power MOS, and Reset output. ◼ ◼ ◼ ◼ ◼ ◼ Features ◼ ◼ ◼ ◼ ◼ ◼ ◼ ◼ ◼ ◼ ◼ ◼ ◼ ◼ ◼ Low ON-resistance Output H-bridge Driver (2ch) Built-in Regular Current Chopping Function Over-current Protection in H-bridge Driver 3-line Serial Type Interface H-bridge Parallel Driver (Large Mode) Single Purpose SWREG (CH1) with Built-in P-ch Power DMOS FET High Efficiency SWREG Function Soft Start Function in SWREG Over-current Protection (OCP) in SWREG Output Under Voltage Protection (UVLO) in SWREG SWREG Enable Function Thermal Shutdown Function (TSD) Power ON Reset VBB Drop Detection Function Micro Type, Ultra-thin Type, High Heat Dissipation (Back side heat radiation) Package Input Voltage Range 9.0 V to 45.0 V Motor Rated Output Current 2.0 A/Phase SWREG1 Output Current Range 0 A to 2.0 A SWREG2 Output Current Range 0 A to 1.4 A Operating Temperature Range -25 °C to +85 °C Standby Current 100 µA (Max) Package VQFN048V7070 W (Typ) x D (Typ) x H (Max) 7.0 mm x 7.0 mm x 1.0 mm Applications ◼ ◼ Business Inkjet Printers Large Format Printer, etc. Typical Application Circuit VBBA VREFA 4bit DAC (1/10) OUTAP OUTAM RNFAS RNFA RNFAS VREFB PRE DRIVER LOGIC VBBB SLEEP ENBA,ENBB CLK,STB(LD),DAT ID0,ID1,ID2 RSTIN ENBSW1 ENBSW2 PWM MODE OUTBP OUTBM internal reg. RNFB RNFBS internal reg. VBBSW1 R Q S DAC for soft start FB1 PRE DRIVER OSC SWOUT1 FB1 BOOT DAC for soft start R Q S FB2 COMP PRE DRIVER VINSW2 SWOUT2 OSC PGNDSW2 internal reg. Regulator Clock TSD OCP UVDETIN FB2 OCPDET UVDET RESET UVP GND 〇Product structure : Silicon monolithic integrated circuit www.rohm.com © 2017 ROHM Co., Ltd. All rights reserved. TSZ22111 • 14 • 001 〇This product has no designed protection against radioactive rays 1/36 TSZ02201-0P2P0B001840-1-2 16.Nov.2020 Rev.005 BD64008MUV Pin Configuration Block Diagram OUTAM PGNDSW2 RNFAS RNFA 31 30 29 28 27 26 25 VBBA OUTBP OUTAP VBBB 32 RNFBS 36 35 34 33 GND RNFB OUTBM [TOP VIEW] VREFA 2 4bit DAC (1/5or1/10) 29 VBBA 30 OUTAP 26 OUTAM 28 RNFA 27 RNFAS RNFAS VREFB VBBSW1 37 24 PGNDSW2 VBBSW1 38 23 SWOUT2 3 SLEEP 4 ENBA,ENBB to CLK,STB(LD),DAT 12 ID0,ID1,ID2 RSTIN 46 PRE DRIVER LOGIC 10 10 32 VBBB 31 OUTBP 35 OUTBM internal reg. SWOUT1 39 22 SWOUT2 SWOUT1 40 21 BOOT GND 41 20 VINSW2 FB1 42 19 VINSW2 OCPDET 43 ENBSW1 ENBSW2 PWM 13 14 33 3 internal reg. MODE 47 17 COMP RESET 45 16 GND RSTIN 46 FB1 MODE 47 COMP R Q S FB2 4 5 6 7 8 9 10 11 12 GND VREFA VREFB SLEEP ENBA ENBB CLK STB(LD) DAT ID0 ID1 3 PRE DRIVER 19 20 OSC 17 Internal reg. Regulator Clock TSD OCP VINSW2 22 23 SWOUT2 24 25 PGNDSW2 18 FB2 43 UVDETIN 48 ID2 2 SWOUT1 21 BOOT DAC for soft start 13 ENBSW1 1 VBBSW1 42 FB1 14 ENBSW2 UVDETIN 48 37 38 39 40 OSC 15 PWM EXP-PAD PRE DRIVER R Q S DAC for soft start 18 FB2 UVDET 44 RNFB 34 RNFBS 3 15 OCPDET 44 UVDET 45 RESET UVP 1 16 36 41 GND Pin Description No. Pin Name I/O 1 GND - 2 VREFA I 3 VREFB 4 SLEEP 5 6 No. Pin Name Ground 25 PGNDSW2 - SWREG2 power ground H-Bridge A output current setting 26 OUTAM O I Connect to VREFA 27 RNFAS I I Sleep mode setting 28 RNFA O H-Bridge A output (-) H-Bridge A current detection input pin H-Bridge A current detection pin ENBA I H-Bridge A enable input 29 VBBA - H-Bridge A power supply (42 V) ENBB - No function (OPEN or GND) 30 OUTAP O H-Bridge A output (+) 7 CLK I Serial CLK input 31 OUTBP O H-Bridge B output (+) 8 STB(LD) I Serial STB(LD) input 32 VBBB - H-Bridge B power supply (42 V) 9 DAT I Serial DAT input 33 RNFB O 10 ID0 I ID 0 setting 34 RNFBS I 11 ID1 I ID 1 setting 35 OUTBM O H-Bridge B current detection pin H-Bridge B current detection input pin H-Bridge B output (-) 12 ID2 I ID 2 setting 36 GND - Ground 13 ENBSW1 I SWREG1 enable input 37 VBBSW1 - SWREG1 power supply (42 V) 14 ENBSW2 I SWREG2 enable input 38 VBBSW1 - SWREG1 power supply (42 V) 15 PWM I SWREG2 PWM compulsion 39 SWOUT1 O SWREG1 output 16 GND - Ground 40 SWOUT1 O SWREG1 output 17 COMP I/O SWREG2 phase compensation 41 GND - Ground 18 FB2 I SWREG2 feedback 42 FB1 I SWREG1 feedback 19 VINSW2 - SWREG2 power supply (5 V) 43 OCPDET O OCP detection 20 VINSW2 - SWREG2 power supply (5 V) 44 UVDET O VBB drop detection 21 BOOT I SWREG2 H-side Nch booster 45 RESET O Reset out 22 SWOUT2 O SWREG2 output 46 RSTIN I Reset input 23 SWOUT2 O SWREG2 output 47 MODE I Connect to GND - SWREG2 power ground The EXP-PAD is connected to GND. 48 UVDETIN I UVDET setting - - - 24 PGNDSW2 - EXP-PAD - Function www.rohm.com © 2017 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 2/36 I/O Function - TSZ02201-0P2P0B001840-1-2 16.Nov.2020 Rev.005 BD64008MUV Absolute Maximum Ratings (Ta = 25 °C) Parameter Symbol Limit Unit VBB -0.4 to +50.0 V VMOUT -0.4 to +50.0 V VSWOUT1 -0.4 to +50.0 V VINSW2 -0.4 to +7.0 V VSWOUT2 -0.4 to +7.0 V VLI -0.4 to +5.5 V VLO 5.5 V RNF Voltage (DC) VRNF(DC) 0.55 V RNF Voltage (peak)(Note 6) VRNF(peak) 2.5 V VBB Applied Voltage(Note 1)(Note 2) Motor Output Voltage(Note 3) SWOUT1 Voltage VINSW2 Applied Voltage(Note 1) SWOUT2 Voltage Logic Input Voltage(Note 4) Logic Output Power Voltage(Note 5) Dissipation(Note 7) Pd 4.83 W Motor Output Current (DC)(Note 1) IOMAXMT(DC) 2.0 A/Phase SWOUT1 Output Current (DC)(Note 1) IOMAXSW1(DC) 2.2 A IOMAXSW1(peak) 2.4 A IOMAXSW2(DC) 1.5 A IOMAXSW2(peak) Tstg 1.65 A -55 to +150 °C Tjmax 150 °C SWOUT1 Output Current (peak)(Note 1)(Note 6) SWOUT2 Output Current (DC)(Note 1) SWOUT2 Output Current (peak)(Note 1)(Note 6) Storage Temperature Range Maximum Junction Temperature Caution 1: Operating the IC over the absolute maximum ratings may damage the IC. The damage can either be a short circuit between pins or an open circuit between pins and the internal circuitry. Therefore, it is important to consider circuit protection measures, such as adding a fuse, in case the IC is operated over the absolute maximum ratings. Caution 2: Should by any chance the maximum junction temperature rating be exceeded the rise in temperature of the chip may result in deterioration of the properties of the chip. In case of exceeding this absolute maximum rating, design a PCB with power dissipation taken into consideration by increasing board size and copper area so as not to exceed the maximum junction temperature rating. (Note 1) Must not exceed Pd and Tj = 150 °C (Note 2) Supply = VBBA, VBBB, VBBSW1 (Note 3) Motor Output = OUTAP, OUTAM, OUTBP, OUTBM (Note 4) Logic Input = SLEEP, ENBA, ENBB, CLK, STB(LD), DAT, ID0, ID1, ID2, ENBSW1, ENBSW2, PWM, RSTIN, MODE (Note 5) Logic Output = OCPDET, UVDET, RESET (Note 6) peak = 1 μs (Note 7) When mounted on a 4-layer recommended board (74.2 mm x 74.2 mm x 1.6 mm), reduce by 37.3 mW/°C when Ta ≥ 25 °C Recommended Operating Conditions Parameter Symbol Min Typ Operating Temperature Topr -25 VBB Applied Voltage(Note 8)(Note 9) VBB 9.0 CLK Max Operating Frequency fCLOCK - SWREG1 Output Voltage Setting VOUT1 3.0 SWREG2 Output Voltage Setting VOUT2 ISW1 SWREG1 Output Current(Note 10) SWREG2 Output Current(Note 10) VINSW2 Applied Voltage Max Unit - +85 °C - 45.0 V 40 - MHz - 13.0 V 0.8 - 3.6 V 0 - 2.0 A ISW2 0 - 1.4 A VINSW2 3.0 - 5.5 V (Note 8) When VBB is under POR, H-Bridge, SWREG and circuit protection are disabled. (Note 9) Supply = VBBA, VBBB, VBBSW1 (Note 10) Must not exceed Pd and Tj = 150 °C www.rohm.com © 2017 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 3/36 TSZ02201-0P2P0B001840-1-2 16.Nov.2020 Rev.005 BD64008MUV Electrical Characteristics (Unless otherwise specified VBB = 42 V, Ta = 25 °C) Parameter Symbol Specification Unit Conditions Min Typ Max IBBST - 20 100 µA SLEEP = L, ENBSW1 = H IBB - 8.5 13.0 mA SLEEP = H, ENBSW1 = L IINSW2 - 0 10 µA [Overall] VBB Current (Standby)(Note 1) VBB Current (Active)(Note 1) VINSW2 Current POR Threshold Voltage H VPORH 6 7 8 V POR Hysteresis Voltage VPORHY 0.5 1.0 1.5 V VBB Input timing Output ON-Resistance (H-side) RONH - 0.75 1.05 Ω IOUT = 1 A Output ON-Resistance (L-side) Built-in Diode Forward Voltage (H-side) Built-in Diode Forward Voltage (L-side) [Current Control] RONL - 0.45 0.75 Ω IOUT = 1 A VFH - 1.0 1.3 V IOUT = 1 A VFL - 1.0 1.3 V IOUT = 1 A VREF Voltage Range VVREF 0 - 3.7 V VREF Input Current IVREF -1 0 +1 µA RNF Input Current IRNF 5 15 30 µA VOFST(Note2) -4 0 +4 % [H-Bridge] VREF to RNFS Offset Voltage VVREF = 3.3 V VVREF = 3.3 V [Control Logic 1 (DAT, CLK, STB(LD), ENBA, ENBB, SLEEP, RSTIN, ID0, ID1, ID2)] H Level Input Voltage 1 VIN1H L Level Input Voltage 1 VIN1L IIN1 Input Current 1 2.0 V - - - - 0.8 V 15 33 50 µA Input voltage = 3.3 V [Control Logic 2 (ENBSW1, ENBSW2, PWM)] H Level Input Voltage 2 VIN2H 2.0 - - V L Level Input Voltage 2 VIN2L - - 0.8 V IIN2 -18 -9 -3 µA Input voltage = 0 V IIN3 -85 -50 -30 µA Input voltage = 0 V FB1 Threshold Voltage VFBSW1 0.99 1.00 1.01 V Output ON-Resistance RONSW1 - 0.65 0.85 Ω ISWOUT1 = 1 A FB1 Pin Current IFBSW1 -0.1 0 +0.1 µA VFB1 = 1 V VFBUVP1 0.71 0.75 0.79 V Common with RESET detection FB2 Threshold Voltage VFBSW2 0.792 0.800 0.808 V Output ON-Resistance (H-side) RONHSW2 - 0.20 0.26 Ω ISWOUT2 = 1 A Output ON-Resistance (L-side) RONLSW2 - 0.20 0.26 Ω ISWOUT2 = 1 A VFB2 = 0.8 V Input Current 2 [Control Logic 3 (MODE)] Input Current [Switching Regulator 1 Block] FB1 Low Input Voltage [Switching Regulator 2 Block] FB2 Pin Current FB2 Low Input Voltage IFBSW2 -0.1 0 +0.1 µA VFBUVP2 0.28 0.40 0.52 V [RESET, UVDET, OCPDET] Low Output Voltage VOD - - 0.2 V RESET Output Delay Time RSTIN Minimum Input Pulse Width UVDET Base Voltage tRST 40 50 60 ms tRSTIN - - 13 µs VUV 0.552 0.600 0.648 V VUVHYS - 0.05 - V UVDET Hysteresis Voltage IOUT = 1 mA Refer to P.7 1.4 (Note 1) Total current value of the VBBA, VBBB, VBBSW1 pins. (Note 2) VOFST = ((VVREF × Current_Ratio / α) – VRNFS) / (VVREF × Current_Ratio / α), α = 10 www.rohm.com © 2017 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 4/36 TSZ02201-0P2P0B001840-1-2 16.Nov.2020 Rev.005 BD64008MUV Recommended Range of External Constants Characteristics may vary due to factors such as the mounting conditions and the temperature dependence of the external parts. Be certain to evaluate these values with respect to the actual intended application. VBBA VREFA 0.01 µF 220 µF 4bit DAC (1/10) OUTAP OUTAM RNFAS RNFA RNFAS VREFB LOGIC PRE DRIVER VBBB SLEEP ENBA,ENBB CLK,STB(LD),DAT ID0,ID1,ID2 RSTIN OUTBP OUTBM C3 internal reg. C3 RNFB RNFBS ENBSW1 ENBSW2 PWM MODE internal reg. VBBSW1 R Q S DAC for soft start FB1 SWOUT1 PRE DRIVER L1 C1 R1 C2 R2 OSC FB1 BOOT DAC for soft start R Q S FB2 COMP R5 0.1 µF VINSW2 PRE DRIVER C4 SWOUT2 OSC Internal reg. PGNDSW2 L2 C5 C6 2700 pF R3 R4 Regulator Clock TSD OCP FB2 OCPDET UVDET RESET UVDETIN UVP GND Figure 1. BD64008MUV Recommended Range of External Components Circuit Diagram Parameter Symbol Recommended Values Min Typ Max Unit SWOUT1 (5 V setting) C1 220 330 470 µF SWOUT1 (3.3 V setting) C1 220 470 µF SWOUT1 C2 0 330 - 22 µF 1000 pF 40 µF OUTxx(Note 1) C3 - - VINSW2-PGNDSW2 C4 10 22 SWOUT2 C5 / C6 - 20 / 20 - µF SWOUT1 L1 33 47 68 µH SWOUT2 L2 1.5 1.8 µH FB1 (5 V setting) R1 / R2 3.3 / 0.82 33 / 8.2 2.2 - FB1 (3.3 V setting) R1 / R2 3.0 / 1.3 30 / 13 - kΩ kΩ (50 V capacity) kΩ FB2 (3.3 V setting) R3 / R4 - 75 / 24 - FB2 (1.8 V setting) R3 / R4 - 30 / 24 - kΩ FB2 (1.5 V setting) R3 / R4 1.3 / 1.5 13 / 15 - kΩ kΩ FB2 (1.125 V setting) R3 / R4 3.3 / 8.2 33 / 82 - COMP (3.3 V setting) R5 18 - kΩ 9.1 - kΩ 8.2 - kΩ COMP (1.5 V to 1.8 V setting) R5 - COMP (1.125 V setting) R5 - (Note 1) xx = AP, AM, BP, BM. www.rohm.com © 2017 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 5/36 TSZ02201-0P2P0B001840-1-2 16.Nov.2020 Rev.005 BD64008MUV Pin Processing • Condition List 1 Pin Connections when H-Bridge is Not in Use The pin processing shown in the table below is recommended. To use H-bridge in parallel, please set Ach and Bch at the same time. When H-Bridge is in use, refer to 6. ENBx(Note 1) VREFx(Note 1) RNFx(Note 1) RNFxS(Note 1) OUTxP(Note 1) OUTxM(Note 1) Ach OPEN or GND GND GND OPEN Bch OPEN or GND GND GND OPEN (Note 1) x = A, B The overcurrent protection may fail if VREFx and RNFx/RNFxS are left OPEN. (However, there is no problem even if Voltage is applied to the VREFx pin only when ENBx is Low and output is open with no serial input.) 2 Pin Connections when SWREG is Not in Use The pin processing shown in the table below is recommended. ENBSWx(Note 2) FBx(Note 2) SWOUTx(Note 2) COMP BOOT VINSW2 1ch OPEN GND OPEN - - - 2ch OPEN GND OPEN OPEN OPEN OPEN (Note 2) x = 1, 2 3 Condition of the MODE pin Please connect the MODE pin to GND by all means. 4 Active Condition of Logic Input Pins 5 Logic input pins Active condition Non-active condition (OPEN case) DAT, CLK, STB(LD), ENBA, ENBB, SLEEP, RSTIN, ID0, ID1, ID2 H (2.0 V or more) L (0.8 V or less) ENBSW1, ENBSW2, PWM L (0.8 V or less) H (2.0 V or more) Data accept mode Power save mode Condition of the SLEEP pin Logic input pins SLEEP H (2.0 V or more) L (0.8 V or less) When SLEEP = L, ENBSW1 = H and ENBSW2 = H, the condition is stand-by. The IC switches to power save mode. In this case, RESET output (P.7), Thermal shutdown (P.24), over-current (P.24) and output under voltage protection turn OFF. 6 Processing of Bch Pins To use H-Bridge in parallel, please don’t set Bch independently. Please obey the following instructions. Pins Method of processing ENBB OPEN or connect with GND VREFB OPEN or connect with VREFA RNFB Connect with RNFA RNFBS Connect with RNFAS OUTBP Connect with OUTAP OUTBM Connect with OUTAM www.rohm.com © 2017 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 6/36 TSZ02201-0P2P0B001840-1-2 16.Nov.2020 Rev.005 BD64008MUV Explanation of Block Operation BD64008MUV is composed of four blocks namely; H-Bridge Driver, SWREG1, SWREG2, and Protection Function block as shown in Figure 2. VREFA 2 29 VBBA 4bit DAC (1/5or1/10) 30 OUTAP RNFAS VREFB 26 OUTAM 3 SLEEP 4 ENBA,ENBB to CLK,STB(LD),DAT 12 ID0,ID1,ID2 RSTIN 46 ENBSW1 13 ENBSW2 14 PWM 15 MODE 47 LOGIC 28 RNFA 27 RNFAS PRE DRIVER 32 VBBB 31 OUTBP 35 OUTBM 33 RNFB 34 RNFBS H-Bridge Driver SWREG SWREG1 DAC for soft start R Q S FB1 PRE DRIVER 37 38 VBBSW1 39 40 SWOUT1 OSC 42 FB1 21 BOOT DAC for soft start R Q S FB2 PRE DRIVER OSC COMP 17 SWREG2 19 20 VINSW2 22 23 24 25 PGNDSW2 SWOUT2 Internal reg. UVDETIN 48 Regulator Clock 18 FB2 TSD OCP 43 OCPDET 44 UVDET UVP Protection Function 1 45 RESET 16 36 41 GND Figure 2. Explanation of Circuit Operation 1 Overall 1.1 Power supply (VBB) input Input power supply 300 µs or more at 0 V to VPORH (7 V (Typ)) 1.2 Control Logic Input Control logic input for DAT, CLK, STB(LD), ENBA, ENBB, SLEEP, RSTIN, ID0, ID1, ID2, ENBSW1, ENBSW2, PWM is implemented with a Schmitt trigger, with hysteresis. Design values Min Typ Max 200 mV 300 mV 400 mV 1.3 Power-On RESET Function A Power-On RESET circuit is built-in for VBB. When VBB rises to VPORH level (7.0 V (Typ)) or higher at the time of power ON, SWREG1 activates by a soft start. After soft start, the state of the serial port RESET is cleared. In addition, hysteresis is established at the time of power-down to turn all outputs OFF with VPORH-VPORHY (1.0 V (Typ)) and reset the serial ports. 1.4 Reset Timing, VBB Drop Detection Function After detecting Power-On RESET release, FB1 ≥ 0.75 V (Typ) and RSTIN = L, RESET output becomes H level after 50 ms (Typ). Meanwhile UVDET output only depends on VBB. It becomes L level with any voltage by external resistance. In addition, inputting H pulse (over 10 µs (Typ), 13 µs (Max)) into the RSTIN pin makes RESET output L level. RESET output table is shown below (Values at the table are all typical. VBB has hysteresis). VBB FB1 RSTIN RESET Output Unstable Under 7.0 V Don’t Care Don’t Care (IC internal circuit stops) Under 0.75 V H L 7.0 V or more 0.75 V or more H Under 0.75 V L L 0.75 V or more L H (50 ms after detection) www.rohm.com © 2017 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 L 7/36 TSZ02201-0P2P0B001840-1-2 16.Nov.2020 Rev.005 BD64008MUV Explanation of Block Operation – continued 2 H-Bridge Driver 2.1 Power Save Mode When the SLEEP = L, H-Bridge will cause the circuit to enter standby state, with only SWREG1 and SWREG2 active. Serial ports are reset in power save mode. SLEEP pin Mode L Power Save Mode H Normal (active) Mode Be sure driver outputs are in the OFF state when switching modes with the SLEEP pin. 2.2 ID Setting Setting the identification code of the device with the ID0, ID1 and ID2 pins. ID pin is always monitored. ID2 ID1 ID0 Identification code (D20, D19, D18) L L L Driven by Serial interface 2 L L H 1 (001) L H L 2 (010) L H H 3 (011) H L L 4 (100) H L H 5 (101) H H L 6 (110) H H H 7 (111) Don’t care Don’t care Don’t care All IC reply (000) Identification code 1, 3, 5, 7 is triggered in the falling edge of CLK only, identification code 2, 4, 6 and serial interface 2 is triggered in the rising edge of CLK only. 2.3 MODE Setting Please connect the MODE pin to GND by all means. MODE Pin state H-Bridge-A L GND DC motor (Large Mode(Note 1)) H-Bridge-B (VREF voltage splitting ratio α = 10) (Note 1) Large Mode: Connect the two H-Bridge in parallel and drive one DC motor. www.rohm.com © 2017 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 8/36 TSZ02201-0P2P0B001840-1-2 16.Nov.2020 Rev.005 BD64008MUV 2 H-Bridge Driver ― continued 2.4 Serial Interface 1 21-bit, 3-linear type serial interface (DAT, CLK, STB(LD)) is provided to set the operation and the value of current limit. DAT logic for each channel is sent to the internal shift register on the edge of CLK signal according to the identification code in the L area of STB(LD) signal. The data of the shift register appoints a device code in D20, D19, and D18. Identification codes 1, 3, 5, 7 is triggered on the falling edge of CLK, and in the case of (D20, D19, D18) = (000), identification codes 2, 4, 6 is triggered on the rising edge of CLK. According to address data of D17, D16, D15, D14, word setting write the data on an appropriate address of the internal memory of 3 x 14 bit at the rising edge of the STB(LD) signal. The input order of serial data is from D20 to D0. After SLEEP changes from L to H, serial data inputs are only valid after 10 µs. Serial port write timing is described in the figure below, and the respective minimum timing values are specified as follows: A B C D : : : : DAT Setup Time DAT Hold Time CLK High Pulse Width CLK Low Pulse Width ········ ········ ········ ········ 7.5 ns 5 ns 25 ns 25 ns STB(LD) A A B C B D CLK A LSB D0 DAT A B B MSB D20 LSB D0 CLK PD2 ND3 PD1 ND2 PD0 ND1 Ch-P shift in Ch-N shift in Ch-P shift in Ch-N shift in Ch-P shift in Ch-N shift in DAT ND0 PD20 PD1 PD0 STB(LD) Ch-N shift in Ch-P shift in Ch-N shift in Ch-P shift in Ch-P shift in Ch-N shift in Ch-P shift in Figure 3. Serial Port Write Timing of Serial Interface 1 www.rohm.com © 2017 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 9/36 TSZ02201-0P2P0B001840-1-2 16.Nov.2020 Rev.005 BD64008MUV 2 H-Bridge Driver ― continued 2.5 Serial Data Allotment (Serial Interface 1) Address Data WORD A Initial DAT D0 Watch Dog Timer LSB D1 D16 Word Select 2 D15 Word Select 1 D14 Word Select 0 Word Select 0 D17 Word Select 3 Watch Dog Timer MSB 0 1 1 1 1 WORD A D2 - - 0 0 0 0 WORD B D3 - - 0 0 0 1 WORD C D4 - - 0 0 1 0 WORD D 0 1 1 Rohm Reserved WORD E D5 - - 0 D6 - - 0 1 0 0 D7 - - 0 1 0 1 WORD F 1 1 0 WORD G 1 1 1 WORD H D8 - - 0 D9 - - 0 D10 - - D11 - - D12 - - D13 - - D14 Word Select 0 = 1 1 D15 Word Select 1 = 1 1 D16 Word Select 2 = 1 1 D17 Word Select 3 = 1 1 D18 - - D19 - - D20 - - www.rohm.com © 2017 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 Rohm Reserved denotes a special mode-setting port for inspection at shipment. If the Word Select 3, 2, 1, and 0 are set to “0,0,1,1” by mistake, it may cause malfunctions. Therefore, be careful NOT to implement this setting. 10/36 TSZ02201-0P2P0B001840-1-2 16.Nov.2020 Rev.005 BD64008MUV 2.5 Serial Data Allotment (Serial Interface 1) ― continued WORD B (H-Bridge-A Specific) Initial DAT WORD C (H-Bridge-B Specific) Initial DAT WORD D H-Bridge-A-B General Initial DAT D0 Blank Time LSB 0 Rohm Reserved - Don’t care - D1 Blank Time MSB 0 Rohm Reserved - Don’t care - D2 Off Time LSB 0 Rohm Reserved - Don’t care - D3 Off Time Bit1 0 Rohm Reserved - Don’t care - D4 Off Time Bit2 0 Rohm Reserved - Don’t care - D5 Off Time Bit3 0 Rohm Reserved - Don’t care - D6 Off Time MSB 1 Rohm Reserved - Don’t care - D7 Fast Decay Time LSB 0 Rohm Reserved - D8 Fast Decay Time Bit1 0 Rohm Reserved - D9 Fast Decay Time Bit2 0 Rohm Reserved - D10 Fast Decay Time MSB 0 Rohm Reserved - D11 Sync. Rect. Control 0 Rohm Reserved - D12 Sync. Rect. Enable 0 Rohm Reserved - D13 Don’t care - Don’t care - D14 Word Select 0 = 0 0 Word Select 0 = 1 1 Word Select 0 = 0 0 D15 Word Select 1 = 0 0 Word Select 1 = 0 0 Word Select 1 = 1 1 D16 Word Select 2 = 0 0 Word Select 2 = 0 0 Word Select 2 = 0 0 D17 Word Select 3 = 0 0 Word Select 3 = 0 0 Word Select 3 = 0 0 D18 ID Bit0 - ID Bit0 - ID Bit0 - D19 ID Bit1 - ID Bit1 - ID Bit1 - D20 ID Bit2 - ID Bit2 - ID Bit2 - Internal PWM Mode for H-Bridge-A External PWM Mode for H-Bridge-A Phase for H-Bridge-A DAC LSB for H-Bridge-A DAC Bit1 for H-Bridge-A DAC Bit2 for H-Bridge-A DAC MSB for H-Bridge-A 0 0 0 0 0 0 0 Rohm Reserved denotes a special mode-setting port for inspection at shipment. If you set it by mistake, it may cause malfunctions. Therefore, be careful NOT to implement this setting . www.rohm.com © 2017 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 11/36 TSZ02201-0P2P0B001840-1-2 16.Nov.2020 Rev.005 BD64008MUV 2.5 Serial Data Allotment (Serial Interface 1) ― continued WORD E (H-Bridge-A Specific) Initial DAT WORD F (H-Bridge-B Specific) Initial DAT D0 EN A PWM Cycle Time LSB 0 Don’t care 0 D1 EN A PWM Cycle Time Bit1 0 Don’t care 0 D2 EN A PWM Cycle Time Bit2 0 Don’t care 0 D3 EN A PWM Cycle Time Bit3 0 Don’t care 0 D4 EN A PWM Cycle Time Bit4 0 Don’t care 0 D5 EN A PWM Cycle Time Bit5 0 Don’t care 0 D6 EN A PWM Cycle Time Bit6 0 Don’t care 0 D7 EN A PWM Cycle Time Bit7 0 Don’t care 0 D8 EN A PWM Cycle Time Bit8 0 Don’t care 0 D9 EN A PWM Cycle Time Bit9 0 Don’t care 0 D10 EN A PWM Cycle Time Bit10 0 Don’t care 0 D11 EN A PWM Cycle Time Bit11 0 Don’t care 0 D12 EN A PWM Cycle Time MSB 0 Don’t care 0 D13 Don’t care - Don’t care - D14 Word Select 0 = 0 0 Word Select 0 = 1 1 D15 Word Select 1 = 0 0 Word Select 1 = 0 0 D16 Word Select 2 = 1 1 Word Select 2 = 1 1 D17 Word Select 3 = 0 0 Word Select 3 = 0 0 D18 ID Bit0 - ID Bit0 - D19 ID Bit1 - ID Bit1 - D20 ID Bit2 - ID Bit2 - WORD G (H-Bridge-A Specific) Initial DAT WORD H (H-Bridge-B Specific) Initial DAT D0 EN A PWM On Time LSB 0 Don’t care 0 D1 EN A PWM On Time Bit1 0 Don’t care 0 D2 EN A PWM On Time Bit2 0 Don’t care 0 D3 EN A PWM On Time Bit3 0 Don’t care 0 D4 EN A PWM On Time Bit4 0 Don’t care 0 D5 EN A PWM On Time Bit5 0 Don’t care 0 D6 EN A PWM On Time Bit6 0 Don’t care 0 D7 EN A PWM On Time Bit7 0 Don’t care 0 D8 EN A PWM On Time Bit8 0 Don’t care 0 D9 EN A PWM On Time Bit9 0 Don’t care 0 D10 EN A PWM On Time Bit10 0 Don’t care 0 D11 EN A PWM On Time Bit11 0 Don’t care 0 D12 EN A PWM On Time MSB 0 Don’t care 0 D13 Phase for H-Bridge-A 0 Don’t care 0 D14 Word Select 0 = 0 0 Word Select 0 = 1 1 D15 Word Select 1 = 1 1 Word Select 1 = 1 1 D16 Word Select 2 = 1 1 Word Select 2 = 1 1 D17 Word Select 3 = 0 0 Word Select 3 = 0 0 D18 ID Bit0 - ID Bit0 - D19 ID Bit1 - ID Bit1 - D20 ID Bit2 - ID Bit2 - www.rohm.com © 2017 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 12/36 TSZ02201-0P2P0B001840-1-2 16.Nov.2020 Rev.005 BD64008MUV 2 H-Bridge Driver ― continued 2.6 Serial Interface 2 16-bit, 3-line type serial interface (CLK, DAT, STB(LD)) sets the operation and the value of current limit. DAT logic for each channel is sent to the internal shift register on the rising edge of the CLK pin in the L area of the STB(LD) pin. Shift register data are written in an appropriate address of internal memory of 3 x 14 bit on the rising edge of the STB(LD) pin corresponding to the address data of D15 and D14. The input order of serial data is from D15 to D0. After SLEEP changes from L to H, serial data inputs are only valid after 10 µs. Serial port write timing is described in the figure below, and the respective minimum timing values are specified as follows: Address data A : DAT Setup Time ········ 15 ns D15 D14 Word Select B : DAT Hold Time ········ 10 ns 0 0 WORD0 C : Setup STB(LD) to CLK Rising Edge ········ 50 ns D : CLK High Pulse Width ········ 50 ns 0 1 WORD1 E : CLK Low Pulse Width ········ 50 ns 1 0 WORD2 F : Setup CLK Rising Edge to STB(LD) ········ 50 ns 1 1 Rohm Reserved G : STB(LD) Pulse Width ········ 50 ns Rohm Reserved is a special mode setting port for factory inspection, etc. Please be careful not to set it as it may cause malfunction if it is set incorrectly. STB(LD) C D E F G CLK A DAT B MSB D15 LSB D0 Figure 4. Serial Port Write Timing of Serial Interface 2 www.rohm.com © 2017 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 13/36 TSZ02201-0P2P0B001840-1-2 16.Nov.2020 Rev.005 BD64008MUV 2 H-Bridge Driver ― continued 2.7 Serial Data Allotment (Serial Interface 2) WORD0 (H-Bridge-A Specific) Initial DAT WORD1 (H-Bridge-B Specific) Initial DAT WORD2 H-Bridge-A-B General Initial DAT D0 Blank Time LSB 0 Rohm Reserved - Don’t care - D1 Blank Time MSB 0 Rohm Reserved - Don’t care - D2 Off Time LSB 0 Rohm Reserved - Don’t care - D3 Off Time Bit1 0 Rohm Reserved - Don’t care - D4 Off Time Bit2 0 Rohm Reserved - Don’t care - D5 Off Time Bit3 0 Rohm Reserved - Don’t care - D6 Off Time MSB 1 Rohm Reserved - Don’t care - D7 Fast Decay Time LSB 0 Rohm Reserved - D8 Fast Decay Time Bit1 0 Rohm Reserved - D9 Fast Decay Time Bit2 0 Rohm Reserved - D10 Fast Decay Time MSB 0 Rohm Reserved - D11 Sync. Rect. Control 0 Rohm Reserved - D12 Sync. Rect. Enable 0 Rohm Reserved - D13 Don’t care - Don’t care - D14 Word Select 0 = 0 - Word Select 0 = 1 - Word Select 0 = 0 - D15 Word Select 1 = 0 - Word Select 1 = 0 - Word Select 1 = 1 - Internal PWM Mode for H-Bridge-A External PWM Mode for H-Bridge-A Phase for H-Bridge-A DAC LSB for H-Bridge-A DAC Bit1 for H-Bridge-A DAC Bit2 for H-Bridge-A DAC MSB for H-Bridge-A 0 0 0 0 0 0 0 Rohm Reserved denotes a special mode-setting port for inspection at shipment. If you set it by mistake, it may cause malfunctions. Therefore, be careful NOT to implement this setting . www.rohm.com © 2017 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 14/36 TSZ02201-0P2P0B001840-1-2 16.Nov.2020 Rev.005 BD64008MUV 2 H-Bridge Driver ― continued 2.8 Explanation of Serial Port · H-Bridge Operation H-Bridge is in active mode when the SLEEP pin is H and in decay mode when it is L. All serial input time settings are determined by the internal clock (40 MHz (Typ) ±15 % (Ta = 25 °C)) and have the same degree of variation and temperature dependence as the clock. 2.8.1 Blank Time D0 to D1: WORD0 / WORD1 The current-limit comparator monitors the RNFxS(Note 1) pin voltage and sets the current limit. However, the RNFxS pin voltage is not detected during the switch to BLANK TIME to avoid misdetection due to noise spikes that occurs at the time of the switching. (1) PHASE switching time (2) When ENBA switches ON (L → H) (3) When output is ON at current chopping drive time, and Off Time has finished (1) PHASE switching time D1 D0 Blank Time [µs] 0 0 1.0 0 1 1.5 1 0 3.0 1 1 6.0 PHASE signal MOTOR current MASK interval BLANK TIME (2) When ENBA switches ON (L→H) (3) When output is ON at current chopping drive time, and Off Time has finished ENBA RNF voltage MOTOR current MASK interval MASK interval BLANK TIME Off Time BLANK TIME (Note 1) x = A, B Figure 5. Blank Time 2.8.2 Off Time D2 to D6: WORD0 / WORD1 Off Time is set by the following equation: 𝑡𝑂𝐹𝐹 = (1 + 𝑁) × 8 × 0.25 − 0.25 [µs] tOFF N : is the Off Time. : is set by the serial bit: 0 to 31. For example, if N = 0, the Off Time setting is as follows: 𝑡𝑂𝐹𝐹 = (1 + 0) × 8 × 0.25 − 0.25 = 1.75 [µs] 2.8.3 Fast Decay Time D7 to D10: WORD0 / WORD1 Fast Decay Time is set by the following equation: 𝑡𝐹𝐷 = (1 + 𝑁) × 8 × 0.25 − 0.25 [µs] tFD N : is the Fast Decay Time. : is set by the serial bit: 0 to 15. For example, if N = 0, the Fast Decay Time setting is as follows: 𝑡𝐹𝐷 = (1 + 0) × 8 × 0.25 − 0.25 = 1.75 [µs] www.rohm.com © 2017 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 15/36 TSZ02201-0P2P0B001840-1-2 16.Nov.2020 Rev.005 BD64008MUV 2.8 Explanation of Serial Port · H-Bridge Operation ― continued 2.8.4 Sync. Rect. Control D11: WORD0 / WORD1 At Fast Decay Mode Synchronous rectification, make settings related to reverse energization of the motor current. D11 Sync. Rect. Cont. Function 0 ACTIVE Detects motor current at 0 A, switches synchronous rectification OFF and prevents reverse energization. 1 PASSIVE Permits reverse energization; switches synchronous rectification OFF when current reaches the ITRIP. 𝐼𝑇𝑅𝐼𝑃 = 𝑉𝑅𝐸𝐹 × 𝐷𝐴𝐶𝑣𝑎𝑙𝑢𝑒(𝐶𝑢𝑟𝑟𝑒𝑛𝑡_𝑅𝑎𝑡𝑖𝑜)⁄(𝛼 × 𝑅𝑠𝑒𝑛𝑠𝑒) ITRIP VREF α Rsense DACvalue(Current_Ratio) : : : : : [A] is the motor current limit, established by the formula above. Is the output current value setting voltage. is the VREF voltage division ratio (α = 10). is the Current detection resistance value. is refer to table below. 2.8.5 DAC value (Current_Ratio) D3 to D6 / D10 to D13: WORD2 MSB D6 / D13 Bit2 D5 / D12 Bit1 D4 / D11 LSB D3 / D10 Current_Ratio [%] 1 1 1 1 100.00 1 1 1 0 98.08 1 1 0 1 95.69 1 1 0 0 92.39 1 0 1 1 88.19 1 0 1 0 83.15 1 0 0 1 77.30 1 0 0 0 70.71 0 1 1 1 63.44 0 1 1 0 55.56 0 1 0 1 47.14 0 1 0 0 38.27 0 0 1 1 29.03 0 0 1 0 19.51 0 0 0 1 9.80 0 0 0 0 Disable 2.8.6 Sync. Rect. Enable D12: WORD0 / WORD1 In current decay mode, D12 value enables or disables synchronous rectification. D12 Sync. Rect. En. Function No synchronous 0 Disabled rectification Synchronous 1 Enabled rectification implemented www.rohm.com © 2017 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 16/36 TSZ02201-0P2P0B001840-1-2 16.Nov.2020 Rev.005 BD64008MUV 2.8 Explanation of Serial Port · H-Bridge Operation ― continued 2.8.7 Internal PWM Mode D0 / D7: WORD2 In current decay mode, this data sets the motor current regeneration method. Mixed Decay setting: During Off Time, the Fast Decay Time is set for Fast regeneration mode. For the rest of the time, it is set to Slow regeneration. In this scheme, if Fast Decay Time is longer than Off Time, Fast regeneration becomes the only operative mode. When Sync. Rect. Control = Active and 0 A is detected in Fast regeneration mode, the regeneration mode will switch to Slow, once all outputs are OFF and the Fast Decay Time period has finished. D0 / D7 Mode 0 Mixed 1 Slow 2.8.8 External PWM Mode D1 / D8: WORD2 Sets the motor current regeneration mode when ENBA = L. Motor current regeneration is triggered by the falling edge of the ENBA pin logic. Therefore, this mode is not synchronized with the clock. D1 / D8 Mode 0 Fast 1 Slow 2.8.9 Phase D2 / D9: WORD2 Sets the motor drive rotational direction. D2 / D9 Direction OUT(A-B)P 0 Reverse L OUT(A-B)M H 1 Forward H L There is a Phase bit in WORD D, WORD G, WORD H, and last updated WORD is reflected. For example, when Phase D2: WORD D ”0”, Phase D13: WORD G ”0”, Phase D13: WORD G ”1”, Phase setting is forward detection. And when Phase D2: WORD D ”0”, Phase D13: WORD H ”0”, Phase D2: WORD D ”1”, Phase setting is forward detection. 2.8.10 PWM Cycle Time D0 to D12: WORD E / WORD F PWM Cycle Time setting. PWM Cycle Time is accomplished using the equation: 𝑡𝑃𝑊𝑀 = 𝑁 × 25𝑛 tPWM N : : [s] is the PWM Cycle Time. is set by the serial bit: 0 to 8191. For example, when N = 4000, 𝑡𝑃𝑊𝑀 = 4000 × 25𝑛 = 100 [µs] When N = 0 is set, external enable becomes active. On the other hand, internal PWM becomes active when N > 0 is set. www.rohm.com © 2017 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 17/36 TSZ02201-0P2P0B001840-1-2 16.Nov.2020 Rev.005 BD64008MUV 2.8 Explanation of Serial Port · H-Bridge Operation ― continued 2.8.11 PWM ON Time D0 to D12: WORD G / WORD H PWM ON Time setting. PWM ON Time is accomplished using the equation: 𝑡𝑂𝑁 = 𝑁 × 25𝑛 tON N : : [s] is the PWM ON Time. is set by the serial bit: 0 to 8191. For example, when N = 1000, 𝑡𝑂𝑁 = 1000 × 25𝑛 = 25 [µs] (The frequency of the internal clock becomes 30 MHz (Min) or more) A B Figure 6. Relationship Diagram of PWM Cycle Time and PWM ON Time A: PWM Cycle Time B: PWM ON Time Section B is ON section. The end of section A is OFF section from the end of section B (Slow Decay or Fast Decay). Example) PWM ON Time: when N = 1000, 1000 x 25 ns = 25 µs PWM Cycle Time: when N = 4000, 4000 x 25 ns = 100 µs Therefore, PWM period is 100 µs (section A), ON Time is 25 µs (section B), OFF Time is 75 µs (section B to section A). 2.8.12 Watch Dog Timer D0 / D1: WORD A A counter improves when setting value to a start register. When setting the time, this IC turn OFF motor output. The A side and the B side can be set individually. (Usage example) 1. Set the A side time at 180 s 2. Initiate the A side start register and start timer count. 3. A side motor drives. 4. When the motor stops, it clears the start register and the timer count is reset. In case step 4 did not function in the sequence mentioned above and the start register is not cleared (with a field anomaly relaxation method overrun and a bug) for more than 180 s, turn OFF motor driver output. In addition, if you set it to 180 s again within 180 s after setting it to 180 s, the count is restarted from there. Time (s) D1 D0 Min Typ Max 0 0 Infinity (default) Infinity (default) Infinity (default) 0 1 50 60 70 1 0 150 180 210 1 1 250 300 350 www.rohm.com © 2017 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 18/36 TSZ02201-0P2P0B001840-1-2 16.Nov.2020 Rev.005 BD64008MUV 2 H-Bridge Driver ― continued 2.9 Current Decay Mode For the PWM constant current drive of this series, the current decay modes (FAST DECAY / SLOW DECAY) can be set. The state of output transistor and the route of motor’s regenerative current during current decay for each decay mode are as follows. FAST DECAY SLOW DECAY OFF→OFF ON→OFF M M ON→OFF OFF→ON OFF→OFF ON→OFF OFF→ON ON→ON When output ON When Current Decay Figure 7. Route of Regenerated Current during Current Decay The merits of each decay mode are as follows: 2.9.1 SLOW DECAY When the current decay, the voltage between motor coils is small and the regenerative current decreases slowly. Current ripple also decreases, which improves motor torque. At the same time, the output current increases due to the deterioration of current control characteristic in the small current region; it is also easily affected by motor's BEMF at the time of high pulse rate drive. Therefore, change of current limit value cannot be followed, current waveform distorts and motor vibration increases. It is most suitable to FULL STEP and low pulse rate drive. 2.9.2 FAST DECAY Because of sudden decrease of regenerative current, distortion of current waveform related to high pulse rate drive can be reduced. However, because the output current’s ripple gets larger, the average current decreases, so (1) motor torque decreases (increasing the current limit value can cope with the problem, but it is necessary to take the rated output current into consideration), (2) motor’s loss gets larger causing heat radiation to also increase. If there are no problems of (1) and (2), it is most suitable to the modes that are of high pulse rate drive. There is the Mixed Decay mode that can improve the problem related to Slow Decay mode and Fast Decay mode. Due to switching between Fast Decay and Slow Decay, the current control characteristic can be improved without making the current ripple larger during current decay. This IC can change the time ratio of Slow Decay and Fast Decay during Mixed Decay, so the optimal control state for every motor can be achieved. During Mixed Decay, the first half X % (between t1 and t2) of the discharge interval in the chopping cycle is Fast Decay time, and the remaining interval is Slow Decay time (between t2 and t3). t1 t2 t3 1 cycle Output current Current setting value SLOW DECAY 0A 　FAST DECAY Motor output current (DC): to 2.0 A/Phase Motor output current (peak): to 6.0 A/Phase Figure 8. Mixed Decay Diagram www.rohm.com © 2017 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 19/36 TSZ02201-0P2P0B001840-1-2 16.Nov.2020 Rev.005 BD64008MUV Explanation of Block Operation – continued 3 SWREG VBBSW1 Current Detection Soft Start DAC gmAMP R VBIAS Q L Pre Driver VOUT SWOUT1 S C1 R1 OSC FB1 R2 Figure 9. SWREG1 Block Diagram (SWREG2: Synchronous and VBBSW → VINSW2) 3.1 Basic Operation This IC incorporates 2ch of switching regulator circuit that repeats ON/OFF, synchronized with an internal clock (SWCLK), 1ch SWREG operates by 250 kHz (Typ) ±15 % and 2ch SWREG operates by 1 MHz (Typ) ±20 %. Startup output voltage SWOUT1 begins switching and the V OUT1 slowly ramps up with a soft start at VBB power-on (VBB > VPORH) and ENBSW1 = L. And startup output voltage SWOUT2 begins switching at the time of a soft start, while the VOUT2 slowly ramps up at VBB power-on (VBB > VPORH) and ENBSW2 = L. When ENBSW1 = H and ENBSW2 = H, the IC doesn’t work. Input power supply 300 µs or more at 0 V to VPORH (7 V (Typ)) Output voltage is determined with external resistance by using the following equation: 𝑉𝑂𝑈𝑇 = 𝑉𝐵𝐼𝐴𝑆 × {(𝑅1 + 𝑅2 )⁄𝑅2 } VOUT VBIAS R1, R2 [V] is the output voltage. is the FB1 voltage. is the external resistance. Note that the external LC filter constant should be set to optimize output ripple voltage (V RIP). This is accomplished using the equation below: 𝑉𝑅𝐼𝑃 = 𝐼𝑅𝐼𝑃 × {(𝐸𝑆𝑅 + 1)⁄𝑓𝑆𝑊 ⁄𝐶𝑂𝑈𝑇 /8} VRIP IRIP ESR fSW COUT : : : : : [V] is the output ripple voltage. is the output ripple current. is the equivalent series resistance. is the switching frequency. is the output capacitance. 𝐼𝑅𝐼𝑃 = 𝑉𝑂𝑈𝑇 ⁄𝐿 × 𝑉𝐵𝐵𝑆𝑊 − 𝑉𝑂𝑈𝑇 ⁄𝑉𝐵𝐵𝑆𝑊 × 1⁄𝑓𝑆𝑊 L VBBSW : : [A] is the inductance. is the applied voltage. 3.2 Skip Mode Operation In certain run modes, such as when output load is low, gmAMP output (COMP) voltage exceeds the current detection level at the SWCLK rising edge. In this case, output will not switch ON. 3.3 MAX DUTY In certain run modes, such as when output load is high, if the COMP voltage level does not reach the current detection level, output MAX DUTY (90 %) will force the output OFF. www.rohm.com © 2017 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 20/36 TSZ02201-0P2P0B001840-1-2 16.Nov.2020 Rev.005 BD64008MUV 3 SWREG ― continued 3.4 Operation Timing Operation timing under light, normal and heavy loads are respectively described in the charts below. Normal operation SWCLK (MAX DUTY) Current detection COMP SWOUT VOUT Light operation SWCLK (MAX DUTY) COMP Current detection SWOUT VOUT Heavy operation SWCLK (MAX DUTY) Current detection COMP SWOUT VOUT Figure 10. Operation Timing of Light Loads, Normal Loads and Heavy Loads www.rohm.com © 2017 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 21/36 TSZ02201-0P2P0B001840-1-2 16.Nov.2020 Rev.005 BD64008MUV 3 SWREG ― continued 3.5 SWREG1 Soft Start (at power-on, with ENBSW1 = L) At the time of power-on, VOUT1 ramps up slowly with a soft start The rising edge of SWREG1 is synchronized with the timing when ENBSW1 = L and POR release. VUVHYS (depends on the external resistor) VUV (depends on the external resistor) VBB VPORH (7.0 V Typ) VPORL (6.0 V Typ) (VPORH-VPORHY) 3.9 kHz CLOCK (Generated by dividing the internal standard clock) Oscillation POR signal ENBSW1 0V 012 Counter output 32 63 Duty Increase SWOUT1 DAC1 output Constant ON Duty ON Duty = VOUT/VBB 2.0 V 1.0 V 0V VOUT1 x 75 % VOUT1 0V t1 = 8.2 ms (Typ) t2 = 16.4 ms (Typ) 50 ms (Typ) RESET output UVDET output Figure 11. SWREG1 Soft Start Operation Timing Diagram This soft start method is realized by linearly changing the negative side voltage of the gmAMP by using DAC. Soft start time t1 is constant, regardless of VBB. Parameter Specification Min Typ Max Unit Soft start time (t1) 6.97 8.20 9.43 ms Count finish time (t2) 13.94 16.40 18.86 ms www.rohm.com © 2017 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 22/36 TSZ02201-0P2P0B001840-1-2 16.Nov.2020 Rev.005 BD64008MUV 3 SWREG ― continued 3.6 SWREG2 Operation SWREG2 is a synchronous rectifying step-down switching regulator that achieves faster transient response by employing current mode PWM control system. It utilizes switching operation in PWM (Pulse Width Modulation) mode for heavier load, while it utilizes SLLMTM (Simple Light Load Mode) control for lighter load to improve efficiency. Efficiency η[%] (1) SLLMTM Control (2) PWM Control Output Current IOUT [A] Figure 12. Efficiency (SLLMTM Control and PWM Control) 3.6.1 Basic Function SWREG2 works forcibly with fixed frequency PWM mode when the PWM pin is H. SLLMTM control is enabled, SLLMTM control and fixed frequency PWM mode becomes active automatically when the PWM pin is L. When the logic of the PWM pin is switched during SWREG2 operation, the output voltage may decrease. Fix the logic of the PWM pin to H (2.0 V or more) or L (0.8 V or less) before the SWREG2 start (Note 1), and do not change during operation. (Note 1) Before start means the ENBSW2 = H state or before UVLO release of SWREG2. 3.6.2 Enable Control The SWREG2 shutdown can be controlled by the voltage applied to the ENBSW2 Pin. When ENBSW2 = L, the internal circuit is activated and the SWREG2 starts up. To shutdown control with the ENBSW2 Pin, the shutdown interval (H level interval of ENSW2) must be set to 100 µs or longer. 3.7 Reference efficiency (It does not do the all quantity measurement.) Efficiency Unit Channel Conditions (Typ) VBBSW1 = 12 V, VOUT1 = 5.0 V, IOUT1 87 % 50 mA SWREG1 VBBSW1 = 12 V, VOUT1 = 3.3 V, IOUT1 85 % 50 mA VINSW2 = 3.3 V, VOUT2 = 1.1 V, IOUT2 88 % 50 mA SWREG2 VINSW2 = 3.3 V, VOUT2 = 1.5 V, IOUT2 86 % 50 mA www.rohm.com © 2017 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 23/36 Notes = = = = DS126C2 B953AS-680M(TOKO) RB050L-60TE25(ROHM) DS126C2 B953AS-680M(TOKO) RB050L-60TE25(ROHM) NRS6045T1R8NMGK (TAIYO YUDEN) NRS5040T1R5NMGJ (TAIYO YUDEN) TSZ02201-0P2P0B001840-1-2 16.Nov.2020 Rev.005 BD64008MUV Explanation of Block Operation – continued 4 Protection Functions 4.1 Protection Circuits Overall Overheating protection H-Bridge drive circuit Over-current protection Over-current protection, output low voltage protection SWREG circuit 4.1.1 Overheating protection Turns OFF all output functions in response to junction temperature rise. Output is restored when the system powers on again. Thermal shutdown Hysteresis Restart temperature 175 °C (Typ) None 4.1.2 Over-current protection (H-Bridge) Detects current flowing to H-Bridge output, turns OFF all H-Bridge outputs at the end of Mask time. Output is restored at the SLEEP pin = H→L→H Set current Mask time Restart 3.5 A (Typ) 3 µs (Typ) SLEEP 4.1.3 Over-current protection (H-Bridge) detect function The OCPDET output detects that the over-current protection of the H-Bridge has worked and becomes L level at the timing of turnning OFF all H-Bridge outputs. 4.1.4 Over-current protection (SWREG1) Detects current flowing to SWREG1 output. After Mask time, SWREG1 is turned OFF between 256 µs to 512 µs (Typ) at the timing of detection. When protection operation is complete, normal operation resumes. Channel Set current Mask time Restart SWREG1 5.0 A (Typ) 0.15 µs (Typ) - 4.1.5 Over-current protection (SWREG2) It becomes activated by confining current flowing through the upper part MOSFET of SWREG2 to every 1 cycle of the switching frequency. Channel Set current SWREG2 5.0 A (Typ) 4.1.6 Output low voltage protection (SWREG1) Monitors the FB1 pin voltage of the SWREG1 circuit. If the FB1 pin voltage is less than 0.75 V (Typ) only SWREG1 is turned OFF after mask time. Output is restored at the ENBSW1 pin = L → H → L Set voltage Mask time Restart < 0.75 V (Typ) 10 µs (Typ) ENBSW1 Note that output under-voltage protection does not work until the soft start count is complete (16.4 ms (Typ)). 4.1.7 Output low voltage protection (SWREG2) Monitors the FB2 pin voltage of the SWREG2 circuit. It activates when the FB2 pin voltage is less than 0.4 V (Typ). SWREG2 is turned OFF when the state continues for 1 ms (Typ). Output under-voltage Set voltage Mask time protection operation < 0.4 V (Typ) 1 ms (Typ) ON > 0.4 V (Typ) www.rohm.com © 2017 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 OFF - 24/36 Restart ENBSW2 reboot - TSZ02201-0P2P0B001840-1-2 16.Nov.2020 Rev.005 BD64008MUV 4 Protection Functions ― continued 4.2 Over-current protection circuit operation current Design value Function Block H-Bridge SWREG1 SWREG2 Operation current Mask time Operation current Operation current Min Typ Max 2.5 A 3.5 A 4.5 A 2.4 µs 3 µs 3.6 µs 2.3 A 5.0 A 6.9 A 2.05 A 5.00 A 6.90 A The over-current protection circuit’s only aim is to prevent the destruction of the IC from irregular situations such as motor output shorts, and is not meant to be used as protection or surety for the set. Therefore, sets should not be designed to take into account this circuit’s functions. After the OCP activates, if the return by power reactivation or the reset by the SLEEP pin in an abnormal state, the OCP operation may be repeated in the order of latch → recovery → latch, which may cause heat generation or deterioration of the IC. Please note that. If the L value of the wiring is large, such as the wiring is long when the motor outputs are shorted VCC or GND or other outputs, the output pin voltage jumps after an overcurrent flows, and if it exceeds the absolute maximum rating, it may be destroyed. Also, when current which is over the output current rating and under the OCP detection current flows, the IC may heat up to over Tjmax = 150 °C and can deteriorate, so current which exceeds the output rating should not be applied. This value is design level and is not the guaranteed value that is measured by total inspection. 4.3 Timing of output low voltage protection (SWREG1) When the switching regulator output current is large enough to reach a detection threshold 5.0 A (Typ), the output is shut OFF for a period of 256 µs to 512 µs (Typ). Then, output is restored to the normal ON state by the timing of the next ON switching cycle. Repeated large current outflows will cause this operation to implement continuously, which in turn will gradually lower the output voltage. Consequently, when it detects that the voltage at the FB pin (output voltage feedback pin) has fallen below 0.75 V (Typ), it latches the output OFF after a mask time of 10 µs (Typ). At this time, all outputs except the switching regulator are turned off at the same time. SWOUT1 Limit value (5.0 A (Typ)) I_SWOUT1 FB1: 1.0 V (Typ) ±0.5 % (0 °C ≤ Tj ≤ 125 °C) FB1 FB1 undervoltage Protection value (0.75 V (Typ)) OFF period at over-current limit (256 µs to 512 µs (Typ)) Mask time (10 µs (Typ)) Figure 13. Timing of SWREG1 Protection Operation Diagram FB1 under-voltage protection will not operate during the soft start period (t 2), If abnormal FB1 voltage is produced during a soft start, the IC will not shut OFF until the soft start is complete. www.rohm.com © 2017 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 25/36 TSZ02201-0P2P0B001840-1-2 16.Nov.2020 Rev.005 BD64008MUV 4 Protection Functions ― continued 4.4 Soft Start (at power-on, with ENBSW2 = L) At the time of power-on, VOUT2 ramps up slowly with a soft start. The rising edge of SWREG2 is synchronized with the timing when ENBSW2 = L and POR release of VBB. 4.5 Operation Timing of malfunction protection circuit at output low voltage protection (SWREG2) This IC has a built-in malfunction protection circuit at low voltage (Under Voltage Lock Out: UVLO circuit) to prevent false operation such as the output during power supply under voltage. When the applied voltage to the VINSW2 pin goes under 2.45 V (Typ), the output is set to OFF state. This switching voltage has a 0.2 V (Typ) hysteresis to prevent false operation by noise etc. This value is design level and is not the guaranteed value that is measured by total inspection. UVLO OFF VINSW2 2.65 V HYS UVLO ON 2.45 V 0V ENBSW2 0V Soft Start t3 VOUT2 FB2: 0.8 V (Typ) ±0.5 % (0 °C ≤ Tj ≤ 125 °C) High-side MOSFET Gate Low-side MOSFET Gate Normal operation UVLO Normal operation Figure 14. SWREG2 Protection Operate Timing and Soft Start Timing Parameter Soft Start Time (t3) www.rohm.com © 2017 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 Specification Min Typ Max 0.8 1.0 1.2 26/36 Unit ms TSZ02201-0P2P0B001840-1-2 16.Nov.2020 Rev.005 BD64008MUV Precautions of Board Layout Consider the following key points when designing board layout: 1 Key points and precautions concerning the H-Bridge 1.1 VBBA, VBBB / H-Bridge Power supply Pin Motor’s drive current is flowing in it, so the wire is thick and short and has low impedance. VBBx(Note 1) may have big fluctuations due to motor back EMF, PWM switching noise, etc., so you must arrange the bypass capacitor of about over 220 μF as close to the pin as possible and adjust V BBx is stable. Increase the capacitance if needed, especially when a large current is used or motors that have great back electromotive force are used. In addition, for the purpose of reducing the power supply’s impedance in wide frequency bandwidth, parallel connection of multi-layered ceramic capacitor of 0.01 µF to 0.1 μF etc. is recommended. Extreme care must be used to make sure that VBBx does not exceed the rating even for a moment. VBBA and VBBB are shorted inside IC, so be sure to short externally VBBA and VBBB when using. If used without shorting, malfunction or destruction may occur because of concentration of current routes etc. Moreover, in the power supply pin, there is a built-in clamp component for preventing of electrostatic destruction. If steep pulse or voltage of surge exceeding the maximum absolute rating is applied, this clamp component operates. As a result, there is danger of destruction, so make sure that the maximum absolute rating is not exceeded. It is effective to mount a Zener diode about the maximum absolute rating. Also, a diode for preventing electrostatic destruction is inserted between the VBBx pin and GND pin, as a result there is the danger of IC destruction if reverse voltage is applied between the VBBx pin and GND pin, so be careful. (Note 1) x = A, B 1.2 OUTAP, OUTAM, OUTBP, OUTBM / H-Bridge output Pin Motor’s drive current is flowing in it, so the wire is thick and short and has low impedance. It is also effective to add a Schottky diode if output has big positive or negative fluctuations when large current is used, etc., for example, if counter electromotive voltage, etc. is big. Moreover, in the output pin, there is a built-in clamp component for preventing electrostatic destruction. If a steep pulse or voltage surge exceeding the maximum absolute rating is applied, this clamp component operates, but there is still the danger of destruction, so make sure that the maximum absolute rating is not exceeded. 1.3 RNFA, RNFB / H-Bridge Connection Pin of resistor for detecting of output current Connect the resistor for current detection between this pin and GND. In view of the power consumption of the current-detecting resistor, determine the resistor that W = IOUT2 x R [W] does not exceed the power dissipation of the resistor. In addition, wire has low impedance and does not have impedance in common with other GND patterns because motor’s drive current flows in the pattern through the RNFx (Note 2) pin to current-detecting resistor to GND. Do not exceed the rating because there is the possibility of circuit malfunction, etc. if the RNFx voltage has exceeded the maximum rating (0.55 V). Moreover, be careful because if the RNFx pin is shorted to GND, large current flows without normal PWM constant current control, then there is the danger that OCP or TSD will operate. If the RNFx pin is open, there is the possibility of such malfunction as output current does not flow either, so do not leave it open. (Note 2) x = A, B 2 Key points and precautions concerning the switching regulator 2.1 VBBSW1, SWOUT1 / SWREG1 power supply pins, SWREG1 output SWOUT1 is a high-voltage line and a possible source of switching noise. For that reason, the thickest, shortest, lowest-impedance wire possible should be used in the pattern design. Meanwhile, to reduce the switching current noise, the following loop should be kept as short as possible: bypass capacitor → VBBSW1 → SWOUT1 → Schottky diode → GND. To lessen the impact of coupling capacitance noise, position the FB1 feedback resistor away from the SWOUT1 pattern and components. 2.2 VINSW2, SWOUT2 / SWREG2 power supply pins, SWREG2 output SWOUT2 is a high-voltage line and a possible source of switching noise. For that reason, the thickest, shortest, lowest-impedance wire possible should be used in the pattern design. Meanwhile, to reduce the switching current noise, the following loop should be kept as short as possible: bypass capacitor → VINSW2 → SWOUT2 → GND. To lessen the impact of coupling capacitance noise, position the FB2 feedback resistor away from the SWOUT2 pattern and components. 3 Other key points and precautions 3.1 GND, PGNDSW / Ground Pin In order to reduce noise caused by the switching current and to stabilize the internal reference voltage of the IC, keep the wiring impedance from this pin as low as possible. The design should enable the lowest electrical potential in any operating state. In addition, be sure this wiring does not share common impedance with other GND patterns. www.rohm.com © 2017 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 27/36 TSZ02201-0P2P0B001840-1-2 16.Nov.2020 Rev.005 BD64008MUV Reference Data 40.0 10.0 4 VBB (down) 9.0 8.0 30.0 3 IBBST[µA] IBB[mA] 6.0 5.0 4.0 3.0 POR[V] 7.0 20.0 10.0 2 VBB (up) 1 2.0 1.0 0.0 0.0 0 10 20 30 40 0 0 50 Supply voltage :VBB[V] 10 20 30 40 50 5 Figure 15. VBB Current1 (Ta = 25 °C) (SLEEP = H: Active Mode) 7 8 Supply voltage :VBB[V] Figure 17. POR Threshold Voltage (Ta = 25 °C) Figure 16. VBB Current2 (Ta = 25 °C) (SLEEP = L: Sleep Mode) 2.0 2.0 1.2 1.5 1.5 VOH[V] 0.8 VOL[V] VOH[V] 6 Supply voltage :VBB[V] 1.0 1.0 0.4 0.5 0.5 0.0 0 500 1000 1500 0.0 0.0 2000 0 Supply current :Io[mA] 500 1000 1500 0 2000 Figure 19. OUTA Output Voltage L (sink side, Ta = 25 °C) 1.2 0.9 0.8 0.6 2000 100 Efficiency[%] VSW [V] VOL[V] 1500 Figure 20. OUTB Output Voltage H (source side, Ta = 25 °C) 90 0.4 1000 Supply current :Io[mA] Supply current :Io[mA] Figure 18. OUTA Output Voltage H (source side, Ta = 25 °C) 500 0.3 VBBSW1 = 12 V VBBSW1 = 44.1 V 80 70 60 0.0 0 500 1000 1500 50 0.0 2000 0 Supply current :Io[mA] 500 0 1000 Supply current :Io[mA] Figure 21. OUTB Output Voltage L (sink side, Ta = 25 °C) Figure 22. SWREG1 Output Voltage H (Ta = 25 °C) 100 500 1000 1500 2000 Output current :Io[mA] Figure 23. SWREG1 Efficiency-1 (5.0 V setting, Ta = 25 °C) 100 100 VBBSW1 = 12 V 90 90 VBBSW1 = 12 V 90 80 VBBSW1 = 44.1 V 70 60 Efficiency[%] Efficiency[%] Efficiency[%] VBBSW1 = 12 V 80 VBBSW1 = 44.1 V 70 60 50 50 100 150 200 Output current :Io[mA] Figure 24. SWREG1 Efficiency-2 (5.0 V setting, Ta = 25 °C) www.rohm.com © 2017 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 70 VBBSW1 = 44.1 V 60 50 0 VBBSW1 = 12 V 80 50 0 500 1000 1500 2000 Output current :Io[mA] Figure 25. SWREG1 Efficiency-1 (3.3 V setting, Ta = 25 °C) 28/36 0 50 100 150 200 Output current :Io[mA] Figure 26. SWREG1 Efficiency-2 (3.3 V setting, Ta = 25 °C) TSZ02201-0P2P0B001840-1-2 16.Nov.2020 Rev.005 BD64008MUV Reference Data - continued 100 100 VIMSW2 = 3.0 V 90 80 70 VIMSW2 2=5.5V = 5.5 V VIMSW VIMSW 2=5.5V 80 70 60 60 0 100 200 300 400 80 70 50 0 500 VIMSW2 =2=5.5V 5.5 V VIMSW 60 50 50 VIMSW2 = 3.0 V 90 Efficiency[%] VIMSW2 = 5.5 V Efficiency[%] Efficiency[%] 90 100 VVIMSW2=3.0V IMSW2 = 3.0 V 50 100 150 200 0 Output current :Io[mA] Output current :Io[mA] Figure 27. SWREG2 Efficiency SLLM-1 (1.5 V setting, Ta = 25 °C) VINSW2 = 3.0 V VINSW2 = 3.0 V 70 VINSW2 = 5.5 V 60 90 80 VINSW2 = 5.5 V 70 60 50 50 100 150 200 VINSW2 = 5.5 V 70 50 0 Output current :Io[mA] 100 200 300 400 500 Output current :Io[mA] Figure 30. SWREG2 Efficiency PWM-2 (1.5 V setting, Ta = 25 °C) 80 60 50 0 0 50 100 150 200 Output current :Io[mA] Figure 31. SWREG2 Efficiency SLLM-1 (1.125 V setting, Ta = 25 °C) Figure 32. SWREG2 Efficiency SLLM-2 (1.125 V setting, Ta = 25 °C) 100 100 VIMSW2 = 3.0 V 80 VIMSW2 = 3.0 V 90 Efficiency[%] 90 Efficiency[%] Efficiency[%] Efficiency[%] Efficiency[%] 80 1000 100 90 VINSW2 = 3.0 V 750 Figure 29. SWREG2 Efficiency PWM-1 (1.5 V setting, Ta = 25°C) 100 90 500 Output current :Io[mA] Figure 28. SWREG2 Efficiency SLLM-2 (1.5 V setting, Ta = 25 °C) 100 250 VIMSW2 = 5.5 V 70 VIMSW2 = 5.5 V 80 70 60 60 50 50 0 250 500 750 1000 Output current :Io[mA] Figure 33. SWREG2 Efficiency PWM1 (1.125 V setting, Ta = 25 °C) 0 50 100 150 200 Output current :Io[mA] Figure 34. SWREG2 Efficiency PWM2 (1.125 V setting, Ta = 25 °C) SWREG1: RCH110BENP-470(SUMIDA), EC30QSA065(Nihon inter) SWREG2: NRS5024T1R5NMGJ(TAIYO YUDEN) www.rohm.com © 2017 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 29/36 TSZ02201-0P2P0B001840-1-2 16.Nov.2020 Rev.005 BD64008MUV Power Dissipation VQFN048V7070 is designed with a heat sink metal on the backside of IC to perform heat dissipation treatment using through hole from backside. Before use, be sure to connect to the GND plane on the board with solder and make the GND pattern as wide as possible to secure a sufficient heat dissipation area. Note that the power dissipation described below may not be assured when not connecting by solder. The back metal is shorted with the backside of the IC chip that is a GND potential. There is a possibility for malfunction or destruction if it is shorted with any potential other than GND, which should be avoided. Please note that it has been assumed that this product will be used in the condition of this back metal performed heat dissipation treatment for increasing heat dissipation efficiency. Package thermal resistor Board θJA [°C/W] 5.0 D 4.83 W 4.0 C 4.29 W Pd [W] 3.0 2.0 B 1.16 W 1.0 A 0.51 W 0.0 0 25 50 75 100 125 150 Board A 240.4 Board B 107.8 Board C 29.1 Board D 25.9 PCB size: 74.2 mm x 74.2 mm x 1.6 mmt (): Copper foil pattern area size Board A: Package only Board B: 1 layer PCB (1 layer: 34.09 mm2) Board C: 4 layer PCB (1, 4 layer: 34.09 mm2. 2, 3 layer: 5505 mm2) Board D: 4 layer PCB (all layers: 5505 mm2) Values in derating curve and packaged thermal resistor are tested values AMBIENT TEMPERATURE [°C] Figure 35. Thermal Derating Curve (VQFN048V7070) www.rohm.com © 2017 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 30/36 TSZ02201-0P2P0B001840-1-2 16.Nov.2020 Rev.005 BD64008MUV I/O Equivalent Circuit No. Pin Name Equivalent Circuit FB1 13 43 OCPDET 44 UVDET 45 RESET OCPDET UVDET RESET 20 kΩ FB2 20 kΩ ENBSW1 Internal Power Internal Power Supply2 Supply2 Internal Power Supply1 100 kΩ MODE 500 kΩ 14 Equivalent Circuit 10 kΩ FB2 18 Pin Name 10 kΩ FB1 42 No. ENBSW2 47 10 kΩ MODE Internal Power Supply2 10 kΩ 15 PWM 9 7 8 4 5 6 46 10 11 12 DAT CLK STB(LD) SLEEP ENBA ENBB RSTIN ID0 ID1 ID2 21 BOOT VINSW2 Internal Power Supply2 40 Ω 10 kΩ 17 COMP 2 VREFA 3 VREFB COMP 10 kΩ 100 kΩ BOOT Internal Power Supply2 SWOUT2 BOOT 19 20 VINSW2 22 23 SWOUT2 29 VBBA 32 VINSW2 SWOUT2 VINSW2 VREFA VREFB 30 kΩ 30 kΩ 10 kΩ UVDETIN 130 Ω 48 UVDETIN 37 38 VBBSW1 VBBSW1 VBBB VBBX SWOUT1 200 kΩ 30 OUTAP 26 OUTAM 31 OUTBP 35 OUTBM Internal Power Supply2 39 40 SWOUT1 OUTXX Internal Power Supply2 27 200 kΩ RNFAS RNFX 15 kΩ Internal Circuit 28 RNFA 33 RNFB RNFXS 34 www.rohm.com © 2017 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 31/36 RNFBS TSZ02201-0P2P0B001840-1-2 16.Nov.2020 Rev.005 BD64008MUV Operational Notes 1 Reverse Connection of Power Supply Connecting the power supply in reverse polarity can damage the IC. Take precautions against reverse polarity when connecting the power supply, such as mounting an external diode between the power supply and the IC’s power supply pins. 2 Power Supply Lines Design the PCB layout pattern to provide low impedance supply lines. Furthermore, connect a capacitor to ground at all power supply pins. Consider the effect of temperature and aging on the capacitance value when using electrolytic capacitors. 3 Ground Voltage Ensure that no pins are at a voltage below that of the ground pin at any time, even during transient condition. 4 Ground Wiring Pattern When using both small-signal and large-current ground traces, the two ground traces should be routed separately but connected to a single ground at the reference point of the application board to avoid fluctuations in the small-signal ground caused by large currents. Also ensure that the ground traces of external components do not cause variations on the ground voltage. The ground lines must be as short and thick as possible to reduce line impedance. 5 Recommended Operating Conditions The function and operation of the IC are guaranteed within the range specified by the recommended operating conditions. The characteristic values are guaranteed only under the conditions of each item specified by the electrical characteristics. 6 Inrush Current When power is first supplied to the IC, it is possible that the internal logic may be unstable and inrush current may flow instantaneously due to the internal powering sequence and delays, especially if the IC has more than one power supply. Therefore, give special consideration to power coupling capacitance, power wiring, width of ground wiring, and routing of connections. 7 Testing on Application Boards When testing the IC on an application board, connecting a capacitor directly to a low-impedance output pin may subject the IC to stress. Always discharge capacitors completely after each process or step. The IC’s power supply should always be turned off completely before connecting or removing it from the test setup during the inspection process. To prevent damage from static discharge, ground the IC during assembly and use similar precautions during transport and storage. 8 Inter-pin Short and Mounting Errors Ensure that the direction and position are correct when mounting the IC on the PCB. Incorrect mounting may result in damaging the IC. Avoid nearby pins being shorted to each other especially to ground, power supply and output pin. Inter-pin shorts could be due to many reasons such as metal particles, water droplets (in very humid environment) and unintentional solder bridge deposited in between pins during assembly to name a few. 9 Unused Input Pins Input pins of an IC are often connected to the gate of a MOS transistor. The gate has extremely high impedance and extremely low capacitance. If left unconnected, the electric field from the outside can easily charge it. The small charge acquired in this way is enough to produce a significant effect on the conduction through the transistor and cause unexpected operation of the IC. So unless otherwise specified, unused input pins should be connected to the power supply or ground line. www.rohm.com © 2017 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 32/36 TSZ02201-0P2P0B001840-1-2 16.Nov.2020 Rev.005 BD64008MUV Operational Notes – continued 10 Regarding the Input Pin of the IC This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them isolated. P-N junctions are formed at the intersection of the P layers with the N layers of other elements, creating a parasitic diode or transistor. For example (refer to figure below): When GND > Pin A and GND > Pin B, the P-N junction operates as a parasitic diode. When GND > Pin B, the P-N junction operates as a parasitic transistor. Parasitic diodes inevitably occur in the structure of the IC. The operation of parasitic diodes can result in mutual interference among circuits, operational faults, or physical damage. Therefore, conditions that cause these diodes to operate, such as applying a voltage lower than the GND voltage to an input pin (and thus to the P substrate) should be avoided. Resistor Transistor (NPN) Pin A Pin B C E Pin A N P+ P N N P+ N Pin B B Parasitic Elements N P+ N P N P+ B N C E Parasitic Elements P Substrate P Substrate GND GND Parasitic Elements GND Parasitic Elements GND N Region close-by Figure 36. Example of Monolithic IC Structure 11 Ceramic Capacitor When using a ceramic capacitor, determine a capacitance value considering the change of capacitance with temperature and the decrease in nominal capacitance due to DC bias and others. 12 Thermal Shutdown Circuit (TSD) This IC has a built-in thermal shutdown circuit that prevents heat damage to the IC. Normal operation should always be within the IC’s maximum junction temperature rating. If however the rating is exceeded for a continued period, the junction temperature (Tj) will rise which will activate the TSD circuit that will turn OFF power output pins. The IC should be powered down and turned ON again to resume normal operation because the TSD circuit keeps the outputs at the OFF state even if the Tj falls below the TSD threshold. Note that the TSD circuit operates in a situation that exceeds the absolute maximum ratings and therefore, under no circumstances, should the TSD circuit be used in a set design or for any purpose other than protecting the IC from heat damage. 13 Over Current Protection Circuit (OCP) This IC incorporates an integrated overcurrent protection circuit that is activated when the load is shorted. This protection circuit is effective in preventing damage due to sudden and unexpected incidents. However, the IC should not be used in applications characterized by continuous operation or transitioning of the protection circuit. www.rohm.com © 2017 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 33/36 TSZ02201-0P2P0B001840-1-2 16.Nov.2020 Rev.005 BD64008MUV Technical information (Exempt from guarantee) 1 About logic input pins for control Response time from rising edge of CLK signal is 20 µs. 2 In case RESET function is used when SWREG is unused Divide the power supply (VBB) by resistor voltage divider, and input into the FB1 pin. In doing so, using RESET function becomes possible. In this case, it is necessary to make ENBSW1 L level. Because this function is only assumed when designing, evaluate and confirm it. 3 Internal power supply 1 Internal power supply 1 applies 4.4 V (Typ) ±10 % dispersion. 4 Internal power supply 2 Internal power supply 2 applies 5 V (Typ) ±10 % dispersion. 5 VREF to RNFS offset voltage (Refer P.4) DAC = 3, accuracy ±10 % DAC = 15, accuracy ±4 % 6 ON-Resistance (H-Bridge) Listed value is only for IOUT = 1 A, but the value is equal about IOUT = 0.5 A. 7 Thermal Shutdown Circuit (TSD) The overheat protection works in 175 °C (Typ), but the overheat protection temperature cannot be less than 150 °C even if it varies with each IC. 8 Adjacent Pins short When VBBx(Note 1) and RNFx(Note 1) short-circuits, the IC may destroy it. (Note 1) x = A, B Ordering Information B D 6 4 0 0 8 M U V - Package MUV: VQFN048V7070 Part Number E2 Packaging and forming specification E2: Embossed tape and reel Marking Diagram VQFN048V7070 (TOP VIEW) Part Number Marking BD64008 LOT Number Pin 1 Mark www.rohm.com © 2017 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 34/36 TSZ02201-0P2P0B001840-1-2 16.Nov.2020 Rev.005 BD64008MUV Physical Dimension and Packing Information Package Name www.rohm.com © 2017 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 VQFN048V7070 35/36 TSZ02201-0P2P0B001840-1-2 16.Nov.2020 Rev.005 BD64008MUV Revision History Date Revision 13.Oct.2017 001 08.Mar.2019 002 20.Dec.2019 003 15.Jan.2020 16.Nov.2020 004 005 www.rohm.com © 2017 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 Changes New Release P.22 RESET OUT truth table changed. Update new format P.7 to P.26 Changed index P.7 (3), (4) Changed place from P.23 P.23 (1) Added explanation P.31 Changed I/O Equivalence Circuit Updated according to the latest format. 36/36 TSZ02201-0P2P0B001840-1-2 16.Nov.2020 Rev.005 Notice Precaution on using ROHM Products 1. Our Products are designed and manufactured for application in ordinary electronic equipment (such as AV equipment, OA equipment, telecommunication equipment, home electronic appliances, amusement equipment, etc.). If you intend to use our Products in devices requiring extremely high reliability (such as medical equipment (Note 1), transport equipment, traffic equipment, aircraft/spacecraft, nuclear power controllers, fuel controllers, car equipment including car accessories, safety devices, etc.) and whose malfunction or failure may cause loss of human life, bodily injury or serious damage to property (“Specific Applications”), please consult with the ROHM sales representative in advance. Unless otherwise agreed in writing by ROHM in advance, ROHM shall not be in any way responsible or liable for any damages, expenses or losses incurred by you or third parties arising from the use of any ROHM’s Products for Specific Applications. (Note1) Medical Equipment Classification of the Specific Applications JAPAN USA EU CHINA CLASSⅢ CLASSⅡb CLASSⅢ CLASSⅢ CLASSⅣ CLASSⅢ 2. ROHM designs and manufactures its Products subject to strict quality control system. However, semiconductor products can fail or malfunction at a certain rate. Please be sure to implement, at your own responsibilities, adequate safety measures including but not limited to fail-safe design against the physical injury, damage to any property, which a failure or malfunction of our Products may cause. The following are examples of safety measures: [a] Installation of protection circuits or other protective devices to improve system safety [b] Installation of redundant circuits to reduce the impact of single or multiple circuit failure 3. Our Products are designed and manufactured for use under standard conditions and not under any special or extraordinary environments or conditions, as exemplified below. Accordingly, ROHM shall not be in any way responsible or liable for any damages, expenses or losses arising from the use of any ROHM’s Products under any special or extraordinary environments or conditions. If you intend to use our Products under any special or extraordinary environments or conditions (as exemplified below), your independent verification and confirmation of product performance, reliability, etc, prior to use, must be necessary: [a] Use of our Products in any types of liquid, including water, oils, chemicals, and organic solvents [b] Use of our Products outdoors or in places where the Products are exposed to direct sunlight or dust [c] Use of our Products in places where the Products are exposed to sea wind or corrosive gases, including Cl2, H2S, NH3, SO2, and NO2 [d] Use of our Products in places where the Products are exposed to static electricity or electromagnetic waves [e] Use of our Products in proximity to heat-producing components, plastic cords, or other flammable items [f] Sealing or coating our Products with resin or other coating materials [g] Use of our Products without cleaning residue of flux (Exclude cases where no-clean type fluxes is used. However, recommend sufficiently about the residue.) ; or Washing our Products by using water or water-soluble cleaning agents for cleaning residue after soldering [h] Use of the Products in places subject to dew condensation 4. The Products are not subject to radiation-proof design. 5. Please verify and confirm characteristics of the final or mounted products in using the Products. 6. In particular, if a transient load (a large amount of load applied in a short period of time, such as pulse, is applied, confirmation of performance characteristics after on-board mounting is strongly recommended. Avoid applying power exceeding normal rated power; exceeding the power rating under steady-state loading condition may negatively affect product performance and reliability. 7. De-rate Power Dissipation depending on ambient temperature. When used in sealed area, confirm that it is the use in the range that does not exceed the maximum junction temperature. 8. Confirm that operation temperature is within the specified range described in the product specification. 9. ROHM shall not be in any way responsible or liable for failure induced under deviant condition from what is defined in this document. Precaution for Mounting / Circuit board design 1. When a highly active halogenous (chlorine, bromine, etc.) flux is used, the residue of flux may negatively affect product performance and reliability. 2. In principle, the reflow soldering method must be used on a surface-mount products, the flow soldering method must be used on a through hole mount products. If the flow soldering method is preferred on a surface-mount products, please consult with the ROHM representative in advance. For details, please refer to ROHM Mounting specification Notice-PGA-E © 2015 ROHM Co., Ltd. All rights reserved. Rev.004 Precautions Regarding Application Examples and External Circuits 1. If change is made to the constant of an external circuit, please allow a sufficient margin considering variations of the characteristics of the Products and external components, including transient characteristics, as well as static characteristics. 2. You agree that application notes, reference designs, and associated data and information contained in this document are presented only as guidance for Products use. Therefore, in case you use such information, you are solely responsible for it and you must exercise your own independent verification and judgment in the use of such information contained in this document. ROHM shall not be in any way responsible or liable for any damages, expenses or losses incurred by you or third parties arising from the use of such information. Precaution for Electrostatic This Product is electrostatic sensitive product, which may be damaged due to electrostatic discharge. Please take proper caution in your manufacturing process and storage so that voltage exceeding the Products maximum rating will not be applied to Products. Please take special care under dry condition (e.g. Grounding of human body / equipment / solder iron, isolation from charged objects, setting of Ionizer, friction prevention and temperature / humidity control). Precaution for Storage / Transportation 1. Product performance and soldered connections may deteriorate if the Products are stored in the places where: [a] the Products are exposed to sea winds or corrosive gases, including Cl 2, H2S, NH3, SO2, and NO2 [b] the temperature or humidity exceeds those recommended by ROHM [c] the Products are exposed to direct sunshine or condensation [d] the Products are exposed to high Electrostatic 2. Even under ROHM recommended storage condition, solderability of products out of recommended storage time period may be degraded. It is strongly recommended to confirm solderability before using Products of which storage time is exceeding the recommended storage time period. 3. Store / transport cartons in the correct direction, which is indicated on a carton with a symbol. Otherwise bent leads may occur due to excessive stress applied when dropping of a carton. 4. Use Products within the specified time after opening a humidity barrier bag. Baking is required before using Products of which storage time is exceeding the recommended storage time period. Precaution for Product Label A two-dimensional barcode printed on ROHM Products label is for ROHM’s internal use only. Precaution for Disposition When disposing Products please dispose them properly using an authorized industry waste company. Precaution for Foreign Exchange and Foreign Trade act Since concerned goods might be fallen under listed items of export control prescribed by Foreign exchange and Foreign trade act, please consult with ROHM in case of export. Precaution Regarding Intellectual Property Rights 1. All information and data including but not limited to application example contained in this document is for reference only. ROHM does not warrant that foregoing information or data will not infringe any intellectual property rights or any other rights of any third party regarding such information or data. 2. ROHM shall not have any obligations where the claims, actions or demands arising from the combination of the Products with other articles such as components, circuits, systems or external equipment (including software). 3. No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of ROHM or any third parties with respect to the Products or the information contained in this document. Provided, however, that ROHM will not assert its intellectual property rights or other rights against you or your customers to the extent necessary to manufacture or sell products containing the Products, subject to the terms and conditions herein. Other Precaution 1. This document may not be reprinted or reproduced, in whole or in part, without prior written consent of ROHM. 2. The Products may not be disassembled, converted, modified, reproduced or otherwise changed without prior written consent of ROHM. 3. In no event shall you use in any way whatsoever the Products and the related technical information contained in the Products or this document for any military purposes, including but not limited to, the development of mass-destruction weapons. 4. The proper names of companies or products described in this document are trademarks or registered trademarks of ROHM, its affiliated companies or third parties. Notice-PGA-E © 2015 ROHM Co., Ltd. All rights reserved. Rev.004 Datasheet General Precaution 1. Before you use our Products, you are requested to carefully read this document and fully understand its contents. ROHM shall not be in any way responsible or liable for failure, malfunction or accident arising from the use of any ROHM’s Products against warning, caution or note contained in this document. 2. All information contained in this document is current as of the issuing date and subject to change without any prior notice. Before purchasing or using ROHM’s Products, please confirm the latest information with a ROHM sales representative. 3. The information contained in this document is provided on an “as is” basis and ROHM does not warrant that all information contained in this document is accurate and/or error-free. ROHM shall not be in any way responsible or liable for an y damages, expenses or losses incurred b y you or third parties resulting from inaccuracy or errors of or concerning such information. Notice – WE © 2015 ROHM Co., Ltd. All rights reserved. Rev.001