BD7003NUX

1/4 Structure Product Name Type Functions Silicon Monolithic Integrated Circuit Dual, Low-Dropout Linear Regulators B D7003NUX ・2-channel 300mA, CMOS-type LDOs. ・Pin-Programmable Output Voltage. （9 steps adjustable VO；See the Table of “Output-Voltage Programming”.） ・LDOs Power ON/OFF Enable Control. ・2.0mm×2.0mm Package. ・Small Ceramic Output Capacitors(1μF) ・Equipped with Over Current Limiter and Thermal Shutdown Circuit(TSD) . Absolute Maximum Ratings (Ta=25℃) Parameter Maximum Supply Voltage (VIN) Maximum Input Voltage 1 (P1,P2,EN1,EN2) Maximum Input Voltage 2 (Vout1,Vout2) Power Dissipation Operating Temperature Range Storage Temperature Range Symbol VIN VINMAX1 VINMAX2 Pd Topr Tstg Rating -0.3 ～ 7 -0.3 ～ 7 -0.3～Vin+0.3 1360 -40 ～ +85 -55 ～ +150 Unit V V V mW ℃ ℃ *This is the allowable loss of when it is mounted on a ROHM specification board 40mm×40mm×1.5mmt To use at temperature higher than 25C , derate 10.9mW per 1C. Operating range (Ta=-40C～+85℃) Parameter Input Power Supply Voltage Range (Do not exceed Pd) Symbol VIN Range 2.5～5.5 Unit V ◎This product is not especially designed to be protected from radioactivity. REV. A 2/4 Electrical Characteristics Vin=3.7V, EN1=EN2=Vin,Ta =+25℃, unless otherwise noted. Parameter Output Voltage range Input Voltage range Output Voltage Accuracy Maximum Output Current Short Circuit Current Ground Pin Current Symbol VOUT VIN Δvout Imax Isc Iq Min 1.5 2.5 -1.8 300 Dropout Voltage Vdrop Line Regulation Load Regulation Ripple Rejection Output Noise ●EN1,EN2 Enable Input Threshold Enable Input Leakage Current Shutdown Supply Current ViH ViL Ien IQSHDN 1.2 0.1 0.1 0.5 1 1 V μA μA Regulator enabled Regulator shutdown Ven=VIN , Ta=+25℃ Vout=0V , Ta=+25℃ ΔVLNR ΔVLDR PSRR en Typ 150 55 35 120 90 70 360 270 210 0.02 0.2 66 150 Max 3.3 5.5 1.8 95 65 170 140 120 510 420 360 0.2 0.6 %/V % dB mV Unit V V % mA mA μA VOUT = 0V Iout=0mA One LDO shutdown, Iout=0mA VIN=2.5V, VOUT=2.6V, Iout=100mA VIN=2.7V, VOUT=2.8V, Iout=100mA VIN=3.2V, VOUT=3.3V,Iout=100mA VIN=2.5V, VOUT=2.6V, Iout=300mA VIN=2.7V, VOUT=2.8V, Iout=300mA VIN=3.2V, VOUT=3.3V, Iout=300mA VIN=VOUT+1V to VIN=5.5V, Iout=10mA Iout=1mA to 300mA f=100Hz,Iout=10mA@VOUT=1.5V Iout=1mA Condition μVRMS fBW=10Hz to 100kHz;Iout=10mA Output-Voltage Programming PIN Name P1 P2 VOUT1 VOUT2 OPEN OPEN 1.50 2.80 OPEN GND 1.80 2.60 OPEN VIN 1.80 2.70 GND OPEN 1.80 2.80 Set up GND GND 1.80 2.90 GND VIN 2.60 2.80 VIN OPEN 2.80 2.80 VIN GND 2.90 2.90 VIN VIN 2.80 3.30 Output voltages, VOUT1 and VOUT2, are determined at power up by the state of P1 and P2(see the table of “Output-Voltage Programming”). Subsequent charges to P1 and P2 do not change the output voltages unless the supply power is cycled, or all EN inputs are simultaneously driven low to shutdown the device. REV. A 3/4 Package BD7 003 Lot No. [unit: mm] Block Diagram PIN description VIN 1 PIN No. 1 2 3 4 5 6 7 8 PIN Name VIN EN1 P2 P1 EN2 GND VOUT2 VOUT1 EN1 2 EN2 5 SHUTDOWN AND POWER-ON CONTROL P ERROR AMP OVER CURRENT PROTECTION P1 P2 4 3 OUTPUT VOLTAGE CONTROL EN1 DISCHARGE CIRCUIT 8 VOUT1 LDO1 VIN VREF & TSD LDO2 GND 6 7 VOUT2 REV. A 4/4 ● Use-related Cautions (1) Absolute maximum ratings If applied voltage (VIN), operating temperature range (Topr), or other absolute maximum ratings are exceeded, there is a risk of damage. Since it is not possible to identify short, open, or other damage modes, if special modes in which absolute maximum ratings are exceeded are assumed, consider applying fuses or other physical safety measures. (2) Recommended operating range This is the range within which it is possible to obtain roughly the expected characteristics. For electrical characteristics, it is those that are guaranteed under the conditions for each parameter. Even when these are within the recommended operating range, voltage and temperature characteristics are indicated. (3) Reverse connection of power supply connector There is a risk of damaging the LSI by reverse connection of the power supply connector. For protection from reverse connection, take measures such as externally placing a diode between the power supply and the power supply pin of the LSI. (4) Power supply lines In the design of the board pattern, make power supply and GND line wiring low impedance. When doing so, although the digital power supply and analog power supply are the same potential, separate the digital power supply pattern and analog power supply pattern to deter digital noise from entering the analog power supply due to the common impedance of the wiring patterns. Similarly take pattern design into account for GND lines as well. Furthermore, for all power supply pins of the LSI, in conjunction with inserting capacitors between power supply and GND pins, when using electrolytic capacitors, determine constants upon adequately confirming that capacitance loss occurring at low temperatures is not a problem for various characteristics of the capacitors used. (5) GND voltage Make the potential of a GND pin such that it will be the lowest potential even if operating below that. In addition, confirm that there are no pins for which the potential becomes less than a GND by actually including transition phenomena. (6) Shorts between pins and misinstallation When installing in the set board, pay adequate attention to orientation and placement discrepancies of the LSI. If it is installed erroneously, there is a risk of LSI damage. There also is a risk of damage if it is shorted by a foreign substance getting between pins , between a pin and a power supply or GND. (7) Operation in strong magnetic fields Be careful when using the LSI in a strong magnetic field, since it may malfunction. (8) Inspection in set board When inspecting the LSI in the set board, since there is a risk of stress to the LSI when capacitors are connected to low impedance LSI pins, be sure to discharge for each process. Moreover, when getting it on and off of a jig in the inspection process, always connect it after turning off the power supply, perform the inspection, and remove it after turning off the power supply. Furthermore, as countermeasures against static electricity, use grounding in the assembly process and take appropriate care in transport and storage. (9) Input pins Parasitic elements inevitably are formed on an LSI structure due to potential relationships. Because parasitic elements operate, they give rise to interference with circuit operation and may be the cause of malfunctions as well as damage. Accordingly, take care not to apply a lower voltage than GND to an input pin or use the LSI in other ways such that parasitic elements operate. Moreover, do not apply a voltage to an input pin when the power supply voltage is not being applied to the LSI. Furthermore, when the power supply voltage is being applied, make each input pin a voltage less than the power supply voltage as well as within the guaranteed values of electrical characteristics. (10) Ground wiring pattern When there is a small signal GND and a large current GND, it is recommended that you separate the large current GND pattern and small signal GND pattern and provide single point grounding at the reference point of the set so that voltage variation due to resistance components of the pattern wiring and large currents do not cause the small signal GND voltage to change. Take care that the GND wiring pattern of externally attached components also does not change. (11) Externally attached capacitors When using ceramic capacitors for externally attached capacitors, determine constants upon taking into account a lowering of the rated capacitance due to DC bias and capacitance change due to factors such as temperature. (12) Thermal shutdown circuit (TSD) When the junction temperature reaches the defined value, the thermal shutdown circuit operates and turns the switch OFF. The thermal shutdown circuit, which is aimed at isolating the LSI from thermal runaway as much as possible, is not aimed at the protection or guarantee of the LSI. Therefore, do not continuously use the LSI with this circuit operating or use the LSI assuming its operation. (13) Thermal design Perform thermal design in which there are adequate margins by taking into account the permissible dissipation (Pd) in actual states of use. (14) Rush Current Extra care must be taken on power coupling, power, ground line impedance, and PCB design while excess amount of rush current might instantly flow through the power line when powering-up a LSI which is equipped with several power supplies, depending on on/off sequence, and ramp delays. REV. A Notice Notes No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM Co.,Ltd. The content specified herein is subject to change for improvement without notice. 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