BD71815AGW-E2

Platform Design Guide BD71815AGW (Power Management IC designed for “Freescale i.MX 7Solo and i.MX 7Dual Processors”) Platfrom Design Guide June 2017 Revision 1.30 BD71815AGW Design Guide Rev.1.30 1/31 Revision History Revision Number Description 1.00 Initial release 1.10 Replaced Figure. 4-3-1-1 since pin name of A9 and B9 were modified as PGND1A and PGND1B 1.20 Fixed typo 1.30 Deleted the description of “Rohm confidential” BD71815AGW Design Guide Revision Date October 2016 January 2017 June 2017 June 2017 Rev.1.30 2/31 Contents Revision History................................................................................................. 2 1 Introduction ..................................................................................................... 4 1.1 Terminology ....................................................................................................................... 4 1.2 Reference Documents ....................................................................................................... 4 2 System Features............................................................................................. 5 3 General Design Considerations ...................................................................... 7 3.1 Package Dimension of BD71815AGW .............................................................................. 7 3.2 Pin Configuration ............................................................................................................... 8 3.3 General Stack-up Recommendations ................................................................................ 9 3.4 6-layer Board Stack-up ...................................................................................................... 9 3.5 General PCB Pad Design Guidelines ................................................................................ 9 3.5.1 Pad Size and Shape..................................................................................................................................................... 9 3.6 Via Guidelines .................................................................................................................. 10 3.7 BD71815AGW Breakout Example ................................................................................... 11 4 Platform Power Delivery Guidelines .............................................................. 14 4.1 Platform Power Delivery .................................................................................................. 14 4.2 General Layout Guideline ................................................................................................ 16 4.2.1 Overall component Placement Example ................................................................................................................. 16 4.2.2 Large Current Loop ................................................................................................................................................... 17 4.2.3 Power GND................................................................................................................................................................. 18 4.2.4 VIN (Power supply for BD71815AGW analog circuit) ............................................................................................. 18 4.2.5 Other Signal Pattern Precautions ............................................................................................................................ 18 4.2.6 Feedback sense line.................................................................................................................................................. 18 4.3 Switching regulators......................................................................................................... 19 4.3.1 BUCK1 ........................................................................................................................................................................ 19 4.3.2 BUCK2 ........................................................................................................................................................................ 20 4.3.3 BUCK3 ........................................................................................................................................................................ 22 4.3.4 BUCK4 ........................................................................................................................................................................ 23 4.3.5 BUCK5 ........................................................................................................................................................................ 25 4.3.6 LED Driver .................................................................................................................................................................. 27 4.4 Linear VR ......................................................................................................................... 28 4.4.1 LDO1-5 / VODVREF / SNVSC .................................................................................................................................... 28 4.5 Interfaces ......................................................................................................................... 29 4.5.1 I2C ............................................................................................................................................................................... 29 4.5.2 GPO ............................................................................................................................................................................ 29 4.5.3 Charger, Coulomb counter, OVP .............................................................................................................................. 29 4.5.4 RTC ............................................................................................................................................................................. 31 4.5.5 System Control signals............................................................................................................................................. 31 4.5.6 MISC ........................................................................................................................................................................... 31 BD71815AGW Design Guide Rev.1.30 3/31 1 Introduction BD71815AGW is a Power Management Integrated Circuit (PMIC) for battery-powered portable devices. It integrates 5 Bucks, 8 LDOs, a boost driver for LED, 500mA single-cell linear charger, Coulomb counter, RTC, 32 kHz crystal circuitry and a GPO. And it is designed to support the specific power requirement of Freescale i.MX 7Solo and i.MX 7Dual platforms with minimum cost requirement. The “BD71815AGW Platform Design Guide” provides design guideline which is recommended to PCB layer stack up, the components placement and the PCB routing. To reduce the risk that comes from PCB layout or parts placement, the guideline is strongly recommended to be adapted to the PCB design. 1.1 Terminology Table 1-1-1. Acronyms, Conventions and Terminology Term Definition BOM Bill Of Materials FET Field Effect Transistor I2C Inter-Integrated Circuit IRQ Interrupt Request LDO Low Drop-Out regulator OCP Over Current Protection OVP Over Voltage Protection PFM Pulse-Frequency Modulation PWM Pulse-Width Modulation RTC Real-Time Clock SoC System-On-a-Chip UVLO Under Voltage-LockOut DVS Dynamic Voltage Scaling 1.2 Reference Documents Table 1-1-2. Reference Documents Document BD71815AGW(EN)_Rev001, Oct, 2016 BD71815AGW Design Guide Rev.1.30 4/31 2 System Features BD71815AGW is used to supply the required power to the SoC and peripheral devices. Once powered up, it can be controlled by I2C bus to determine internal settings. The following explains the features that are incorporated in the IC. Voltage Rails ■ 5 Buck regulators BUCK1: Initial 1.100V, 0.800V – 2.000V / 25mV step DVS, IOMAX = 800mA  BUCK2: Initial 1.000V, 0.800V – 2.000V / 25mV step DVS, IOMAX = 1000mA  BUCK3: 1.800V, 1.200V – 2.700V / 50mV step programmable, IOMAX = 500mA  BUCK4: 1.200V, 1.000V – 1.850V / 50mV step programmable, IOMAX = 1000mA  BUCK5: 3.300V, 1.800V – 3.300V / 50mV step programmable, IOMAX = 1000mA  ■ 3 LDO regulators (General purpose) LDO1: 3.3V, 0.8V – 3.3V / 50mV step programmable, IOMAX = 100mA  LDO2: 3.3V, 0.8V – 3.3V / 50mV step programmable, IOMAX = 100mA  LDO3: 3.3V, 0.8V – 3.3V / 50mV step programmable, IOMAX = 50mA  ■ LDO for SD Card with dedicated enable terminal LDO4: 3.3V, 0.8V – 3.3V / 50mV step programmable, IOMAX = 400mA  ■ LDO for SD Card Interface with dedicated terminal to dynamically change output voltage LDO5: 1.8V / 3.3V, 0.8V – 3.3V / 50mV step programmable, IOMAX = 250mA  ■ LDO for DDR Reference Voltage VODVREF: DVREFIN/2, IOMAX = 10mA  ■ LDO for Secure Non-Volatile Storage SNVSC: 3.0V, IOMAX = 25mA  ■ LDO for Low-Power State Retention LDOLPSR: 1.8V, IOMAX = 100mA  White LED Boost Converter  ~ 25mA LED Boost Converter Single-cell Linear LIB Charger with 30V OVP        Selectable Charging Voltage: 3.72V – 4.34V Programmable Charge Current: 100mA – 500mA Support for up to 2000mA charge current using external MOSFET DCIN Over Voltage Protection Battery Over Voltage Protection Support Battery Supplement Mode Battery Short Circuit Detection BD71815AGW Design Guide Rev.1.30 5/31 Voltage Measurement for Thermistor  CHGREF: Bias Voltage Output for External Thermistor Embedded Coulomb Counter for Battery Fuel Gauging    15-bit ΔΣ-ADC with External Current Sense Resistor (10 mΩ, ±1%) 1sec cycle, 28-bit Accumulation Coulomb Count while Charging/Discharging Battery Monitoring and Alarm Output     Under Voltage Alarm while Discharging Over Discharge Current Alarm Over/Under Temperature Alarm Programmable Thresholds and Time Durations Real Time Clock with 32.768kHz Crystal Oscillator  CLK32KOUT: 32.768kHz Clock Output (Open Drain or CMOS Output Selectable) 1 GPO  GPO (Open Drain or CMOS Output Selectable) Power Control I/O     PWRON: Power ON/OFF Control Input STANDBY: Standby Input for Switching ON / STANDBY Mode RESETINB: Reset Input to Reset Hung PMIC POR: Power ON Reset Output Serial Interface  I2C interface provides access to configuration registers. BD71815AGW Design Guide Rev.1.30 6/31 3 General Design Considerations This chapter provides general PCB design guidelines such as BD71815AGW general parts placement. 3.1 Package Dimension of BD71815AGW Figure 3-1-1 shows the package dimension of BD71815AGW. D71815A Lot Number Figure 3-1-1 BD71815AGW Package Dimension BD71815AGW Design Guide Rev.1.30 7/31 3.2 Pin Configuration Figure 3-2-1 shows the BD71815AGW pin configuration with which signals from respective blocks are effectively routed out from PMIC to SoC, SDRAM, and other platform components. BOTTOM VIEW J GND HX6 PVIN3 LX3 PGND3 SNVSC PGND4 LX4 GND H LX6 FB6 PVIN6 FB3 SDA VODVREF FB4 VO4 PVIN4 G PGND5 PGND6 VO6 DVDD SCL LDO4 VEN DVREFIN VO5 VINL2 F LX5 GND RESET INB GND GND GND INTB GND PGND2 E PVIN5 FB5 STANDBY GND GND GND POR FB2 LX2 D XOUT GPO1 WDOGB GND GND VO3 VO2 PVIN2 C XIN PWRON CLK32K OUT LDO5 VSEL BATTP TS CHGLED VO1 VINL1 B DCIN READY VIN PGATE CHGGND BATTM VOLPSR FB1 PGND1 A DCIN DCIN VSYS VSYS VBAT CHGREF PVIN1 LX1 PGND1 1 2 3 4 5 6 7 8 9 Figure 3-2-1 Pin Configuration BD71815AGW Design Guide Rev.1.30 8/31 3.3 General Stack-up Recommendations Type-4 and 6 layers PCB technology is used for BD71815AGW. The following general stack-up is strongly recommended to be applied to all the routings on the PCB.     Surface plane layer are recommended to be 2.0 Mils thick copper. Internal plane layers are recommended to be 1.3 Mils thick copper. It is recommended that I2C signals have reference to solid planes over the length of their routing and do not cross plane splits. Ground is preferred as reference. PCB should be filled with as much ground or other power rails as possible with copper. There should not be any large areas with no metal in the board. Heat dissipation gets improved with larger metal areas. Large metal area also reduces stray resistance and inductance. 3.4 6-layer Board Stack-up BD71815AGW Boards uses the PCB technologies of a high density interconnect, Type 4, 6-layer board. Figure 3-3-1 shows PCB 1-4-1 stack-up. L1: Signals including LX, PVIN and PGND lines of DCDC L2: GND plane L3: Power plane L4: Signals L5: Signals L6: Signals Figure 3-3-1 6-Layer PCB Stack-up 3.5 General PCB Pad Design Guidelines The following guidelines are to improve mechanical robustness and solder joint reliability (SJR) of Pbfree SLI. The following guidelines are highly recommended to be followed for robust platform signal integrity. 3.5.1 Pad Size and Shape 1. The ratio of package solder resist opening (SRO) to PCB pad size must be less than 1:1.1. The pad size can be calculated by the package side SRO. First, the side package length is divided by 1.1 then the result is rounded up to the next whole number by mil. 250/ 1.1 = 227.27 μm, 227.27μml = 8.95 mils = ~9 mils 2. If SRO is not provided, the alternate method for calculating pad size is that the nominal ball diameter is multiplied by 0.8, then rounded up to the nearest whole mil. BD71815AGW Design Guide Rev.1.30 9/31 3.6 Via Guidelines This section explains proper via-drill, pad, and anti-pad size. Note: Improper drill, pad, and anti-pad size may cause some trouble on the PCB cost, reliability, manufacturability, and electrical characteristics. Type-3 PCB technology employs plated through-hole (PTH) vias for breakout routing. The dimension of PTH vias may vary as necessary. Table 3-6-1 shows the recommended via dimension used for the breakout areas of BD71815AGW. Figure 3-6-1 shows about the dimensions of via. Type-4 PCB technology employs plated through-hole (PTH) vias and micro via holes (MVH) for breakout routing. Since the PTH vias are used in less space-constrained areas outside the BGA field, the dimension of PTH vias may vary as necessary. Table 3-6-1 shows the recommended via dimension used for the breakout areas of BD71815AGW. Figure 3-6-1 shows about the dimensions of via. Table 3-6-1: Platform via Examples Via type Micro via holes (MVH) Plated through-hole (PTH) Hole size Pad size Anti-Pad size 6 mil 10 mil 12 mil 22 mil 16 mil 30 mil Hole size Pad size Anti-Pad size Figure 3-6-1: Dimension of via BD71815AGW Design Guide Rev.1.30 10/31 3.7 BD71815AGW Breakout Example For the breakout routing on Layer 1(Top layer) thru 6 (Bottom layer), refer to Figure 3-7-1 thru Figure 3-7-6. BUCK1 VOLPSR LDO1 LDO2 LDO3 Crystal BUCK2 BUCK5 LDO5 LDO4 LED Driver BUCK3 BUCK4 VODVREF SNVSC Figure 3-7-1 BD71815AGW Reference Board Breakout and Parts Placement (Top Layer) Figure 3-7-2 BD71815AGW Reference Board Breakout (Layer 2) BD71815AGW Design Guide Rev.1.30 11/31 VSYS Figure 3-7-3 BD71815AGW Reference Board Breakout (Layer 3) Figure 3-7-4 BD71815AGW Reference Board Breakout (Layer 4) BD71815AGW Design Guide Rev.1.30 12/31 Figure 3-7-5 BD71815AGW Reference Board Breakout (Layer 5) Figure 3-7-6 BD71815AGW Reference Board Breakout (Layer 6) BD71815AGW Design Guide Rev.1.30 13/31 4 Platform Power Delivery Guidelines BD71815AGW is a PMIC (Power Management Integrated Circuit) that incorporates single-channel switching regulators (Buck), Linear VRs (LDO), LED Driver, RTC, Single-cell Linear LIB charger and Coulomb counter. It is essential to follow the guidelines for stable power delivery to the SoC and the system. 4.1 Platform Power Delivery Figure 4-1-1-1 shows the voltages BD71815AGW provides to the SoC and the other devices in the system and Table 4-1-1-1 provides the maximum current guideline for respective voltage rail. Table 4-1-1-1 DC-to-DC converters and Linear VRs Maximum Design Power Voltage Rail Type Input Voltage Default Output Voltage [V] Max Current [mA] BUCK1 BUCK2 BUCK3 BUCK4 BUCK5 LDO1 LDO2 LDO3 LDO4 LDO5 VODVREF SNVSC LDOLPSR Buck [DVS] Buck [DVS] Buck Buck Buck LDO LDO LDO LDO LDO LDO LDO LDO PVIN1 PVIN2 PVIN3 PVIN4 PVIN5 VINL1 VINL1 VINL1 VINL2 VINL2 VIN VIN VIN 1.100 1.000 1.800 1.200 3.300 3.300 3.300 3.300 3.300 1.800 / 3.300 0.5*DVREFIN 3.000 1.800 800 1000 500 1000 1000 100 100 50 400 250 10 25 100 BD71815AGW Design Guide Rev.1.30 14/31 BD71815AGW DVDD I2C Register SDA SCL WDOGB READY INTB POR Power Control PWRON LDO_SNVS 3.0V 25mA PMIC_ON_REQ STANDBY PMIC_STBY_REQ SNVSC VDD_SNVS VDD_SNVS _1P8_CAP Coin Cell XIN CLK32KOUT RTC_XTALI 32K OSC X’tal i.MX7Dual SNVS domain PMIC PAD ONOFF LDO_SNVS_1P8 32KRTC SNVS & TAMPER DETECTEON XOUT LPSR domain LDO_LPSR 1.8V 100mA HX6 VOLPSR VDD_LPSR LDO_LPSR_1P0 SOC LPSR LOGIC NVCC_GPIO1 LX6 SBD VO6 POR_B 1.8V GPIO PAD White LED Boost Converter LDO1 3.3V 100mA 25mA VO1 NVCC_GPIO2 3.3V GPIO PAD (ON/OFF) FB6 DVS (1.0V/1.1V) BUCK5 WiFi BUCK5 3.3V 1000mA BUCK1 1.0V/1.1V 800mA BUCK1 VDD_ARM BUCK2 1.0V 1000mA BUCK2 VDD_SOC BUCK3 1.8V 500mA BUCK3 VDDA_1P8 Cortex A7 Platform SOC Logic Analog Modules PMIC_RDY Touch I/O NVCC_XXX 1.8V GPIO PAD WDOG_B SCL SDA DCIN DCINOK 28V OVP VO2 LDO3 3.3V 50mA VO3 BUCK4 1.2V 1000mA VSYS External MOSFET (Optional) (ON/OFF) LDO2 3.3V 100mA PGATE NVCC_XXX 3.3V GPIO PAD VDDA_USB1_3P3 VDDA_USB2_3P3 BUCK4 NVCC_DRAM_CKE USB OTG1/2 PHY DRAM_CKE/RESET TAMPER9 VBAT CHGREF Battery Pack Linear Charger DVREF 1/2xDVREFIN 10mA DVREFIN NVCC_DRAM VODVREF DRAM_VREF DRAM PAD LPDDR2 SDXC I/F PAD SD Card TS LDO4 3.3V 400mA BATTP BATTM Coulomb Counter LDO5 3.3V/1.8V 250mA VO4 LDO4VEN SD_RESET VO5 LDO5VSEL SD_VSELECT Figure 4-1-1-1: BD71815AGW typical application (E-Book Reader with i.Mx7D) BD71815AGW Design Guide Rev.1.30 15/31 4.2 General Layout Guideline This section explains the guideline for Voltage Regulators. High current voltage rails must be carefully laid out to avoid unwanted noise interference from other signals and voltage drop. Especially for switching regulators, abrupt current/ voltage change occurs around the switch-nodes, so please note this in your layout and be sure to follow all the guidelines in this section. 4.2.1 Overall component Placement Example Figure 4-2-1 shows the overall component-placement example. The figure shows the components that are needed to put closely to the BD71815AGW. It is strongly recommended that power components are put prior to any other components so that the signals do not interfere with each other. BUCK1 VOLPSR LDO1 LDO2 LDO3 Crystal BUCK2 BUCK5 LDO5 LDO4 LED Driver BUCK3 BUCK4 VODVREF SNVSC Figure 4-2-1: Overall component placement example BD71815AGW Design Guide Rev.1.30 16/31 4.2.2 Large Current Loop There are 2 high pulsing current flowing loops in the buck regulator system. Loop1: When Tr2 turns ON, the loop starts from the input capacitor, to VIN terminal, to LX terminal, to L (inductor), to output capacitors, and then returns to the input capacitor through GND. Loop2: When Tr1 turns ON, the loop starts from Tr1, to L (inductor), to output capacitors, and then returns to Tr1 through GND. To reduce the noise and improve the efficiency, please minimize these two loops area. Figure 4-2-2-1 shows the current loops which needs to be designed by taking care of parts placement and the routings. VIN Tr2 Vout ① Cin LX L Tr1 Cout ② ① GND Figure 4-2-2-1: DC-to-DC Converter Large Current Loops As Figure 4-2-2-2 shows, please route patterns which load heavy current with short and wide traces as much as possible to suppress noise that comes from parasitic inductance on PCB and switching operation, especially for the node’s current that changes drastically such as VIN (input voltage) and power ground (GND). L COUT PVIN1 PGND1 LX1 Figure 4-2-2-2: Example of parts placement and routing in the top layer of a buck regulator (BUCK1) BD71815AGW Design Guide Rev.1.30 17/31 4.2.3 Power GND Power grounds of DC-to-DC Converters (PGNDx) are noisy ground due to current loops indicated in the previous section. Thus, power grounds should take large area as much as possible to keep impedance low and reduce the swing ground voltage level. 4.2.4 VIN (Power supply for BD71815AGW analog circuit) VIN should not connect with plane VSYS directly to avoid external noise from PVINx due to common impedance. Also, please place a capacitor near this pin as much as possible to stabilize input power. VIN 10uF BD71815AGW PTH (Top layer) VSYS (Inner layer) Figure 4-2-4: Layout for VIN 4.2.5 Other Signal Pattern Precautions Make sure to leave adequate space between noisy lines of voltage rail and serial interface (I2C). 4.2.6 Feedback sense line Feedback Sense terminals (FBx) are used for voltage rails to send out the accurate voltage. In order for output voltage of each VRs to avoid voltage drop caused by the large current and the parasitic impedance, please make sure that the feedback sense lines are independently routed from the point near output capacitors. BD71815AGW Design Guide Rev.1.30 18/31 4.3 Switching regulators 4.3.1 BUCK1 BUCK1 is a high-efficiency single buck regulator with integrated FET that converts the VSYS voltage to a regulated voltage. This VR can dynamically change its output voltage setting using the I2C interface. BUCK1 output voltage range is from 0.8V to 2.0V (25mV/ step). 4.3.1.1 Schematic Example Figure 4-3-1-1 BUCK1 Schematic Example 4.3.1.2 Schematic checklist Table4-3-1-2 BUCK1 schematic checklist Pin Names Dir. Notes (Unit of parts size : inch) Check BUCK1 PVIN1 I PGND1[1:0] I LX1 O FB1 I Connect to VSYS. As decoupling capacitor, use one 4.7μF. Connect to Power GND. Connect one 0.47uH inductor to LX1. As output capacitors, use one 10uF capacitors. Connect to BUCK1 output voltage which is regulated by the DC/DC converter of BD71815AGW. BD71815AGW Design Guide Rev.1.30 19/31 4.3.1.3 Layout Example BUCK1 Figure 4-3-1-2 BUCK1 Layout Example (Top Layer) 4.3.2 BUCK2 BUCK2 is a high-efficiency single buck regulator with integrated FET that converts the VSYS voltage to a regulated voltage. This VR can dynamically change its output voltage setting using the I2C interface. BUCK2 output voltage range is from 0.8V to 2.0V (25mV/ step). 4.3.2.1 Schematic Example Figure 4-3-2-1 BUCK2 Schematic Example BD71815AGW Design Guide Rev.1.30 20/31 4.3.2.2 Schematic checklist Table4-3-2-2 BUCK2 schematic checklist Pin Names Dir. Notes (Unit of parts size : inch) Check BUCK2 PVIN2 I PGND2 I LX2 O FB2 I Connect to VSYS. As decoupling capacitor, use one 4.7μF. Connect to Power GND. Connect one 0.47uH inductor to LX2. As output capacitors, use one 10uF capacitors. Connect to BUCK2 output voltage which is regulated by the DC/DC converter of BD71815AGW. 4.3.2.3 Layout Example BUCK2 Figure 4-3-2-2 BUCK2 Layout Example (Top Layer) BD71815AGW Design Guide Rev.1.30 21/31 4.3.3 BUCK3 BUCK3 is a high-efficiency single buck regulator with integrated FET that converts the VSYS voltage to a regulated voltage. 4.3.3.1 Schematic Example Figure 4-3-3-1 BUCK3 Schematic Example 4.3.3.2 Schematic checklist Table4-3-3-2 BUCK3 schematic checklist Pin Names Dir. Notes (Unit of parts size : inch) Check BUCK3 PVIN3 I PGND3 I LX3 O FB3 I Connect to VSYS. As decoupling capacitor, use one 4.7μF. Connect to Power GND. Connect one 0.47uH inductor to LX3. As output capacitors, use one 10uF capacitors. Connect to BUCK3 output voltage which is regulated by the DC/DC converter of BD71815AGW. BD71815AGW Design Guide Rev.1.30 22/31 4.3.3.3 Layout Example BUCK3 Figure 4-3-3-2 BUCK3 Layout Example (Top Layer) 4.3.4 BUCK4 BUCK4 is a high-efficiency single buck regulator with integrated FET that converts the VSYS voltage to a regulated voltage. 4.3.4.1 Schematic Example Figure 4-3-4-1 BUCK4 Schematic Example BD71815AGW Design Guide Rev.1.30 23/31 4.3.4.2 Schematic checklist Table4-3-4-2 BUCK4 schematic checklist Pin Names Dir. Notes (Unit of parts size : inch) Check BUCK4 PVIN4 I PGND4 I LX4 O FB4 I Connect to VSYS. As decoupling capacitor, use one 4.7μF. Connect to Power GND. Connect one 0.47uH inductor to LX4. As output capacitors, use one 10uF capacitors. Connect to BUCK4 output voltage which is regulated by the DC/DC converter of BD71815AGW. 4.3.4.3 Layout Example BUCK4 Figure 4-3-4-2 BUCK4 Layout Example (Top Layer) BD71815AGW Design Guide Rev.1.30 24/31 4.3.5 BUCK5 BUCK5 is a high-efficiency single buck regulator with integrated FET that converts the VSYS voltage to a regulated voltage. 4.3.5.1 Schematic Example Figure 4-3-5-1 BUCK5 Schematic Example 4.3.5.2 Schematic checklist Table4-3-5-2 BUCK5 schematic checklist Pin Names Dir. Notes (Unit of parts size : inch) Check BUCK5 PVIN5 I PGND5 I LX5 O FB5 I Connect to VSYS. As decoupling capacitor, use one 4.7μF. Connect to Power GND. Connect one 0.47uH inductor to LX5. As output capacitors, use one 10uF capacitors. Connect to BUCK5 output voltage which is regulated by the DC/DC converter of BD71815AGW. BD71815AGW Design Guide Rev.1.30 25/31 4.3.4.3 Layout Example BUCK5 Figure 4-3-5-2 BUCK5 Layout Example (Top Layer) BD71815AGW Design Guide Rev.1.30 26/31 4.3.6 LED Driver 4.3.6.1 Schematic Example Figure 4-3-6-1 LED Driver Schematic Example 4.3.6.2 Schematic checklist Table4-3-6-2 LED Driver schematic checklist Pin Names Dir. Notes (Unit of parts size : inch) Check LED Driver PVIN6 PGND6 I I HX6 / LX6 O VO6 FB6 O I Connect to VSYS. Connect to Power GND. Connect One 2.2uH inductor to HX6 / LX6. Connect Shottky Diode between LX6 and VO6. RB550VA-30TR (ROHM) Connect LEDs between VO6 and FB6 up to a maximum of 6pcs. 4.3.6.2 Layout An input capacitor dedicated to PVIN6 is not needed if the trace of PVIN6 is merged with the one of PVIN3 since PVIN6 can share the input capacitor of PVIN3. BD71815AGW Design Guide Rev.1.30 27/31 4.4 Linear VR 4.4.1 LDO1-5 / VODVREF / SNVSC 4.4.1.1 Schematic Examples Figure 4-4-1 LDO1-3 Schematic Example 4.4.1.2 Schematic checklist Table4-4-1 LDO1-3 schematic checklist Pin Names Dir. Notes (Unit of parts size : inch) Check LDO1-3 (Linear VR) VINL1 I VO1 VO2 VO3 O O O Connect to VSYS. As decoupling capacitors, As output capacitors, use As output capacitors, use As output capacitors, use use one 1.0μF. one 1.0uF capacitor. one 1.0uF capacitor. one 1.0uF capacitor. LDO for SD Card (Linear VR) VINL2 I VO4 VO5 O O Connect to VSYS. As decoupling capacitors, use one 1.0μF. As output capacitors, use one 2.2uF capacitor. As output capacitors, use one 1.0uF capacitor. LDO for DDR Reference Voltage (Linear VR) DVREFIN I VODVREF O Connect to BUCK4 As decoupling capacitors, use one 1.0μF. As output capacitors, use one 1.0uF capacitor. LDO for Secure Non-Volatile Storage (Linear VR) SNVSC O As output capacitors, use one 1.0uF capacitor. Connect a Coin cell backup battery via current limit resistor. LDO for Low-Power State Retention (Linear VR) VOLPSR O As output capacitors, use one 1.0uF capacitor. BD71815AGW Design Guide Rev.1.30 28/31 4.5 Interfaces 4.5.1 I2C Table4-5-1 Schematic checklist of I2C Pin Names Dir. Signal Voltage Level System Pull-up/Pull-down (RTT) Termination if it is not used Notes Check I2C DVDD I SCL I DVDD SDA I/O DVDD - Connect to BUCK3 (1.8V) or LDO2 (3.3V) depending on system requirement 2.2K Ohm pull-up to DVDD - Connect to SOC 2.2K Ohm pull-up to DVDD - Connect to SOC 4.5.2 GPO Table4-5-2 Schematic checklist of GPO Pin Names Dir. Signal Voltage Level System Pull-up/Pull-down (RTT) Termination if it is not used O SNVSC Needed for open drain mode (default) NC Notes Check Notes Check GPO GPO1 4.5.3 Charger, Coulomb counter, OVP Table4-5-3 Schematic checklist of Charger, Coulomb counter, OVP Pin Names Dir. Signal Voltage Level System Pull-up/Pull-down (RTT) Termination if it is not used Charger, Coulomb counter, OVP DCIN[2:0] I - As a decoupling capacitor, use one 1.0μF. VSYS[1:0] O - As an output capacitor, use one 10μF. VBAT I/O - As an output capacitor, use one 10μF. - Connect to gate of Pch MOSFET between VSYS and VBAT. 0.1uF cap is requested to insert between PGATE and the source of Pch MOSFET. RF4C050AP (ROHM) PGATE O CHGLED O NC CHGGND I GND CHGREF O 5.1K Ohm pull-up to CHGREF (NTC=10K Ohm) Connect to LED via current limit resistor Connect to Power GND. NC Connect to a thermistor via 10kΩ resistor NC Connect to Battery Thermistor TS I BATTP I GND BATTM I GND Connect to a current sense resistor (10mΩ) individually for accurate sensing. 0.1uF cap is requested to insert between BATTP and BATTM. Connect to a current sense resistor (10mΩ) individually for accurate sensing. 0.1uF cap is requested to insert between BATTP and BATTM. Note; An input capacitor dedicated to VIN is not needed if the trace of VIN is merged with the one of VSYS since VIN can share the output capacitor of VSYS. BD71815AGW Design Guide Rev.1.30 29/31 4.5.3.1 Schematic Example Figure 4-5-3-1 Charger Layout Example (Top Layer and 4th layer) 4.5.3.2 Layout Example Sense resistor BATTP BATTM Figure 4-5-3-2 Charger Layout Example (Top Layer and 4th layer) Note; Routings of BATTP and BATTM between PMIC and the sense resistor has to be independent for accurate sensing. To avoid any influence of common impedance of soldering, connecting BATTP and BATTM to inside pads of the sense resistor is recommended. BD71815AGW Design Guide Rev.1.30 30/31 4.5.4 RTC Table4-5-4 Schematic checklist of RTC Pin Names Dir. Signal Voltage Level System Pull-up/Pull-down (RTT) Termination if it is not used Notes Check RTC Connect to a crystal oscillator XIN I [SEIKO EPSON: FC-135 is chosen for a crystal oscillator] As input capacitor, use one 22pF. - [Other crystal oscillator is chosen] Please set the input capacitor value on enough matching validation. Connect to a crystal oscillator XOUT O [SEIKO EPSON: FC-135 is chosen for a crystal oscillator] As output capacitor, use one 22pF. - [Other crystal oscillator is chosen] Please set the output capacitor value on enough matching validation. CLK32KOUT Needed for open drain mode (default) O NC 4.5.5 System Control signals Table4-5-5 Schematic checklist of System Control signals Pin Names Dir. Signal Voltage Level System Pull-up/Pull-down (RTT) Termination if it is not used Notes Check Notes Check System Control - Reset, Power, and Control Signals RESETINB I Internal 10K Ohm pull-up to SNVSC NC PWRON I Internal 1.5M Ohm pull-down - Connect to SoC STANDBY I - Connect to SoC LDO4EN I - Connect to SoC LDO5SEL I - Connect to SoC O Needed pull-up resistor to DVDD - Connect to SoC O Needed pull-up resistor to DVDD - Connect to SoC WDOGB I Needed pull-up resistor to DVDD - Connect to SoC READY O Needed pull-up resistor to DVDD - Connect to SoC INTB POR 4.5.6 MISC Table4-5-6 Schematic checklist of MISC Pin Names Dir. Signal Voltage Level I GND System Pull-up/Pull-down (RTT) Termination if it is not used MISC GND[11:0] - Connect to GND plane BD71815AGW Design Guide Rev.1.30 31/31