Datasheet
Power Management Integrated Circuit
BD71850MWV
General Description
BD71850MWV is a programmable Power Management
IC (PMIC) for powering single-core, dual-core, and
quad-core SoC’s such as NXP-i.MX 8M Nano. It is
optimized for low BOM cost and compact solution
footprint. It integrates 6 Buck regulators and 6 LDO’s to
provide all the power rails required by the SoC and the
commonly used peripherals.
QFN package and pinout support low cost Type 3
(non-HDI) PCB. Programmable power sequencing
and output voltages, flexible power state control for
easier system design and supports a wide variety of
processors and system implementations.
Key Specifications
Input Voltage Range (VSYS):
SNVS State Current:
SUSPEND State Current:
IDLE State Current:
RUN State Current:
Operating Temperature Range:
Applications
Streaming Media Boxes and Dongles
AV Receivers and Wireless Sound Bars
Industrial HMI, SBC, IPC and Panel Computer
Package
Features
6 Buck Regulators
2.0 MHz Switching Frequency.
(BUCK1, BUCK2, BUCK5, BUCK7, and BUCK8).
1.5MHz Switching Frequency. (BUCK6)
Target Efficiency: 83% to 95%.
Output Current & Voltage.
BUCK1: 3.0 A, 0.7 V to 1.3 V/10 mV step, DVS
BUCK2: 3.0 A, 0.7 V to 1.3 V/10 mV step, DVS
BUCK5: 3.0 A, 0.70 V to 1.35 V/8steps, DVS
BUCK6: 3.0 A, 2.6 V to 3.3 V/100 mV step
BUCK7: 1.5 A, 1.605 V to 1.995 V/8steps
BUCK8: 3.0 A, 0.8 V to 1.4 V/10 mV step
6ch Linear Regulators (6 LDOs)
LDO1: 10 mA, 3.0 V to 3.3 V, 1.6 V to 1.9 V
LDO2: 10 mA, 0.9 V, 0.8 V
LDO3: 300 mA, 1.8 V to 3.3 V
LDO4: 250 mA, 0.9 V to 1.8 V
LDO5: 300 mA, 0.8 V to 3.3 V
LDO6: 300 mA, 0.9 V to 1.8 V
Power Mux Switch
1.8V Input: 500 mΩ(Max)
3.3V Input: 500 mΩ(Max)
32.768 kHz Crystal Oscillator Driver
Power Button Detector
Protection and Monitoring: Soft Start, Power Rails Fault
Detection, UVLO, OVP and TSD
OTP Configurable Power Sequencing
OTP and Software Programmable Output Voltage,
Ramp rates.
Hardware Signaling with SoC for Transition into or out
of Low Power States
Interfaces:
I2C: 100 kHz/400 kHz, 1 MHz
Power-on Reset Output: POR_B, RTC_RESET_B,
Watchdog Reset Input: WDOG_B:
Power State Control:
PMIC_STBY_REQ, PMIC_ON_REQ, PWRON_B
Interrupt to SoC: IRQ_B
Type3 PCB Applicable
2.7 V to 5.5 V
30 μA(Typ)
115 μA(Typ)
125 μA(Typ)
125 μA(Typ)
-40 °C to +105 °C
UQFN56BV7070
W(Typ) x D(Typ) x H(Max)
7.00 mm x 7.00 mm x 1.00 mm
Product structure : Silicon integrated circuit. This product has no designed protection against radioactive rays
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Contents
General Description ........................................................................................................................................................................ 1
Features.......................................................................................................................................................................................... 1
Key Specifications .......................................................................................................................................................................... 1
Applications .................................................................................................................................................................................... 1
Package
W(Typ) x D(Typ) x H(Max) ................................................................................................................ 1
1. Introduction............................................................................................................................................................................. 7
1.1.
Terminology .................................................................................................................................................................... 7
1.2.
System Power Map & Typical Application Circuit ........................................................................................................... 8
1.3.
Pin Configuration.......................................................................................................................................................... 10
1.4.
Pin Description ............................................................................................................................................................. 11
1.5.
I/O Equivalence Circuit................................................................................................................................................. 12
1.6.
Power Rail .................................................................................................................................................................... 13
1.7.
Register Map ................................................................................................................................................................ 14
1.8.
ESD.............................................................................................................................................................................. 16
2. Operating Conditions ............................................................................................................................................................ 17
2.1.
Absolute Maximum Ratings (Ta=25 ˚C)........................................................................................................................ 17
2.2.
Thermal Resistance ..................................................................................................................................................... 17
2.3.
Recommended Operating Conditions .......................................................................................................................... 18
2.4.
Current Consumption ................................................................................................................................................... 18
2.5.
Power Reference and Detectors (UVLO) ..................................................................................................................... 19
3. Power State Control ............................................................................................................................................................. 20
3.1.
Power Control Signals.................................................................................................................................................. 20
3.1.1.
PWRON_B........................................................................................................................................................... 21
3.1.2.
PMIC_ON_REQ ................................................................................................................................................... 21
3.1.3.
PMIC_STBY_REQ ............................................................................................................................................... 21
3.1.4.
WDOG_B ............................................................................................................................................................. 21
3.1.5.
RTC_RESET_B ................................................................................................................................................... 22
3.1.6.
POR_B................................................................................................................................................................. 22
3.2.
Power States ................................................................................................................................................................ 23
3.2.1.
Power State Diagram ........................................................................................................................................... 23
3.2.2.
Power State Register ........................................................................................................................................... 24
3.2.3.
Power State Definition ......................................................................................................................................... 26
3.2.4.
Power State Control Events ................................................................................................................................. 27
3.2.4.1.
Reset Event ................................................................................................................................................. 27
3.2.4.2.
Emergency Shutdown Event ....................................................................................................................... 29
3.2.5.
Power State Transitions ....................................................................................................................................... 29
3.2.5.1.
OFF to READY ............................................................................................................................................ 29
3.2.5.2.
READY to SNVS ......................................................................................................................................... 30
3.2.5.3.
SNVS to RUN .............................................................................................................................................. 33
3.2.5.4.
RUN to IDLE ................................................................................................................................................ 35
3.2.5.5.
IDLE to RUN................................................................................................................................................ 35
3.2.5.6.
RUN to SUSPEND ...................................................................................................................................... 35
3.2.5.7.
SUSPEND to RUN ...................................................................................................................................... 35
3.2.5.8.
IDLE to SUSPEND ...................................................................................................................................... 36
3.2.5.9.
Emergency Shutdown ................................................................................................................................. 36
3.2.5.10.
VR Fault ...................................................................................................................................................... 37
3.2.5.11.
EMG to OFF ................................................................................................................................................ 41
3.2.5.12.
EMG to READY ........................................................................................................................................... 42
3.2.5.13.
EMG_STAY Condition ................................................................................................................................. 43
3.2.5.14.
Warm Reset................................................................................................................................................. 43
3.2.5.15.
PWROFF ..................................................................................................................................................... 44
3.2.5.16.
PWROFF to READY.................................................................................................................................... 46
3.2.5.17.
PWROFF to SNVS ...................................................................................................................................... 46
3.2.5.18.
PWRON_B Functionality ............................................................................................................................. 46
3.3.
Power Sequence .......................................................................................................................................................... 48
3.3.1.
Power ON Sequence ........................................................................................................................................... 48
3.3.2.
Power OFF Sequence ......................................................................................................................................... 50
3.3.3.
RUN to IDLE ........................................................................................................................................................ 54
3.3.4.
IDLE to RUN ........................................................................................................................................................ 55
3.3.5.
RUN to SUSPEND ............................................................................................................................................... 56
3.3.6.
SUSPEND to RUN ............................................................................................................................................... 57
3.3.7.
IDLE to SUSPEND .............................................................................................................................................. 58
3.3.8.
Emergency Shutdown .......................................................................................................................................... 59
3.3.9.
Warm Reset ......................................................................................................................................................... 60
3.3.10.
Reset Source Indicators....................................................................................................................................... 61
4. I2C and Interrupt .................................................................................................................................................................. 62
4.1.
I2C Bus Interface ......................................................................................................................................................... 62
4.1.1.
I2C Bus Interface Overview ................................................................................................................................. 62
4.1.2.
I2C Bus Interface Electrical Characteristics ......................................................................................................... 63
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4.1.3.
Device Addressing ............................................................................................................................................... 65
4.1.4.
Write / Read Operation ........................................................................................................................................ 66
4.2.
Interrupt ........................................................................................................................................................................ 67
4.2.1.
Interrupt Overview ............................................................................................................................................... 67
5. Power Rails .......................................................................................................................................................................... 70
5.1.
Output Voltage Range .................................................................................................................................................. 70
5.2.
Details of Buck ............................................................................................................................................................. 72
5.2.1.
BUCK1 ................................................................................................................................................................. 72
5.2.1.1.
BUCK1 Block Diagram ................................................................................................................................ 72
5.2.1.2.
BUCK1 Electrical Characteristics ................................................................................................................ 73
5.2.1.3.
BUCK1 Control ............................................................................................................................................ 74
5.2.2.
BUCK2 ................................................................................................................................................................. 76
5.2.2.1.
BUCK2 Block Diagram ................................................................................................................................ 76
5.2.2.2.
BUCK2 Electrical Characteristics ................................................................................................................ 77
5.2.2.3.
BUCK2 Control ............................................................................................................................................ 78
5.2.3.
BUCK5 ................................................................................................................................................................. 80
5.2.3.1.
BUCK5 Block Diagram ................................................................................................................................ 80
5.2.3.2.
BUCK5 Electrical Characteristics ................................................................................................................ 81
5.2.3.3.
BUCK5 Control ............................................................................................................................................ 82
5.2.4.
BUCK6 ................................................................................................................................................................. 83
5.2.4.1.
BUCK6 Block Diagram ................................................................................................................................ 83
5.2.4.2.
BUCK6 Electrical Characteristics ................................................................................................................ 84
5.2.4.3.
BUCK6 Control ............................................................................................................................................ 85
5.2.5.
BUCK7 ................................................................................................................................................................. 86
5.2.5.1.
BUCK7 Block Diagram ................................................................................................................................ 86
5.2.5.2.
BUCK7 Electrical Characteristics ................................................................................................................ 87
5.2.5.3.
BUCK7 Control ............................................................................................................................................ 88
5.2.6.
BUCK8 ................................................................................................................................................................. 89
5.2.6.1.
BUCK8 Block Diagram ................................................................................................................................ 89
5.2.6.2.
BUCK8 Electrical Characteristics ................................................................................................................ 90
5.2.6.3.
BUCK8 Control ............................................................................................................................................ 91
5.3.
Details of LDO .............................................................................................................................................................. 92
5.3.1.
LDO1 ................................................................................................................................................................... 92
5.3.1.1.
LDO1 Block Diagram ................................................................................................................................... 92
5.3.1.2.
LDO1 Electrical Characteristics ................................................................................................................... 93
5.3.1.3.
LDO1 Control .............................................................................................................................................. 94
5.3.2.
LDO2 ................................................................................................................................................................... 95
5.3.2.1.
LDO2 Block Diagram ................................................................................................................................... 95
5.3.2.2.
LDO2 Electrical Characteristics ................................................................................................................... 96
5.3.2.3.
LDO2 Control .............................................................................................................................................. 96
5.3.3.
LDO3 ................................................................................................................................................................... 97
5.3.3.1.
LDO3 Block Diagram ................................................................................................................................... 97
5.3.3.2.
LDO3 Electrical Characteristics ................................................................................................................... 98
5.3.3.3.
LDO3 Control .............................................................................................................................................. 99
5.3.4.
LDO4 ................................................................................................................................................................. 100
5.3.4.1.
LDO4 Block Diagram ................................................................................................................................. 100
5.3.4.2.
LDO4 Electrical Characteristics ................................................................................................................. 101
5.3.4.3.
LDO4 Control ............................................................................................................................................ 102
5.3.5.
LDO5 ................................................................................................................................................................. 103
5.3.5.1.
LDO5 Block Diagram ................................................................................................................................. 103
5.3.5.2.
LDO5 Electrical Characteristics ................................................................................................................. 104
5.3.5.3.
LDO5 Control ............................................................................................................................................ 105
5.3.6.
LDO6 ................................................................................................................................................................. 106
5.3.6.1.
LDO6 Block Diagram ................................................................................................................................. 106
5.3.6.2.
LDO6 Electrical Characteristics ................................................................................................................. 107
5.3.6.3.
LDO6 Control ............................................................................................................................................ 108
5.4.
MUXSW ..................................................................................................................................................................... 109
5.4.1.
MUXSW Block Diagram ..................................................................................................................................... 109
5.4.2.
MUXSW Electrical Characteristics ..................................................................................................................... 110
6. 32.768 kHz Crystal Oscillator Driver ................................................................................................................................... 111
6.1.
32.768 kHz Crystal Oscillator Driver Block Diagram .................................................................................................. 111
6.2.
32.768 kHz Crystal Oscillator Driver Electrical Characteristics .................................................................................. 111
7. Operational Notes .............................................................................................................................................................. 112
8. Ordering Information........................................................................................................................................................... 114
9. Marking Diagram ................................................................................................................................................................ 114
10.
Physical Dimension and Packing Information ................................................................................................................ 115
11.
Revision History ............................................................................................................................................................. 116
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Figure
Figure 1-1. System Power Map ............................................................................................................................................... 8
Figure 1-2. Typical Applications Circuit .................................................................................................................................... 9
Figure 1-3. Pin Configuration (TOP VIEW) ............................................................................................................................ 10
Figure 1-4. I/O Equivalence Circuit 1 ..................................................................................................................................... 12
Figure 2-1. Power Reference and Detectors Block Diagram ................................................................................................. 19
Figure 3-1. Power Control Signals of BD71850MWV ............................................................................................................ 20
Figure 3-2. Power State Transition ........................................................................................................................................ 23
Figure 3-3. Power Sub State Definition.................................................................................................................................. 25
Figure 3-4. VSYS Condition for moving to SNVS .................................................................................................................. 30
Figure 3-5. PMIC_ON_REQ Condition for moving to SNVS .................................................................................................. 30
Figure 3-6. PWRON_B Short Push Condition for moving to SNVS ....................................................................................... 31
Figure 3-7. PWRON_B Long Push Condition for moving to SNVS ........................................................................................ 31
Figure 3-8. Cold Reset Condition for moving to SNVS .......................................................................................................... 31
Figure 3-9. VSYS Condition for moving to RUN .................................................................................................................... 33
Figure 3-10. PMIC_ON_REQ Condition for moving to RUN .................................................................................................. 33
Figure 3-11. PWRON_B Short Push Condition for moving to RUN ....................................................................................... 34
Figure 3-12. PWRON_B Long Push Condition for moving to RUN ........................................................................................ 34
Figure 3-13. Cold Reset Condition for moving to RUN .......................................................................................................... 34
Figure 3-14. Example of VR Fault and Recovery Sequence (RCVLMT[3:0] = 2) .................................................................. 41
Figure 3-15. EMG to OFF Power State Transition ................................................................................................................. 41
Figure 3-16. EMG to READY Power State Transition (VSYS_UVLO) ................................................................................... 42
Figure 3-17. EMG to READY Power State Transition (Die Temperature) .............................................................................. 42
Figure 3-18. Warm Reset by WDOG_B ................................................................................................................................. 43
Figure 3-19. Cold Reset Duration Time set by PONT[3:0] ..................................................................................................... 45
Figure 3-20. Power Button Block Diagram............................................................................................................................. 46
Figure 3-21. Power ON Sequence ......................................................................................................................................... 48
Figure 3-22. Power OFF Sequence (To SNVS) ..................................................................................................................... 50
Figure 3-23. Power OFF Sequence (To READY) .................................................................................................................. 52
Figure 3-24. RUN to IDLE...................................................................................................................................................... 54
Figure 3-25. IDLE to RUN...................................................................................................................................................... 55
Figure 3-26. RUN to SUSPEND ............................................................................................................................................ 56
Figure 3-27. SUSPEND to RUN ............................................................................................................................................ 57
Figure 3-28. IDLE to SUSPEND ............................................................................................................................................ 58
Figure 3-29. Emergency Shutdown ....................................................................................................................................... 59
Figure 3-30. Warm Reset (SWRESET) ................................................................................................................................. 60
Figure 3-31. Warm Reset (WDOG_B) ................................................................................................................................... 60
Figure 3-32. Warm Reset (PWRON_B Long Push) ............................................................................................................... 60
Figure 4-1. I2C (Slave) Block Diagram .................................................................................................................................. 62
Figure 4-2. I2C Bus Interface AC Timing ............................................................................................................................... 64
Figure 4-3. I2C Device Addressing ........................................................................................................................................ 65
Figure 4-4. I2C Write / Read Operation ................................................................................................................................. 66
Figure 4-5. IRQ_B Architecture Block Diagram ..................................................................................................................... 67
Figure 5-1. BUCK1 Block Diagram ........................................................................................................................................ 72
Figure 5-2. BUCK2 Block Diagram ........................................................................................................................................ 76
Figure 5-3. BUCK5 Block Diagram ........................................................................................................................................ 80
Figure 5-4. BUCK6 Block Diagram ........................................................................................................................................ 83
Figure 5-5. BUCK7 Block Diagram ........................................................................................................................................ 86
Figure 5-6. BUCK8 Block Diagram ........................................................................................................................................ 89
Figure 5-7. LDO1 Block Diagram ........................................................................................................................................... 92
Figure 5-8. LDO2 Block Diagram ........................................................................................................................................... 95
Figure 5-9. LDO3 Block Diagram ........................................................................................................................................... 97
Figure 5-10. LDO3 Voltage Source Switching ....................................................................................................................... 99
Figure 5-11. LDO4 Block Diagram ....................................................................................................................................... 100
Figure 5-12. LDO4 Voltage Source Switching ..................................................................................................................... 102
Figure 5-13. LDO5 Block Diagram ....................................................................................................................................... 103
Figure 5-14. LDO6 Block Diagram ....................................................................................................................................... 106
Figure 5-15. MUXSW Block Diagram .................................................................................................................................. 109
Figure 5-16. MUXSW Sequence ......................................................................................................................................... 110
Figure 6-1. 32.768 kHz Crystal Oscillator Driver Block Diagram ......................................................................................... 111
Figure 9-1. Marking Diagram ............................................................................................................................................... 114
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Table
Table 1-1. Acronyms, Conventions and Terminology ............................................................................................................... 7
Table 1-2. Pin Description ...................................................................................................................................................... 11
Table 1-3. Power Rails and Output Signals ........................................................................................................................... 13
Table 1-4. Register Map......................................................................................................................................................... 14
Table 1-5. REV - Revision Register ....................................................................................................................................... 14
Table 1-6. REGLOCK - Lock Register ................................................................................................................................... 15
Table 1-7. OTPVER – OTP Version Register ......................................................................................................................... 15
Table 1-8. ESD ...................................................................................................................................................................... 16
Table 2-1. Absolute Maximum Ratings................................................................................................................................... 17
(Note 1)
Table 2-2. Thermal Resistance
..................................................................................................................................... 17
Table 2-3. Recommended Operating Conditions ................................................................................................................... 18
Table 2-4. Current Consumption ............................................................................................................................................ 18
Table 2-5. Power Reference and Detectors Electrical Characteristics ................................................................................... 19
Table 3-1. PWRON_B Electrical Characteristics .................................................................................................................... 21
Table 3-2. PMIC_ON_REQ Electrical Characteristics ............................................................................................................ 21
Table 3-3. PMIC_STBY_REQ Electrical Characteristics ........................................................................................................ 21
Table 3-4. WDOG_B Electrical Characteristics ...................................................................................................................... 21
Table 3-5. RTC_RESET_B Electrical Characteristics ............................................................................................................ 22
Table 3-6. POR_B Electrical Characteristics.......................................................................................................................... 22
Table 3-7. POW_STATE – Power State Register................................................................................................................... 24
Table 3-8. Voltage Rails ON/OFF for Respective Power State .............................................................................................. 27
Table 3-9. Setting of Cold or Warm Reset Selection .............................................................................................................. 28
Table 3-10. SWRESET - Software Reset Register ................................................................................................................ 28
Table 3-11. PWRCTRL0 - Power Control 0 Register ............................................................................................................. 28
Table 3-12. Conditions from OFF to READY state ................................................................................................................. 29
Table 3-13. Conditions from READY to SNVS ....................................................................................................................... 30
Table 3-14. TRANS_COND0 - Transition Condition Select 0 Register .................................................................................. 32
Table 3-15. Conditions from SNVS to RUN ........................................................................................................................... 33
Table 3-16. Conditions from RUN to IDLE ............................................................................................................................. 35
Table 3-17. PWRCTRL1 - Power Control 1 Register ............................................................................................................. 35
Table 3-18. Conditions from IDLE to RUN ............................................................................................................................. 35
Table 3-19. Conditions from RUN to SUSPEND .................................................................................................................... 35
Table 3-20. Conditions from SUSPEND to RUN .................................................................................................................... 35
Table 3-21. Conditions from IDLE to SUSPEND .................................................................................................................... 36
Table 3-22. Conditions from SNVS, RUN, IDLE, SUSPEND, PWROFF to EMG ................................................................... 36
Table 3-23. VR FAULT threshold and monitoring condition.................................................................................................... 37
Table 3-24. VRFAULTEN - VR FAULT ON/OFF Register: Debugging Purpose ..................................................................... 38
Table 3-25. MVRFLTMASK0 - VR FAULT Mask 0 Register ................................................................................................... 38
Table 3-26. MVRFLTMASK1 - VR FAULT Mask 1 Register ................................................................................................... 39
Table 3-27. MVRFLTMASK2 - VR FAULT Mask 2 Register ................................................................................................... 39
Table 3-28. RCVCFG - Recovery Configuration Register ...................................................................................................... 40
Table 3-29. RCVNUM - Recovery Number Register .............................................................................................................. 40
Table 3-30. Conditions from EMG to OFF.............................................................................................................................. 41
Table 3-31. Conditions from EMG to READY ........................................................................................................................ 42
Table 3-32. Conditions for Stay at EMG................................................................................................................................. 43
Table 3-33. Conditions from RUN, IDLE, SUSPEND to PWROFF ........................................................................................ 44
Table 3-34. TRANS_COND1 - Transition Condition Select 1 Register .................................................................................. 44
Table 3-35. VR Summary After Power OFF Sequence .......................................................................................................... 45
Table 3-36. PWRONCONFIG0 - PWRON_B Configuration 0 Register.................................................................................. 46
Table 3-37. PWRONCONFIG1 - PWRON_B Configuration 1 Register.................................................................................. 47
Table 3-38. Power ON Sequence Timing Specification.......................................................................................................... 49
Table 3-39. Power OFF Sequence Timing Specification (To SNVS) ...................................................................................... 51
Table 3-40. Power OFF Sequence Timing Specification (To READY) ................................................................................... 53
Table 3-41. RUN to IDLE Timing Specification ...................................................................................................................... 54
Table 3-42. IDLE to RUN Timing Specification ...................................................................................................................... 55
Table 3-43. RUN to SUSPEND Timing Specification ............................................................................................................. 56
Table 3-44. SUSPEND to RUN Timing Specification ............................................................................................................. 57
Table 3-45. IDLE to SUSPEND Timing Specification ............................................................................................................. 58
Table 3-46. Emergency Shutdown Timing Specification ........................................................................................................ 59
Table 3-47. Warm Reset (SWRESET) Timing Specification .................................................................................................. 60
Table 3-48. Warm Reset (WDOG_B) Timing Specification .................................................................................................... 60
Table 3-49. Warm Reset (PWRON_B Long Push) Timing Specification ................................................................................ 60
Table 3-50. RESETSRC - Reset Source Indicator Register................................................................................................... 61
Table 4-1. I2C Bus Interface DC Electrical Characteristics .................................................................................................... 63
Table 4-2. I2C Bus Interface AC Timing - Fast Mode ............................................................................................................. 64
Table 4-3. I2C_DEV - I2C Device Address Indicator Register ............................................................................................... 65
Table 4-4. Interrupt Event ...................................................................................................................................................... 67
Table 4-5. IRQ_B Electrical Characteristics ........................................................................................................................... 67
Table 4-6. IRQ - Interrupt Register ......................................................................................................................................... 68
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Table 4-7. MIRQ – IRQ Mask Register .................................................................................................................................. 68
Table 4-8. IN_MON - Input Port Monitor Register .................................................................................................................. 69
Table 5-1. Output Voltage Range1 ......................................................................................................................................... 70
Table 5-2. Output Voltage Range2 ......................................................................................................................................... 71
Table 5-3. BUCK1 Electrical Characteristics .......................................................................................................................... 73
Table 5-4. BUCK1_CTRL - BUCK1 Control Register ............................................................................................................. 74
Table 5-5. BUCK1_VOLT_RUN - BUCK1 Voltage (RUN) Register ........................................................................................ 74
Table 5-6. BUCK1_VOLT_IDLE - BUCK1 Voltage (IDLE) Register ....................................................................................... 75
Table 5-7. BUCK1_VOLT_SUSP - BUCK1 Voltage (SUSPEND) Register ............................................................................ 75
Table 5-8. BUCK2 Electrical Characteristics .......................................................................................................................... 77
Table 5-9. BUCK2_CTRL - BUCK2 Control Register ............................................................................................................. 78
Table 5-10. BUCK2_VOLT_RUN - BUCK2 Voltage (RUN) Register ...................................................................................... 78
Table 5-11. BUCK2_VOLT_IDLE - BUCK2 Voltage (IDLE) Register...................................................................................... 79
Table 5-12. BUCK5 Electrical Characteristics ........................................................................................................................ 81
Table 5-13. BUCK5_CTRL - BUCK5 Control Register ........................................................................................................... 82
Table 5-14. BUCK5_VOLT - BUCK5 Voltage Register ........................................................................................................... 82
Table 5-15. BUCK6 Electrical Characteristics ........................................................................................................................ 84
Table 5-16. BUCK6_CTRL - BUCK6 Control Register ........................................................................................................... 85
Table 5-17. BUCK6_VOLT - BUCK6 Voltage Register ........................................................................................................... 85
Table 5-18. BUCK7 Electrical Characteristics ........................................................................................................................ 87
Table 5-19. BUCK7_CTRL - BUCK7 Control Register ........................................................................................................... 88
Table 5-20. BUCK7_VOLT - BUCK7 Voltage Register ........................................................................................................... 88
Table 5-21. BUCK8 Electrical Characteristics ........................................................................................................................ 90
Table 5-22. BUCK8_CTRL - BUCK8 Control Register ........................................................................................................... 91
Table 5-23. BUCK8_VOLT - BUCK8 Voltage Register ........................................................................................................... 91
Table 5-24. LDO1 Electrical Characteristics .......................................................................................................................... 93
Table 5-25. LDO1_VOLT - LDO1 Voltage Register ................................................................................................................ 94
Table 5-26. LDO2 Electrical Characteristics .......................................................................................................................... 96
Table 5-27. LDO2_VOLT - LDO2 Voltage Register ................................................................................................................ 96
Table 5-28. LDO3 Electrical Characteristics .......................................................................................................................... 98
Table 5-29. LDO3_VOLT - LDO3 Voltage Register ................................................................................................................ 99
Table 5-30. LDO4 Electrical Characteristics ........................................................................................................................ 101
Table 5-31. LDO4_VOLT - LDO4 Voltage Register .............................................................................................................. 102
Table 5-32. LDO5 Electrical Characteristics ........................................................................................................................ 104
Table 5-33. LDO5_VOLT - LDO5 Voltage Register .............................................................................................................. 105
Table 5-34. LDO6 Electrical Characteristics ........................................................................................................................ 107
Table 5-35. LDO6_VOLT - LDO6 Voltage Register .............................................................................................................. 108
Table 5-36. MUXSW Electrical Characteristics .................................................................................................................... 110
Table 5-37. SD_VSELECT Electrical Characteristics........................................................................................................... 110
Table 5-38. MUXSW Sequence Timing................................................................................................................................ 110
Table 5-39. MUXSW_EN - MUXSW Enable Register .......................................................................................................... 110
Table 6-1. C32K_OUT Control Register............................................................................................................................... 111
Table 6-2. 32.768 kHz Crystal Oscillator Driver Electrical Characteristics ........................................................................... 111
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1.
Introduction
1.1. Terminology
Term
Table 1-1. Acronyms, Conventions and Terminology
Definition
BOM
Bill Of Materials
DAC
DVS
Digital to Analog Converter
Dynamic Voltage Scaling
FET
I2C
Field Effect Transistor
Inter-Integrated Circuit
IRQ
LDO
Interrupt Request
Low Drop-Out regulator
NTC
OCP
Negative Temperature Coefficient. (a type of thermistor)
Over Current Protection
OTP
One Time Programmable memory
OVP
PFM
Over Voltage Protection
Pulse-Frequency Modulation
POR
PWM
Power On Reset
Pulse-Width Modulation
SMPS
SoC
Switched Mode Power Supply
System-On-a-Chip
UVLO
VR
Under Voltage-LockOut
Voltage Regulator
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1.2. System Power Map & Typical Application Circuit
BD71850MWV
VSYS(5V)
I2C I/F
i.MX8M Nano
BUCK1 – DVS
3.0 A, 0.7 V to 1.3 V
/10 mV step
0.8 V/0.9 V
BUCK2 – DVS
3.0 A, 0.7 V to 1.3 V
/10 mV step
0.8 V/0.9 V/ 1.0V
VDD_SOC
VDDA_0V8
PHY_0V8
VDD_DRAM
VDD_GPU
VDD_ARM
PWRON_B
PMIC_STBY_REQ
PMIC_ON_REQ
WDOG_B
HOST
I/F
RTC_RESET_B
BUCK5 - DVS
3.0 A, 0.70 V to 1.35 V
/ 8steps
POR_B
OFF
IRQ_B
BUCK8
3.0 A, 0.8 V to 1.4 V
/10 mV step
SD_VSELECT
C32K_OUT
XIN
XOUT
32kHz
Crystal
Driver
1.10 V/1.20 V/1.35 V
LDO1
10 mA, 3.0 V to 3.3 V
/1.6 V to 1.9 V
1.8V
LDO2
10 mA,
0.9 V/0.8 V
0.8V
BUCK6
3.0 A, 2.6 V to 3.3 V
/0.1 V step
NVCC_SNVS
3.3V
LDO3
300 mA,
1.8 V to 3.3 V
1.8V
LDO5
300 mA,
0.8 V to 3.3 V
OFF
BUCK7
1.5 A, 1.605 V to
1.995 V/ 8steps
1.8V
LDO4
250 mA,
0.9 V to 1.8 V
LDO6
300 mA,
0.9 V to 1.8 V
1.8V
150mA MUXSW
NVCC_DRAM
VDD_SNVS
NVCC_3V3
VDDA_1V8
VDDA_DRAM
NVCC_1V8
OFF
1.2V
VDD_PHY_1V2
(MIPI)
1.8V/3.3V(SD CARD)
3.3V
Figure 1-1. System Power Map
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1.2. System Power Map & Typical Application Circuit - continued
BD71850MWV
VDD_V1P5
VDD_V1P5
BUCK1
(VDD_SOC
VDDA_0V8
PHY_0V8
VDD_DRAM
VDD_GPU)
VSYS
VSYS
VDD_V1P5
BUCK1_VIN
VDD_V1P5
VSYS
VREF
BUCK1_LX
BUCK1
INTLDO1P5
AGND
VREF
Voltage
Reference
Buck Converter
DVS 0.7 V to 1.3 V / 3.0 A
Internal
Power On Reset
P GND
BUCK1_FB
UVLO
VDD_V1P5
VSYS
TSD
VSYS
BUCK2_VIN
Connect to the VSYS pin when not use the
Power Button Function
VREF
VDD_V1P5
VSYS
BUCK2
(VDD_ARM)
BUCK2_LX
BUCK2
CLOCK Generator
Buck Converter
DVS 0.7 V to 1.3 V / 3.0 A
PWRON_B
OTP
P GND
BUCK2_FB
Power ON Key
VDD_V1P5
XIN
XOUT
32.768 kHz
Crystal Oscillator Driver
VDD_V1P5
DVDD,VSYS
C32K_OUT
NVCC_SNVS
NVCC_SNVS
DVDD
SCL
I2C Slave Interface
SDA
NVCC_SNVS
POR_B
SOC
IRQ_B
RTC_RESET_B
Power Controll
PMIC_ON_REQ
PMIC_STBY_REQ
SD_VSELECT
WDOG_B
Register
Sequencer
VSYS
BUCK5_VIN
VSYS
VREF
VDD_V1P5
VSYS
VDD_V1P5
VSYS
BUCK5
BUCK5_LX
VSYS
BUCK5
VREF
LDO1_VOUT
LDO2
(VDD_SNVS)
LDO2_VOUT
(Note 1)
Buck Converter
DVS 0.7 V to 1.35 V / 3.0 A
LDO1
LDO1
(NVCC_SNVS)
3.0 V to 3.3 V, 1.6 V
to 1.9 V / 10 mA
P GND
LDO2
BUCK5_FB
0.9 V, 0.8V / 10 mA
VDD_V1P5
VSYS
BUCK6_VIN
VSYS/VIN_1P8
VSYS
VREF
VDD_V1P5
BUCK6
(NVCC_3V3)
BUCK6_LX
BUCK6
BUCK7
Buck Converter
2.6 V to 3.3 V / 3.0 A
VIN_1P8_1
LDO4
0.9 V to1.8 V
/ 250 mA
VSYS
VSYS
P GND
BUCK6_FB
VREF
LDO6
0.9 V to 1.8 V
/ 300 mA
LDO4
VDD_V1P5
VSYS
VSYS
BUCK7_VIN
LDO4_VOUT
(Note 1)
VREF
LDO6
(VDD_PHY_1V2)
LDO6_VOUT
BUCK7
VDD_V1P5
Buck Converter
1.605 V to 1.995 V / 1.5 A
VIN_1P8_2
MUXSW
P GND
1.8 V / 500 mΩ (Max)
3.3 V / 500 mΩ (Max)
LOADSW
(NVCC_SD2)
BUCK7
(NVCC_1V8)
BUCK7_LX
BUCK7
VSYS
BUCK7_FB
MUXSW_VOUT
VSYS/VIN_3P3
BUCK6
VDD_V1P5
VDD_V1P5
VSYS
VI N_3P3
BUCK8_VIN
VSYS
VREF
BUCK8_LX
VSYS
VSYS
VREF
LDO3
BUCK8
(NVCC_DRAM)
Buck Converter
0.8 V to 1.4 V / 3.0 A
1.8 V to 3.3 V
/ 300 mA
LDO3
(VDDA_1V8&VDDA_DRAM)
BUCK8
LDO5
LDO3_VOUT
0.8 V to 3.3 V
/ 300 mA
P GND
BUCK8_FB
LDO5
LDO5_VOUT
(Note 1)
P GND
PGND (EXP-PAD)
(Note 1) Output components of BUCK5, LDO4 and LDO5 can be removed because their default settings of OTP are OFF. Other power rails output components
cannot be removed. If they are removed, VR fault would be detected and PMIC would be shut down.
Figure 1-2. Typical Applications Circuit
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1.3. Pin Configuration
VSYS
PWRON_B
IRQ_B
BUCK8_FB
BUCK8_VIN
BUCK8_LX
BUCK8_LX
BUCK5_LX
BUCK5_LX
BUCK5_VIN
BUCK5_VIN
BUCK5_FB
C32K_OUT
42
41
40
39
38
37
36
35
34
33
32
31
30
29
EXP-PAD
LDO4_VOUT
EXP-PAD
VIN_1P8_1
43
28
DVDD
LDO6_VOUT
44
27
SDA
SD_VSELECT
45
26
SCL
BUCK6_FB
46
25
POR_B
BUCK6_VIN
47
24
BUCK2_FB
BUCK6_VIN
48
23
BUCK2_VIN
BUCK6_LX
49
22
BUCK2_LX
BUCK6_LX
50
21
BUCK2_LX
BUCK7_LX
51
20
BUCK1_LX
BUCK7_LX
52
19
BUCK1_LX
BUCK7_VIN
53
18
BUCK1_VIN
BUCK7_FB
54
17
BUCK1_FB
MUXSW_VOUT
55
16
PMIC_STBY_REQ
VIN_1P8_2
56
15
PMIC_ON_REQ
EXP-PAD
(PGND)
1Pin Mark
7
8
9
10
11
12
13
14
LDO2_VOUT
VSYS
LDO1_VOUT
INTLDO1P5
AGND
XOUT
XIN
6
VIN_3P3
RTC_RESET_B
5
LDO3_VOUT
WDOG_B
4
VSYS
3
LDO5_VOUT
2
VIN_3P3
EXP-PAD
1
EXP-PAD
Figure 1-3. Pin Configuration (TOP VIEW)
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1.4. Pin Description
Table 1-2. Pin Description
Pin#
18
19
20
17
23
21
22
24
31
32
33
34
30
47
48
49
50
46
53
51
52
54
37
35
36
38
9
10
8
43
41
42
44
7
5
6
4
1
56
55
11
12
14
13
28
26
27
29
39
25
3
2
15
16
45
40
-
Block Name
BUCK1
BUCK2
BUCK5
BUCK6
BUCK7
BUCK8
LDO1
LDO2
LDO4
LDO6
LDO3
LDO5
MUXSW
REF
Crystal
Oscillator
Interface
-
Pin Name
Dir
Pin Description
BUCK1_VIN
BUCK1_LX
BUCK1_LX
BUCK1_FB
BUCK2_VIN
BUCK2_LX
BUCK2_LX
BUCK2_FB
BUCK5_VIN
BUCK5_VIN
BUCK5_LX
BUCK5_LX
BUCK5_FB
BUCK6_VIN
BUCK6_VIN
BUCK6_LX
BUCK6_LX
BUCK6_FB
BUCK7_VIN
BUCK7_LX
BUCK7_LX
BUCK7_FB
BUCK8_VIN
BUCK8_LX
BUCK8_LX
BUCK8_FB
VSYS
LDO1_VOUT
LDO2_VOUT
VIN_1P8_1
VSYS
LDO4_VOUT
LDO6_VOUT
VIN_3P3
VSYS
LDO3_VOUT
LDO5_VOUT
VIN_3P3
VIN_1P8_2
MUXSW_VOUT
INTLDO1P5
AGND
XIN
XOUT
DVDD
SCL
SDA
C32K_OUT
IRQ_B
POR_B
RTC_RESET_B
WDOG_B
PMIC_ON_REQ
PMIC_STBY_REQ
SD_VSELECT
PWRON_B
I
O
O
I
I
O
O
I
I
I
O
O
I
I
I
O
O
I
I
O
O
I
I
O
O
I
I
O
O
I
I
O
O
I
I
O
O
I
I
O
O
I
I
O
I
I
I /O
O
O
O
O
I
I
I
I
I
EXP-PAD
(PGND)
-
BUCK1 switcher input supply
BUCK1 switch node connection
BUCK1 switch node connection
BUCK1 feedback sense
BUCK2 switcher input supply
BUCK2 switch node connection
BUCK2 switch node connection
BUCK2 feedback sense
BUCK5 switcher input supply
BUCK5 switcher input supply
BUCK5 switch node connection
BUCK5 switch node connection
BUCK5 feedback sense
BUCK6 switcher input supply
BUCK6 switcher input supply
BUCK6 switch node connection
BUCK6 switch node connection
BUCK6 feedback sense
BUCK7 switcher input supply
BUCK7 switch node connection
BUCK7 switch node connection
BUCK7 feedback sense
BUCK8 switcher input supply
BUCK8 switch node connection
BUCK8 switch node connection
BUCK8 feedback sense
LDO1, LDO2 input supply
LDO1 output
LDO2 output
LDO4, LDO6 input supply
LDO4 input supply
LDO4 output
LDO6 output
LDO3,MUXSW input supply
LDO3,LDO5 input supply
LDO3 output
LDO5 output
LDO3,MUXSW input supply
MUXSW input supply
LOADSW output
Internal LDO for PMIC
AGND
32.768kHz crystal input
32.768kHz crystal output
Interface input supply
I2C CLOCK
2
I C DATA
32.768kHz clock output
Interrupt signal to processor(Open Drain)
Power on reset output(Open Drain)
Power OK signal for LDO1,2(Open Drain)
Watchdog input from processor
Power on/off control Input
Standby input signal
Voltage select for SD
Power Button
Power Ground. Connect the center EXP-PAD in the Figure 1-3
to the GND plane of PCB. The EXP-PADs on the 4-corner have
the same potential as the center EXP-PAD. The EXP-PADs on
the 4-coner are recommended to be soldered to PCB (GND or
open).
PWR
/GND
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
GND
PWR
-
Voltage
Level
VSYS
VSYS
VSYS
BUCK1
VSYS
VSYS
VSYS
BUCK2
VSYS
VSYS
VSYS
VSYS
BUCK5
VSYS
VSYS
VSYS
VSYS
BUCK6
VSYS
VSYS
VSYS
BUCK7
VSYS
VSYS
VSYS
BUCK8
VSYS
LDO1
LDO2
BUCK7
VSYS
LDO4
LDO6
BUCK6
VSYS
LDO3
LDO5
BUCK6
BUCK7
LOADSW
INTLDO1P5
0V
INTLDO1P5
INTLDO1P5
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
VSYS
DVDD
DVDD
VSYS
Terminal
Equivalent
H1_1
H1_1
H1_1
D2_1
H1_1
H1_1
H1_1
D2_1
H1_1
H1_1
H1_1
H1_1
D2_1
H1_1
H1_1
H1_1
H1_1
D2_1
H1_1
H1_1
H1_1
D2_1
H1_1
H1_1
H1_1
D2_1
G1_1
G1_1
G1_1
G1_2,G3_1
G1_1,G3_1
G3_1
G1_2
G3_2
G1_1,G3_2
G3_2
G1_1
F2_1
F2_1
F2_1
G1_3
Z1_1
E1_1
E1_1
Z1_1
A1_1
A3_1
C1_1
C1_1
C1_1
C1_1
C1_1
A6_1
C1_1
C1_1
A6_1
Internal
pull-up/down
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No(Note 1)
(Note 1)
No
No
(Note 1)
No
No(Note 1)
(Note 1)
No
No
No
No
No
No
GND
0V
Z1_1
No
(Note 1) Need to pull-up external resistance to DVDD
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1.5. I/O Equivalence Circuit
VDD
VDD
A1_1)
VDD=DVDD
GND=AGND
VDD
A3_1)
VDD=DVDD
GND=AGND
A6_1)
VDD=VSY S
GND
GND GND
GND
GND
(A1_1)
GND
GND
(A3_1)
VDD
C1_1)
VDD=DVDD
GND=AGND
(A6_1)
D2_1)
GND=AGND
E1_1)
VDD=INTLDO1P5
GND=AGND
VDD
VDD
XOUT
XIN
GND GND
GND GND
(C1_1)
GND
(D2_1)
F2_1)
IN1=VIN_3P3
IN2=VIN_1P8_2
OUT
=MUXSW_VOUT
IN1
AGND
G1_1)
VDD=VSY S
GND=AGND
OUT=LDO1,LDO2,
LDO5
G1_2)
VDD=VIN_1P8_1
GND=AGND
OUT=LDO6
G1_3)
VDD=VSY S
GND=AGND
OUT=INTLDO1P5
VDD
GND
GND
OUT
OUT
IN2
GND
GND
(E1_1)
VDD1
G3_1)
VDD1=VSY S
VDD2=VIN_1P8_1
GND=AGND
OUT=LDO4
G3_2)
VDD1=VSY S
VDD2=VIN_3P3
GND=AGND
OUT=LDO3
GND
VDD2
GND
OUT
GND
GND
GND
GND
GND
(F2_1)
H1_1)
VDD=BUCK1_VIN,
BUCK2_VIN,
BUCK5_VIN
to BUCK8_VIN
LX =BUCK1_LX,
BUCK2_LX,
BUCK5_LX
to BUCK8_LX
GND=PGND
AGND
(G1_1,2,3)
VDD
GND
AGND
(G3_1,2)
BUCK1_VIN, BUCK2_VIN,
BUCK5_VIN to BUCK8_VIN
DVDD
INTLDO1P5
LX
VSY S
PGND
AGND
GND
(H1_1)
(Z1_1)
Figure 1-4. I/O Equivalence Circuit 1
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1.6. Power Rail
Table 1-3. Power Rails and Output Signals
Sequence
Order
Function
Rail/Signal
Name
Type
Input
Rail
Output Voltage
Initial
Value [V]
Output Voltage
Adjustable
Range [V]
DVS
IOMAX [A]
1
NVCC_SNVS
LDO1
Source LDO
VSYS
1.8
3.0 to 3.3,1.6 to 1.9
(100 mV step)
-
0.01
2
VDD_SNVS
LDO2
Source LDO
VSYS
0.8
0.9, 0.8
-
0.01
3
RTC_RESET_B
RTC_RESET_B
Open drain
-
-
-
-
-
4
32K_OUT
C32K_OUT
CMOS
DVDD
-
-
-
-
5
VDD_SOC,
VDDA_0V8,
PHY_0V8,
VDD_DRAM,
VDD_GPU
BUCK1
SMPS
VSYS
0.8
0.7 to 1.3
(10 mV step)
DVS
3.0
6
VDD_ARM
BUCK2
SMPS
VSYS
0.9
DVS
3.0
6
VDDA_1V8,
VDDA_DRAM
LDO3
Source LDO
VSYS/
BUCK6
1.8
-
0.3
7
NVCC_1V8
BUCK7
SMPS
VSYS
1.8
-
1.5
8
NVCC_DRAM
BUCK8
SMPS
VSYS
1.1
-
3.0
9
NVCC_3V3
BUCK6
SMPS
VSYS
3.3
-
3.0
9
NVCC_SD2
MUXSW
MUX Switch
BUCK6/
BUCK7
3.3/1.8
-
-
0.15
10
VDD_PHY_1V2
LDO6
Source LDO
BUCK7
1.2
0.9 to 1.8
(100 mV step)
-
0.3
11
POR_B
POR_B
Open drain
-
-
-
-
-
-
-
BUCK5
SMPS
VSYS
0.9
DVS
3.0
-
-
LDO4
Source LDO
VSYS/
BUCK7
0.9
-
0.25
-
-
LDO5
Source LDO
VSYS
3.3
-
0.3
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0.7 to 1.3
(10 mV step)
1.8 to 3.3
(100 mV step)
1.605,1.695,1.755,
1.800,1.845,1.905,
1.950,1.995
0.8 to 1.4
(10 mV step)
2.6 to 3.3
(100mVstep)
0.70,0.80,0.90,1.00
1.05,1.10,1.20,1.35
0.9 to 1.8
(100 mV step)
0.8 to 3.3
(100 mV step)
TSZ02201-0Q2Q0A500680-1-2
16.Mar.2020 Rev.002
BD71850MWV
1.7. Register Map
Table 1-4. Register Map
Reset
Address
Condition
(Hex)
(Note 1)
00
01
02
03
04
05
06
07
NA
UVLO
UVLO
UVLO
UVLO
READY
READY
-
Register Nam e
D7
REV
SWRESET
I2C_DEV
PWRCTRL0
PWRCTRL1
BUCK1_CTRL
BUCK2_CTRL
-
D6
D5
D4
D3
D2
RELOAD_REG
-
-
BUCK1_PWM_FIX
BUCK2_PWM_FIX
-
-
MAJREV[3:0]
DEBUG_STATE[1:0]
BUCK1_RAMPRATE[1:0]
BUCK2_RAMPRATE[1:0]
-
D1
D0
MINREV[3:0]
SWRESET_SEL[1:0]
SWRESET
I2C_DEV_ADRS[1:0]
WDOGB_SEL[1:0]
IDLE_MODE
BUCK1_SEL
BUCK1_EN
BUCK2_SEL
BUCK2_EN
-
Initial
Value
(Hex)
Access
(R, W, R/W)
OTP
A1
04
03
A2
00
40
40
-
R
R/W
R
R/W
R/W
R/W
R/W
-
No
No
Yes
Yes
Yes
Yes
Yes
-
Write
Access
Lock
(Note 2)
PWRSEQ
VREG
VREG
-
08
-
-
-
-
-
-
-
-
-
-
-
-
-
-
09
READY
BUCK5_CTRL
-
-
-
-
BUCK5_PWM_FIX
-
BUCK5_SEL
BUCK5_EN
02
R/W
Yes
VREG
0A
READY
BUCK6_CTRL
-
-
-
-
BUCK6_PWM_FIX
-
BUCK6_SEL
BUCK6_EN
00
R/W
Yes
VREG
0B
READY
BUCK7_CTRL
-
-
-
-
BUCK7_PWM_FIX
-
BUCK7_SEL
BUCK7_EN
00
R/W
Yes
VREG
0C
READY
BUCK8_CTRL
-
-
-
-
BUCK8_PWM_FIX
-
BUCK8_SEL
BUCK8_EN
00
R/W
Yes
VREG
0D
READY
BUCK1_VOLT_RUN
-
BUCK1_VOLT_RUN[6:0]
0A
R/W
Yes
VREG
0E
READY
BUCK1_VOLT_IDLE
-
BUCK1_VOLT_IDLE[6:0]
0A
R/W
Yes
VREG
0F
READY
BUCK1_VOLT_SUSP
-
BUCK1_VOLT_SUSP[6:0]
0A
R/W
Yes
VREG
10
READY
BUCK2_VOLT_RUN
-
BUCK2_VOLT_RUN[6:0]
14
R/W
Yes
VREG
11
READY
BUCK2_VOLT_IDLE
-
0A
R/W
Yes
VREG
12
13
-
-
-
-
-
-
-
14
READY
BUCK5_VOLT
BUCK5_VOLT[2:0]
02
R/W
Yes
VREG
15
16
READY
READY
BUCK6_VOLT
BUCK7_VOLT
-
BUCK6_VOLT[1:0]
BUCK7_VOLT[2:0]
03
03
R/W
R/W
Yes
Yes
VREG
VREG
17
READY
BUCK8_VOLT
-
1E
R/W
Yes
VREG
18
19
1A
1B
1C
1D
1E
READY
READY
READY
READY
READY
READY
-
LDO1_VOLT
LDO2_VOLT
LDO3_VOLT
LDO4_VOLT
LDO5_VOLT
LDO6_VOLT
-
R/W
R/W
R/W
R/W
R/W
R/W
-
Yes
Yes
Yes
Yes
Yes
Yes
-
VREG
VREG
VREG
VREG
VREG
VREG
-
UVLO
TRANS_COND0
LDO1_EN
LDO2_EN
LDO3_EN
LDO4_EN
LDO5_EN
LDO6_EN
C1_
PMIC_ON_
REQ_EN
22
20
00
80
8F
03
-
1F
LDO1_SEL
LDO2_SEL
LDO3_SEL
LDO4_SEL
LDO5_SEL
LDO6_SEL
C1_
VSYS_3P0_
ONLY_EN
48
R/W
Yes
PWRSEQ
20
UVLO
TRANS_COND1
C0
R/W
Yes
PWRSEQ
21
UVLO
VRFAULTEN
MBUCK7_
VOUTOKL
Yes
-
MVRFLTMASK0
MBUCK7_
VOUTOKH
R/W
UVLO
MBUCK8_
VOUTOKL
01
22
MBUCK8_
VOUTOKH
00
R/W
Yes
-
23
UVLO
MVRFLTMASK1
-
-
-
-
00
R/W
Yes
-
24
UVLO
MVRFLTMASK2
-
00
R/W
Yes
-
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
UVLO
UVLO
UVLO
UVLO
UVLO
UVLO
UVLO
UVLO
UVLO
READY
READY
READY
RCVCFG
RCVNUM
PWRONCONFIG0
PWRONCONFIG1
RESETSRC
MIRQ
IRQ
IN_MON
POW_STATE
OUT32K
REGLOCK
MUXSW_EN
4C
00
16
00
00
7F
00
00
00
01
11
01
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R/W
R/W
R/W
Yes
No
Yes
Yes
No
No
No
No
No
Yes
No
Yes
-
FF
NA
OTPVER
C3
R
Yes
-
BUCK2_VOLT_IDLE[6:0]
-
BUCK5_VOLT_SEL[1:0]
BUCK6_VOLT_SEL
-
-
-
-
-
-
-
-
-
-
-
-
-
-
BUCK8_VOLT[6:0]
LDO1_VOLT_SEL
LDO2_VOLT_SEL
LDO5_VOLT_SEL
C1_
SHORT_
PUSH_EN
C1_
LONG_
PUSH_EN
-
MLDO6_
MLDO5_
VOUTOKL
VOUTOKL
RCVLMT[3:0]
PBDBNCT[1:0]
RWDOG
RSWRST
RPMIC_ON_REQ
MSWRST
MPWRON_S
MPWRON_L
SWRST
PWRON_S
PWRON_L
POW_ST[3:0]
VREG
-
-
LDO1_VOLT[1:0]
LDO3_VOLT[3:0]
LDO4_VOLT[3:0]
LDO5_VOLT[3:0]
LDO6_VOLT[3:0]
C0_
C0_
C0_
PMIC_ON_
SHORT_
LONG_
REQ_EN
PUSH_EN
PUSH_EN
WDOG_
SWRST_
ON_REQ_
POFF_TO_
POFF_TO_
POFF_TO_
READY
READY
READY
VRFLTEN
MBUCK6_
MBUCK5_
MBUCK5_
VOUTOKL
VOUTOKH
VOUTOKL
MBUCK2_
MBUCK1_
MBUCK1_
VOUTOKL
VOUTOKH
VOUTOKL
MLDO3_
MLDO2_
MLDO1_
VOUTOKL
VOUTOKL
VOUTOKL
RCVDT[3:0]
RCVNUM[3:0]
SHORTT[3:0]
LONGT[3:0]
RTEMP
ROCP
RVR_FAULT
MWDOG
MON_REQ
MSTBY_REQ
WDOG
ON_REQ
STBY_REQ
STAT_WDOG
STAT_ON_REQ
STAT_STBY_REQ
POW_SUB[1:0]
OUT32K_EN
PWRSEQ
MUXSW_EN
C0_
VSYS_3P0_
ONLY_EN
PWRON_
POFF_TO_
READY
MBUCK6_
VOUTOKH
MBUCK2_
VOUTOKH
MLDO4_
VOUTOKL
PONT[3:0]
RPWRON
-
-
RVSYS_2P7
MPWRON
PWRON
STAT_PWRON
OTPVER[7:0]
(Note 1) Reset Condition of each register is classified as follow s.
UVLO: When INTLDO1P5_UVLO=0, register values are reset to the default value.
READY: When Pow er State enters READY, register values are reset to the default value.
(Note 2) Regarding registes labeled in this column, its w rite access is disabled as follow s.
PWRSEQ: When PWRSEQ in REGLOCK register is set to 1, w rite access is disabled.
VREG: When VREG in REGLOCK register is set to 1, w rite access is disabled.
Table 1-5. REV - Revision Register
Register Name
R/W
REV
R
D7
D6
D5
D4
D3
D2
MAJREV[3:0]
D1
MINREV[3:0]
Initial
Address
0xA1
0x00
Bit
Name
D[7:4]
MAJREV[3:0]
Major Revision
1010
D[3:0]
MINREV[3:0]
Minor Revision
0001
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1.7.
Register Map – continued
Table 1-6. REGLOCK - Lock Register
Register Name
R/W
D7
D6
D5
D4
D3
D2
D1
D0
Initial
Address
REGLOCK
R/W
-
-
-
VREG
-
-
-
PWRSEQ
0x11
0x2F
Bit
Name
D[4]
VREG
Function
Write access to following 21 registers is controlled by this bit.
0 = Enable the write access
1 = Disable the write access
BUCK1_CTRL, BUCK2_CTRL,
BUCK5_CTRL, BUCK6_CTRL, BUCK7_CTRL, BUCK8_CTRL
BUCK1_VOLT_RUN, BUCK1_VOLT_IDLE
BUCK1_VOLT_SUSP, BUCK2_VOLT_RUN
BUCK2_VOLT_IDLE, BUCK5_VOLT, BUCK6_VOLT, BUCK7_VOLT
BUCK8_VOLT, LDO1_VOLT, LDO2_VOLT, LDO3_VOLT
LDO4_VOLT, LDO5_VOLT, LDO6_VOLT
1
Write access to following 3 registers is controlled by this bit.
0 = Enable the write access
1 = Disable the write access
PWRSEQ
D[0]
Initial
1
PWRCTRL0, TRANS_COND0, TRANS_COND1
Table 1-7. OTPVER – OTP Version Register
Register Name
R/W
OTPVER
R
D7
D6
D5
D4
D3
D2
OTPVER[7:0]
Bit
Name
D[7:0]
OTP_VER[7:0]
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Function
OTP Version
D1
D0
Initial
Address
0xC3
0xFF
Initial
0xC3
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1.8. ESD
Table 1-8. ESD
Minimum
Parameter
Limit
Unit
Human Body Model(HBM)
±2000
V
Charged Device Model(CDM)
±1000
V
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2.
Operating Conditions
2.1. Absolute Maximum Ratings (Ta=25 ˚C)
Table 2-1. Absolute Maximum Ratings
Parameter
Limit
Symbol
Voltage Range in PINs:
VSYS, BUCK1_VIN, BUCK2_VIN, BUCK5_VIN to BUCK8_VIN,
VIN_1P8_1, VIN_1P8_2, VIN_3P3, PWRON_B, PMIC_ON_REQ
Voltage Range in PIN:
DVDD
Voltage Range in PIN:
INTLDO1P5
Voltage Range in PINs:
BUCK1_LX, BUCK2_LX, BUCK5_LX to BUCK8_LX
Voltage Range in PINs:
SCL,SDA,IRQ_B,POR_B,WODG_B, RTC_RESET_B
PMIC_STBY_REQ,SD_VSELECT,C32K_OUT
Voltage Range in PINs:
BUCK1_FB, BUCK2_FB, BUCK5_FB to BUCK8_FB,
LDO1_VOUT to LDO6_VOUT, MUXSW_VOUT
Voltage Range in PINs:
XIN, XOUT
Maximum Junction Temperature
Storage Temperature Range
Unit
Min
Max
VAMR_1
-0.3
+6.0
V
VAMR_2
-0.3
+4.5
V
VAMR_3
-0.3
+2.1
V
VAMR_4
-1.0(DC)
-2.0(10 ns)
+7.0
V
VAMR_5
-0.3
+4.5
V
VAMR_6
-0.3
+4.5
V
VAMR_7
-0.3
+2.1
V
Tjmax
-
150
°C
Tstg
-55
+150
°C
Caution 1: Operating the IC over the absolute maximum ratings may damage the IC. The damage can either be a short circuit between pins or an open circuit
between pins and the internal circuitry. Therefore, it is important to consider circuit protection measures, such as adding a fuse, in case the IC is
operated over the absolute maximum ratings.
Caution 2: Should by any chance the maximum junction temperature rating be exceeded the rise in temperature of the chip may result in deterioration of the
properties of the chip. In case of exceeding this absolute maximum rating, design a PCB with thermal resistance taken into consideration by increasing
board size and copper area so as not to exceed the maximum junction temperature rating.
2.2. Thermal Resistance
Table 2-2. Thermal Resistance
Parameter
Symbol
(Note 1)
Thermal Resistance (Typ)
1s
(Note 3)
2s2p
(Note 4)
Unit
UQFN56BV7070
Junction to Ambient
Junction to Top Characterization Parameter
(Note 2)
θJA
76.8
28.1
°C/W
ΨJT
6
6
°C/W
(Note 1) Based on JESD51-2A(Still-Air).
(Note 2) The thermal characterization parameter to report the dif f erence between junction temperature and the temperature at the top center of the outside
surf ace of the component package.
(Note 3) Using a PCB board based on JESD51-3.
(Note 4) Using a PCB board based on JESD51-5, 7.
Layer Number of
Measurement Board
Material
Board Size
Single
FR-4
114.3mm x 76.2mm x 1.57mmt
Top
Copper Pattern
Thickness
Footprints and Traces
70μm
Layer Number of
Measurement Board
Material
Board Size
4 Layers
FR-4
114.3mm x 76.2mm x 1.6mmt
(Note 6)
Top
Thermal Via
Pitch
Diameter
2 Internal Layers
Φ0.30mm
1.20mm
Bottom
Copper Pattern
Thickness
Copper Pattern
Thickness
Copper Pattern
Thickness
Footprints and Traces
70μm
74.2mm x 74.2mm
35μm
74.2mm x 74.2mm
70μm
(Note 5) This thermal v ia connects with the copper pattern of all lay ers.
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2.3. Recommended Operating Conditions
Table 2-3. Recommended Operating Conditions
Parameter
Limit
Symbol
Voltage Range in PINs:
VSYS, BUCK1_VIN, BUCK2_VIN,
BUCK5_VIN to BUCK8_VIN (Note 1)
Voltage Range in PIN:
(Note 2)
VIN_3P3
Voltage Range in PIN:
(Note 3)
VIN_1P8_1
Voltage Range in PIN:
VIN_1P8_2 (Note 3)
Voltage Range in PIN:
DVDD
Operating Temperature
Unit
Min
Typ
Max
VOPR_1
2.70
5.00
5.50
V
VOPR_2
2.70
3.30
3.60
V
VOPR_3
1.71
1.80
5.50
V
VOPR_4
1.71
1.80
1.89
V
VOPR_5
1.71
1.80
3.60
V
Topr
-40
+25
+105
°C
(Note 1) It is necessary to supply the same v oltage to the VSY S pin and the BUCK1_VIN, BUCK2_VIN, and BUCK5_VIN to BUCK8_VIN pins.
(Note 2) The VIN_3P3 pin is recommended to connect with BUCK6 outputs.
(Note 3) The VIN_1P8_1 pin and the VIN_1P8_2 pin are recommended to connect with BUCK7 outputs.
2.4. Current Consumption
Table 2-4. Current Consumption
(Unless otherwise specified, Ta=+25 °C, VSYS=5.0 V, DVDD=1.8 V)
Parameter
Symbol
Limit
Min
Typ
Max
Unit
Condition
VSYS Circuit Current 1
IQ_VSYS1
-
14
23
μA
READY State
VSYS Circuit Current 2
VSYS Circuit Current 3
VSYS Circuit Current 4
VSYS Circuit Current 5
DVDD Circuit Current 1
IQ_VSYS2
IQ_VSYS3
IQ_VSYS4
IQ_VSYS5
IQ_DVDD1
-
30
115
125
125
-
50
180
185
185
2
μA
μA
μA
μA
μA
DVDD Circuit Current 2
IQ_DVDD2
-
4
-
μA
SNVS State (Note 1)
SUSPEND State (Note 1)
IDLE State (Note 1)
Run State (Note 1)
DVDD static current (OUT32K_EN=0)
DVDD oparation current (OUT32K_EN=1)
(Note 1)
(Note 2)
(Note 1) When DVDD is connected with LDO1, total circuit current is the v alue that added VSY S and DVDD circuit current of this table.
(Note 2) This circuit current is af f ected by parasitic capacitance of the board.
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2.5. Power Reference and Detectors (UVLO)
VSYS
VDD_V1P5
+
VDD_V1P5
INTLDO1P5
Ref
Sequencer
-
VSYS
+
VSYS
INTLDO1P5_UVLO
+
VSYS_UVLO
VDD_V1P5
Thermal
Sensor
+
Debounce
Alert Temp Detect
Figure 2-1. Power Reference and Detectors Block Diagram
Table 2-5. Power Reference and Detectors Electrical Characteristics
(Unless otherwise specified, Ta=+25 °C, VSYS=5.0 V)
Parameter
Symbol
Limit
Min
Typ
Max
Unit
Remarks
Voltage Detector - VSYS under voltage(VSYS_UVLO)
Release Voltage
VUVLORL
2.65
3.00
3.35
V
VSYS=Sweep up
Detect Voltage
VUVLODT
2.65
2.70
2.75
V
VSYS =Sweep down
Hysteresis Voltage
VUVLOHYS
0.3
Voltage Detector - INTLDO1P5 under voltage(INTLDO1P5_UVLO)
-
V
Release Voltage
1.39
-
V
VSYS=Sweep up
Detect Voltage
VINTUVLODT
1.35
PMIC Die Critical Temperature Detector (Thermal Shutdown factor)
-
V
VSYS =Sweep down
Detect Temperature
Power Reference
TCTD
-
150
-
°C
INTLDO1P5 Output Voltage
VLDO15
-
1.5
-
V
CO_LDO15
0.5
1.0
5.0
μF
COUT Capacitor
VINTUVLORL
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Die Temperature=Sweep up
This output voltage is for internal
use only.
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3.
Power State Control
3.1. Power Control Signals
VSYS
[Internal Logic Circuit]
VSYS
Ena ble sig nal for
PWRON_B
PWRON_B
VR
(BUCK1,BUCK2,
BUCK5 to B UCK8)
(LDO1 to L DO6)
VSYS
PMIC_ON_REQ
POR_B
DVDD
PMIC_STBY_REQ
GND
RTC_RESET_B
WDOG_B
GND
Figure 3-1. Power Control Signals of BD71850MWV
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3.1.1. PWRON_B
PWRON_B is an active-low input for triggering the system to power on or off. Normally, PWRON_B is connected to a
power button.
Table 3-1. PWRON_B Electrical Characteristics
(Unless otherwise specified, Ta= +25°C, VSYS=5.0 V, DVDD=1.8 V)
Limit
Parameter
Symbol
Min
Typ
Max
Input "H" Level
VIH_PWRON
1.44
Input "L" Level
VIL_PWRON
0.40
Unit
Condition
V
V
3.1.2. PMIC_ON_REQ
PMIC_ON_REQ is an active-high input for going to RUN state.
Table 3-2. PMIC_ON_REQ Electrical Characteristics
(Unless otherwise specified, Ta= +25°C, VSYS=5.0 V, DVDD=1.8 V)
Limit
Parameter
Symbol
Min
Typ
Max
Input "H" Level
VIH_ONREQ
1.44
Input "L" Level
VIL_ONREQ
0.40
Unit
Condition
V
V
3.1.3. PMIC_STBY_REQ
PMIC_STBY_REQ is an active-high input for going to SUSPEND state.
Table 3-3. PMIC_STBY_REQ Electrical Characteristics
(Unless otherwise specified, Ta= +25 °C, VSYS=5.0 V, DVDD=1.8 V)
Limit
Parameter
Symbol
Min
Typ
Max
Input "H" Level
VIH_STBYREQ
DVDD x 0.75
Input "L" Level
VIL_STBYREQ
DVDD x 0.25
Unit
Condition
V
V
3.1.4. WDOG_B
WDOG_B is an active-low input for triggering Cold Reset or Warm Reset.
Table 3-4. WDOG_B Electrical Characteristics
(Unless otherwise specified, Ta= +25 °C, VSYS=5.0 V, DVDD=1.8 V)
Limit
Parameter
Symbol
Min
Typ
Max
Input "H" Level
VIH_WDOG
DVDD x 0.75
Input "L" Level
VIL_WDOG
DVDD x 0.25
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Unit
Condition
V
V
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16.Mar.2020 Rev.002
BD71850MWV
3.1.5. RTC_RESET_B
RTC_RESET_B is an active-low output for RTC.
Table 3-5. RTC_RESET_B Electrical Characteristics
(Unless otherwise specified, Ta= +25 °C, VSYS=5.0 V, DVDD=1.8 V)
Limit
Parameter
Symbol
Min
Typ
Max
Output "L" Level Voltage
VOL_RTCRESET
DVDD x 0.2
Output Off Leak Current
IOLK_RTCRESET
-1
+1
Unit
Condition
V
μA
IOL=3 mA Sink
Unit
Condition
V
μA
IOL=3 mA Sink
3.1.6. POR_B
POR_B is an active-low output for the reset of SoC.
Table 3-6. POR_B Electrical Characteristics
(Unless otherwise specified, Ta= +25 °C, VSYS=5.0 V, DVDD=1.8 V)
Limit
Parameter
Symbol
Min
Typ
Max
Output "L" Level Voltage
VOL_POR
DVDD x 0.2
Output Off Leak Current
IOLK_POR
-1
+1
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3.2. Power States
3.2.1. Power State Diagram
BD71850MWV has eight power states or modes: OFF, READY, SNVS, RUN, IDLE, SUSPEND, PWROFF and EMG.
Figure 3-2 shows the state transition diagram along with the conditions to enter and exit each state.
READY_TO_SNVS Condition is described in 3.2.5.2. This condition is configurable by TRANS_COND0 registers.
SNVS_TO_RUN Condition is described in 3.2.5.3. This condition is configurable by TRANS_COND0 registers.
BD71850MWV has Thermal Shutdown, OCP, VR Fault, and VSYS_UVLO=0 as Emergency Shutdown events.
Emergency Shutdown Condition is described in 3.2.5.9. EMG_TO_READY Condition is described in 3.2.5.12.
EMG_STAY Condition is described in 3.2.5.13.
BD71850MWV has WDOG_B, SWRESET, and PWRON_B long detection as Cold Reset events. COLD_RESET
Condition is described in 3.2.4.1. After cold reset events or PMIC_ON_REQ=0, BD71850MWV is configurable that it
returns to READY or SNVS state. POFF_TO_READY Condition is described in 3.2.5.16. POFF_TO_SNVS Condition
is described in 3.2.5.17. Concerning VSYS_UVLO and INTLDO1P5_UVLO, please refer to 2.5.
Any
state
INTLDO1P5_UVLO = 0
OFF
INTLDO1P5_UVLO = 0
VSYS_UVLO = 1
VSYS_UVLO = 0
READY
EMG_TO_READY
Condition
(All Emergency shutdown
events are not met,
or VR fault recovery attempt.)
POFF_TO_READY Condition
(Default setting: Not available)
READY_TO_SNVS
Condition
(Default setting: VSYS_UVLO =1)
POFF_TO_SNVS Condition
(Default setting: PMIC_ON_REQ=0,
SWRESET=1, WDOG_B=0, or
PWRON_B long push)
PWROFF
EMG
SNVS
COLD_RESET Condition
or PMIC_ON_REQ = 0
IDLE
EMG_STAY
Condition
(VSYS_UVLO=0, Thermal
shutdown(T>130˚C),
or VR fault recovery failed.)
Emergency Shutdown
Condition
Emergency Shutdown
SNVS_TO_RUN
Condition
Condition
(Default setting: PMIC_ON_REQ=1)
PMIC_STBY_REQ = 1
PMIC_ON_REQ = 1
SUSPEND
(reg) IDLE_MODE = 1
PMIC_STBY_REQ = 1
PMIC_ON_REQ = 1
PMIC_STBY_REQ = 0
PMIC_ON_REQ = 1
(reg) IDLE_MODE = 0
RUN
Emergency Shutdown Condition
COLD_RESET Condition:
WDOG_B = 0
SWRESET = 1
PWRON_B long push
Emergency Shutdown Condition:
Thermal Shutdown(T>150˚C)
OCP, VR Fault, VSYS_UVLO=0
COLD_RESET Condition
or PMIC_ON_REQ = 0
Figure 3-2. Power State Transition
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3.2.2. Power State Register
The POW_STATE register shows current power state and power sub state in Table 3-7. The power sub state definition
is illustrated in Figure 3-3.
Table 3-7. POW_STATE – Power State Register
Register Name
R/W
POW_STATE
R
Bit
D[7:4]
D[1:0]
D7
D6
D5
D4
POW_ST[3:0]
Name
POW_ST[3:0]
POW_SUB[1:0]
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D3
D2
-
-
Function
This bit field shows current power state.
0x0 = OFF
0x1 = READY
0x2 = SNVS
0x8 = RUN
0x9 = IDLE
0xA = SUSPEND
0xB = PWROFF 0xC = EMG
This bit field shows current power sub state.
00 = Stable
01 = Up
10 = Down
11 = Counting Cold Reset duration time (set by PONT[3:0])
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D1
D0
POW_SUB[1:0]
Initial
Address
0x00
0x2D
Initial
0000
00
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3.2.2.
Power State Register – continued
Stable
OFF
(0x0)
Any
state
Down
Down
Up
Down
Stable
READY
(0x1)
Down
Down
Up
Stable
Stable
Stable
PWROFF
(0xB)
EMG
(0xC)
Up
SNVS
(0x2)
Down
Down
Down
Up
Stable
Stable
Down
IDLE
(0x9)
SUSPEND
(0xA)
Down
Stable
Down
Up
Up
RUN
(0x8)
Down
Down
Figure 3-3. Power Sub State Definition
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3.2.3. Power State Definition
(a) OFF state
BD71850MWV is in OFF state when INTLDO1P5_UVLO is detected. If INTLDO1P5_UVLO is 0, the data in all
registers are reset to their default values.
To exit this state, VSYS voltage must exceed 3.0 V (VSYS_UVLO = 1)
(b) READY state
In this state, VSYS voltage is over 3.0V. When power state transitions from OFF state to READY state, OTP data will
only be loaded to registers with "Yes" in "OTP" column of Register Map (Table 1-4). When power state transitions
from PWROFF or EMG state to READY state, OTP data will only be loaded to registers with reset condition during
READY state and "Yes" condition in "OTP" column. This OTP loading can be skipped depending on the value of
RELOAD_REG in PWRCTRL0 register.
(c) SNVS state
If READY_TO_SNVS condition is satisfied, the power state changes to SNVS state. In this state, LDO1(NVCC_SNVS)
and LDO2(VDD_SNVS) are turned on as shown in Table 3-8.
(d) RUN state
If SNVS_TO_RUN condition is satisfied, the power state changes to RUN state. In this state, the VR’s shown in Table
3-8 are turned ON.
The voltage of BUCK1(VDD_SOC, VDDA_0V8, PHY_0V8) depends on BUCK1_VOLT_RUN register.
The voltage of BUCK2(VDD_ARM) depends on BUCK2_VOLT_RUN register.
(e) IDLE state
If IDLE_MODE in PWRCTRL1 register is set to 1, the power state changes to IDLE state. The voltage of
BUCK1(VDD_SOC, VDDA_0V8, PHY_0V8) depends on BUCK1_VOLT_IDLE register. The voltage of
BUCK2(VDD_ARM) depends on BUCK2_VOLT_IDLE register.
(f) SUSPEND state
If PMIC_STBY_REQ is set to 1, the power state changes to SUSPEND state. The voltage of BUCK1(VDD_SOC,
VDDA_0V8, PHY_0V8) depends on BUCK1_VOLT_SUSP register.
(g) EMG state
If Emergency Shutdown Condition is satisfied, the power state changes to EMG state. In this state, all VR’s are OFF.
(h) PWROFF state
If COLD_RESET Condition is satisfied or PMIC_ON_REQ is reset to 0, the power state changes to PWROFF state. In
this state, all VR’s except LDO1(NVCC_SNVS) and LDO2(VDD_SNVS) are OFF. The next state of PWROFF is either
READY or SNVS. TRANS_COND1[3:0] values decide which power state to go.
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3.2.3.
VR No.
Power State Definition – continued
Table 3-8. Voltage Rails ON/OFF for Respective Power State
Function
Rail Name
Power State
OFF
READY
SNVS
(Note)
SUSPEND (Note)
IDLE(Note)
RUN(Note)
PWROFF
EMG
VR1
NVCC_SNVS
LDO1
OFF
OFF
ON
ON
ON
ON
ON/OFF
OFF
VR2
LDO2
OFF
OFF
ON
ON
ON
ON
ON/OFF
OFF
BUCK1
OFF
OFF
OFF
ON
ON
ON
OFF
OFF
VR4
VDD_SNVS
VDD_SOC,
VDDA_0V8,
PHY_0V8,
VDD_DRAM,
VDD_GPU
VDD_ARM
BUCK2
OFF
OFF
OFF
OFF
ON
ON
OFF
OFF
VR5
-
-
-
-
-
-
-
-
-
-
VR6
-
-
-
-
-
-
-
-
-
-
VR7
-
BUCK5
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
LDO3
OFF
OFF
OFF
ON
ON
ON
OFF
OFF
VR3
VR9
VDDA_1V8,
VDDA_DRAM
-
LDO4
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
VR10
NVCC_3V3
BUCK6
OFF
OFF
OFF
ON
ON
ON
OFF
OFF
VR11
NVCC_1V8
BUCK7
OFF
OFF
OFF
ON
ON
ON
OFF
OFF
VR12
NVCC_DRAM
BUCK8
OFF
OFF
OFF
ON
ON
ON
OFF
OFF
VR13
-
LDO5
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
VR14
VDD_PHY_1V2
LDO6
OFF
OFF
OFF
ON
ON
ON
OFF
OFF
VR15
-
-
-
-
-
-
-
-
-
-
VR16
NVCC_SD2
MUXSW
OFF
OFF
OFF
ON
ON
ON
OFF
OFF
VR8
(Note) ON/OFF setting of each VR at SNVS/SUSPEND/IDLE/RUN state can be conf igured by OTP.
3.2.4. Power State Control Events
3.2.4.1.
Reset Event
BD71850MWV has Cold and Warm resets.
Cold reset initiates POR_B asserted to L and power rails are turned off. Then, the power state changes to
either READY state or SNVS state. Next, the power state returns to RUN state automatically.
Warm reset initiates POR_B asserted to L for 1 ms. It does not affect the on/off status of all power rails.
Warm reset does not initiate the power state transition.
BD71850MWV has three reset sources as follows.
• PWRON_B terminal is set H to L. (PWRON_B Long Push reset)
• WDOG_B terminal is set H to L. (WDOG_B reset)
• SWRESET in SWRESET register is set 0 to 1 (Software reset)
The cold or warm reset selection setting is shown in Table 3-9.
The details of the two registers related to the setting are shown in Table 3-10 and Table 3-11.
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3.2.4.1.
Reset Source
PWRON_B
Long Push
WDOG_B
Software
Reset Event – continued
Table 3-9. Setting of Cold or Warm Reset Selection
Register Name
Register Bit Name
PWRCTRL0
DEBUG_STATE[1:0]
PWRCTRL0
WDOGB_SEL[1:0]
SWRESET
SWRESET_SEL[1:0]
Value
Cold/Warm Reset or No Reset
10 (default)
Cold reset
11
Warm reset
00 or 01
No reset action
10 (default)
Cold reset
11
Warm reset
00 or 01
No reset action
10 (default)
Cold reset
11
Warm reset
00 or 01
No reset action
Table 3-10. SWRESET - Software Reset Register
Register Name
R/W
D7
D6
D5
D4
D3
SWRESET
R/W
-
-
-
-
-
Bit
D[2:1]
D[0]
D2
D1
SWRESET_SEL[1:0]
D0
Initial
Address
SWRESET
0x04
0x01
Name
Function
Initial
SWRESET_SEL[1:0]
Select Cold reset, Warm reset or No reset action when SWRESET bit ( D[0]) is set
to 1.
00 = No reset action
01 = No reset action
10 = Cold reset
11 = Warm reset
10
SWRESET
0 – No action
1 – Initiates Cold Reset or Warm Reset in accordance with SWRESET_SEL bit.
Writing 1 to SWRESET bit, then SWRESET bit is automatically cleared to 0 when
Cold Reset or Warm Reset operation is completed.
Writing 1 to SWRESET bit can be done when Power State = RUN, IDLE and
SUSPEND.
0
Table 3-11. PWRCTRL0 - Power Control 0 Register
Register Name
PWRCTRL0
Bit
R/W
R/W
D7
D6
DEBUG_STATE[1:0]
D5
D4
D3
D2
RELOAD_
REG
-
-
-
D1
D0
Initial
Address
WDOGB_SEL[1:0]
0xA2
0x03
Name
Function
Initial
D[7:6]
DEBUG_STATE[1:0]
Select Cold reset, Warm reset or No reset action when PWRON_B long push is
detected.
00 = No reset action
01 = No reset action
10 = Cold reset
11 = Warm reset
10
D[5]
RELOAD_REG
Select OTP configurable registers initialization when the power state goes through
READY state.
0 = No initialization
1= Reload OTP registers and set to initial value
1
WDOGB_SEL[1:0]
Select Cold reset, Warm reset or No reset action when WDOG_B is asserted to 0.
00 = No reset action
01 = No reset action
10 = Cold reset
11 = Warm reset
10
D[1:0]
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3.2.4.2.
Emergency Shutdown Event
There are four Emergency Shutdown Events as follows:
• Thermal Shutdown (Thermal Protection)
If the die temperature surpasses 150ºC, the thermal protection circuit will shut down all VR’s to avoid
damage. This detection is not valid at OFF, READY and SNVS state.
• OCP
If the OCP is triggered in any VR’s, all VR’s are turned off.
• VR Fault
If the voltage of VR is not within the regular range, all VR’s are turned off.
• VSYS_UVLO = 0
If the VSYS_UVLO = 0, Emergency Shutdown sequence is initiated.
3.2.5. Power State Transitions
3.2.5.1.
OFF to READY
Table 3-12 shows the conditions for exiting OFF state. “VSYS_UVLO = 1” is necessary.
Event Trigger
Table 3-12. Conditions from OFF to READY state
Conditions
Next State
(All must be satisfied per Event Trigger)
1) VSYS Voltage Up
from 0 V or 2.7 V
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VSYS_UVLO = 1
(VSYS > 3.0 V)
READY
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Notes
VSYS Insertion or
VSYS recovery from 2.7 V
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3.2.5.2.
READY to SNVS
There are six event triggers for shifting from READY to SNVS as shown in Table 3-13. The event trigger of
VSYS_UVLO, PMIC_ON_REQ, PWRON_B Short Push, and PWRON_B Long Push are configurable to be
valid or invalid by TRANS_COND0 registers. VSYS_UVLO condition is valid with default setting.
Table 3-13. Conditions from READY to SNVS
Conditions
(All must be satisfied per Event Trigger)
Next State
Notes
VSYS_UVLO = 1
SNVS
No other event is necessary.
Valid with default setting
2) PMIC_ON_REQ
VSYS_UVLO = 1 and
PMIC_ON_REQ = 1
SNVS
Invalid with default setting
3) PWRON_B Short
Push
VSYS_UVLO = 1 and
PWRON_B = 0 ==> Short Push Detection
SNVS
Invalid with default setting
4) PWRON_B Long
Push
VSYS_UVLO = 1 and
PWRON_B = 0 ==> Long Push Detection
SNVS
Invalid with default setting
5) Cold Reset
Sequence
VSYS_UVLO = 1 and
Cold_Reset_flag = 1
SNVS
On the way back to RUN state
in Cold Reset sequence
6) VR Fault Recovery
Attempt
VSYS_UVLO = 1 and
VR Fault Recovery
SNVS
Event Trigger
1) VSYS_UVLO
1) VSYS_UVLO
The power state shifts to SNVS if VSYS_UVLO = 1 as shown in Figure 3-4. No other conditions are
necessary.
3.0 V
VSYS
0V
VSYS_UVLO
Power State
OFF
READY
SNVS
Figure 3-4. VSYS Condition for moving to SNVS
2) PMIC_ON_REQ
The power state shifts to SNVS if PMIC_ON_REQ = 1 as shown in Figure 3-5.
3.0 V
VSYS
0V
VSYS_UVLO
PMIC_ON_REQ
Power State
OFF
READY
SNVS
Figure 3-5. PMIC_ON_REQ Condition for moving to SNVS
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READY to SNVS – continued
3) PWRON_B Short Push
The power state shifts to SNVS if PWRON_B Short Push is detected as shown in Figure 3-6.
3.2.5.2.
3.0 V
VSYS
0V
VSYS_UVLO
PWRON_B
Short Push is detected.
Power State
OFF
READY
SNVS
Figure 3-6. PWRON_B Short Push Condition for moving to SNVS
4) PWRON_B Long Push
The power state shifts to SNVS if PWRON_B Long Push is detected as shown in Figure 3-7.
3.0 V
VSYS
0V
VSYS_UVLO
PWRON_B
Long Push is detected.
Power State
OFF
READY
SNVS
Figure 3-7. PWRON_B Long Push Condition for moving to SNVS
5) Cold Reset
The power state shifts to SNVS if Cold_Reset_flag = 1 as shown in Figure 3-8.
High
VSYS_UVLO
Cold Reset
Event occurs
Cold_Reset_flag
(PMIC Internal Signal)
Power State
RUN
PWROFF
READY
SNVS
Figure 3-8. Cold Reset Condition for moving to SNVS
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3.2.5.2.
READY to SNVS – continued
6) VR Fault Recovery Attempt
Please see 3.2.5.10.
It is possible to use each four event triggers such as:
VSYS_UVLO,
PMIC_ON_REQ,
PWRON_B Short Push and
PWRON_B Long Push
These triggers are configurable to use them respectively by D[3:0] in TRANS_COND0 register as shown
in Table 3-14.
Table 3-14. TRANS_COND0 - Transition Condition Select 0 Register
Register Name
TRANS_COND0
Bit
R/W
D7
D6
D5
D4
D3
D2
D1
D0
Initial
Address
R/W
C1_
VSYS_3P0_
ONLY_EN
C1_
PMIC_ON_
REQ_EN
C1_
SHORT_
PUSH_EN
C1_
LONG_
PUSH_EN
C0_
VSYS_3P0_
ONLY_EN
C0_
PMIC_ON_
REQ_EN
C0_
SHORT_
PUSH_EN
C0_
LONG_
PUSH_EN
0x48
0x1F
Name
Function
Initial
Select only VSYS_UVLO = 1 as SNVS ==> RUN transition condition or not
0 = VSYS_UVLO = 1 is not used as the condition
1 = VSYS_UVLO = 1 is used as the condition
0
D[7]
C1_VSYS_3P0_ONLY_EN
D[6]
C1_PMIC_ON_REQ_EN
Select PMIC_ON_REQ as SNVS ==> RUN transition condition or not
0 = PMIC_ON_REQ is not used as the condition
1 = PMIC_ON_REQ is used as the condition
1
D[5]
C1_SHORT_PUSH_EN
Select PWRON_B Short Push as SNVS ==> RUN transition condition or not
0 = PWRON_B Short Push is not used as the condition
1 = PWRON_B Short Push is used as the condition
0
D[4]
C1_LONG_PUSH_EN
Select PWRON_B Long Push as SNVS ==> RUN transition condition or not
0 = PWRON_B Long Push is not used as the condition
1 = PWRON_B Long Push is used as the condition
0
D[3]
C0_VSYS_3P0_ONLY_EN
Select only VSYS_UVLO = 1 as READY ==> SNVS transition condition or not
0 = VSYS_UVLO = 1 is not used as the condition
1 = VSYS_UVLO = 1 is used as the condition
1
D[2]
C0_PMIC_ON_REQ_EN
Select PMIC_ON_REQ as READY ==> SNVS transition condition or not
0 = PMIC_ON_REQ is not used as the condition
1 = PMIC_ON_REQ is used as the condition
0
D[1]
C0_SHORT_PUSH_EN
Select PWRON_B Short Push as READY ==> SNVS transition condition or not
0 = PWRON_B Short Push is not used as the condition
1 = PWRON_B Short Push is used as the condition
0
D[0]
C0_LONG_PUSH_EN
Select PWRON_B Long Push as READY ==> SNVS transition condition or not
0 = PWRON_B Long Push is not used as the condition
1 = PWRON_B Long Push is used as the condition
0
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3.2.5.3.
SNVS to RUN
There are six event triggers for shifting from SNVS to RUN as shown in Table 3-15. The event trigger of
VSYS_UVLO=1 PMIC_ON_REQ, PWRON_B Short Push, and PWRON_B Long Push are configurable to
be valid or invalid by TRANS_COND0 registers. PMIC_ON_REQ condition is valid with default setting.
Table 3-15. Conditions from SNVS to RUN
(Note)
Conditions
(All must be satisfied per Event Trigger)
Next State
Notes
VSYS_UVLO = 1
RUN
No other event is necessary.
Invalid with default setting
2) PMIC_ON_REQ
VSYS_UVLO = 1 and
PMIC_ON_REQ = 1
RUN
Valid with default setting
3) PWRON_B Short
Push
VSYS_UVLO = 1 and
PWRON_B = 0 ==> Short Push Detection
RUN
Invalid with default setting
4) PWRON_B Long
Push
VSYS_UVLO = 1 and
PWRON_B = 0 ==> Long Push Detection
RUN
Invalid with default setting
5) Cold Reset
Sequence
VSYS_UVLO = 1 and
Cold_Reset_flag = 1
RUN
On the way back to RUN state
in Cold Reset sequence
6) VR Fault Recovery
Attempt
VSYS_UVLO = 1 and
VR Fault Recovery
RUN
Event Trigger
1) VSYS_UVLO
(Note) Die Temperature must be less than 150 ºC.
1) VSYS_UVLO
The power state shifts to RUN if VSYS_UVLO = 1 as shown in Figure 3-9. No other condition is required.
VSYS_UVLO
Power State
OFF
READY
SNVS
RUN
Figure 3-9. VSYS Condition for moving to RUN
2) PMIC_ON_REQ
The power state shifts to RUN if PMIC_ON_REQ = 1 as shown in Figure 3-10.
VSYS_UVLO
PMIC_ON_REQ
Power State
OFF
READY
SNVS
RUN
Figure 3-10. PMIC_ON_REQ Condition for moving to RUN
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SNVS to RUN – continued
3) PWRON_B Short Push
3.2.5.3.
VSYS_UVLO
PWRON_B
Short Push is detected.
Power State
OFF
READY
SNVS
RUN
Figure 3-11. PWRON_B Short Push Condition for moving to RUN
4) PWRON_B Long Push
The power state shifts to RUN if PWRON_B Long Push is detected as shown in Figure 3-12.
VSYS_UVLO
PWRON_B
Long Push is detected.
Power State
OFF
READY
SNVS
RUN
Figure 3-12. PWRON_B Long Push Condition for moving to RUN
5) Cold Reset
The power state shifts to RUN if Cold_Reset_flag = 1 as shown in Figure 3-13.
High
VSYS_UVLO
Cold Reset
Event occurs
Cold_Reset_flag
(PMIC Internal Signal)
Power State
RUN
PWROFF
READY
SNVS
RUN
Figure 3-13. Cold Reset Condition for moving to RUN
6) VR Fault Recovery Attempt
Please see 3.2.5.10.
It is possible to use each four event triggers such as:
VSYS_UVLO,
PMIC_ON_REQ,
PWRON_B Short Push and
PWRON_B Long Push
These triggers are configurable to use them respectively by D[7:4] in TRANS_COND0 register as shown in
Table 3-14.
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3.2.5.4.
RUN to IDLE
Table 3-16 shows the conditions for shifting from RUN to IDLE. The details of PWRCTRL1 register were
described in Table 3-17.
Table 3-16. Conditions from RUN to IDLE
(Note)
Conditions
(All must be satisfied)
Event Trigger
Next State
Notes
IDLE
Register Write Operation
PMIC_STBY_REQ = 0
Set IDLE_MODE
(PWRCTRL1
register) = 1
PMIC_ON_REQ = 1
Set (reg) IDLE_MODE = 1
(Note) Die Temperature must be less than 150 ºC. VSY S_UVLO = 1.
Table 3-17. PWRCTRL1 - Power Control 1 Register
Register Name
R/W
D7
D6
D5
D4
D3
D2
D1
D0
Initial
Address
PWRCTRL1
R/W
-
-
-
-
-
-
-
IDLE_
MODE
0x00
0x04
Bit
D[0]
3.2.5.5.
Event Trigger
Set IDLE_MODE
(PWRCTRL1
register) = 0
Name
Function
IDLE_MODE
Initial
Control power state transition between RUN and IDLE
0 = Exit IDLE and back to RUN, or indicates power state = except IDLE
1 = Enter IDLE from RUN, or indicates power state = IDLE
Note : this bit automatically returns to 0 when power state enters PWROFF,
EMG and SUSPEND.
0
IDLE to RUN
Table 3-18 shows the conditions for shifting from IDLE to RUN.
Table 3-18. Conditions from IDLE to RUN
Conditions (Note)
Next State
(All must be satisfied)
PMIC_STBY_REQ = 0
RUN
PMIC_ON_REQ = 1
Set (reg) IDLE_MODE = 0
Notes
Register Write Operation
(Note) Die Temperature must be less than 150 ºC. VSY S_UVLO = 1.
3.2.5.6.
Event Trigger
PMIC_STBY_REQ
RUN to SUSPEND
Table 3-19 shows the conditions for shifting from RUN to SUSPEND.
Table 3-19. Conditions from RUN to SUSPEND
Conditions (Note)
Next State
(All must be satisfied)
PMIC_STBY_REQ = 1
SUSPEND
PMIC_ON_REQ = 1
Notes
(Note) Die Temperature must be less than 150 ºC. VSY S_UVLO = 1.
3.2.5.7.
Event Trigger
PMIC_STBY_REQ
SUSPEND to RUN
Table 3-20 shows the conditions for shifting from SUSPEND to RUN.
Table 3-20. Conditions from SUSPEND to RUN
Conditions (Note)
Next State
(All must be satisfied)
PMIC_STBY_REQ = 0
RUN
PMIC_ON_REQ = 1
Notes
(Note) Die Temperature must be less than 150 ºC. VSY S_UVLO = 1.
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3.2.5.8.
IDLE to SUSPEND
Table 3-21 shows the conditions for shifting from IDLE to SUSPEND. IDLE_MODE in PWRCTRL1 register
automatically returns to 0.
Table 3-21. Conditions from IDLE to SUSPEND
Conditions (Note)
Next State
(All must be satisfied)
PMIC_STBY_REQ = 1
SUSPEND
PMIC_ON_REQ = 1
Event Trigger
PMIC_STBY_REQ
Notes
(Note) Die Temperature must be less than 150 ºC. VSY S_UVLO = 1.
3.2.5.9.
Emergency Shutdown
There are four Emergency Shutdown events which are:
Thermal Shutdown (Thermal Protection)
OCP
VR Fault
VSYS_UVLO = 0 as shown in Table 3-22.
Table 3-22. Conditions from SNVS, RUN, IDLE, SUSPEND, PWROFF to EMG
Conditions
Next State
(All must be satisfied per Event Trigger)
Event Trigger
1) Thermal Shutdown
Die Temperature > 150 ºC
EMG
Any VR's OCP
EMG
Any VR's out of the target voltage
EMG
VSYS_UVLO = 0
EMG
2) OCP
3) VR Fault
4) VSYS_UVLO = 0
Notes
Thermal Protection
This protection is invalid at OFF,
READY, and SNVS state
The detail of VR Fault is described in 3.2.5.10.
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3.2.5.10.
VR Fault
BD71850MWV has VR fault detection function which monitors all relevant VR’s of the system. The system
is shut down when a monitored voltage rail goes out of the target voltage. Once the system has shut down,
the system tries to boot up several times which is determined by RCVLMT[3:0] in RCVCFG register.
Table 3-23 shows the VR fault threshold and monitoring conditions. Even if one of output rails which are
described “Y” in Table 3-23 are not used, output inductors and capacitors are needed. If they are not
connected, PMIC would be shut down because of VR fault detection.
Table 3-23. VR FAULT threshold and monitoring condition
SNVS
SUSPEND
IDLE
RUN
Monitor
Y/N
Voltage
Target
Range
Monitor
Y/N
Voltage
Target
Range
Monitor
Y/N
Voltage
Target
Range
Monitor
Y/N
Voltage
Target
Range
LDO1
Y
80% <
LDO1
Y
80% <
LDO1
Y
80% <
LDO1
Y
80% <
LDO1
VDD_SNVS
LDO2
Y
80% <
LDO2
Y
80% <
LDO2
Y
80% <
LDO2
Y
80% <
LDO2
VR3
VDD_SOC,
VDDA_0V8,
PHY_0V8
BUCK1
N
-
Y
80% <
BUCK1
< 130%
Y
80% <
BUCK1
< 130%
Y
80% <
BUCK1
< 130%
VR4
VDD_ARM
BUCK2
N
-
N
-
Y
80% <
BUCK2
< 130%
Y
80% <
BUCK2
< 130%
VR5
-
-
-
-
-
-
-
-
-
-
VR6
-
-
-
-
-
-
-
-
-
-
VR7
-
BUCK5
N
-
N
-
N
-
N
-
VR8
VDDA_1V8,
VDDA_DRAM
LDO3
N
-
Y
80% <
LDO3
Y
80% <
LDO3
Y
80% <
LDO3
VR9
-
LDO4
N
-
N
-
N
-
N
-
VR10
NVCC_3V3
BUCK6
N
-
Y
80% <
BUCK6
< 130%
Y
80% <
BUCK6
< 130%
Y
80% <
BUCK6
< 130%
VR11
NVCC_1V8
BUCK7
N
-
Y
80% <
BUCK7
< 130%
Y
80% <
BUCK7
< 130%
Y
80% <
BUCK7
< 130%
VR12
NVCC_DRAM
BUCK8
N
-
Y
80% <
BUCK8
< 130%
Y
80% <
BUCK8
< 130%
Y
80% <
BUCK8
< 130%
VR13
-
LDO5
N
-
N
-
N
-
N
-
VR14
VDD_PHY_1V2
LDO6
N
-
Y
80% <
LDO6
Y
80% <
LDO6
Y
80% <
LDO6
VR15
-
-
-
-
-
-
-
-
-
-
VR16
NVCC_SD
MUXSW
Not
available
-
Not
available
-
Not
available
-
Not
available
-
VR No.
Function
Rail Name
VR1
NVCC_SNVS
VR2
Y: VR output is monitored to trigger VR Fault Emergency Shutdown sequence.
N: Not monitored at default (If the VR is turned ON by changing the register setting, its output is monitored for the VR Fault event trigger)
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3.2.5.10.
VR Fault – continued
BD71850MWV monitors each rail. If a monitored VR goes out of the target voltage in a certain time, the
system will shut down. When the system cannot shift to RUN state after Power ON sequence several times
which is defined by RCVLMT[3:0] in RCVCFG register, the system stays at EMG state until
INTLDO1P5_UVLO = 0.
If a VR is turned OFF by VR control registers (BUCK1, BUCK2, BUCK5 to BUCK8 and LDO1 to LDO6), VR
fault of that VR is masked.
BD71850MWV has VR individual masking registers as shown in Table 3-25, Table 3-26 and Table 3-27.
This masking function is used for mainly debugging in development phase.
Table 3-24. VRFAULTEN - VR FAULT ON/OFF Register: Debugging Purpose
Register Name
R/W
D7
D6
D5
D4
D3
D2
D1
D0
Initial
Address
VRFAULTEN
R/W
-
-
-
-
-
-
-
VRFLTEN
0x01
0x21
Bit
D[0]
Name
Function
Initial
VRFLTEN
VR Fault enable bit
0 = VR Fault is disabled.
1 = VR Fault is enabled.
This bit is used for debugging purpose.Please do not set 0x00 in normal
operation.
1
Table 3-25. MVRFLTMASK0 - VR FAULT Mask 0 Register
Register Name
R/W
D7
D6
D5
D4
D3
D2
D1
D0
Initial
Address
MVRFLTMASK0
R/W
MBUCK8_
VOUTOKH
MBUCK8_
VOUTOKL
MBUCK7_
VOUTOKH
MBUCK7_
VOUTOKL
MBUCK6_
VOUTOKH
MBUCK6_
VOUTOKL
MBUCK5_
VOUTOKH
MBUCK5_
VOUTOKL
0x00
0x22
Bit
Name
D[7]
MBUCK8_VOUTOKH
D[6]
MBUCK8_VOUTOKL
Masking bit of BUCK8 80% threshold for target voltage
0 = monitoring 80% threshold
1 = masked 80% threshold
0
D[5]
MBUCK7_VOUTOKH
Masking bit of BUCK7 130% threshold for target voltage
0 = monitoring 130% threshold
1 = masked 130% threshold
0
D[4]
MBUCK7_VOUTOKL
Masking bit of BUCK7 80% threshold for target voltage
0 = monitoring 80% threshold
1 = masked 80% threshold
0
D[3]
MBUCK6_VOUTOKH
Masking bit of BUCK6 130% threshold for target voltage
0 = monitoring 130% threshold
1 = masked 130% threshold
0
D[2]
MBUCK6_VOUTOKL
Masking bit of BUCK6 80% threshold for target voltage
0 = monitoring 80% threshold
1 = masked 80% threshold
0
D[1]
MBUCK5_VOUTOKH
Masking bit of BUCK5 130% threshold for target voltage
0 = monitoring 130% threshold
1 = masked 130% threshold
0
D[0]
MBUCK5_VOUTOKL
Masking bit of BUCK5 80% threshold for target voltage
0 = monitoring 80% threshold
1 = masked 80% threshold
0
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Function
Masking bit of BUCK8 130% threshold for target voltage
0 = monitoring 130% threshold
1 = masked 130% threshold
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Initial
0
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BD71850MWV
3.2.5.10.
VR Fault – continued
Table 3-26. MVRFLTMASK1 - VR FAULT Mask 1 Register
Register Name
R/W
D7
D6
D5
D4
D3
D2
D1
D0
Initial
Address
MVRFLTMASK1
R/W
-
-
-
-
MBUCK2_
VOUTOKH
MBUCK2_
VOUTOKL
MBUCK1_
VOUTOKH
MBUCK1_
VOUTOKL
0x00
0x23
Bit
Name
Function
Masking bit of BUCK2 130% threshold for target voltage
0 = monitoring 130% threshold
1 = masked 130% threshold
Initial
D[3]
MBUCK2_VOUTOKH
D[2]
MBUCK2_VOUTOKL
Masking bit of BUCK2 80% threshold for target voltage
0 = monitoring 80% threshold
1 = masked 80% threshold
0
D[1]
MBUCK1_VOUTOKH
Masking bit of BUCK1 130% threshold for target voltage
0 = monitoring 130% threshold
1 = masked 130% threshold
0
D[0]
MBUCK1_VOUTOKL
Masking bit of BUCK1 80% threshold for target voltage
0 = monitoring 80% threshold
1 = masked 80% threshold
0
0
Table 3-27. MVRFLTMASK2 - VR FAULT Mask 2 Register
Register Name
R/W
D7
D6
D5
D4
D3
D2
D1
D0
Initial
Address
MVRFLTMASK2
R/W
-
-
MLDO6_
VOUTOKL
MLDO5_
VOUTOKL
MLDO4_
VOUTOKL
MLDO3_
VOUTOKL
MLDO2_
VOUTOKL
MLDO1_
VOUTOKL
0x00
0x24
Bit
Name
Function
Initial
D[5]
MLDO6_VOUTOKL
Masking bit of LDO6 80% threshold for target voltage
0 = monitoring 80% threshold
1 = masked 80% threshold
D[4]
MLDO5_VOUTOKL
Masking bit of LDO5 80% threshold for target voltage
0 = monitoring 80% threshold
1 = masked 80% threshold
0
D[3]
MLDO4_VOUTOKL
Masking bit of LDO4 80% threshold for target voltage
0 = monitoring 80% threshold
1 = masked 80% threshold
0
D[2]
MLDO3_VOUTOKL
Masking bit of LDO3 80% threshold for target voltage
0 = monitoring 80% threshold
1 = masked 80% threshold
0
D[1]
MLDO2_VOUTOKL
Masking bit of LDO2 80% threshold for target voltage
0 = monitoring 80% threshold
1 = masked 80% threshold
0
D[0]
MLDO1_VOUTOKL
Masking bit of LDO1 80% threshold for target voltage
0 = monitoring 80% threshold
1 = masked 80% threshold
0
0
Following a VR Fault and an Emergency Shutdown sequence, BD71850MWV stays in READY state for a
programmed time which is specified by RCVDT[3:0] of RCVCFG register. Power ON sequence is then
initiated once RCVDT[3:0] time has elapsed.
To prevent an infinite loop of VR Fault induced power cycles, BD71850MWV limits the number of attempts
to recover the system by RCVLMT[3:0] of RCVCFG register when these failures occur. Once
BD71850MWV has attempted to recover from a VR Fault for a number of times which is specified by
RCVLMT[3:0], the next VR Fault results in BD71850MWV staying in EMG state until INTLDO1P5_UVLO =
0.
The ability to reset RCVNUM register which tracks the number of VR Fault recovery attempts via I2C is
supported. This will allow the SoC to reset this count value when needed.
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3.2.5.10.
VR Fault – continued
Table 3-28. RCVCFG - Recovery Configuration Register
Register Name
R/W
RCVCFG
R/W
Bit
D7
D6
D5
D4
D3
D2
RCVLMT[3:0]
D1
D0
RCVDT[3:0]
Name
Initial
Address
0x4C
0x25
Function
Initial
The limit number of attempts to recover the system after a VR Fault occurred.
0000 = No recovery. BD71850MWV stays in EMG state until VSYS is triggered
again.
0001 = 1 time
0010 = 2 times
0011 = 3 times
0100 = 4 times
:
1110 = 14 times
1111 = No limit of attempts to recover
RCVLMT[3:0]
D[7:4]
D[3:0]
0100
The duration time during which BD71850MWV stays in READY state after a VR
Fault event.
BD71850MWV remains in READY state for the duration programmed here then
BD71850MWV performs a Power ON sequence, if RCVLMT[3:0] is not 0x0 or 0xF
and RCVLMT[3:0] is not equal to RCVNUM[3:0] of RCVNUM register.
0000 = 5 ms
0001 = 10 ms
0010 = 15 ms
0011 = 20 ms
0100 = 25 ms
0101 = 30 ms
0110 = 35 ms
0111 = 40 ms
1000 = 45 ms
1001 = 50 ms
1010 = 75 ms
1011 = 100 ms
1100 = 250 ms
1101 = 500 ms
1110 = 750 ms
1111 = 1500 ms
RCVDT[3:0]
1100
Table 3-29. RCVNUM - Recovery Number Register
Register Name
R/W
D7
D6
D5
D4
RCVNUM
R/W
-
-
-
-
Bit
D[3:0]
Name
RCVNUM[3:0]
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D3
D2
D1
D0
RCVNUM[3:0]
Function
Address
0x00
0x26
Initial
The number of attempts to recover the system after a VR Fault occurred.
Once BD71850MWV has attempted to recover from a power failure times which is
indicated in RCVLMT[3:0] in RCVCFG register, the next failure shall result in
BD71850MWV staying in EMG state until VSYS is triggered again.
When SoC writes RCVNUM register via I2C, then RCVNUM[3:0] is cleared to 0000.
As a result, the tracking number of power failure recovery attempts is reset.
Note : When RCVLMT[3:0] = 0xF (no limit of attempts to recover) and the number of
attempt is over 0xF, RCVNUM[3:0] value is fixed to 0xF.
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Initial
0000
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BD71850MWV
3.2.5.10.
VR Fault – continued
VR Fault occurred
and shutdown.
▼
VRs
Power ON
▼
VR Fault occurred
and shutdown.
▼
RCVLMT[3:0]
0
1
2
▲
RCVDT[3:0] Increment by PMIC
Power State
Due to {RCVLMT == RCVNUM},
Power ON does not occur and
▽ PMIC keeps EMG state
VR Fault occurred
and shutdown.
▼
2
RCVNUM[3:0]
RVR_FAULT
in RESETSRC
Register
Power ON
▼
0
1
0
▲
Set by PMIC
RUN
▲
RCVDT[3:0] Increment by PMIC
1
0
▲
▲
Cleared by SoCSet by PMIC
READY
SNVS, RUN
EMG
RCVDT[3:0]
1
▲
▲
Cleared by SoCSet by PMIC
READY
SNVS, RUN
EMG
EMG
Figure 3-14. Example of VR Fault and Recovery Sequence (RCVLMT[3:0] = 2)
3.2.5.11.
EMG to OFF
Table 3-30 shows the conditions for shifting from EMG to OFF. If INTLDO1P5_UVLO = 0 after entry to EMG,
the power state immediately goes to OFF as shown in Figure 3-15.
Event Trigger
VSYS Voltage Low
Table 3-30. Conditions from EMG to OFF
Conditions
Next State
(All must be satisfied per Event Trigger)
INTLDO1P5_UVLO = 0
Notes
OFF
2.7V
VSYS
0V
1.35V
INTLDO1P5
0V
VSYS_UVLO
INTLDO1P5_UVLO
Power State
RUN
EMG
OFF
0V
All VRs
0V
Emergency
Shutdown
0V
Figure 3-15. EMG to OFF Power State Transition
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3.2.5.12.
EMG to READY
Table 3-31 shows the conditions for shifting from EMG to READY. Basically, the power state can exit EMG
when no emergency events are found as shown in Figure 3-14, Figure 3-16, and Figure 3-17.
Event Trigger
Table 3-31. Conditions from EMG to READY
Conditions
Next State
(All must be satisfied per Event Trigger)
Notes
VSYS_UVLO = 1
1) No Emergency
Event
Die Temperature < 150 ºC
READY
No OCP
No VR Fault
VSYS_UVLO = 1
2) VR Fault Recovery
Attempt
Die Temperature < 150 ºC
READY
During VR Fault Recovery Attempt
VSYS_UVLO
Power State
IDLE
EMG
READY
0V
0V
All VRs
Emergency
Shutdown
0V
Figure 3-16. EMG to READY Power State Transition (VSYS_UVLO)
VSYS
more than 3.0 V
150 ºC
Die Temperature
Power State
IDLE
EMG
READY
0V
All VRs
0V
Emergency
Shutdown
0V
Figure 3-17. EMG to READY Power State Transition (Die Temperature)
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3.2.5.13.
EMG_STAY Condition
Table 3-32 shows the conditions for staying at EMG. Basically, the power state stays at EMG when
emergency events are found as shown in Figure 3-14, Figure 3-16, and Figure 3-17.
Note: In case of 3) VR Fault Recovery Failure in Table 3-32; in order to exit EMG, VSYS voltage must be
less than 2.7V and then the power state goes to OFF.
Table 3-32. Conditions for Stay at EMG
Conditions
Next State
(All must be satisfied per Event Trigger)
Event Trigger
VSYS_UVLO = 0
1) VSYS < 2.7 V
Notes
EMG
INTLDO1P5_UVLO = 1
2) Thermal Shutdown
Die Temperature > 150 ºC
EMG
Thermal Protection
INTLDO1P5_UVLO = 1
3) VR Fault Recovery
Failure
3.2.5.14.
VR Fault Recovery Attempt Failed
EMG
INTLDO1P5_UVLO = 1
Warm Reset
Warm Reset is executed when the power state = RUN, IDLE and SUSPEND.
Warm Reset set POR_B = L for 1 ms as shown in Figure 3-18.
Please refer to the Table 3-9 for necessary register setting.
Power State
RUN, IDLE or SUSPEND
WDOG_B
POR_B
1 ms
Figure 3-18. Warm Reset by WDOG_B
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3.2.5.15.
PWROFF
Table 3-33 shows the conditions for shifting from RUN, IDLE, SUSPEND to PWROFF.
When the power state is PWROFF, BD71850MWV runs Power OFF sequence and VR’s are turned OFF in
a defined sequential order.
In the end of the sequence, the on-off state of C32K_OUT, RTC_RESET_B, LDO2 and LDO1 depends on
the setting of TRANS_COND1 register as shown in Table 3-34. The summary is shown in Table 3-35.
Table 3-33. Conditions from RUN, IDLE, SUSPEND to PWROFF
Conditions
Next State
(All must be satisfied per Event Trigger)
Event Trigger
1) PWRON_B Long
Push
Notes
PWRON_B = 0 ==> Long Push Detection
PWROFF
COLD_RESET event
WDOG_B = 0
PWROFF
COLD_RESET event
3) Software Reset
Write 1 to SWRESET in SWRESET register
PWROFF
COLD_RESET event
4) PMIC_ON_REQ
PMIC_ON_REQ = 0
PWROFF
2) WDOG_B
(Note) Die Temperature must be less than 150 ºC. VSY S_UVLO = 1.
Table 3-34. TRANS_COND1 - Transition Condition Select 1 Register
Register Name
TRANS_COND1
Bit
R/W
D7
D6
D5
D4
PONT[3:0]
R/W
Name
D3
D2
D1
D0
Initial
Address
PWRON_
POFF_TO_
READY
WDOG_
POFF_TO_
READY
SWRST_
POFF_TO_
READY
ON_REQ_
POFF_TO_
READY
0xC0
0x20
Function
Initial
COLD RESET duration during which the BD71850MWV stays in READY or SNVS in
a COLD RESET event.
The BD71850MWV remains in READY or SNVS for the duration programmed here
then BD71850MWV performs a Power ON sequence.
0000 = 5 ms
0001 = 10 ms
0010 = 15 ms
0011 = 20 ms
0100 = 25 ms
0101 = 30 ms
0110 = 35 ms
0111 = 40 ms
1000 = 45 ms
1001 = 50 ms
1010 = 75 ms
1011 = 100 ms
1100 = 250 ms
1101 = 500 ms
1110 = 750 ms
1111 = 1500 ms
D[7:4]
PONT[3:0]
D[3]
PWRON_
POFF_TO_READY
Set which power state to go after PWROFF triggered by PWRON_B Long Push
0 = to SNVS
1 = to READY
0
D[2]
WDOG_
POFF_TO_READY
Set which power state to go after PWROFF triggered by WDOG_B = 0
0 = to SNVS
1 = to READY
0
D[1]
SWRST_
POFF_TO_READY
Set which power state to go after PWROFF triggered by Software Reset
0 = to SNVS
1 = to READY
0
D[0]
ON_REQ_
POFF_TO_READY
Set which power state to go after PWROFF triggered by PMIC_ON_REQ = 0
0 = to SNVS
1 = to READY
0
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BD71850MWV
PWROFF – continued
3.2.5.15.
more than 3.0 V
VSYS
VRs
Power State
PWROFF
(Power Off Sequence)
SNVS/
READY
RUN/SNVS
(Power On Sequence)
SNVS/READY
(POW_SUB[1:0]=11)
PONT[3:0] in
TRANS_COND1 register
Figure 3-19. Cold Reset Duration Time set by PONT[3:0]
Table 3-35. VR Summary After Power OFF Sequence
PWROFF trigger
PWRON_B Long Push
WDOG_B = 0
Software Reset
PMIC_ON_REQ = 0
PWRON_
POFF_TO_
READY
WDOG_
POFF_TO_
READY
SWRST_
POFF_TO_
READY
ON_REQ_
POFF_TO_
READY
C32K_
OUT
RTC_
RESET_B
LDO2
LDO1
0
-
-
-
On
High
On
On
1
-
-
-
Off
Low
Off
Off
-
0
-
-
On
High
On
On
-
1
-
-
Off
Low
Off
Off
-
-
0
-
On
High
On
On
-
-
1
-
Off
Low
Off
Off
-
-
-
0
On
High
On
On
-
-
-
1
Off
Low
Off
Off
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3.2.5.16.
PWROFF to READY
After the completion of Power OFF sequence, the power state goes READY if the POFF_TO_READY = 1.
This is in accordance with PWROFF trigger event in the TRANS_COND1 register.
3.2.5.17.
PWROFF to SNVS
After the completion of Power OFF sequence, the power state goes SNVS if the POFF_TO_READY = 0.
This is in accordance with PWROFF trigger event in the TRANS_COND1 register.
3.2.5.18.
PWRON_B Functionality
The system has a button that can be used for triggering the system to power on or off. PWRON_B is an
active-low input to BD71850MWV. Timer circuitry measures the length of time the button is pressed. Then
the timer detects short push and long push events.
BD71850MWV
VSYS
PWRON_B
IRQ_B
IRQ
Control
Short Push
Debouncer
Edge
Detector
Timer
Long Push
Power
State
Machine
Power Button
STAT_PWRON
IN_MON
PWRONCONFIG0
SHORTT
PBDBNCT
PWRONCONFIG1
LONGT
Figure 3-20. Power Button Block Diagram
Table 3-36. PWRONCONFIG0 - PWRON_B Configuration 0 Register
Register Name
R/W
D7
D6
PWRONCONFIG0
R/W
-
-
Bit
D[5:4]
D[3:0]
D5
D4
SHORTT[3:0]
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D2
PBDBNCT[1:0]
Name
PBDBNCT[1:0]
D3
D1
SHORTT[3:0]
Function
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Initial
Address
0x16
0x27
Initial
PWRON_B Input Pin Debounce Time
00 = 10 ms 01 = 30 ms(default) 10 = 60 ms 11 = 100 ms
Short Push Timer :
0000 = 10 ms
0001 = 0.5 s
0010 = 1.0 s
0011 = 1.5 s
0100 = 2.0 s
0101 = 2.5 s
0110 = 3.0 s (default)
0111 = 3.5 s
1000 = 4.0 s
1001 = 4.5 s
1010 = 5.0 s
1011 = 5.5 s
1100 = 6.0 s
1101 = 6.5 s
1110 = 7.0 s
1111 = 7.5 s
D0
01
0110
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BD71850MWV
3.2.5.18.
PWRON_B Functionality – continued
Table 3-37. PWRONCONFIG1 - PWRON_B Configuration 1 Register
Register Name
R/W
D7
D6
D5
D4
PWRONCONFIG1
R/W
-
-
-
-
Bit
D[3:0]
Name
LONGT[3:0]
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D3
D2
LONGT[3:0]
Function
Long Push Timer :
0000 = 10 ms (default)
0001 = 1 s
0010 = 2 s
0011 = 3 s
0100 = 4 s
0101 = 5 s
0110 = 6 s
0111 = 7 s
1000 = 8 s
1001 = 9 s
1010 = 10 s
1011 = 11 s
1100 = 12 s
1101 = 13 s
1110 = 14 s
1111 = 15 s
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D1
D0
Initial
Address
0x00
0x28
Initial
0000
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BD71850MWV
3.3. Power Sequence
3.3.1. Power ON Sequence
Figure 3-21 shows an example when TRANS_COND0 = 0x48, which are:
READY to SNVS condition: VSYS_UVLO = 1
SNVS to RUN condition: PMIC_ON_REQ
Power State
OFF
READY
SNVS
RUN
3.0 V
VSYS
0V
INTLDO1P5
0V
VSYS_UVLO
(PMIC Internal)
t0
LDO1 (1.8 V)
(NVCC_SNVS)
t1
LDO2 (0.8 V)
(VDD_SNVS)
RTC clock
(PMIC Internal)
S top
RTC_RESET_B
(PMIC -> SOC)
C32K_OUT
(PMIC -> SOC)
t2
t3
S top
PMIC_ON_REQ
(SOC -> PMIC)
PMIC internal ON
signal
Masked to L
PMIC_STBY_REQ
(SOC -> PMIC)
Masked to L
t15
L
t4
BUCK1 (0.8 V)
(VDD_SOC,VDDA_0V8,PHY_0V8)
BUCK5 (0.9 V)
OFF
LDO4 (0.9 V)
OFF
t7
BUCK2 (0.9 V)
(VDD_ARM)
LDO3 (1.8 V)
(VDDA_1V8,VDDA_DRAM)
t9
BUCK7 (1.8 V)
(NVCC_1V8)
t10
BUCK8 (1.1 V)
(NVCC_DRAM)
t11
BUCK6 (3.3 V)
(NVCC_3V3)
t12
LDO6 (1.2 V)
(VDD_PHY_1V2)
t13
POR_B
(PMIC -> SOC)
WDO G_B
(SOC -> PMIC)
LDO5 (3.3 V)
t14
Masked to H
LDO5 is turned on by Software
OFF
Figure 3-21. Power ON Sequence
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Power ON Sequence – continued
Table 3-38. Power ON Sequence Timing Specification
Symbol
Description
Min
Typ
3.3.1.
Max
Unit
t0
VSYS = 3.0 V to LDO1 Assert Delay
0
20
22
ms
t1
LDO1 Assert to LDO2 Assert Delay
0
2.0
2.4
ms
t2
LDO2 Assert to RTC_RESET_B De-assert Delay
0
10
12
ms
t3
RTC_RESET_B De-assert to C32K_OUT Output Delay
0
40
90
μs
t4
PMIC_ON_REQ Assert to BUCK1 Assert Delay
0
0.20
12.49
ms
0
4.0
4.8
ms
t7
BUCK1 Assert to BUCK2 Assert Delay
BUCK1 Assert to LDO3 Assert Delay
t9
LDO3 Assert to BUCK7 Assert Delay
0
2.0
2.4
ms
t10
BUCK7 Assert to BUCK8 Assert Delay
0
2.0
2.4
ms
t11
BUCK8 Assert to BUCK6 Assert Delay
0
2.0
2.4
ms
t12
BUCK6 Assert to LDO6 Assert Delay
0
2.0
2.4
ms
t13
LDO6 Assert to POR_B De-assert Delay
0
20
22
ms
t14
POR_B De-assert to WDOG_B Internal Mask Disabled
0
10
12
ms
t15
POR_B De-assert to PMIC_STBY_REQ Internal Mask
Disabled
0
10
12
ms
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3.3.2. Power OFF Sequence
Figure 3-22 shows an example when triggered by PMIC_ON_REQ when ON_REQ_POFF_TO_READY = 0 in
TRANS_COND1 register.
Power State
RUN
PWROFF
SNVS
VSYS
INTLDO1P5
VSYS_UVLO
(PMIC Internal)
H
H
RTC clock
(PMIC Internal)
PMIC_ON_REQ
(SOC -> PMIC)
PMIC_STBY_REQ
(SOC -> PMIC)
L
WDOG_B
(SOC -> PMIC)
Masked to H
POR_B
(PMIC -> SOC)
LDO5 (3.3 V)
t0
OFF
LDO6 (1.2 V)
(VDD_PHY_1V2)
t2
BUCK6 (3.3 V)
(NVCC_3V3)
t3
BUCK8 (1.1 V)
(NVCC_DRAM)
t4
BUCK7 (1.8 V)
(NVCC_1V8)
t5
LDO3 (1.8 V)
(VDDA_1V8,VDDA_DRAM)
t6
BUCK2 (0.9 V)
(VDD_ARM)
t7
LDO4 (0.9 V)
OFF
BUCK5 (0.9 V)
OFF
BUCK1 (0.8 V)
(VDD_SOC,VDDA_0V8,PHY_0V8)
t10
C32K_OUT
(PMIC -> SOC)
RTC_RESET_B
(PMIC -> SOC)
H
LDO2 (0.8 V)
(VDD_SNVS)
0.8 V
LDO1 (1.8 V)
(NVCC_SNVS)
1.8 V
Figure 3-22. Power OFF Sequence (To SNVS)
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Power OFF Sequence – continued
Table 3-39. Power OFF Sequence Timing Specification (To SNVS)
Symbol
Description
Min
Typ
3.3.2.
Max
Unit
t0
PMIC_ON_REQ De-assert to POR_B Assert Delay
0
120
200
μs
t2
POR_B De-assert to LDO6 De-assert Delay
0
40
48
ms
t3
LDO6 De-assert to BUCK6 De-assert Delay
0
10
12
ms
t4
BUCK6 De-assert to BUCK8 De-assert Delay
0
10
12
ms
t5
BUCK8 De-assert to BUCK7 De-assert Delay
0
10
12
ms
t6
BUCK7 De-assert to LDO3 De-assert Delay
0
10
12
ms
t7
LDO3 De-assert to BUCK2 De-assert Delay
0
10
12
ms
t10
BUCK2 De-assert to BUCK1 De-assert Delay
0
30
36
ms
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3.3.2.
Power OFF Sequence – continued
Figure 3-23 shows an example when triggered by PMIC_ON_REQ when ON_REQ_POFF_TO_READY = 1 in
TRANS_COND1 register.
Power State
RUN
PWROFF
READY
VSYS
INTLDO1P5
VSYS_UVLO
(PMIC Internal)
H
H
RTC clock
(PMIC Internal)
PMIC_ON_REQ
(SOC -> PMIC)
PMIC_STBY_REQ
(SOC -> PMIC)
L
WDO G_B
(SOC -> PMIC)
Masked to H
POR_B
(PMIC -> SOC)
LDO5 (3.3 V)
t0
OFF
LDO6 (1.2 V)
(VDD_PHY_1V2)
t2
BUCK6 (3.3 V)
(NVCC_3V3)
t3
BUCK8 (1.1 V)
(NVCC_DRAM)
t4
BUCK7 (1.8 V)
(NVCC_1V8)
t5
LDO3 (1.8 V)
(VDDA_1V8,VDDA_DRAM)
t6
BUCK2 (0.9 V)
(VDD_ARM)
t7
LDO4 (0.9 V)
OFF
BUCK5 (0.9 V)
OFF
BUCK1 (0.8 V)
(VDD_SOC,VDDA_0V8,PHY_0V8)
t10
t12
C32K_OUT
(PMIC -> SOC)
RTC_RESET_B
(PMIC -> SOC)
t11
t13
H
LDO2 (0.8 V)
(VDD_SNVS)
0.8 V
LDO1 (1.8 V)
(NVCC_SNVS)
1.8 V
t14
Figure 3-23. Power OFF Sequence (To READY)
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Power OFF Sequence – continued
Table 3-40. Power OFF Sequence Timing Specification (To READY)
Symbol
Description
Min
Typ
3.3.2.
Max
Unit
t0
PMIC_ON_REQ De-assert to POR_B Assert Delay
0
120
200
μs
t2
POR_B De-assert to LDO6 De-assert Delay
0
40
48
ms
t3
LDO6 De-assert to BUCK6 De-assert Delay
0
10
12
ms
t4
BUCK6 De-assert to BUCK8 De-assert Delay
0
10
12
ms
t5
BUCK8 De-assert to BUCK7 De-assert Delay
0
10
12
ms
t6
BUCK7 De-assert to LDO3 De-assert Delay
0
10
12
ms
t7
LDO3 De-assert to BUCK2 De-assert Delay
0
10
12
ms
t10
BUCK2 De-assert to BUCK1 De-assert Delay
0
30
36
ms
t11
BUCK1 De-assert to C32K_OUT Output Stop Delay
0
10
12
ms
t12
C32K_OUT Output Stop to RTC_RESET_B Assert Delay
0
10
12
ms
t13
RTC_RESET_B Assert to LDO2 De-assert Delay
0
10
12
ms
t14
LDO2 De-assert to LDO1 De-assert Delay
0
10
12
ms
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3.3.3. RUN to IDLE
Power State
RUN
IDLE
RTC clock
(PMIC Internal)
RTC_RESET_B
(PMIC -> SOC)
H
C32K_OUT
(PMIC -> SOC)
PMIC_ON_REQ
(SOC -> PMIC)
PMIC_STBY_REQ
(SOC -> PMIC)
H
L
WDOG_B
(SOC -> PMIC)
H
POR_B
(PMIC -> SOC)
H
I2C Interface
(SOC -> PMIC)
LDO5 (3.3 V)
LDO6 (1.2 V)
(VDD_PHY_1V2)
BUCK6 (3.3 V)
(NVCC_3V3)
BUCK8 (1.1 V)
(NVCC_DRAM)
BUCK7 (1.8 V)
(NVCC_1V8)
Write 1 to IDLE_MODE in
PWRCTRL1 register
OFF
1.2 V
3.3 V
1.1 V
1.8 V
LDO3 (1.8 V)
1.8 V
(VDDA_1V8,VDDA_DRAM)
Voltage specified by BUCK2_VOLT_RUN[6:0]
0.9 V
BUCK2 (0.9 V)
(VDD_ARM)
t0
Voltage specified by BUCK2_VOLT_IDLE[6:0]
LDO4 (0.9 V)
OFF
BUCK5 (0.9 V)
t1
OFF
BUCK1 (0.8 V)
(VDD_SOC,VDDA_0V8,PHY_0V8)
Voltage specified by BUCK1_VOLT_IDLE[6:0]
0.8 V
LDO2 (0.8 V)
(VDD_SNVS)
0.8 V
LDO1 (1.8 V)
(NVCC_SNVS)
1.8 V
Figure 3-24. RUN to IDLE
Table 3-41. RUN to IDLE Timing Specification
Description
Min
Symbol
Typ
Max
Unit
t0
End of I2C Access to BUCK2 Voltage Change Start
0
120
200
μs
t1
BUCK2 to BUCK1 Voltage Change Delay
0
120
200
μs
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3.3.4. IDLE to RUN
Power State
IDLE
RUN
RTC clock
(PMIC Internal)
RTC_RESET_B
(PMIC -> SO C)
H
C32K_OUT
(PMIC -> SOC)
PMIC_ON_REQ
(SOC -> PMIC)
H
PMIC_STBY_REQ
(SOC -> PMIC)
H
WDOG_B
(SOC -> PMIC)
H
POR_B
(PMIC -> SO C)
H
I2C Interface
(SOC -> PMIC)
Write 0 to IDLE_MODE in
PWRCTRL1 register
LDO5 (3.3 V)
OFF
LDO6 (1.2 V)
(VDD_PHY_1V2)
1.2 V
BUCK6 (3.3 V)
(NVCC_3V3)
3.3 V
BUCK8 (1.1 V)
(NVCC_DRAM)
1.1 V
BUCK7 (1.8 V)
(NVCC_1V8)
1.8 V
LDO3 (1.8 V)
(VDDA_1V8,VDDA_DRAM)
1.8 V
t1
BUCK2 (0.9 V)
(VDD_ARM)
0.9V = Voltage specified by BUCK2_VOLT_RUN[6:0]
Voltage specified by BUCK2_VOLT_IDLE[6:0]
LDO4 (0.9 V)
OFF
t0
BUCK5 (0.9 V)
OFF
BUCK1 (0.8 V)
(VDD_SO C,VDDA_0V8,PHY_0V8)
Voltage specified by BUCK1_VOLT_IDLE[6:0]
LDO2 (0.8 V)
(VDD_SNVS)
0.8 V
LDO1 (1.8 V)
(NVCC_SNVS)
1.8 V
0.8V = Voltage specified by BUCK1_VOLT_RUN[6:0]
Figure 3-25. IDLE to RUN
Table 3-42. IDLE to RUN Timing Specification
Description
Min
Symbol
Typ
Max
Unit
t0
End of I2C Access to BUCK1 Voltage Change Start
0
120
200
μs
t1
BUCK1 to BUCK2 Voltage Change Delay
0
120
200
μs
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3.3.5. RUN to SUSPEND
Power State
RUN
SUSPEND
RTC clock
(PMIC Internal)
RTC_RESET_B
(PMIC -> SOC)
H
C32K_OUT
(PMIC -> SOC)
PMIC_ON_REQ
(SOC -> PMIC)
H
PMIC_STBY_REQ
(SOC -> PMIC)
H
WDOG_B
(SOC -> PMIC)
H
POR_B
(PMIC -> SO C)
H
LDO5 (3.3 V)
OFF
LDO6 (1.2 V)
(VDD_PHY_1V2)
1.2 V
BUCK6 (3.3 V)
(NVCC_3V3)
3.3 V
BUCK8 (1.1 V)
(NVCC_DRAM)
1.1 V
BUCK7 (1.8 V)
(NVCC_1V8)
1.8 V
LDO3 (1.8 V)
(VDDA_1V8,VDDA_DRAM)
1.8 V
0.9 V
BUCK2 (0.9 V)
(VDD_ARM)
0 V (OFF )
t0
LDO4 (0.9 V)
OFF
BUCK5 (0.9 V)
OFF
BUCK1 (0.8 V)
(VDD_SOC,VDDA_0V8,PHY_0V8)
0.8 V
LDO2 (0.8 V)
(VDD_SNVS)
0.8 V
LDO1 (1.8 V)
(NVCC_SNVS)
1.8 V
Voltage specified by BUCK1_VOLT_SUSP[6:0]
t2
Figure 3-26. RUN to SUSPEND
Symbol
Table 3-43. RUN to SUSPEND Timing Specification
Description
Min
Typ
Max
Unit
t0
PMIC_STBY_REQ High to BUCK2 De-assert Delay
0
120
200
μs
t2
BUCK2 to BUCK1 Voltage Change Delay
0
20
24
ms
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3.3.6. SUSPEND to RUN
Power State
SUSPEND
RUN
RTC clock
(PMIC Internal)
RTC_RESET_B
(PMIC -> SOC)
H
C32K_OUT
(PMIC -> SOC)
PMIC_ON_REQ
(SOC -> PMIC)
H
PMIC_STBY_REQ
(SOC -> PMIC)
H
WDOG_B
(SOC -> PMIC)
H
POR_B
(PMIC -> SO C)
H
LDO5 (3.3 V)
OFF
LDO6 (1.2 V)
(VDD_PHY_1V2)
1.2 V
BUCK6 (3.3 V)
(NVCC_3V3)
3.3 V
BUCK8 (1.1 V)
(NVCC_DRAM)
1.1 V
BUCK7 (1.8 V)
(NVCC_1V8)
1.8 V
LDO3 (1.8 V)
(VDDA_1V8,VDDA_DRAM)
BUCK2 (0.9 V)
(VDD_ARM)
1.8 V
t2
0.9 V
0 V (OFF )
LDO4 (0.9 V)
OFF
BUCK5 (0.9 V)
OFF
BUCK1 (0.8 V)
(VDD_SOC,VDDA_0V8,PHY_0V8)
t0
Voltage specified by BUCK1_VO LT_RUN[6:0]
Voltage specified by BUCK1_VOLT_SUSP[6:0]
LDO2 (0.8 V)
(VDD_SNVS)
0.8 V
LDO1 (1.8 V)
(NVCC_SNVS)
1.8 V
Figure 3-27. SUSPEND to RUN
Symbol
Table 3-44. SUSPEND to RUN Timing Specification
Description
Min
Typ
Max
Unit
t0
PMIC_STBY_REQ Low to BUCK1 Voltage Change Start
0
120
200
μs
t2
BUCK1 to BUCK2 Voltage Change Delay
0
2.0
2.4
ms
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3.3.7. IDLE to SUSPEND
Power State
IDLE
SUSPEND
RTC clock
(PMIC Internal)
RTC_RESET_B
(PMIC -> SO C)
H
C32K_OUT
(PMIC -> SOC)
PMIC_ON_REQ
(SOC -> PMIC)
PMIC_STBY_REQ
(SOC -> PMIC)
H
L
IDLE_MODE in
PWRCTRL1
(PMIC Internal)
Automatically return to 0 when exiting IDLE
WDOG_B
(SOC -> PMIC)
H
POR_B
(PMIC -> SO C)
H
LDO5 (3.3 V)
LDO6 (1.2 V)
(VDD_PHY_1V2)
OFF
1.2 V
BUCK6 (3.3 V)
(NVCC_3V3)
3.3 V
BUCK8 (1.1 V)
(NVCC_DRAM)
1.1 V
BUCK7 (1.8 V)
(NVCC_1V8)
1.8 V
LDO3 (1.8 V)
(VDDA_1V8,VDDA_DRAM)
1.8 V
BUCK2 (0.9 V)
(VDD_ARM)
t0
Voltage specified by BUCK2_VOLT_IDLE[6:0]
0 V (OFF )
LDO4 (0.9 V)
OFF
BUCK5 (0.9 V)
OFF
BUCK1 (0.8 V)
(VDD_SO C,VDDA_0V8,PHY_0V8)
Voltage specified by BUCK1_VOLT_IDLE[6:0]
Voltage specified by BUCK1_VOLT_SUSP[6:0]
t2
LDO2 (0.8 V)
(VDD_SNVS)
0.8 V
LDO1 (1.8 V)
(NVCC_SNVS)
1.8 V
Figure 3-28. IDLE to SUSPEND
Symbol
Table 3-45. IDLE to SUSPEND Timing Specification
Description
Min
Typ
Max
Unit
t0
PMIC_STBY_REQ High to BUCK2 De-assert Delay
0
120
200
μs
t2
BUCK2 to BUCK1 Voltage Change Delay
0
20
24
ms
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3.3.8. Emergency Shutdown
Power State
Any State except OFF and READY
EMG
VSYS
INTLDO1P5
VSYS_UVLO
(PMIC Internal)
H
H
RTC clock
(PMIC Internal)
RTC_RESET_B
(PMIC -> SOC)
H
C32K_OUT
(PMIC -> SOC)
Thermal S hutdown E vent occurs .
Emergency
Event
When P ower S tat e = RUN, IDLE and SUS PE ND
POR_B
(PMIC -> SO C)
When P ower S tat e = S NV S
t0
LDO5 (3.3 V)
LDO6 (1.2 V)
(VDD_PHY_1V2)
BUCK6 (3.3 V)
(NVCC_3V3)
BUCK8 (1.1 V)
(NVCC_DRAM)
BUCK7 (1.8 V)
(NVCC_1V8)
t1
LDO3 (1.8 V)
(VDDA_1V8,VDDA_DRAM)
BUCK2 (0.9 V)
(VDD_ARM)
LDO4 (0.9 V)
BUCK5 (0.9 V)
OFF
OFF
BUCK1 (0.8 V)
(VDD_SOC,VDDA_0V8,PHY_0V8)
LDO2 (0.8 V)
(VDD_SNVS)
LDO1 (1.8 V)
(NVCC_SNVS)
Figure 3-29. Emergency Shutdown
Symbol
Table 3-46. Emergency Shutdown Timing Specification
Description
Min
Typ
t0
Emergency Event to POR_B Assert and
All VRs Except BUCK7 De-assert Delay
0
t1
POR_B Assert to BUCK7 De-assert Delay
0
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Max
Unit
120
200
μs
30
35
ms
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BD71850MWV
3.3.9. Warm Reset
I2C Write Access for SWRESET = 1
STOP
SDA
D0
ACK
SCL
t1
POR_B
t0
Figure 3-30. Warm Reset (SWRESET)
Table 3-47. Warm Reset (SWRESET) Timing Specification
Description
Min
Typ
Symbol
Unit
-
-
1.0
μs
0.95
1.00
1.05
ms
Table 3-48. Warm Reset (WDOG_B) Timing Specification
Description
Min
Typ
Max
Unit
t0
SCL rising to POR_B assert delay
t1
POR_B assert duration time
WDOG_B
Max
t0
Including debounce time = 100μs
t1
POR_B
Figure 3-31. Warm Reset (WDOG_B)
Symbol
t0
WDOG_B falling to POR_B assert delay
100
110
120
μs
t1
POR_B assert duration time
0.95
1.00
1.05
ms
t0
PWRON_B
t1
POR_B
Figure 3-32. Warm Reset (PWRON_B Long Push)
Symbol
Table 3-49. Warm Reset (PWRON_B Long Push) Timing Specification
Description
Min
Typ
t0
PWRON_B falling to POR_B assert delay
t1
POR_B assert duration time
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Max
Unit
PBDBNCT[1:0] in
PWRONCONFIG0
+ LONGT[3:0] in
PWRONCONFIG1
-50
PBDBNCT[1:0] in
PWRONCONFIG0
+ LONGT[3:0] in
PWRONCONFIG1
PBDBNCT[1:0] in
PWRONCONFIG0
+ LONGT[3:0] in
PWRONCONFIG1
+50
ms
0.95
1.00
1.05
ms
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3.3.10.Reset Source Indicators
The BD71850MWV has RESETSRC register which is intended to store the cause of a shutdown or reset, the firmware
reads this data on the next startup. Depending on the cause of a shutdown or reset, the only bit of RESETSRC register
is 1.
Table 3-50. RESETSRC - Reset Source Indicator Register
Register Name
RESETSRC
R/W
R/W
D7
RPWRON
Bit
Name
D[7]
RPWRON
D[6]
D6
RWDOG
D5
RSWRST
D4
D3
RPMIC_ON_
RVSYS_2P7
REQ
D2
D1
D0
Initial
Address
RTEMP
ROCP
RVR_FAULT
0x00
0x29
Function
Initial
0 = Default
1 = Previous shutdown was due to the PWRON_B Long Push Cold Reset
(Write-1-clear bit)
0
RWDOG
0 = Default
1 = Previous shutdown was due to the WDOG_B Cold Reset
(Write-1-clear bit)
0
D[5]
RSWRST
0 = Default
1 = Previous shutdown was due to the Software Cold Reset
(Write-1-clear bit)
0
D[4]
RPMIC_ON_REQ
0 = Default
1 = Previous shutdown was due to the PMIC_ON_REQ = 0
(Write-1-clear bit)
0
D[3]
RVSYS_2P7
0 = Default
1 = Previous shutdown was due to the Emergency VSYS < 2.7V
(Write-1-clear bit)
0
D[2]
RTEMP
0 = Default
1 = Previous shutdown was due to the Emergency Thermal Shutdown
(Write-1-clear bit)
0
D[1]
ROCP
0 = Default
1 = Previous shutdown was due to the Emergency OCP
(Write-1-clear bit)
0
D[0]
RVR_FAULT
0 = Default
1 = Previous shutdown was due to the Emergency VR Fault
(Write-1-clear bit)
0
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4.
I2C and Interrupt
4.1. I2C Bus Interface
4.1.1. I2C Bus Interface Overview
I2C access is not permitted when the power state = READY.
DVDD
DVDD
[Internal Logic Circuit]
I2C slave controller
DVDD
SCL
Spike Filter
DVDD
SDA
Spike Filter
GND
Figure 4-1. I2C (Slave) Block Diagram
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4.1.2. I2C Bus Interface Electrical Characteristics
Table 4-1. I2C Bus Interface DC Electrical Characteristics
(Unless otherwise specified, Ta=+25°C, VSYS=5.0 V, DVDD=1.8 V)
Limit
Parameter
Symbol
Min
Typ
Max
Digital pin characteristics – Input (SCL)
SCL
VIH_SCL
Input "H" Level
SCL
VIL_SCL
Input "L" Level
SCL
VIHYS_SCL
Input Hysteresis
SCL
IOFF1_SCL
Input Leak Current(Input=0 V)
SCL
IOFF2_SCL
Input Leak Current(Input=5.5 V)
Digital pin characteristics – Input (SDA)
SDA
VIH_SDA
Input "H" Level
SDA
VIL_SDA
Input "L" Level
SDA
VIHYS_SDA
Input Hysteresis
SDA
IOFF1_SDA
Input Leak Current(Input=0 V)
SDA
IOFF2_SDA
Input Leak Current(Input=5.5 V)
Digital pin characteristics - Output (SDA)
SDA
VOL_SDA
Output "L" Level Voltage
Output Off Leak Current(Input=0
IOFF3_SDA
V)
Output Off Leak
IOFF4_SDA
Current(Input=5.5 V)
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DVDD
x 0.7
-
-0.3
-
0.1
-
-
V
-1
-
+1
μA
-1
-
+1
μA
DVDD
x 0.7
-
-0.3
-
0.1
-
-
V
-1
-
+1
μA
-1
-
+1
μA
-
-
0.4
V
-1
-
+1
μA
-1
-
+1
μA
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DVDD
+ 0.3
DVDD
x 0.3
Unit
DVDD
+ 0.3
DVDD
x 0.3
Condition
V
V
V
V
IOL=6mA
TSZ02201-0Q2Q0A500680-1-2
16.Mar.2020 Rev.002
BD71850MWV
I2C Bus Interface Electrical Characteristics – continued
Table 4-2. I2C Bus Interface AC Timing - Fast Mode
(Unless otherwise specified, Ta=+25°C, VSYS=5.0 V, DVDD=1.8 V)
Fast mode
Fast mode plus
Parameter
Symbol
Min
Typ
Max
Min
Typ
Max
4.1.2.
I2C_CLK Clock Frequency
Hold Time START Condition
LOW Period of I2C_CLK Clock
Unit
fSCL
0
-
400
0
-
1000
kHz
tHD_STA
tLOW
0.60
1.3
-
-
0.26
0.5
-
-
μs
μs
tHIGH
0.60
-
-
0.26
-
-
μs
tSU_STA
0.60
-
-
0.26
-
-
μs
HIGH Period of I2C_CLK Clock
Set-up Time for a Repeated START
Condition
Data Hold Time
tHD_DAT
0
-
-
0
-
-
ns
Data Set-up Time
Set-up Time for STOP Condition
tSU_DAT
tSU_STO
100
0.60
-
-
50
0.26
-
-
ns
μs
Fall Time of I2C_DATA Signal
tF
20
300
-
-
120
ns
Capacitive Load for Each Bus Line
Pulse Width of Spikes that are
Suppressed by the Input Filter
Bus Free Time
CB
-
-
400
-
-
550
pF
tSP
0
-
50
0
-
50
ns
tBUF
1.3
-
-
0.5
-
-
μs
tVD_DAT
tVD_ACK
-
-
0.90
0.90
-
-
0.45
0.45
μs
μs
Data Valid Time
Data Valid Acknowledge Time
tF
tR
tSU_DAT
70%
SDA
30%
tF
70%
SCL
tVD_DAT
tHD_DAT
30%
tHD_STA
1 / fSCL
tLOW
tR
S
tHIGH
tBUF
70%
SDA
30%
tSU_STA
SCL
tHD_STA
tSP
tSU_STO
tVD_ACK
70%
30%
Sr
P
S
Figure 4-2. I2C Bus Interface AC Timing
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4.1.3. Device Addressing
Table 4-3. I2C_DEV - I2C Device Address Indicator Register
Register Name
R/W
D7
D6
D5
D4
D3
D2
I2C_DEV
R
-
-
-
-
-
-
Bit
D[1:0]
Name
00 = I2C 7 bit Device Address
01 = I2C 7 bit Device Address
10 = I2C 7 bit Device Address
11 = I2C 7 bit Device Address
0
1
0
0
0
0
0
1
0
0
1
0x03
0x02
Initial
11
R/W
R/W
LSB
0
0
1
0
1
0
MSB
1
Address
LSB
MSB
1
Initial
Read / Write instruction bit
MSB
1
I2C_DEV_ADRS[1:0]
= 0x48
= 0x49
= 0x4A
= 0x4B
I2C Device Address
0
D0
Function
I2C_DEV_ADRS[1:0]
1
D1
R/W
LSB
0
0
1
0
1
MSB
1
R/W
a
LSB
I2C Device Address is decided by OTP setting.
Figure 4-3. I2C Device Addressing
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4.1.4. Write / Read Operation
Write single register
S
7-bit Device
Address
W
Ack
8-bit Data
(Reg. Address)
Ack
8-bit Data
(Write Data)
Ack
8-bit Data
(Write Data #1)
Ack
8-bit Data
(Write Data #1)
Ack
Ack
8-bit Data
(Write Data #N)
Ack
P
Write multiple registers (Address Auto-Increment)
S
7-bit Device
Address
W
Ack
8-bit Data
(Reg. Address)
Ack
8-bit Data
(Write Data #2)
Ack
8-bit Data
(Write Data #3)
Ack
Ack
8-bit Data
(Reg. Address)
Ack
Sr
7-bit Device
Address
R
Ack
8-bit Data
(Read Data)
NAck
Sr
7-bit Device
Address
R
Ack
8-bit Data
(Read Data #1)
Ack
Ack
8-bit Data
NAck
(Read Data #N)
P
Read single register
S
7-bit Device
Address
W
P
Read multiple registers (Address Auto-Increment)
S
7-bit Device
Address
W
Ack
8-bit Data
(Reg. Address)
Ack
8-bit Data
(Read Data #2)
Ack
8-bit Data
(Read Data #3)
Ack
S
Start Condition
Sr
Repeat Start Condition
W
Write (= Low)
R
Read (= High)
Ack Acknowledge (= Low, driven by I2C Slave)
P
P
Stop Condition
Ack Acknowledge (= Low, driven by I2C Master)
NAck Not Acknowledge (= High, driven by I2C Master)
Figure 4-4. I2C Write / Read Operation
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4.2. Interrupt
4.2.1. Interrupt Overview
IRQ Event
PWRON
PWRON_S
PWRON_L
WDOG
SWRST
ON_REQ
STBY_REQ
Write 1 Clear
Table 4-4. Interrupt Event
Definition
PWRON_B Pin Level Changed
PWRON_B Short Push Detection
PWRON_B Long Push Detection
WDOG_B Pin Level Changed
Written 1 to SWRESET in SWRESET Register
PMIC_ON_REQ Pin Level Changed
PMIC_STBY_REQ Pin Level Changed
Mask bit from
MIRQ register
IRQ_B
RN
D Q
IRQ Event
CP
to IRQ register
Figure 4-5. IRQ_B Architecture Block Diagram
Table 4-5. IRQ_B Electrical Characteristics
(Unless otherwise specified, Ta=+25°C, VSYS=5.0 V, DVDD=1.8 V)
Limit
Parameter
Symbol
Min
Typ
Max
Output "L" Level Voltage
VOL_IRQB
DVDD x 0.2
Output Off Leak Current
IOLK_IRQB
-1
+1
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Unit
Condition
V
μA
IOL=3 mA Sink
TSZ02201-0Q2Q0A500680-1-2
16.Mar.2020 Rev.002
BD71850MWV
4.2.1.
Interrupt Overview – continued
Table 4-6. IRQ - Interrupt Register
Register Name
R/W
D7
D6
D5
D4
D3
D2
D1
D0
Initial
Address
IRQ
R/W
-
SWRST
PWRON_S
PWRON_L
PWRON
WDOG
ON_REQ
STBY_REQ
0x00
0x2B
Bit
Name
Function
Initial
0 = SWRESET in SWRESET register is not written 1
1 = SWRESET in SWRESET register is written 1
This bit is a write-1-to-clear bit.
0
D[6]
SWRST
D[5]
PWRON_S
0 = PWRON_B Short Push not detected
1 = PWRON_B Short Push detected
This bit is a write-1-to-clear bit.
0
D[4]
PWRON_L
0 = PWRON_B Long Push not detected
1 = PWRON_B Long Push detected
This bit is a write-1-to-clear bit.
0
D[3]
PWRON
0 = PWRON_B level change not generated
1 = PWRON_B level change generated
This bit is a write-1-to-clear bit.
0
D[2]
WDOG
0 = WDOG_B level change not generated
1 = WDOG_B level change generated
This bit is a write-1-to-clear bit.
0
D[1]
ON_REQ
0 = PMIC_ON_REQ level change not generated
1 = PMIC_ON_REQ level change generated
This bit is a write-1-to-clear bit.
0
D[0]
STBY_REQ
0 = PMIC_STBY_REQ level change not generated
1 = PMIC_STBY_REQ level change generated
This bit is a write-1-to-clear bit.
0
Table 4-7. MIRQ – IRQ Mask Register
Register Name
R/W
D7
D6
MIRQ
R/W
-
MSWRST
Bit
D5
D4
MPWRON_ MPWRON_
S
L
Name
D3
D2
D1
D0
Initial
Address
MPWRON
MWDOG
MON_REQ
MSTBY_
REQ
0x7F
0x2A
Function
Initial
D[6]
MSWRST
0 = No Mask
1 = Mask Interrupt
D[5]
MPWRON_S
0 = No Mask
1 = Mask Interrupt
1
D[4]
MPWRON_L
0 = No Mask
1 = Mask Interrupt
1
D[3]
MPWRON
0 = No Mask
1 = Mask Interrupt
1
D[2]
MWDOG
0 = No Mask
1 = Mask Interrupt
1
D[1]
MON_REQ
0 = No Mask
1 = Mask Interrupt
1
D[0]
MSTBY_REQ
0 = No Mask
1 = Mask Interrupt
1
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BD71850MWV
4.2.1.
Interrupt Overview – continued
Table 4-8. IN_MON - Input Port Monitor Register
Register Name
R/W
D7
D6
D5
D4
D3
D2
D1
D0
Initial
Address
IN_MON
R
-
-
-
-
STAT_
PWRON
STAT_
WDOG
STAT_
ON_REQ
STAT_
STBY_REQ
0x00
0x2C
Bit
Name
D[3]
STAT_PWRON
D[2]
STAT_WDOG
D[1]
STAT_ON_REQ
D[0]
STAT_STBY_REQ
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Function
Initial
0 = PWRON_B level is 0
1 = PWRON_B level is 1
0
0 = WDOG_B level is 0
1 = WDOG_B level is 1
0
0 = PMIC_ON_REQ level is 0
1 = PMIC_ON_REQ level is 1
0
0 = PMIC_STBY_REQ level is 0
1 = PMIC_STBY_REQ level is 1
0
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5.
Power Rails
5.1. Output Voltage Range
Table 5-1. Output Voltage Range1
Data
[Hex]
BUCK1 BUCK2
-
-
BUCK5 BUCK6 BUCK7 BUCK8 LDO1
LDO5
LDO6
1.80
0.90
0.90
(Note 1)
3.10
1.90
1.00
1.90
1.00
0.82
3.20
2.00
1.10
2.00
1.10
0.83
3.30
2.10
1.20
2.10
0.84
2.20
1.30
2.20
1.30
1.905
0.85
2.30
1.40
2.30
1.40
1.20
1.950
0.86
2.40
1.50
2.40
1.50
1.35
1.995
0.87
2.50
1.60
2.50
1.60
0.78
0.88
2.60
1.70
2.60
1.70
0.79
0.89
2.70
1.80
2.70
1.80
0.80
0.90
2.80
2.80
0.70
0.70
3.00
1.605
0.80
3.00
01
0.71
0.71
0.80
3.10
1.695
0.81
02
0.72
0.72
3.20
1.755
03
0.73
0.73
1.00
3.30
1.800
(Note 1)
(Note 1)
04
0.74
0.74
1.05
1.845
05
0.75
0.75
1.10
06
0.76
0.76
07
0.77
0.77
08
0.78
09
0.79
(Note 1)
LDO4
1.80
0.70
0A
LDO3
(Note 1)
00
0.80
LDO2
0.90
(Note 1)
0.90
0B
0.81
0.81
0.91
2.90
2.90
0C
0.82
0.82
0.92
3.00
3.00
0D
0.83
0.83
0.93
3.10
3.10
0E
0.84
0.84
0.94
3.20
3.20
0F
0.85
0.85
0.95
3.30
10
0.86
0.86
0.96
11
0.87
0.87
0.97
12
0.88
0.88
0.98
13
0.89
0.89
0.99
14
0.90
15
0.91
0.91
1.01
16
0.92
0.92
1.02
17
0.93
0.93
1.03
18
0.94
0.94
1.04
19
0.95
0.95
1.05
1A
0.96
0.96
1.06
1B
0.97
0.97
1.07
1C
0.98
0.98
1.08
1D
0.99
0.99
1.09
1E
1.00
1.00
1F
1.01
1.01
0.90
-
1.20
(Note 1)
3.30
(Note 1)
1.00
(Note 1)
1.10
(Note 1)
1.11
(Note 1) initial voltage(run mode)
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5.1. Output Voltage Range – continued
Table 5-2. Output Voltage Range2
Data
[Hex]
BUCK1 BUCK2
-
-
BUCK5 BUCK6 BUCK7 BUCK8 LDO1
20
1.02
1.02
1.12
1.60
21
1.03
1.03
1.13
1.70
22
1.04
1.04
1.14
23
1.05
1.05
1.15
24
1.06
1.06
1.16
25
1.07
1.07
1.17
26
1.08
1.08
1.18
27
1.09
1.09
1.19
28
1.10
1.10
1.20
29
1.11
1.11
1.21
2A
1.12
1.12
1.22
2B
1.13
1.13
1.23
2C
1.14
1.14
1.24
2D
1.15
1.15
1.25
2E
1.16
1.16
1.26
2F
1.17
1.17
1.27
30
1.18
1.18
1.28
31
1.19
1.19
1.29
32
1.20
1.20
1.30
33
1.21
1.21
1.31
34
1.22
1.22
1.32
35
1.23
1.23
1.33
36
1.24
1.24
1.34
37
1.25
1.25
1.35
38
1.26
1.26
1.36
39
1.27
1.27
1.37
3A
1.28
1.28
1.38
3B
1.29
1.29
1.39
3C
1.30
1.30
1.40
LDO2
LDO3
LDO4
LDO5
LDO6
-
0.80
(Note 1)
1.80
(Note 1)
1.90
3D
3E
3F
(Note 1) initial voltage(run mode)
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TSZ02201-0Q2Q0A500680-1-2
16.Mar.2020 Rev.002
BD71850MWV
5.2. Details of Buck
5.2.1. BUCK1
5.2.1.1.
BUCK1 Block Diagram
VSYS
INT LDO 1P5
BUCK1_VIN
OCP
V RE F
V oltage set ting
OSC
DAC
BUCK1_LX
-
Soft Start
Switch
Control
LBK 1
COB K1
+
P GND
(EX P-P AD)
EN
BUCK1_FB
Discharge
Resistor
V R Controller
EN
GND
P GND
(EX P-P AD)
V R Fault S ignal
VR Fault
Detector
Figure 5-1. BUCK1 Block Diagram
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TSZ02201-0Q2Q0A500680-1-2
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BD71850MWV
5.2.1.2.
BUCK1 Electrical Characteristics
Table 5-3. BUCK1 Electrical Characteristics
(Unless otherwise specified, Ta=+25 °C, VSYS=5.0 V)
Parameter
Symbol
Limit
Unit
Condition
Min
Typ
Max
VO_BK1
0.791
0.800
0.809
V
Vo = 0.8 V
Io = 200 mA, PWM fix Mode
VORG_BK1
0.7
-
1.3
V
10 mV step
IQ_BK1
-
15
-
µA
Vo = 0.8 V
Io = 0 mA, Auto mode
Maximum Output Current
IOMAX_BK1
3000
-
-
mA
Over Current Protection
IOCP_BK1
4500
-
-
mA
Peak current of inductor
ΔVLDR_BK1
-1
0
+1
%
Io = 1 mA to Iomax, PWM fix Mode
ηBK1_1mA
-
80
-
%
Io = 1 mA, Vo = 0.8 V
ηBK1_500mA
-
84
-
%
Io = 500 mA, Vo = 0.8 V
ηBK1_max
-
70
-
%
Io = Iomax, Vo = 0.8 V
Oscillating Frequency
fSW_BK1
-
2
-
MHz
Start up Time
tST_BK1
-
144
500
µs
Discharge Resistance
R D_BK1
-
100
-
Ω
DVRFBK1_L
-
80
-
%
DVRFBK1_LHYS
-
10
-
%
DVRBK1_H
-
130
-
%
DVRFBK1_HHYS
-
20
-
%
LBK1
-
0.47
-
μH
C OBK1
22
44
100
μF
Output Voltage
Programmable
Output Voltage Range
Quiescent Current
DC Output Voltage Load Regulation
Efficiency
Low Side VR Fault Detect Level
Low Side VR Fault Detect Hysteresis
High Side VR Fault Detect Level
High Side VR Fault Detect Hysteresis
Output Inductance
Output Capacitance
(Note 1)
PWM fix mode, Io = 0 mA
During EN to 90 % of nominal Voltage,
BUCK1_RAMPRATE_RUN[1:0] = 01
Vo = 0.8 V (FB = Sweep down)
VR fault detect level / Vo x 100
(VR fault release level - detect level) / Vo x
100
Vo = 0.8 V (FB = Sweep up)
Power good detect level / Vo x 100
(VR fault detect level - release level) / Vo x
100
(Note 2)
(Note 2)
Effective capacitance with BUCK's DC bias
Max value is limited by ramp rate.
ramp rate 1.25 mV, 2.5 mV, 5 mV : 100 µF
ramp rate 10 mV : 50 µF
(Note 1) For Buck- DCDC converters, (minimum Over Current Protection Current – ½ inductor ripple current) is the maximum output current.
(Note 2) This part value range need to be guaranteed over the operating surrounding temperature.
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BD71850MWV
5.2.1.3.
BUCK1 Control
Table 5-4. BUCK1_CTRL - BUCK1 Control Register
Register Name
BUCK1_CTRL
R/W
R/W
Bit
D[7:6]
D7
D6
BUCK1_RAMPRATE
[1:0]
D5
-
D4
D3
D2
-
BUCK1_
PWM_FIX
-
Name
D1
D0
BUCK1_SEL BUCK1_EN
Initial
Address
0x40
0x05
Function
BUCK1_RAMPRATE[1:0]
Initial
BUCK1 DVS ramp rate
00 = 10 mV/μs
01 = 5 mV/μs
10 = 2.5 mV/μs
11 = 1.25 mV/μs
Note : When BUCK1 voltage starts up from 0V,
the ramp rate is fixed 5mV/μs, regardless of the value of
BUCK1_RAMPRATE[1:0].
01
0 – AUTO PWM/PFM mode
VR adjusts the operating mode (PFM/PWM) automatically based on the load
current to maximize power efficiency.
1 – Forced PWM Mode
VR operates in PWM mode only.
0
D[3]
BUCK1_PWM_FIX
D[1]
BUCK1_SEL
BUCK1 control select bit
0 = BUCK1 ON/OFF is controlled by state machine.
1 = BUCK1 ON/OFF is controlled by D[0] on this register.
0
BUCK1_EN
BUCK1 control bit with condition of D[1]
0 = BUCK1 OFF
1 = BUCK1 ON
This bit returns to 0 at the beginning of PWROFF sequence or emergency
shutdown.
When system is in SNVS, BUCK1_SEL = 1 and BUCK1_EN = 1, BUCK1
voltage is specified by BUCK1_VOLT_SUSP register.
0
D[0]
Table 5-5. BUCK1_VOLT_RUN - BUCK1 Voltage (RUN) Register
Register Name
R/W
D7
BUCK1_VOLT_RUN
R/W
-
Bit
D[6:0]
D6
D5
D4
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D2
D1
BUCK1_VOLT_RUN[6:0]
Name
BUCK1_VOLT_RUN[6:0]
D3
Function
BUCK1 voltage when Power State = RUN
0x00 = 0.70 V
0x01 = 0.71 V
0x02 = 0.72 V
0x04 = 0.74 V
0x05 = 0.75 V
0x06 = 0.76 V
0x08 = 0.78 V
0x09 = 0.79 V
0x0A = 0.80V(initial)
0x0B = 0.81 V
0x0C = 0.82 V
0x0D = 0.83 V
0x0F = 0.85 V
0x10 = 0.86 V
0x11 = 0.87 V
0x13 = 0.89 V
0x14 = 0.90 V
0x15 = 0.91 V
0x16 = 0.92 V
0x17 = 0.93 V
0x19 = 0.95 V
0x1A = 0.96 V
0x1B = 0.97 V
0x1D = 0.99 V
0x1E = 1.00 V
0x1F = 1.01 V
0x21 = 1.03 V
0x22 = 1.04 V
0x23 = 1.05 V
0x25 = 1.07 V
0x26 = 1.08 V
0x27 = 1.09 V
0x29 = 1.11 V
0x2A = 1.12 V
0x2B = 1.13 V
0x2D = 1.15 V
0x2E = 1.16 V
0x2F = 1.17 V
0x31 = 1.19 V
0x32 = 1.20 V
0x33 = 1.21 V
0x35 = 1.23 V
0x36 = 1.24 V
0x37 = 1.25 V
0x39 = 1.27 V
0x3A = 1.28 V
0x3B = 1.29 V
0x3D-0x7F = reserved
74/116
D0
Initial
Address
0x0A
0x0D
Initial
0x03 = 0.73 V
0x07 = 0.77 V
0x0E = 0.84 V
0x12 = 0.88 V
0x18 = 0.94 V
0x1C = 0.98 V
0x20 = 1.02 V
0x24 = 1.06 V
0x28 = 1.10 V
0x2C = 1.14 V
0x30 = 1.18 V
0x34 = 1.22 V
0x38 = 1.26 V
0x3C = 1.30 V
0001010
TSZ02201-0Q2Q0A500680-1-2
16.Mar.2020 Rev.002
BD71850MWV
5.2.1.3.
BUCK1 Control – continued
Table 5-6. BUCK1_VOLT_IDLE - BUCK1 Voltage (IDLE) Register
Register Name
R/W
D7
BUCK1_VOLT_IDLE
R/W
-
Bit
D[6:0]
D6
D5
D4
D3
D2
D1
D0
BUCK1_VOLT_IDLE[6:0]
Name
Initial
Address
0x0A
0x0E
Function
BUCK1_VOLT_IDLE[6:0]
Initial
BUCK1 voltage when Power State = IDLE
0x00 = 0.70 V
0x01 = 0.71 V
0x02 = 0.72 V
0x04 = 0.74 V
0x05 = 0.75 V
0x06 = 0.76 V
0x08 = 0.78 V
0x09 = 0.79 V
0x0A = 0.80 V(initial)
0x0B = 0.81 V
0x0C = 0.82 V
0x0D = 0.83 V
0x0F = 0.85 V
0x10 = 0.86 V
0x11 = 0.87 V
0x13 = 0.89 V
0x14 = 0.90 V
0x15 = 0.91 V
0x16 = 0.92 V
0x17 = 0.93 V
0x19 = 0.95 V
0x1A = 0.96 V
0x1B = 0.97 V
0x1D = 0.99 V
0x1E = 1.00 V
0x1F = 1.01 V
0x21 = 1.03 V
0x22 = 1.04 V
0x23 = 1.05 V
0x25 = 1.07 V
0x26 = 1.08 V
0x27 = 1.09 V
0x29 = 1.11 V
0x2A = 1.12 V
0x2B = 1.13 V
0x2D = 1.15 V
0x2E = 1.16 V
0x2F = 1.17 V
0x31 = 1.19 V
0x32 = 1.20 V
0x33 = 1.21 V
0x35 = 1.23 V
0x36 = 1.24 V
0x37 = 1.25 V
0x39 = 1.27 V
0x3A = 1.28 V
0x3B = 1.29 V
0x3D-0x7F = reserved
0x03 = 0.73 V
0x07 = 0.77 V
0x0E = 0.84 V
0x12 = 0.88 V
0x18 = 0.94 V
0x1C = 0.98 V
0x20 = 1.02 V
0x24 = 1.06 V
0x28 = 1.10 V
0x2C = 1.14 V
0x30 = 1.18 V
0x34 = 1.22 V
0x38 = 1.26 V
0x3C = 1.30 V
0001010
Table 5-7. BUCK1_VOLT_SUSP - BUCK1 Voltage (SUSPEND) Register
Register Name
R/W
D7
BUCK1_VOLT_SUSP
R/W
-
Bit
D[6:0]
D6
D5
D4
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D2
D1
BUCK1_VOLT_SUSP[6:0]
Name
BUCK1_VOLT_SUSP[6:0]
D3
Function
BUCK1 voltage when Power State = SUSPEND
0x00 = 0.70 V
0x01 = 0.71 V
0x02 = 0.72 V
0x04 = 0.74 V
0x05 = 0.75 V
0x06 = 0.76 V
0x08 = 0.78 V
0x09 = 0.79 V
0x0A = 0.80V(initial)
0x0B = 0.81 V
0x0C = 0.82 V
0x0D = 0.83 V
0x0F = 0.85 V
0x10 = 0.86 V
0x11 = 0.87 V
0x13 = 0.89 V
0x14 = 0.90 V
0x15 = 0.91 V
0x16 = 0.92 V
0x17 = 0.93 V
0x19 = 0.95 V
0x1A = 0.96 V
0x1B = 0.97 V
0x1D = 0.99 V
0x1E = 1.00 V
0x1F = 1.01 V
0x21 = 1.03 V
0x22 = 1.04 V
0x23 = 1.05 V
0x25 = 1.07 V
0x26 = 1.08 V
0x27 = 1.09 V
0x29 = 1.11 V
0x2A = 1.12 V
0x2B = 1.13 V
0x2D = 1.15 V
0x2E = 1.16 V
0x2F = 1.17 V
0x31 = 1.19 V
0x32 = 1.20 V
0x33 = 1.21 V
0x35 = 1.23 V
0x36 = 1.24 V
0x37 = 1.25 V
0x39 = 1.27 V
0x3A = 1.28 V
0x3B = 1.29 V
0x3D-0x7F = reserved
75/116
D0
Initial
Address
0x0A
0x0F
Initial
0x03 = 0.73 V
0x07 = 0.77 V
0x0E = 0.84 V
0x12 = 0.88 V
0x18 = 0.94 V
0x1C = 0.98 V
0x20 = 1.02 V
0x24 = 1.06 V
0x28 = 1.10 V
0x2C = 1.14 V
0x30 = 1.18 V
0x34 = 1.22 V
0x38 = 1.26 V
0x3C = 1.30 V
0001010
TSZ02201-0Q2Q0A500680-1-2
16.Mar.2020 Rev.002
BD71850MWV
5.2.2. BUCK2
5.2.2.1.
BUCK2 Block Diagram
VSYS
INT LDO 1P5
BUCK2_VIN
OCP
V RE F
V oltage set ting
OSC
DAC
BUCK2_LX
-
Soft Start
Switch
Control
LBK 2
COB K2
+
P GND
(EX P-P AD)
EN
BUCK2_FB
Discharge
Resistor
V R Controller
EN
GND
P GND
(EX P-P AD)
V R Fault S ignal
VR Fault
Detector
Figure 5-2. BUCK2 Block Diagram
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5.2.2.2.
BUCK2 Electrical Characteristics
Table 5-8. BUCK2 Electrical Characteristics
(Unless otherwise specified, Ta=+25 °C, VSYS=5.0 V)
Parameter
Symbol
Limit
Unit
Condition
Min
Typ
Max
VO_BK2
0.89
0.90
0.91
V
Vo = 0.9 V
Io = 200 mA, PWM fix Mode
VORG_BK2
0.7
-
1.3
V
10 mV step
IQ_BK2
-
15
-
µA
Vo = 0.9 V
Io = 0 mA, Auto mode
Maximum Output Current
IOMAX_BK2
3000
-
-
mA
Over Current Protection
IOCP_BK2
4500
-
-
mA
Peak current of inductor
ΔVLDR_BK2
-1
0
+1
%
Io = 1 mA to Iomax, PWM fix Mode
ηBK2_1mA
-
79
-
%
Io = 1 mA, Vo = 0.9 V
ηBK2_500mA
-
84
-
%
Io = 500 mA, Vo = 0.9 V
ηBK2_max
-
71
-
%
Io = Iomax, Vo = 0.9 V
Oscillating Frequency
fSW_BK2
-
2
-
MHz
Start up Time
tST_BK2
-
162
500
µs
Discharge Resistance
RD_BK2
-
100
-
Ω
D VRFBK2_L
-
80
-
%
DVRFBK2_LHYS
-
10
-
%
D VRBK2_H
-
130
-
%
Vo = 0.9 V (FB = Sweep up)
Power good detect level / Vo x 100
DVRFBK2_HHYS
-
20
-
%
(VR fault detect level - release level) / Vo x
100
LBK2
-
0.47
-
μH
COBK2
22
44
100
μF
Output Voltage
Programmable
Output Voltage Range
Quiescent Current
DC Output Voltage Load Regulation
Efficiency
Low Side VR Fault Detect Level
Low Side VR Fault Detect Hysteresis
High Side VR Fault Detect Level
High Side VR Fault Detect Hysteresis
Output Inductance
Output Capacitance
(Note 1)
PWM fix mode, Io = 0 mA
During EN to 90 % of nominal Voltage,
BUCK2_RAMPRATE_RUN[1:0] = 01
Vo = 0.9 V (FB = Sweep down)
VR fault detect level / Vo x 100
(VR fault release level - detect level) / Vo x
100
(Note 2)
(Note 2)
Effective capacitance with BUCK's DC bias
Max value is limited by ramp rate.
ramp rate 1.25 mV, 2.5 mV, 5 mV : 100 µF
ramp rate 10 mV : 50 µF
(Note 1) For Buck- DCDC converters, (minimum Over Current Protection Current – ½ inductor ripple current) is the maximum output current.
(Note 2) This part value range need to be guaranteed over the operating surrounding temperature.
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BD71850MWV
5.2.2.3.
BUCK2 Control
Table 5-9. BUCK2_CTRL - BUCK2 Control Register
Register Name
R/W
BUCK2_CTRL
R/W
Bit
D[7:6]
D7
D6
BUCK2_RAMPRATE[1:0]
D5
D4
-
-
D3
BUCK2_
PWM_FIX
Name
D2
-
D1
D0
BUCK2_SEL BUCK2_EN
Initial
Address
0x40
0x06
Function
BUCK2_RAMPRATE[1:0]
Initial
BUCK2 DVS ramp rate
00 = 10 mV/μs
01 = 5 mV/μs
10 = 2.5 mV/μs
11 = 1.25 mV/μs
Note : When BUCK2 voltage starts up from 0V,
the ramp rate is fixed 5mV/μs, regardless of the value of
BUCK2_RAMPRATE[1:0].
01
0 – AUTO PWM/PFM mode
VR adjusts the operating mode (PFM/PWM) automatically based on the load
current to maximize power efficiency.
1 – Forced PWM Mode
VR operates in PWM mode only.
0
D[3]
BUCK2_PWM_FIX
D[1]
BUCK2_SEL
BUCK2 control select bit
0 = BUCK2 ON/OFF is controlled by state machine.
1 = BUCK2 ON/OFF is controlled by D[0] on this register.
0
BUCK2_EN
BUCK2 control bit with condition of D[1]
0 = BUCK2 OFF
1 = BUCK2 ON
This bit returns to 0 at the beginning of PWROFF sequence or emergency
shutdown.
When system is in SNVS or SUSPEND, BUCK2_SEL = 1 and BUCK2_EN = 1,
BUCK2 voltage is specified by BUCK2_VOLT_IDLE register.
0
D[0]
Table 5-10. BUCK2_VOLT_RUN - BUCK2 Voltage (RUN) Register
Register Name
R/W
D7
BUCK2_VOLT_RUN
R/W
-
Bit
D[6:0]
D6
D5
D4
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D2
D1
BUCK2_VOLT_RUN[6:0]
Name
BUCK2_VOLT_RUN[6:0]
D3
Function
BUCK2 voltage when Power State = RUN
0x00 = 0.70 V
0x01 = 0.71 V
0x02 = 0.72 V
0x04 = 0.74 V
0x05 = 0.75 V
0x06 = 0.76 V
0x08 = 0.78 V
0x09 = 0.79 V
0x0A = 0.80 V
0x0C = 0.82 V
0x0D = 0.83 V
0x0E = 0.84 V
0x10 = 0.86 V
0x11 = 0.87 V
0x12 = 0.88 V
0x14 = 0.90 V (initial)
0x15 = 0.91 V
0x16 = 0.92 V
0x17 = 0.93 V
0x19 = 0.95 V
0x1A = 0.96 V
0x1B = 0.97 V
0x1D = 0.99 V
0x1E = 1.00 V
0x1F = 1.01 V
0x21 = 1.03 V
0x22 = 1.04 V
0x23 = 1.05 V
0x25 = 1.07 V
0x26 = 1.08 V
0x27 = 1.09 V
0x29 = 1.11 V
0x2A = 1.12 V
0x2B = 1.13 V
0x2D = 1.15 V
0x2E = 1.16 V
0x2F = 1.17 V
0x31 = 1.19 V
0x32 = 1.20 V
0x33 = 1.21 V
0x35 = 1.23 V
0x36 = 1.24 V
0x37 = 1.25 V
0x39 = 1.27 V
0x3A = 1.28 V
0x3B = 1.29 V
0x3D-0x7F = reserved
78/116
D0
Initial
Address
0x14
0x10
Initial
0x03 = 0.73 V
0x07 = 0.77 V
0x0B = 0.81 V
0x0F = 0.85 V
0x13 = 0.89 V
0x18 = 0.94 V
0x1C = 0.98 V
0x20 = 1.02 V
0x24 = 1.06 V
0x28 = 1.10 V
0x2C = 1.14 V
0x30 = 1.18 V
0x34 = 1.22 V
0x38 = 1.26 V
0x3C = 1.30 V
0010100
TSZ02201-0Q2Q0A500680-1-2
16.Mar.2020 Rev.002
BD71850MWV
5.2.2.3.
BUCK2 Control – continued
Table 5-11. BUCK2_VOLT_IDLE - BUCK2 Voltage (IDLE) Register
Register Name
R/W
D7
BUCK2_VOLT_IDLE
R/W
-
Bit
D[6:0]
D6
D5
D4
Name
BUCK2_VOLT_IDLE[6:0]
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TSZ22111 • 15 • 001
D3
D2
D1
BUCK2_VOLT_IDLE[6:0]
Function
BUCK2 voltage when Power State = IDLE
0x00 = 0.70 V
0x01 = 0.71 V
0x02 = 0.72 V
0x04 = 0.74 V
0x05 = 0.75 V
0x06 = 0.76 V
0x08 = 0.78 V
0x09 = 0.79 V
0x0A = 0.80V(initial)
0x0B = 0.81 V
0x0C = 0.82 V
0x0D = 0.83 V
0x0F = 0.85 V
0x10 = 0.86 V
0x11 = 0.87 V
0x13 = 0.89 V
0x14 = 0.90 V
0x15 = 0.91 V
0x16 = 0.92 V
0x17 = 0.93 V
0x19 = 0.95 V
0x1A = 0.96 V
0x1B = 0.97 V
0x1D = 0.99 V
0x1E = 1.00 V
0x1F = 1.01 V
0x21 = 1.03 V
0x22 = 1.04 V
0x23 = 1.05 V
0x25 = 1.07 V
0x26 = 1.08 V
0x27 = 1.09 V
0x29 = 1.11 V
0x2A = 1.12 V
0x2B = 1.13 V
0x2D = 1.15 V
0x2E = 1.16 V
0x2F = 1.17 V
0x31 = 1.19 V
0x32 = 1.20 V
0x33 = 1.21 V
0x35 = 1.23 V
0x36 = 1.24 V
0x37 = 1.25 V
0x39 = 1.27 V
0x3A = 1.28 V
0x3B = 1.29 V
0x3D-0x7F = reserved
79/116
D0
Initial
Address
0x0A
0x11
Initial
0x03 = 0.73 V
0x07 = 0.77 V
0x0E = 0.84 V
0x12 = 0.88 V
0x18 = 0.94 V
0x1C = 0.98 V
0x20 = 1.02 V
0x24 = 1.06 V
0x28 = 1.10 V
0x2C = 1.14 V
0x30 = 1.18 V
0x34 = 1.22 V
0x38 = 1.26 V
0x3C = 1.30 V
0001010
TSZ02201-0Q2Q0A500680-1-2
16.Mar.2020 Rev.002
BD71850MWV
5.2.3. BUCK5
5.2.3.1.
BUCK5 Block Diagram
VSYS
INT LDO 1P5
BUCK5_VIN
OCP
V RE F
V oltage set ting
OSC
DAC
BUCK5_LX
-
Soft Start
Switch
Control
LBK 5
COB K5
+
P GND
(EX P-P AD)
EN
BUCK5_FB
Discharge
Resistor
V R Controller
EN
GND
P GND
(EX P-P AD)
V R Fault S ignal
VR Fault
Detector
Figure 5-3. BUCK5 Block Diagram
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BD71850MWV
5.2.3.2.
BUCK5 Electrical Characteristics
Table 5-12. BUCK5 Electrical Characteristics
(Unless otherwise specified, Ta=+25 °C, VSYS=5.0 V)
Parameter
Symbol
Limit
Unit
Condition
Min
Typ
Max
VO_BK5
0.89
0.90
0.91
V
VORG_BK5
0.70
-
1.35
V
IQ_BK5
-
15
-
µA
Maximum Output Current
IOMAX_BK5
3000
-
-
mA
Over Current Protection
IOCP_BK5
4500
-
-
mA
Peak current of inductor(Note 1)
ΔVLDR_BK5
-1
0
+1
%
Io = 1 mA to Iomax, PWM fix Mode
ηBK5_1mA
-
79
-
%
Io = 1 mA, Vo = 0.9 V
ηBK5_500mA
-
84
-
%
Io = 500 mA, Vo = 0.9 V
ηBK5_max
-
71
-
%
Io = Iomax, Vo = 0.9 V
Oscillating Frequency
fSW_BK5
-
2
-
MHz
Start up Time
tST_BK5
-
162
500
µs
Discharge Resistance
RD_BK5
-
100
-
Ω
DVRFBK5_L
-
80
-
%
DVRFBK5_LHYS
-
10
-
%
DVRBK5_H
-
130
-
%
DVRFBK5_HHYS
-
20
-
%
LBK5
-
0.47
-
μH
(Note 2)
COBK5
22
44
100
μF
(Note 2)
Effective capacitance with BUCK's DC bias
Output Voltage
Programmable
Output Voltage Range
Quiescent Current
DC Output Voltage Load Regulation
Efficiency
Low Side VR Fault Detect Level
Low Side VR Fault Detect Hysteresis
High Side VR Fault Detect Level
High Side VR Fault Detect Hysteresis
Output Inductance
Output Capacitance
Vo = 0.9 V
Io = 200 mA, PWM fix Mode
0.70 V, 0.80 V, 0.90 V, 1.00 V,
1.05 V, 1.10 V, 1.20 V, 1.35 V
Vo = 0.9 V
Io = 0 mA, Auto mode
PWM fix mode, Io = 0 mA
During EN to 90 % of nominal Voltage
Vo = 0.9 V (FB = Sweep down)
VR fault detect level / Vo x 100
(VR fault release level - detect level) / Vo x
100
Vo = 0.9 V (FB = Sweep up)
Power good detect level / Vo x 100
(VR fault detect level - release level) / Vo x
100
(Note 1) For Buck- DCDC converters, (minimum Over Current Protection Current – ½ inductor ripple current) is the maximum output current.
(Note 2) This part value range need to be guaranteed over the operating surrounding temperature.
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BD71850MWV
5.2.3.3.
BUCK5 Control
Table 5-13. BUCK5_CTRL - BUCK5 Control Register
Register Name
R/W
D7
D6
D5
D4
BUCK5_CTRL
R/W
-
-
-
-
Bit
D3
BUCK5_PW
M_FIX
Name
D2
-
D1
D0
BUCK5_SEL BUCK5_EN
Initial
Address
0x02
0x09
Function
Initial
0 – AUTO PWM/PFM mode
VR adjusts the operating mode (PFM/PWM) automatically based on the load
current to maximize power efficiency.
1 – Forced PWM Mode
VR operates in PWM mode only.
0
D[3]
BUCK5_PWM_FIX
D[1]
BUCK5_SEL
BUCK5 control select bit
0 = BUCK5 ON/OFF is controlled by state machine.
1 = BUCK5 ON/OFF is controlled by D[0] on this register.
1
BUCK5_EN
BUCK5 control bit with condition of D[1]
0 = BUCK5 OFF
1 = BUCK5 ON
This bit returns to 0 at the beginning of PWROFF sequence or emergency
shutdown.
0
D[0]
Table 5-14. BUCK5_VOLT - BUCK5 Voltage Register
Register Name
R/W
BUCK5_VOLT
R/W
D7
D6
BUCK5_
VOLT_SEL[1:0]
Bit
Name
D[7:6]
BUCK5_VOLT_SEL[1:0]
D[2:0]
BUCK5_VOLT[2:0]
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D5
D4
D3
-
-
-
D2
D1
BUCK5_VOLT[2:0]
Function
Initial
Address
0x02
0x14
Initial
Select the BUCK5 voltage range set by D[2:0].
00 = 0.70 V to 1.35 V
01 = 0.55 V to 0.90 V
10 = 0.675 V to 1.325 V 11 = reserved
00
BUCK5 voltage
If D[7:6]=00
000 = 0.70 V 001 = 0.80 V 010 = 0.90 V (Initial) 011 = 1.00 V
100 = 1.05 V 101 = 1.10 V 110 = 1.20 V
111 = 1.35 V
If D[7:6]=01
000 = 0.55 V 001 = 0.60 V 010 = 0.65 V 011 = 0.70 V
100 = 0.75 V 101 = 0.80 V 110 = 0.85 V 111 = 0.90 V
If D[7:6]=10
000 = 0.675 V 001 = 0.775 V 010 = 0.875 V 011 = 0.975 V
100 = 1.025 V 101 = 1.075 V 110 = 1.175 V 111 = 1.325 V
82/116
D0
010
TSZ02201-0Q2Q0A500680-1-2
16.Mar.2020 Rev.002
BD71850MWV
5.2.4. BUCK6
5.2.4.1.
BUCK6 Block Diagram
VSYS
INT LDO 1P5
BUCK6_VIN
OCP
V RE F
V oltage set ting
OSC
DAC
BUCK6_LX
-
Soft Start
Switch
Control
LBK 6
COB K6
+
P GND
(EX P-P AD)
EN
BUCK6_FB
Discharge
Resistor
V R Controller
EN
GND
P GND
(EX P-P AD)
V R Fault S ignal
VR Fault
Detector
Figure 5-4. BUCK6 Block Diagram
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BD71850MWV
5.2.4.2.
BUCK6 Electrical Characteristics
Table 5-15. BUCK6 Electrical Characteristics
(Unless otherwise specified, Ta=+25 °C, VSYS=5.0 V)
Parameter
Symbol
Limit
Unit
Condition
Min
Typ
Max
VO_BK6
3.267
3.300
3.333
V
Vo=3.3 V
Io = 200 mA, PWM fix Mode
VORG_BK6
2.6
-
3.3
V
100 mV step
IQ_BK6
-
9
-
µA
Vo=3.3 V
Io=0 mA, Auto mode
Maximum Output Current
IOMAX_BK6
3000
-
-
mA
Over Current Protection
IOCP_BK6
4500
-
-
mA
Peak current of inductor(Note 1)
ΔVLDR_BK6
-1
0
+1
%
Io=1 mA to Iomax, PWM fix Mode
ηBK6_1mA
-
93
-
%
Io = 1 mA, Vo=3.3 V
ηBK6_500mA
-
95
-
%
Io = 500 mA, Vo=3.3 V
ηBK6_max
-
88
-
%
Io = Iomax, Vo=3.3 V
Oscillating Frequency
fSW_BK6
-
1.5
-
MHz
Start up Time
tST_BK6
-
240
500
µs
Discharge Resistance
RD_BK6
-
100
-
Ω
DVRFBK6_L
-
80
-
%
DVRFBK6_LHYS
-
10
-
%
DVRBK6_H
-
130
-
%
DVRFBK6_HHYS
-
20
-
%
LBK6
-
1
-
μH
COBK6
15.4
44
100
μF
Output Voltage
Programmable
Output Voltage Range
Quiescent Current
DC Output Voltage Load Regulation
Efficiency
Low Side VR Fault Detect Level
Low Side VR Fault Detect Hysteresis
High Side VR Fault Detect Level
High Side VR Fault Detect Hysteresis
Output Inductance
Output Capacitance
PWM fix mode, Io = 0 mA
During EN to 90% of nominal Voltage
Vo = 3.3 V (FB = Sweep down)
VR fault detect level / Vo x 100
(VR fault release level - detect level) / Vo x
100
Vo = 3.3 V (FB = Sweep up)
Power good detect level / Vo x 100
(VR fault detect level - release level) / Vo x
100
(Note 2)
(Note 2)
Effective capacitance with BUCK's DC bias
(Note 1) For Buck- DCDC converters, (minimum Over Current Protection Current – ½ inductor ripple current) is the maximum output current.
(Note 2) This part value range need to be guaranteed over the operating surrounding temperature.
Headroom for BUCK6
BUCK6 can’t maintain output voltage when the input voltage close to output voltage. The headroom voltage is
determined by output current and the impedance from VSYS to BUCK6 output including the inductor parasitic
impedance (DCR). The PMIC internal impedance from BUCK6_VIN to BUCK6_LX is 121 mΩ at the worst case.
Please calculate total impedance using this value, and secure enough headroom for VSYS according to the output
current and voltage.
(Example – ROHM Evaluation Board case)
Vo = 3.3V setting: VO
VSYS to BUCK6_VIN impedance of the EVB = 3 mΩ: RVIN
BUCK6_LX to inductor impedance of the EVB = 6 mΩ: RLX
Inductor parasitic impedance (DCR) = 45 mΩ: RIND
PMIC internal impedance from BUCK6_VIN to BUCK6_LX = 121 mΩ: RPMIC
Total impedance = 175 mΩ: RTOTAL=RVIN+RLX+RIND+RPMIC
Headroom = RTOTAL x Output Current
Output current
Required minimum VSYS voltage
1.0 A
3.475 V
2.0 A
3.650 V
3.0 A
3.825 V
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TSZ02201-0Q2Q0A500680-1-2
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BD71850MWV
5.2.4.3.
BUCK6 Control
Table 5-16. BUCK6_CTRL - BUCK6 Control Register
Register Name
R/W
D7
D6
D5
D4
BUCK6_CTRL
R/W
-
-
-
-
Bit
D3
BUCK6_PW
M_FIX
Name
D2
-
D1
D0
BUCK6_SEL BUCK6_EN
Initial
Address
0x00
0x0A
Function
Initial
0 – AUTO PWM/PFM mode
VR adjusts the operating mode (PFM/PWM) automatically based on the load
current to maximize power efficiency.
1 – Forced PWM Mode
VR operates in PWM mode only.
0
D[3]
BUCK6_PWM_FIX
D[1]
BUCK6_SEL
BUCK6 control select bit
0 = BUCK6 ON/OFF is controlled by state machine.
1 = BUCK6 ON/OFF is controlled by D[0] on this register.
0
BUCK6_EN
BUCK6 control bit with condition of D[1]
0 = BUCK6 OFF
1 = BUCK6 ON
This bit returns to 0 at the beginning of PWROFF sequence or emergency
shutdown.
0
D[0]
Table 5-17. BUCK6_VOLT - BUCK6 Voltage Register
Register Name
R/W
D7
BUCK6_VOLT
R/W
-
D6
BUCK6_
VOLT_SEL
Bit
Name
D[6]
BUCK6_VOLT_SEL
D[1:0]
BUCK6_VOLT[1:0]
D5
D4
D3
D2
-
-
-
-
D1
D0
BUCK6_VOLT[1:0]
Function
Select the BUCK6 voltage range set by D[6].
0 =3.0 V to 3.3 V 1 = 2.6 V to 2.9 V
Initial
Address
0x03
0x15
Initial
Note: Changing BUCK6 voltage value is not allowed when BUCK6 is still ON.
In the case where this register value is changed, BUCK6 should be turned
OFF.
BUCK6 voltage
If D[6]=0
00 = 3.0 V 01 = 3.1 V 10 = 3.2 V 11 = 3.3 V(Initial)
If D[6]=1
00 = 2.6 V 01 = 2.7 V 10 = 2.8 V 11 = 2.9 V
0
11
Note: Changing BUCK6 voltage value is not allowed when BUCK6 is still ON.
In the case where this register value is changed, BUCK6 should be turned
OFF.
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5.2.5. BUCK7
5.2.5.1.
BUCK7 Block Diagram
VSYS
INT LDO 1P5
BUCK7_VIN
OCP
V RE F
V oltage set ting
OSC
DAC
BUCK7_LX
-
Soft Start
Switch
Control
LBK 7
COB K7
+
P GND
(EX P-P AD)
EN
BUCK7_FB
Discharge
Resistor
V R Controller
EN
GND
P GND
(EX P-P AD)
V R Fault S ignal
VR Fault
Detector
Figure 5-5. BUCK7 Block Diagram
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5.2.5.2.
BUCK7 Electrical Characteristics
Table 5-18. BUCK7 Electrical Characteristics
(Unless otherwise specified, Ta=+25 °C, VSYS=5.0 V)
Parameter
Symbol
Limit
Unit
Condition
Min
Typ
Max
VO_BK7
1.782
1.800
1.818
V
VORG_BK7
1.605
-
1.995
V
IQ_BK7
-
15
-
µA
Maximum Output Current
IOMAX_BK7
1500
-
-
mA
Over Current Protection
IOCP_BK7
3000
-
-
mA
Peak current of inductor(Note 1)
ΔVLDR_BK7
-1
0
+1
%
Io = 1 mA to Iomax, PWM fix Mode
ηBK7_1mA
-
85
-
%
Io = 1 mA, Vo=1.8 V
ηBK7_500mA
-
89
-
%
Io = 500 mA, Vo=1.8 V
ηBK7_max
-
85
-
%
Io = Iomax, Vo=1.8 V
Oscillating Frequency
fSW_BK7
-
2
-
MHz
Start up Time
tST_BK7
-
220
500
µs
Discharge Resistance
RD_BK7
-
100
-
Ω
DVRFBK7_L
-
80
-
%
DVRFBK7_LHYS
-
10
-
%
DVRBK7_H
-
130
-
%
DVRFBK7_HHYS
-
20
-
%
LBK7
-
0.47
-
μH
COBK7
11
22
100
μF
Output Voltage
Programmable
Output Voltage Range
Quiescent Current
DC Output Voltage Load Regulation
Efficiency
Low Side VR Fault Detect Level
Low Side VR Fault Detect Hysteresis
High Side VR Fault Detect Level
High Side VR Fault Detect Hysteresis
Output Inductance
Output Capacitance
Vo = 1.8 V
Io = 200 mA, PWM fix Mode
1.605 V, 1.695 V, 1.755 V, 1.800 V,
1.845 V, 1.905 V, 1.950 V, 1.995 V
Vo = 1.8 V
Io = 0 mA, Auto mode
PWM fix mode, Io = 0 mA
During EN to 90 % of nominal Voltage
Vo = 1.8 V (FB = Sweep down)
VR fault detect level / Vo x 100
(VR fault release level - detect level) / Vo x
100
Vo = 1.8 V (FB = Sweep up)
Power good detect level / Vo x 100
(VR fault detect level - release level) / Vo x
100
(Note 2)
(Note 2)
Effective capacitance with BUCK's DC bias
(Note 1) For Buck- DCDC converters, (minimum Over Current Protection Current – ½ inductor ripple current) is the maximum output current.
(Note 2) This part value range need to be guaranteed over the operating surrounding temperature.
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5.2.5.3.
BUCK7 Control
Table 5-19. BUCK7_CTRL - BUCK7 Control Register
Register Name
R/W
D7
D6
D5
D4
BUCK7_CTRL
R/W
-
-
-
-
Bit
D3
BUCK7_PW
M_FIX
Name
D2
-
D1
D0
BUCK7_SEL BUCK7_EN
Initial
Address
0x00
0x0B
Function
Initial
0 – AUTO PWM/PFM mode
VR adjusts the operating mode (PFM/PWM) automatically based on the load
current to maximize power efficiency.
1 – Forced PWM Mode
VR operates in PWM mode only.
0
D[3]
BUCK7_PWM_FIX
D[1]
BUCK7_SEL
BUCK7 control select bit
0 = BUCK7 ON/OFF is controlled by state machine.
1 = BUCK7 ON/OFF is controlled by D[0] on this register.
0
BUCK7_EN
BUCK7 control bit with condition of D[1]
0 = BUCK7 OFF
1 = BUCK7 ON
This bit returns to 0 at the beginning of PWROFF sequence or emergency
shutdown.
0
D[0]
Table 5-20. BUCK7_VOLT - BUCK7 Voltage Register
Register Name
R/W
D7
D6
D5
D4
D3
BUCK7_VOLT
R/W
-
-
-
-
-
Bit
D[2:0]
Name
BUCK7_VOLT[2:0]
D2
D1
D0
BUCK7_VOLT[2:0]
Function
Initial
Address
0x03
0x16
Initial
BUCK7 voltage
000 = 1.605 V
001 = 1.695 V
010 = 1.755 V
011 = 1.800 V (Initial)
100 = 1.845 V
101 = 1.905 V
110 = 1.950 V
111 = 1.995 V
011
Note: Changing BUCK7 voltage value is not allowed when BUCK7 is still ON.
In the case where this register value is changed, BUCK7 should be turned
OFF.
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5.2.6. BUCK8
5.2.6.1.
BUCK8 Block Diagram
VSYS
INT LDO 1P5
BUCK8_VI N
OCP
V RE F
V oltage set ting
OSC
DAC
BUCK8_LX
-
Soft Start
Switch
Control
LBK 8
COB K8
+
P GND
(EX P-P AD)
EN
BUCK8_FB
Discharge
Resistor
V R Controller
EN
GND
P GND
(EX P-P AD)
V R Fault S ignal
VR Fault
Detector
Figure 5-6. BUCK8 Block Diagram
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5.2.6.2.
BUCK8 Electrical Characteristics
Table 5-21. BUCK8 Electrical Characteristics
(Unless otherwise specified, Ta=+25 °C, VSYS=5.0 V)
Parameter
Symbol
Limit
Unit
Condition
Min
Typ
Max
VO_BK8
1.089
1.100
1.111
V
Vo = 1.1 V
Io = 200 mA, PWM fix Mode
VORG_BK8
0.8
-
1.4
V
10 mV step
IQ_BK8
-
15
-
µA
Vo = 1.1 V
Io = 0 mA, Auto mode
Maximum Output Current
IOMAX_BK8
3000
-
-
mA
Over Current Protection
IOCP_BK8
4500
-
-
mA
Peak current of inductor (note 1)
ΔVLDR_BK8
-1
0
+1
%
Io = 1 mA to Iomax, PWM fix Mode
ηBK8_1mA
-
82
-
%
Io = 1 mA, Vo=1.1 V
ηBK8_500mA
-
86
-
%
Io = 500 mA, Vo=1.1 V
ηBK8_max
-
75
-
%
Io = Iomax, Vo=1.1 V
Oscillating Frequency
fSW_BK8
-
2
-
MHz
Start up Time
tST_BK8
-
200
500
µs
Discharge Resistance
RD_BK8
-
100
-
Ω
DVRFBK8_L
-
80
-
%
DVRFBK8_LHYS
-
10
-
%
DVRBK8_H
-
130
-
%
DVRFBK8_HHYS
-
20
-
%
LBK8
-
0.47
-
μH
COBK8
22
44
100
μF
Output Voltage
Programmable
Output Voltage Range
Quiescent Current
DC Output Voltage Load Regulation
Efficiency
Low Side VR Fault Detect Level
Low Side VR Fault Detect Hysteresis
High Side VR Fault Detect Level
High Side VR Fault Detect Hysteresis
Output Inductance
Output Capacitance
PWM fix mode, Io = 0 mA
During EN to 90 % of nominal Voltage
Vo = 1.1 V (FB = Sweep down)
VR fault detect level / Vo x 100
(VR fault release level - detect level) / Vo x
100
Vo = 1.1 V (FB = Sweep up)
Power good detect level / Vo x 100
(VR fault detect level - release level) / Vo x
100
(Note 2)
(Note 2)
Effective capacitance with BUCK's DC bias
(Note 1) For Buck- DCDC converters, (minimum Over Current Protection Current – ½ inductor ripple current) is the maximum output current.
(Note 2) This part value range need to be guaranteed over the operating surrounding temperature.
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5.2.6.3.
BUCK8 Control
Table 5-22. BUCK8_CTRL - BUCK8 Control Register
Register Name
R/W
D7
D6
D5
D4
BUCK8_CTRL
R/W
-
-
-
-
Bit
D3
BUCK8_PW
M_FIX
Name
D2
-
D1
D0
BUCK8_SEL BUCK8_EN
Initial
Address
0x00
0x0C
Function
Initial
0 – AUTO PWM/PFM mode
VR adjusts the operating mode (PFM/PWM) automatically based on the load
current to maximize power efficiency.
1 – Forced PWM Mode
VR operates in PWM mode only.
0
D[3]
BUCK8_PWM_FIX
D[1]
BUCK8_SEL
BUCK8 control select bit
0 = BUCK8 ON/OFF is controlled by state machine.
1 = BUCK8 ON/OFF is controlled by D[0] on this register.
0
BUCK8_EN
BUCK8 control bit with condition of D[1]
0 = BUCK8 OFF
1 = BUCK8 ON
This bit returns to 0 at the beginning of PWROFF sequence or emergency
shutdown.
0
D[0]
Table 5-23. BUCK8_VOLT - BUCK8 Voltage Register
Register Name
R/W
D7
BUCK8_VOLT
R/W
-
Bit
D[6:0]
D6
D5
D4
D3
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D1
BUCK8_VOLT[6:0]
Name
BUCK8_VOLT[6:0]
D2
Function
BUCK8 voltage
0x00 = 0.80 V
0x01 = 0.81 V
0x04 = 0.84 V
0x05 = 0.85 V
0x08 = 0.88 V
0x09 = 0.89 V
0x0C = 0.92 V
0x0D = 0.93 V
0x10 = 0.96 V
0x11 = 0.97 V
0x14 = 1.00 V
0x15 = 1.01 V
0x18 = 1.04 V
0x19 = 1.05 V
0x1C = 1.08 V
0x1D = 1.09 V
0x1E = 1.10 V (initial)
0x1F = 1.11 V
0x20 = 1.12 V
0x23 = 1.15 V
0x24 = 1.16 V
0x27 = 1.19 V
0x28 = 1.20 V
0x2B = 1.23 V
0x2C = 1.24 V
0x2F = 1.27 V
0x30 = 1.28 V
0x33 = 1.31 V
0x34 = 1.32 V
0x37 = 1.35 V
0x38 = 1.36 V
0x3B = 1.39 V
0x3C = 1.40 V
0x3D-0x7F = reserved
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D0
Initial
Address
0x1E
0x17
Initial
0x02 = 0.82 V
0x06 = 0.86 V
0x0A = 0.90 V
0x0E = 0.94 V
0x12 = 0.98 V
0x16 = 1.02 V
0x1A = 1.06 V
0x03 = 0.83 V
0x07 = 0.87 V
0x0B = 0.91 V
0x0F = 0.95 V
0x13 = 0.99 V
0x17 = 1.03 V
0x1B = 1.07 V
0x21 = 1.13 V
0x25 = 1.17 V
0x29 = 1.21 V
0x2D = 1.25 V
0x31 = 1.29 V
0x35 = 1.33 V
0x39 = 1.37 V
0x22 = 1.14 V
0x26 = 1.18 V
0x2A = 1.22 V
0x2E = 1.26 V
0x32 = 1.30 V
0x36 = 1.34 V
0x3A = 1.38 V
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TSZ02201-0Q2Q0A500680-1-2
16.Mar.2020 Rev.002
BD71850MWV
5.3. Details of LDO
5.3.1. LDO1
5.3.1.1.
LDO1 Block Diagram
OCP
VSYS
VSYS
V RE F
DAC
V oltage set ting
-
Soft Start
+
LDO1_VO UT
COLDO1
EN
Discharge
V R Controller
Resistor
EN
GND
P GND
(EX P-P AD)
V R Fault S ignal
VR Fault
Detector
Figure 5-7. LDO1 Block Diagram
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5.3.1.2.
LDO1 Electrical Characteristics
Table 5-24. LDO1 Electrical Characteristics
(Unless otherwise specified, Ta = +25 °C, VSYS = 5.0 V, VIN_3P3 = 3.3 V, VIN_1P8_1 = 1.8 V, Vo = 1.8 V setting)
Limit
Parameter
Symbol
Unit
Condition
Min
Typ
Max
VO=1.8 V setting
Output Voltage
VO_LDO1
1.782
1.800
1.818
V
Io=1 mA
Output Voltage Range 1
VORG_LDO1_1
1.600
-
1.900
V
100 mV step
Output Voltage Range 2
VORG_LDO1_2
3.000
-
3.300
V
100 mV step
Maximum Output Current
IOMAX_LDO1
10
-
-
mA
Over Current Protection
IOCP_LDO1
20
-
-
mA
IQ_LDO1
-
6
-
µA
ΔVODP_LDO1
-
40
-
mV
tST_LDO1
-
440
1000
µs
DC Output Voltage Load Regulation
ΔVLDR_LDO1
-
10
20
mV
Io=1 mA to Iomax
DC Output Voltage Line Regulation
ΔVLNR_LDO1
-
2
5
mV
VSYS = 4.5 V to 5.5 V, Io=Iomax
Discharge Resistance
RDIS_LDO1
-
100
200
Ω
VR Fault Detect Level
DVRFLDO1
-
80
-
%
DVRFLDO1_HYS
-
10
-
%
Ripple Rejection Ratio
RRLDO1
-
60
-
dB
VSYS = 5.0 V, IO=Iomax/2
VR = -20 dBV, fR=100 Hz
BW=20 Hz to 20 kHz
Output Capacitance
COLDO1
0.5
1.0
5.0
μF
(Note 1)
Effective capacitance with LDO's DC bias
Quiescent Current
Dropout Voltage
Start up Time
VR Fault Detect Hysteresis
Io=0 mA
Io = Iomax
VSYS=3.2 V, VO=3.3 V setting
Io=0 mA,
During EN to 90 % of nominal Voltage
Output = Sweep down
Power good detect level / Vo x 100
(VR fault release level - detect level) / Vo x
100
(Note 1) This part value range need to be guaranteed over the operating surrounding temperature.
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5.3.1.3.
LDO1 Control
Table 5-25. LDO1_VOLT - LDO1 Voltage Register
Register Name
LDO1_VOLT
R/W
R/W
D7
LDO1_SEL
D6
D5
D4
D3
D2
LDO1_EN
LDO1_VOL
T_SEL
-
-
-
D1
D0
Initial
Address
LDO1_VOLT[1:0]
0x22
0x18
Bit
Name
D[7]
LDO1_SEL
LDO1 control select bit
0 = LDO1 ON/OFF is controlled by state machine.
1 = LDO1 ON/OFF is controlled by D[6] on this register.
0
LDO1_EN
LDO1 control bit with condition of D[7]
0 = LDO1 OFF
1 = LDO1 ON
This bit returns to 0 at the beginning of PWROFF sequence or emergency
shutdown.
0
D[6]
D[5]
LDO1_VOLT_SEL
Function
Initial
Select the LDO1 voltage range set by D[1:0].
0 = 3.0 V to 3.3 V
1 = 1.6 V to 1.9 V
1
Note: Changing LDO1 voltage value is not allowed when LDO1 is still ON.
In the case where this register value is changed, LDO1 should be turned OFF.
D[1:0]
LDO1_VOLT[1:0]
LDO1 voltage
If D[5]=0,
00 = 3.0 V
01 = 3.1 V
10 = 3.2 V
11 = 3.3 V
If D[5]=1,
00 = 1.6 V
01 = 1.7 V
10 = 1.8 V (Initial)
11 = 1.9 V
10
Note: Changing LDO1 voltage value is not allowed when LDO1 is still ON.
In the case where this register value is changed, LDO1 should be turned OFF.
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5.3.2. LDO2
5.3.2.1.
LDO2 Block Diagram
OCP
VSYS
VSYS
V RE F
DAC
V oltage set ting
-
Soft Start
+
LDO2_VO UT
COLDO2
EN
Discharge
V R Controller
Resistor
EN
GND
P GND
(EX P-P AD)
V R Fault S ignal
VR Fault
Detector
Figure 5-8. LDO2 Block Diagram
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5.3.2.2.
LDO2 Electrical Characteristics
Table 5-26. LDO2 Electrical Characteristics
(Unless otherwise specified, Ta = +25 °C, VSYS = 5.0 V, VIN_3P3 = 3.3 V, VIN_1P8_1 = 1.8 V, Vo = 0.8 V setting)
Limit
Parameter
Symbol
Unit
Min
Typ
Max
Condition
VO_LDO2
0.785
0.800
0.815
V
VO=0.8 V setting
Io=1 mA
Output Voltage Range
VORG_LDO2
0.800
-
0.900
V
100 mV step
Maximum Output Current
IOMAX_LDO2
10
-
-
mA
Over Current Protection
IOCP_LDO2
20
-
-
mA
Quiescent Current
IQ_LDO2
-
6
-
µA
Io = 0 mA
Start up Time
tST_LDO2
-
370
1000
µs
Io = 0 mA,
During EN to 90 % of nominal Voltage
DC Output Voltage Load Regulation
ΔVLDR_LDO2
-
10
20
mV
Io = 1 mA to Iomax
DC Output Voltage Line Regulation
ΔVLNR_LDO2
-
2
5
mV
VSYS = 4.5 V to 5.5 V, Io = Iomax
Discharge Resistance
RDIS_LDO2
-
100
200
Ω
VR Fault Detect Level
DVRFLDO2
-
80
-
%
DVRFLDO2_HYS
-
10
-
%
Ripple Rejection Ratio
RRLDO2
-
60
-
dB
VSYS = 5.0 V, IO=Iomax/2
VR = -20 dBV, fR=100 Hz
BW=20 Hz to 20 kHz
Output Capacitance
COLDO2
0.5
1.0
5.0
μF
(Note 1)
Effective capacitance with LDO's DC bias
Output Voltage
VR Fault Detect Hysteresis
Output = Sweep down
Power good detect level / Vo x 100
(VR fault release level - detect level) / Vo x
100
(Note 1) This part value range need to be guaranteed over the operating surrounding temperature.
5.3.2.3.
LDO2 Control
Table 5-27. LDO2_VOLT - LDO2 Voltage Register
Register Name
LDO2_VOLT
R/W
R/W
D7
LDO2_SEL
D6
D5
D4
D3
D2
D1
D0
Initial
Address
LDO2_EN
LDO2_VOL
T_SEL
-
-
-
-
-
0x20
0x19
Bit
Name
D[7]
LDO2_SEL
LDO2 control select bit
0 = LDO2 ON/OFF is controlled by state machine.
1 = LDO2 ON/OFF is controlled by D[6] on this register.
0
LDO2_EN
LDO2 control bit with condition of D[7]
0 = LDO2 OFF
1 = LDO2 ON
This bit returns to 0 at the beginning of PWROFF sequence or emergency
shutdown.
0
D[6]
D[5]
LDO2_VOLT_SEL
Function
Initial
Select the LDO2 voltage.
0 = 0.9V
1 = 0.8V (initial)
1
Note: Changing LDO2 voltage value is not allowed when LDO2 is still ON.
In the case where this register value is changed, LDO2 should be turned OFF.
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5.3.3. LDO3
5.3.3.1.
LDO3 Block Diagram
OCP
Note : The source of LDO3 is VSYS when BUCK6 is OFF.
The source of LDO3 is VIN_3P3 when BUCK6 is ON.
The changing of the source is automatic.
VSYS
VSYS
V RE F
VIN_3P3
DAC
BUCK6
V oltage set ting
-
Soft Start
+
LDO3_VOUT
COLDO3
EN
Discharge
V R Controller
Resistor
EN
GND
P GND
(EX P-P AD)
V R Fault S ignal
VR Fault
Detector
Figure 5-9. LDO3 Block Diagram
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5.3.3.2.
LDO3 Electrical Characteristics
Table 5-28. LDO3 Electrical Characteristics
(Unless otherwise specified, Ta = +25 °C, VSYS = 5.0 V, VIN_3P3 = 3.3 V, VIN_1P8_1 = 1.8 V, Vo = 1.8 V setting)
Limit
Parameter
Symbol
Unit
Min
Typ
Max
Condition
VO_LDO3
1.782
1.800
1.818
V
VO=1.8 V setting
Io=1 mA
Output Voltage Range
VORG_LDO3
1.800
-
3.300
V
100 mV step
Maximum Output Current
IOMAX_LDO3
300
-
-
mA
Over Current Protection
IOCP_LDO3
390
-
-
mA
IQ_LDO3
-
9
-
µA
ΔVODP_LDO3
-
450
-
mV
tST_LDO3
-
310
1000
µs
DC Output Voltage Load Regulation
ΔVLDR_LDO3
-
10
20
mV
Io = 1 mA to Iomax
DC Output Voltage Line Regulation
ΔVLNR_LDO3
-
2
5
mV
VSYS = 4.5 V to 5.5 V, Io = 50 mA
Discharge Resistance
RDIS_LDO3
-
100
200
Ω
VR Fault Detect Level
DVRFLDO3
-
80
-
%
DVRFLDO3_HYS
-
10
-
%
Ripple Rejection Ratio
RRLDO3
-
60
-
dB
VSYS = 5.0 V, IO=Iomax/2
VR = -20 dBV, fR=100 Hz
BW=20 Hz to 20 kHz
Output Capacitance
COLDO3
1.1
2.2
22.0
μF
(Note 1)
Effective capacitance with LDO's DC bias
Output Voltage
Quiescent Current
Dropout Voltage
Start up Time
VR Fault Detect Hysteresis
Io = 0 mA
Io = Iomax
VIN_3P3 = 1.7 V, VO = 1.8V setting
Io = 0 mA,
During EN to 90 % of nominal Voltage
Output = Sweep down
Power good detect level / Vo x 100
(VR fault release level - detect level) / Vo x
100
(Note 1) This part value range need to be guaranteed over the operating surrounding temperature.
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5.3.3.3.
LDO3 Control
Table 5-29. LDO3_VOLT - LDO3 Voltage Register
Register Name
R/W
D7
D6
D5
D4
LDO3_VOLT
R/W
LDO3_SEL
LDO3_EN
-
-
D3
D2
D1
D0
LDO3_VOLT[3:0]
Address
0x00
0x1A
Bit
Name
D[7]
LDO3_SEL
LDO3 control select bit
0 = LDO3 ON/OFF is controlled by state machine.
1 = LDO3 ON/OFF is controlled by D[6] on this register.
0
LDO3_EN
LDO3 control bit with condition of D[7]
0 = LDO3 OFF
1 = LDO3 ON
This bit returns to 0 at the beginning of PWROFF sequence or emergency
shutdown.
0
D[6]
D[3:0]
Function
Initial
LDO3_VOLT[3:0]
Initial
LDO3 voltage
0x0 = 1.8 V (Initial)
0x1 = 1.9 V
0x2 = 2.0 V
0x3 = 2.1 V
0x4 = 2.2 V
0x5 = 2.3 V
0x6 = 2.4 V
0x7 = 2.5 V
0x8 = 2.6 V
0x9 = 2.7 V
0xA = 2.8 V
0xB = 2.9 V
0xC = 3.0 V
0xD = 3.1 V
0xE = 3.2 V
0xF = 3.3 V
0000
Note: Changing LDO3 voltage value is not allowed when LDO3 is still ON.
In the case where this register value is changed, LDO3 should be turned OFF.
It is recommended that the VIN_3P3 pin is connected to BUCK6. LDO3 power source is switched from the
VSYS pin to the VIN_3P3 pin after BUCK6 is turned on. On the other hand, LDO3 power source is switched
from the VIN_3P3 pin to the VSYS pin when BUCK6 is turned off. It takes 3 ms to complete this switching
operation. Therefore, actual BUCK6 turn-off is delayed as shown in Figure 5-10.
BUCK6_SEL
BUCK6_EN
3 ms
Low
BUCK6
0V
LDO3 Source
BUCK6
VSYS
Figure 5-10. LDO3 Voltage Source Switching
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5.3.4. LDO4
5.3.4.1.
LDO4 Block Diagram
Note : The source of LDO4 is VSYS when BUCK7 is OFF.
The source of LDO4 is VIN_1P8_1 when BUCK7 is ON.
The changing of the source is automatic.
VSYS
OCP
VSYS
BUCK7
VIN_1P8_1
V RE F
DAC
V oltage set ting
-
Soft Start
+
LDO4_VOUT
COLDO4
EN
Discharge
V R Controller
Resistor
EN
GND
P GND
(EX P-P AD)
V R Fault S ignal
VR Fault
Detector
Figure 5-11. LDO4 Block Diagram
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5.3.4.2.
LDO4 Electrical Characteristics
Table 5-30. LDO4 Electrical Characteristics
(Unless otherwise specified, Ta = +25 °C, VSYS = 5.0 V, VIN_3P3 = 3.3 V, VIN_1P8_1 = 1.8 V, Vo = 0.9 V setting)
Limit
Parameter
Symbol
Unit
Min
Typ
Max
Condition
VO_LDO4
0.885
0.900
0.915
V
VO=0.9 V setting
Io=1 mA
Output Voltage Range
VORG_LDO4
0.900
-
1.800
V
100 mV step
Maximum Output Current
IOMAX_LDO4
250
-
-
mA
Over Current Protection
IOCP_LDO4
325
-
-
mA
IQ_LDO4
-
9
-
µA
ΔVODP_LDO4
-
450
-
mV
tST_LDO4
-
400
1000
µs
DC Output Voltage Load Regulation
ΔVLDR_LDO4
-
10
20
mV
Io = 1 mA to Iomax
DC Output Voltage Line Regulation
ΔVLNR_LDO4
-
2
5
mV
VSYS = 4.5 V to 5.5 V, Io = 50 mA
Discharge Resistance
RDIS_LDO4
-
100
200
Ω
VR Fault Detect Level
DVRFLDO4
-
80
-
%
DVRFLDO4_HYS
-
10
-
%
Ripple Rejection Ratio
RRLDO4
-
60
-
dB
VSYS = 5.0 V, IO=Iomax/2
VR = -20 dBV, fR=100 Hz
BW=20 Hz to 20 kHz
Output Capacitance
COLDO4
1.1
2.2
22.0
μF
(Note 1)
Effective capacitance with LDO's DC bias
Output Voltage
Quiescent Current
Dropout Voltage
Start up Time
VR Fault Detect Hysteresis
Io = 0 mA
Io = Iomax
VIN_V1P8_1 = 1.7 V, VO = 1.8 V setting
Io = 0 mA,
During EN to 90 % of nominal Voltage
Output = Sweep down
Power good detect level / Vo x 100
(VR fault release level - detect level) / Vo x
100
(Note 1) This part value range need to be guaranteed over the operating surrounding temperature.
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5.3.4.3.
LDO4 Control
Table 5-31. LDO4_VOLT - LDO4 Voltage Register
Register Name
R/W
D7
D6
D5
D4
LDO4_VOLT
R/W
LDO4_SEL
LDO4_EN
-
-
D3
D2
D1
D0
LDO4_VOLT[3:0]
Address
0x80
0x1B
Bit
Name
D[7]
LDO4_SEL
LDO4 control select bit
0 = LDO4 ON/OFF is controlled by state machine.
1 = LDO4 ON/OFF is controlled by D[6] on this register.
1
LDO4_EN
LDO4 control bit with condition of D[7]
0 = LDO4 OFF
1 = LDO4 ON
This bit returns to 0 at the beginning of PWROFF sequence or emergency
shutdown.
0
D[6]
D[3:0]
Function
Initial
LDO4_VOLT[3:0]
Initial
LDO4 voltage
0x0 = 0.9 V (Initial)
0x1 = 1.0 V
0x2 = 1.1 V
0x3 = 1.2 V
0x4 = 1.3 V
0x5 = 1.4 V
0x6 = 1.5 V
0x7 = 1.6 V
0x8 = 1.7 V
0x9 = 1.8 V
0xA = 1.8 V
0xB = 1.8 V
0xC = 1.8 V
0xD= 1.8 V
0xE = 1.8 V
0xF = 1.8 V
0000
Note: Changing LDO4 voltage value is not allowed when LDO4 is still ON.
In the case where this register value is changed, LDO4 should be turned OFF.
It is recommended that the VIN_1P8_1 pin is connected to BUCK7. LDO4 power source is switched from
the VSYS pin to the VIN_1P8_1 pin after BUCK7 is turned on. On the other hand, LDO4 power source is
switched from the VIN_1P8_1 pin to the VSYS pin when BUCK7 is turned off. It takes 3 ms to complete this
switching operation. Therefore, actual BUCK7 turn-off is delayed as shown in Figure 5-12.
BUCK7_SEL
BUCK7_EN
3 ms
Low
BUCK7
0V
LDO4 Source
BUCK7
VSYS
Figure 5-12. LDO4 Voltage Source Switching
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5.3.5. LDO5
5.3.5.1.
LDO5 Block Diagram
OCP
VSYS
VSYS
V RE F
DAC
V oltage set ting
-
Soft Start
+
LDO5_VO UT
COLDO5
EN
Discharge
V R Controller
Resistor
EN
GND
P GND
(EX P-P AD)
V R Fault S ignal
VR Fault
Detector
Figure 5-13. LDO5 Block Diagram
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5.3.5.2.
LDO5 Electrical Characteristics
Table 5-32. LDO5 Electrical Characteristics
(Unless otherwise specified, Ta = +25 °C, VSYS = 5.0 V, VIN_3P3 = 3.3 V, VIN_1P8_1 = 1.8 V, Vo = 3.3 V setting)
Limit
Parameter
Symbol
Unit
Min
Typ
Max
Condition
VO_LDO5
3.267
3.300
3.333
V
VO=3.3 V setting
Io=1 mA
Output Voltage Range
VORG_LDO5
0.800
-
3.300
V
100 mV step
Maximum Output Current
IOMAX_LDO5
300
-
-
mA
Over Current Protection
IOCP_LDO5
340
-
-
mA
IQ_LDO5
-
9
-
µA
ΔVODP_LDO5
-
250
-
mV
tST_LDO5
-
530
1000
µs
DC Output Voltage Load Regulation
ΔVLDR_LDO5
-
10
20
mV
Io = 1 mA to Iomax
DC Output Voltage Line Regulation
ΔVLNR_LDO5
-
2
5
mV
VSYS = 4.5 V to 5.5 V, Io = 50 mA
Discharge Resistance
RDIS_LDO5
-
100
200
Ω
VR Fault Detect Level
DVRFLDO5
-
80
-
%
DVRFLDO5_HYS
-
10
-
%
Ripple Rejection Ratio
RRLDO5
-
60
-
dB
VSYS = 5.0 V, IO=Iomax/2
VR = -20 dBV, fR=100 Hz
BW=20 Hz to 20 kHz
Output Capacitance
COLDO5
1.1
2.2
22.0
μF
(Note 1)
Effective capacitance with LDO's DC bias
Output Voltage
Quiescent Current
Dropout Voltage
Start up Time
VR Fault Detect Hysteresis
Io = 0 mA
Io = Iomax
VSYS = 3.2 V, VO = 3.3 V setting
Io = 0 mA,
During EN to 90 % of nominal Voltage
Output = Sweep down
Power good detect level / Vo x 100
(VR fault release level - detect level) / Vo x
100
(Note 1) This part value range need to be guaranteed over the operating surrounding temperature.
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5.3.5.3.
LDO5 Control
Table 5-33. LDO5_VOLT - LDO5 Voltage Register
Register Name
LDO5_VOLT
R/W
R/W
D7
LDO5_SEL
D6
D5
D4
LDO5_EN
LDO5_VOL
T_SEL
-
D3
D2
D1
D0
LDO5_VOLT[3:0]
Address
0x8F
0x1C
Bit
Name
D[7]
LDO5_SEL
LDO5 control select bit
0 = LDO5 ON/OFF is controlled by state machine.
1 = LDO5 ON/OFF is controlled by D[6] on this register.
1
LDO5_EN
LDO5 control bit with condition of D[7]
0 = LDO5 OFF
1 = LDO5 ON
This bit returns to 0 at the beginning of PWROFF sequence or emergency
shutdown.
0
D[6]
D[5]
LDO5_VOLT_SEL
Function
Initial
Initial
Select the LDO5 voltage range set by D[1:0].
0 = 1.8 V to 3.3 V
1 = 0.8 V to 2.3 V
0
Note: Changing LDO5 voltage value is not allowed when LDO5 is still ON.
In the case where this register value is changed, LDO5 should be turned OFF.
D[3:0]
LDO5_VOLT[3:0]
LDO5 voltage
if D[5]=0,
0x0 = 1.8 V 0x1 = 1.9 V
0x4 = 2.2 V 0x5 = 2.3 V
0x8 = 2.6 V 0x9 = 2.7 V
0xC = 3.0 V 0xD= 3.1 V
0x2 = 2.0 V
0x6 = 2.4 V
0xA = 2.8 V
0xE = 3.2 V
0x3 = 2.1 V
0x7 = 2.5 V
0xB = 2.9 V
0xF = 3.3 V(initial)
if D[5]=1,
0x0 = 0.8 V
0x4 = 1.2 V
0x8 = 1.6 V
0xC = 2.0 V
0x2 = 1.0 V
0x6 = 1.4 V
0xA = 1.8 V
0xE = 2.2 V
0x3 = 1.1 V
0x7 = 1.5 V
0xB = 1.9 V
0xF = 2.3 V
1111
0x1 = 0.9 V
0x5 = 1.3 V
0x9 = 1.7 V
0xD= 2.1 V
Note: Changing LDO5 voltage value is not allowed when LDO5 is still ON.
In the case where this register value is changed, LDO5 should be turned OFF.
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5.3.6. LDO6
5.3.6.1.
LDO6 Block Diagram
OCP
BUCK7(1.8V)
VIN_1P8_1
V RE F
DAC
V oltage set ting
-
Soft Start
+
LDO6_VO UT
COLDO6
EN
Discharge
V R Controller
Resistor
EN
GND
P GND
(EX P-P AD)
V R Fault S ignal
VR Fault
Detector
Figure 5-14. LDO6 Block Diagram
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5.3.6.2.
LDO6 Electrical Characteristics
Table 5-34. LDO6 Electrical Characteristics
(Unless otherwise specified, Ta = +25 °C, VSYS = 5.0 V, VIN_3P3 = 3.3 V, VIN_1P8_1 = 1.8 V, Vo = 1.2 V setting)
Limit
Parameter
Symbol
Unit
Min
Typ
Max
Condition
VO_LDO6
1.185
1.200
1.215
V
VO=1.2 V setting
Io=1 mA
Output Voltage Range
VORG_LDO6
0.900
-
1.800
V
100 mV step
Maximum Output Current
IOMAX_LDO6
300
-
-
mA
Over Current Protection
IOCP_LDO6
340
-
-
mA
IQ_LDO6
-
9
-
µA
ΔVODP_LDO6
-
450
-
mV
tST_LDO6
-
400
1000
µs
DC Output Voltage Load Regulation
ΔVLDR_LDO6
-
10
20
mV
Io = 1 mA to Iomax
DC Output Voltage Line Regulation
ΔVLNR_LDO6
-
2
5
mV
VSYS = 4.5 V to 5.5 V, Io = 50 mA
Discharge Resistance
RDIS_LDO6
-
100
200
Ω
VR Fault Detect Level
DVRFLDO6
-
80
-
%
DVRFLDO6_HYS
-
10
-
%
Ripple Rejection Ratio
RRLDO6
-
60
-
dB
VSYS = 5.0 V, IO=Iomax/2
VR = -20 dBV, fR=100 Hz
BW=20 Hz to 20 kHz
Output Capacitance
COLDO6
1.1
2.2
22.0
μF
(Note 1)
Effective capacitance with LDO's DC bias
Output Voltage
Quiescent Current
Dropout Voltage
Start up Time
VR Fault Detect Hysteresis
Io = 0 mA
Io = Iomax
VIN_V1P8_1 = 1.7 V, VO = 1.8 V setting
Io = 0 mA,
During EN to 90 % of nominal Voltage
Output = Sweep down
Power good detect level / Vo x 100
(VR fault release level - detect level) / Vo x
100
(Note 1) This part value range need to be guaranteed over the operating surrounding temperature.
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5.3.6.3.
LDO6 Control
Table 5-35. LDO6_VOLT - LDO6 Voltage Register
Register Name
R/W
D7
D6
D5
D4
LDO6_VOLT
R/W
LDO6_SEL
LDO6_EN
-
-
D3
D2
D1
D0
LDO6_VOLT[3:0]
Address
0x03
0x1D
Bit
Name
D[7]
LDO6_SEL
LDO6 control select bit
0 = LDO6 ON/OFF is controlled by state machine.
1 = LDO6 ON/OFF is controlled by D[6] on this register.
0
LDO6_EN
LDO6 control bit with condition of D[7]
0 = LDO6 OFF
1 = LDO6 ON
This bit returns to 0 at the beginning of PWROFF sequence or emergency
shutdown.
0
D[6]
D[3:0]
LDO6_VOLT[3:0]
Function
Initial
Initial
LDO6 voltage
0x0 = 0.9 V
0x1 = 1.0 V
0x2 = 1.1 V
0x3 = 1.2 V (initial)
0x4 = 1.3 V
0x5 = 1.4 V
0x6 = 1.5 V
0x7 = 1.6 V
0x8 = 1.7 V
0x9 = 1.8 V
0xA = 1.8 V
0xB = 1.8 V
0xC = 1.8 V
0xD= 1.8 V
0xE = 1.8 V
0xF = 1.8 V
0011
Note: Changing LDO6 voltage value is not allowed when LDO6 is still ON.
In the case where this register value is changed, LDO6 should be turned OFF.
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5.4. MUXSW
MUX Switch is for SD card power.
5.4.1. MUXSW Block Diagram
BUCK7
VIN_1P8_2
BUCK6
DVDD
VIN_3P3
SD_VSELECT
MUX
Switch
Controller
MUXSW_VOUT
COMUX SW
MUXSW_EN
DISCHARGE
RESISTOR
P GND
(EX P-P AD)
Figure 5-15. MUXSW Block Diagram
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5.4.2. MUXSW Electrical Characteristics
Table 5-36. MUXSW Electrical Characteristics
(Unless otherwise specified, Ta = +25 °C, VSYS = 5.0 V, VIN_3P3 = 3.3 V, VIN_1P8_2 = 1.8 V, Vo = 3.3 V setting)
Parameter
Limit
Symbol
Min
Typ
Max
Unit
Condition
VIN_3P3 Input Voltage
VIN_3P3
-
3.300
-
V
Switch ON Resistance(3.3 V mode)
RON_3P3
-
-
500
mΩ
VIN_1P8_2 Input Voltage
VIN_1P8
-
1.800
-
V
Switch ON Resistance(1.8 V mode)
RON_1P8
-
-
500
mΩ
Maximum Output Current
IOMAX_MUX
150
-
-
mA
Discharge Resistance
RDIS_MUX
-
30
50
Ω
VIN_1P8_2=0 V, VIN_3P3=0 V, IO=-10 mA
CO_MUX
11
22
33
μF
(Note 1)
Effective capacitance with Output voltage
Output Capacitance
SD_VSELECT=0 V, VIN_3P3>3.2 V
SD_VSELECT=DVDD, VIN_1P8_2>1.7 V
(Note 1) This part value range need to be guaranteed over the operating surrounding temperature.
Table 5-37. SD_VSELECT Electrical Characteristics
(Unless otherwise specified, Ta=25°C, DVDD=1.8 V)
Parameter
Limit
Symbol
Input "H" Level
VIHSDV
Input "L" Level
VILSDV
Unit
Min
DVDD
x 0.75
Typ
Max
-
-
V
-
-
DVDD
x 0.25
V
t1
Condition
t2
SD_VSELECT
3.30 V
tf
tr
3.30 V
MUXSW_VOUT
3.15 V
1.89 V
1.80 V
Figure 5-16. MUXSW Sequence
Table 5-38. MUXSW Sequence Timing
Description
Min
Typ
Symbol
t1
Unit
-
ms
-
-
ms
-
1
ms
1
ms
2
-
(Note 1)
2
-
SD_VSELCT High Time
t2
Max
(Note 1)
tf
SD_VSELCT Low Time
Transition Time 3.3 V to 1.8 V
tr
Transition Time 1.8 V to 3.3 V
(Note 1) t 1 and t 2 need ov er 2ms.
Table 5-39. MUXSW_EN - MUXSW Enable Register
Register Name
R/W
D7
D6
D5
D4
D3
D2
D1
D0
Initial
Address
MUXSW_EN
R/W
-
-
-
-
-
-
-
MUXSW_EN
0x01
0x30
Bit
Name
D[0]
MUXSW_EN
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MUXSW control bit
0 = MUXSW OFF
1 = MUXSW ON
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6.
32.768 kHz Crystal Oscillator Driver
6.1. 32.768 kHz Crystal Oscillator Driver Block Diagram
INTLDO1P5
VDD_V1P5
VDD_V1P5
XOUT
32.768kHz
Crystal
CONTROLLER
XIN
Counter
Oscillator Driver
DVDD
VDD_V1P5
1/375
divider
M
U
X
C32K_OUT
OUT32K_EN
12MHz
Figure 6-1. 32.768 kHz Crystal Oscillator Driver Block Diagram
Table 6-1. C32K_OUT Control Register
Register Name
R/W
D7
D6
D5
D4
D3
D2
D1
D0
Initial
Address
OUT32K
R/W
-
-
-
-
-
-
-
OUT32K_EN
0x01
0x2E
Bit
D[0]
Name
Function
Initial
0 = Disable (C32K_OUT is Low level)
1 = Enable
OUT32K_EN
1
At the beginning of power-on, the C32K_OUT pin output clock is generated from the 12 MHz internal oscillator; the clock
frequency is equal to 12 MHz / 375.
If an external 32.768 kHz crystal is present, the C32K_OUT pin output clock’s clock source is switched from the internal
oscillator to the crystal clock after 3000 crystal clock cycles, i.e., it is assumed that the crystal clock is stable by then.
6.2. 32.768 kHz Crystal Oscillator Driver Electrical Characteristics
Table 6-2. 32.768 kHz Crystal Oscillator Driver Electrical Characteristics
(Unless otherwise specified, Ta = +25°C, VSYS = 5.0 V, DVDD = 1.8 V)
Limit
Parameter
Symbol
Min
Typ
Max
Unit
Condition
Output Frequency
fRTCLK
-
32.768
-
kHz
With external crystal
Output Duty Cycle
DRTCLK
40
50
60
%
Output H Level Voltage
VOH32K
DVDD
x 0.8
-
-
V
IOH = -1 mA
Output L Level Voltage
VOL32K
-
-
0.4
V
IOL = 1 mA
(Note) The f ollowing 32.768 kHz cry stal is recommended.
ST3215SB32768H5HPWAA (KY OCERA: C L=12.5pF)
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7.
Operational Notes
1.
Reverse Connection of Power Supply
Connecting the power supply in reverse polarity can damage the IC. Take precautions against reverse polarity when
connecting the power supply, such as mounting an external diode between the power supply and the IC’s power
supply pins.
2.
Power Supply Lines
Design the PCB layout pattern to provide low impedance supply lines. Separate the ground and supply lines of the
digital and analog blocks to prevent noise in the ground and supply lines of the digital block from affecting the analog
block. Furthermore, connect a capacitor to ground at all power supply pins. Consider the effect of temperature and
aging on the capacitance value when using electrolytic capacitors.
3.
Ground Voltage
Ensure that no pins are at a voltage below that of the ground pin at any time, even during transient condition.
4.
Ground Wiring Pattern
When using both small-signal and large-current ground traces, the two ground traces should be routed separately but
connected to a single ground at the reference point of the application board to avoid fluctuations in the small-signal
ground caused by large currents. Also ensure that the ground traces of external components do not cause variations
on the ground voltage. The ground lines must be as short and thick as possible to reduce line impedance.
5.
Recommended Operating Conditions
The function and operation of the IC are guaranteed within the range specified by the recommended operating
conditions. The characteristic values are guaranteed only under the conditions of each item specified by the electrical
characteristics.
6.
Inrush Current
When power is first supplied to the IC, it is possible that the internal logic may be unstable and inrush current may flow
instantaneously due to the internal powering sequence and delays, especially if the IC has more than one power
supply. Therefore, give special consideration to power coupling capacitance, power wiring, width of ground wiring, and
routing of connections.
7.
Testing on Application Boards
When testing the IC on an application board, connecting a capacitor directly to a low-impedance output pin may
subject the IC to stress. Always discharge capacitors completely after each process or step. The IC’s power supply
should always be turned off completely before connecting or removing it from the test setup during the inspection
process. To prevent damage from static discharge, ground the IC during assembly and use similar precautions during
transport and storage.
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7.
Operational Notes – continued
8.
Inter-pin Short and Mounting Errors
Ensure that the direction and position are correct when mounting the IC on the PCB. Incorrect mounting may result in
damaging the IC. Avoid nearby pins being shorted to each other especially to ground, power supply and output pin.
Inter-pin shorts could be due to many reasons such as metal particles, water droplets (in very humid environment) and
unintentional solder bridge deposited in between pins during assembly to name a few.
9.
Unused Input Pins
Input pins of an IC are often connected to the gate of a MOS transistor. The gate has extremely high impedance and
extremely low capacitance. If left unconnected, the electric field from the outside can easily charge it. The small
charge acquired in this way is enough to produce a significant effect on the conduction through the transistor and
cause unexpected operation of the IC. So unless otherwise specified, unused input pins should be connected to the
power supply or ground line.
10. Regarding the Input Pin of the IC
This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them
isolated. P-N junctions are formed at the intersection of the P layers with the N layers of other elements, creating a
parasitic diode or transistor. For example (refer to figure below):
When GND > Pin A and GND > Pin B, the P-N junction operates as a parasitic diode.
When GND > Pin B, the P-N junction operates as a parasitic transistor.
Parasitic diodes inevitably occur in the structure of the IC. The operation of parasitic diodes can result in mutual
interference among circuits, operational faults, or physical damage. Therefore, conditions that cause these diodes to
operate, such as applying a voltage lower than the GND voltage to an input pin (and thus to the P substrate) should be
avoided.
Resistor
Transistor (NPN)
Pin A
Pin B
C
E
Pin A
N
P+
P
N
N
P+
N
Parasitic
Elements
N
P+
N P
N
P+
B
N
C
E
Parasitic
Elements
P Substrate
P Substrate
GND
Parasitic
Elements
Pin B
B
GND
GND
Parasitic
Elements
GND
N Region
close-by
Figure 7-1. Example of Monolithic IC Structure
11. Ceramic Capacitor
When using a ceramic capacitor, determine a capacitance value considering the change of capacitance with
temperature and the decrease in nominal capacitance due to DC bias and others.
12. Thermal Shutdown Circuit(TSD)
This IC has a built-in thermal shutdown circuit that prevents heat damage to the IC. Normal operation should always
be within the IC’s maximum junction temperature rating. If however the rating is exceeded for a continued period, the
junction temperature (Tj) will rise which will activate the TSD circuit that will turn OFF power output pins. When the Tj
falls below the TSD threshold, the circuits are automatically restored to normal operation.
Note that the TSD circuit operates in a situation that exceeds the absolute maximum ratings and therefore, under no
circumstances, should the TSD circuit be used in a set design or for any purpose other than protecting the IC from
heat damage.
13. Over Current Protection Circuit (OCP)
This IC incorporates an integrated overcurrent protection circuit that is activated when the load is shorted. This
protection circuit is effective in preventing damage due to sudden and unexpected incidents. However, the IC should
not be used in applications characterized by continuous operation or transitioning of the protection circuit.
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8.
Ordering Information
B
D
7
1
8
5
0
Part Number
9.
M
W
V
-
Package
MWV: UQFN56BV7070
E2
Packaging and forming specification
E2: Embossed tape and reel
Marking Diagram
UQFN56BV7070 (TOP VIEW)
Part Number Marking
ROHM
LOT Number
BD71850
Pin 1 Mark
Figure 9-1. Marking Diagram
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10. Physical Dimension and Packing Information
Package Name
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11. Revision History
Date
Revision
Number
27.Sep.2019
001
First Release
002
p.1,18 Changed maximum operating temperature to 105 °C.
p.73,77,81,84,87,90,93,96,98,101,104,107,110
Deleted temperature condition of parts. Added note about parts
temperature.
16.Mar.2020
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Notice
Precaution on using ROHM Products
1.
Our Products are designed and manufactured for application in ordinary electronic equipment (such as AV equipment,
OA equipment, telecommunication equipment, home electronic appliances, amusement equipment, etc.). If you
intend to use our Products in devices requiring extremely high reliability (such as medical equipment (Note 1), transport
equipment, traffic equipment, aircraft/spacecraft, nuclear power controllers, fuel controllers, car equipment including car
accessories, safety devices, etc.) and whose malfunction or failure may cause loss of human life, bodily injury or
serious damage to property (“Specific Applications”), please consult with the ROHM sales representative in advance.
Unless otherwise agreed in writing by ROHM in advance, ROHM shall not be in any way responsible or liable for any
damages, expenses or losses incurred by you or third parties arising from the use of any ROHM’s Products for Specific
Applications.
(Note1) Medical Equipment Classification of the Specific Applications
JAPAN
USA
EU
CHINA
CLASSⅢ
CLASSⅡb
CLASSⅢ
CLASSⅢ
CLASSⅣ
CLASSⅢ
2.
ROHM designs and manufactures its Products subject to strict quality control system. However, semiconductor
products can fail or malfunction at a certain rate. Please be sure to implement, at your own responsibilities, adequate
safety measures including but not limited to fail-safe design against the physical injury, damage to any property, which
a failure or malfunction of our Products may cause. The following are examples of safety measures:
[a] Installation of protection circuits or other protective devices to improve system safety
[b] Installation of redundant circuits to reduce the impact of single or multiple circuit failure
3.
Our Products are designed and manufactured for use under standard conditions and not under any special or
extraordinary environments or conditions, as exemplified below. Accordingly, ROHM shall not be in any way
responsible or liable for any damages, expenses or losses arising from the use of any ROHM’s Products under any
special or extraordinary environments or conditions. If you intend to use our Products under any special or
extraordinary environments or conditions (as exemplified below), your independent verification and confirmation of
product performance, reliability, etc, prior to use, must be necessary:
[a] Use of our Products in any types of liquid, including water, oils, chemicals, and organic solvents
[b] Use of our Products outdoors or in places where the Products are exposed to direct sunlight or dust
[c] Use of our Products in places where the Products are exposed to sea wind or corrosive gases, including Cl2,
H2S, NH3, SO2, and NO2
[d] Use of our Products in places where the Products are exposed to static electricity or electromagnetic waves
[e] Use of our Products in proximity to heat-producing components, plastic cords, or other flammable items
[f] Sealing or coating our Products with resin or other coating materials
[g] Use of our Products without cleaning residue of flux (Exclude cases where no-clean type fluxes is used.
However, recommend sufficiently about the residue.) ; or Washing our Products by using water or water-soluble
cleaning agents for cleaning residue after soldering
[h] Use of the Products in places subject to dew condensation
4.
The Products are not subject to radiation-proof design.
5.
Please verify and confirm characteristics of the final or mounted products in using the Products.
6.
In particular, if a transient load (a large amount of load applied in a short period of time, such as pulse, is applied,
confirmation of performance characteristics after on-board mounting is strongly recommended. Avoid applying power
exceeding normal rated power; exceeding the power rating under steady-state loading condition may negatively affect
product performance and reliability.
7.
De-rate Power Dissipation depending on ambient temperature. When used in sealed area, confirm that it is the use in
the range that does not exceed the maximum junction temperature.
8.
Confirm that operation temperature is within the specified range described in the product specification.
9.
ROHM shall not be in any way responsible or liable for failure induced under deviant condition from what is defined in
this document.
Precaution for Mounting / Circuit board design
1.
When a highly active halogenous (chlorine, bromine, etc.) flux is used, the residue of flux may negatively affect product
performance and reliability.
2.
In principle, the reflow soldering method must be used on a surface-mount products, the flow soldering method must
be used on a through hole mount products. If the flow soldering method is preferred on a surface-mount products,
please consult with the ROHM representative in advance.
For details, please refer to ROHM Mounting specification
Notice-PGA-E
© 2015 ROHM Co., Ltd. All rights reserved.
Rev.004
Precautions Regarding Application Examples and External Circuits
1.
If change is made to the constant of an external circuit, please allow a sufficient margin considering variations of the
characteristics of the Products and external components, including transient characteristics, as well as static
characteristics.
2.
You agree that application notes, reference designs, and associated data and information contained in this document
are presented only as guidance for Products use. Therefore, in case you use such information, you are solely
responsible for it and you must exercise your own independent verification and judgment in the use of such information
contained in this document. ROHM shall not be in any way responsible or liable for any damages, expenses or losses
incurred by you or third parties arising from the use of such information.
Precaution for Electrostatic
This Product is electrostatic sensitive product, which may be damaged due to electrostatic discharge. Please take proper
caution in your manufacturing process and storage so that voltage exceeding the Products maximum rating will not be
applied to Products. Please take special care under dry condition (e.g. Grounding of human body / equipment / solder iron,
isolation from charged objects, setting of Ionizer, friction prevention and temperature / humidity control).
Precaution for Storage / Transportation
1.
Product performance and soldered connections may deteriorate if the Products are stored in the places where:
[a] the Products are exposed to sea winds or corrosive gases, including Cl 2, H2S, NH3, SO2, and NO2
[b] the temperature or humidity exceeds those recommended by ROHM
[c] the Products are exposed to direct sunshine or condensation
[d] the Products are exposed to high Electrostatic
2.
Even under ROHM recommended storage condition, solderability of products out of recommended storage time period
may be degraded. It is strongly recommended to confirm solderability before using Products of which storage time is
exceeding the recommended storage time period.
3.
Store / transport cartons in the correct direction, which is indicated on a carton with a symbol. Otherwise bent leads
may occur due to excessive stress applied when dropping of a carton.
4.
Use Products within the specified time after opening a humidity barrier bag. Baking is required before using Products of
which storage time is exceeding the recommended storage time period.
Precaution for Product Label
A two-dimensional barcode printed on ROHM Products label is for ROHM’s internal use only.
Precaution for Disposition
When disposing Products please dispose them properly using an authorized industry waste company.
Precaution for Foreign Exchange and Foreign Trade act
Since concerned goods might be fallen under listed items of export control prescribed by Foreign exchange and Foreign
trade act, please consult with ROHM in case of export.
Precaution Regarding Intellectual Property Rights
1.
All information and data including but not limited to application example contained in this document is for reference
only. ROHM does not warrant that foregoing information or data will not infringe any intellectual property rights or any
other rights of any third party regarding such information or data.
2.
ROHM shall not have any obligations where the claims, actions or demands arising from the combination of the
Products with other articles such as components, circuits, systems or external equipment (including software).
3.
No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of ROHM or any
third parties with respect to the Products or the information contained in this document. Provided, however, that ROHM
will not assert its intellectual property rights or other rights against you or your customers to the extent necessary to
manufacture or sell products containing the Products, subject to the terms and conditions herein.
Other Precaution
1.
This document may not be reprinted or reproduced, in whole or in part, without prior written consent of ROHM.
2.
The Products may not be disassembled, converted, modified, reproduced or otherwise changed without prior written
consent of ROHM.
3.
In no event shall you use in any way whatsoever the Products and the related technical information contained in the
Products or this document for any military purposes, including but not limited to, the development of mass-destruction
weapons.
4.
The proper names of companies or products described in this document are trademarks or registered trademarks of
ROHM, its affiliated companies or third parties.
Notice-PGA-E
© 2015 ROHM Co., Ltd. All rights reserved.
Rev.004
Datasheet
General Precaution
1. Before you use our Products, you are requested to carefully read this document and fully understand its contents.
ROHM shall not be in any way responsible or liable for failure, malfunction or accident arising from the use of any
ROHM’s Products against warning, caution or note contained in this document.
2. All information contained in this document is current as of the issuing date and subject to change without any prior
notice. Before purchasing or using ROHM’s Products, please confirm the latest information with a ROHM sales
representative.
3.
The information contained in this document is provided on an “as is” basis and ROHM does not warrant that all
information contained in this document is accurate and/or error-free. ROHM shall not be in any way responsible or
liable for an y damages, expenses or losses incurred b y you or third parties resulting from inaccuracy or errors of or
concerning such information.
Notice – WE
© 2015 ROHM Co., Ltd. All rights reserved.
Rev.001
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