Standard LDO Regulators
Standard Fixed Output LDO Regulators
BD80C0AFPS,BD90C0AFPS
No.10021EAT02
●Description The BD80C0AFPS, BD90C0AFPS is low-saturation regulator. This IC has a built-in over-current protection circuit that prevents the destruction of the IC due to output short circuits and a thermal shutdown circuit that protects the IC from thermal damage due to overloading. ●Features 1) Output Current: 1A 2) Output Voltage: 8.0V / 9.0V 3) High Output Voltage Precision: ±1% 4) Low saturation with PDMOS output 5) Built-in over-current protection circuit that prevents the destruction of the IC due to output short circuits 6) Built-in thermal shutdown circuit for protecting the IC from thermal damage due to overloading 7) Low ESR Capacitor 8) TO252S-3 packaging ●Applications Audiovisual equipments, FPDs, televisions, personal computers or any other consumer device ●Absolute maximum ratings (Ta=25℃) Parameter Supply Voltage Power Dissipation Storage Temperature Range Maximum Junction Temperature
*1 *2
Symbol VCC Pd Topr Tstg Tjmax
Ratings -0.3 ~ +35.0 1.2 -40 ~ +105 -55 ~ +150 +150
Unit V W ℃ ℃ ℃
Operating Temperature Range
*1 Not to exceed Pd. *2 TO252S-3:Reduced by 9.6mW / °C over Ta = 25°C, when mounted on glass epoxy board: 70mm×70mm×1.6mm. NOTE: This product is not designed for protection against radioactive rays.
●Operating conditions (Ta=25℃) ■BD80C0AFPS Parameter Supply Voltage Output Current ■BD90C0AFPS Parameter Supply Voltage Output Current Symbol Vcc Io Min. 10.0 0 Max. 25.0 1.0 Unit V A Symbol VCC Io Min. 9.0 0 Max. 25.0 1.0 Unit V A
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2010.11 - Rev.A
BD80C0AFPS,BD90C0AFPS
●Electrical characteristics ■BD80C0AFPS (Unless otherwise specified, Ta=25℃, Vcc=13V, Io=0mA) Parameter Bias Current Output Voltage Dropout Voltage Ripple Rejection Line Regulation Load Regulation Temperature Coefficient of Output Voltage
*1 ein: Input Voltage Ripple
Technical Note
Symbol Ib Vo ΔVd R.R. Reg.I Reg.L Tcvo.1 Tcvo.2
Min - 7.92 - 40 - - - -
Typ 0.6 8.00 0.3 50 20
Max 1.0 8.08 0.5 - 60
Unit mA V V dB mV V %/℃ %/℃
Conditions
Io=500mA VCC=Vo×0.95, Io=500mA
*1 f=120Hz,ein =1Vrms, Io=100mA
VCC=9→25V Io=5mA→1A Io=5mA,Tj=-40 ~ -20℃ Io=5mA,Tj=-20 ~ +105℃
Vo×0.010 Vo×0.015 +0.04 ±0.005 - -
■BD90C0AFPS (Unless otherwise specified, Ta=25℃, Vcc=14V, Io=0mA) Parameter Bias Current Output Voltage Dropout Voltage Ripple Rejection Line Regulation Load Regulation Temperature Coefficient of Output Voltage
*1 ein: Input Voltage Ripple
Symbol Ib Vo ΔVd R.R. Reg.I Reg.L Tcvo.1 Tcvo.2
Min - 8.91 - 40 - - - -
Typ 0.6 9.00 0.3 50 20
Max 1.0 9.09 0.5 - 60
Unit mA V V dB mV V %/℃ %/℃
Conditions
Io=500mA VCC=Vo×0.95, Io=500mA f=120Hz,ein*1=1Vrms, Io=100mA VCC=10→25V Io=5mA→1A Io=5mA,Tj=-40 ~ -20℃ Io=5mA,Tj=-20 ~ +105℃
Vo×0.010 Vo×0.015 +0.04 ±0.005 - -
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2010.11 - Rev.A
BD80C0AFPS,BD90C0AFPS
●Electrical characteristic curves (Reference data) BD80C0AFPS(Unless otherwise specified, Ta=25℃, Vcc=13V, Io=0mA)
1.0
Technical Note
10 9
10 9 OUTPUT VOLTAGE: Vo [V] 8 7 6 5 4 3 2 1 0
CIRCUIT CURRENT: Ib[mA]
OUTPUT VOLTAGE: Vo [V]
0.8
8 7 6 5 4 3 2 1
0.6
0.4
0.2
0.0 0246 8 10 12 14 16 18 20 22 24 SUPPLY VOLTAGE: Vcc [V]
0 0 2 4 6 8 10 12 14 16 18 20 22 24 SUPPLY VOLTAGE: Vcc [V]
0 2 4 6 8 10 12 14 16 18 20 22 24 SUPPLY VOLTAGE: Vcc [V]
Fig.1 Circuit Current
Fig.2 Line Regulation (Io=0mA)
600 DROPOUT VOLTAGE : Δ Vd [mV] 500 400 300 200 100 0
Fig.3 Line Regulation (Io=500mA)
80 RIPPLE REJECTION : R.R. [dB] 70 60 50 40 30 20 10 0
10 9 OUTPUT VOLTAGE : Vo [V] 8 7 6 5 4 3 2 1 0 0 400 800 1200 1600 2000 OUTPUT CURRENT: IO[mA]
0
200 400 600 800 OUTPUT CURRENT: IO [mA]
1000
10
100
1000 10000 100000 1000000 FREQUENCY: f [Hz]
Fig.4 Load Regulation
Fig.5 Dropout Voltage (Vcc=Vo×0.95V) (lo=0mA→1000mA)
1.0
Fig.6 Ripple Rejection (Io =100mA)
10 9 OUTPUT VOLTAGE: Vo [V]
10 9
OUTPUT VOLTAGE: Vo [V]
7 6 5 4 3 2 1 0 -40
CIRCUI T CURRENT: Ib[mA]
8
0.8
8 7 6 5 4 3 2 1
0.6
0.4
0.2
0.0
-20
0
20
40
60
80
100
0
AMBIENT TEMPERATURE: Ta[℃]
200 400 600 800 OUTPUT CURRENT: Io [mA]
1000
0 130
140 150 160 170 180 190 AMBIENT TEMPERATURE: Ta [℃]
Fig.7 Output Voltage Temperature Characteristics
Fig.8 Circuit Current (lo=0mA→1000 mA)
Fig.9 Thermal Shutdown Circuit Characteristics
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2010.11 - Rev.A
BD80C0AFPS,BD90C0AFPS
●Electrical characteristic curves (Reference data) BD90C0AFPS(Unless otherwise specified, Ta=25℃, Vcc=14V, Io=0mA)
1.0
CIRCUIT CURRENT: Ib[mA]
Technical Note
10 9
OUTPUT VOLTAGE: Vo [V] OUTPUT VOLTAGE : Vo [V]
10 9 8 7 6 5 4 3 2 1 0 0 2 4 6 8 10 12 14 16 18 20 22 24 SUPPLY VOLTAGE: Vcc [V] 0 2 4 6 8 10 12 14 16 18 20 22 24 SUPPLY VOLTAGE: Vcc [V]
0.8
8 7 6 5 4 3 2 1
0.6
0.4
0.2
0.0 0 2 4 6 8 10 12 14 16 18 20 22 24 SUPPLY VOLTAGE: Vcc [V]
0
Fig.10 Circuit Current
Fig.11 Line Regulation (Io=0mA)
600 DROPOUT VOLTAGE: ΔVd [mV] RIPPLE REJECTION: R.R. [dB] 500 400 300 200 100 0 80 70 60 50 40 30 20 10 0 0 200 400 600 800 OUTPUT CURRENT: [mA] 1000 10
Fig.12 Line Regulation (Io=500mA)
10 9
OUTPUT VOLTAGE: Vo [V]
8 7 6 5 4 3 2 1 0 0 400 800 1200 1600 2000 OUTPUT CURRENT: IO[mA]
100
1000 10000 100000 1000000 FREQUENCY: f [Hz]
Fig.13 Load Regulation
Fig.14 Dropout Voltage (Vcc=Vo×0.95V) (lo=0mA→1000mA)
1.0 CIRCUIT CURRENT: Ib[mA] 10 9
OUTPUT VOLTAGE : Vo [V]
Fig.15 Ripple Rejection (Io=100mA)
10 9 OUTPUT VOLTAGE : Vo [V] 8 7 6 5 4 3 2 1 0 -40
0.8
8 7 6 5 4 3 2 1
0.6
0.4
0.2
0.0
-20 0 20 40 60 80 100
0
AMBIENT TEMPERATURE: Ta[℃]
200 400 600 800 OUTPUT CURRENT: Io [mA]
1000
0 130
140 150 160 170 180 AMBIENT TEMPERATURE: Ta [℃]
190
Fig.16 Output Voltage Temperature Characteristics
Fig.17 Circuit Current (lo=0mA→1000 mA)
Fig.18 Thermal Shutdown Circuit Characteristics
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2010.11 - Rev.A
BD80C0AFPS,BD90C0AFPS
●BD80C0AFPS, BD90C0AFPS Measurement Circuit for Reference Data
Technical Note
A
Vcc
Vo 1µF GND
Vcc 1µF GND
Vo
Vcc 1 µF 1 µF GND
Vo 1µF V 500mA
1 µF
V
Measurement Circuit of Fig.1 and Fig.10
Measurement Circuit of Fig.2 and Fig.11
Measurement Circuit of Fig.3 and Fig.12
V Vcc 1µF GND Vo 1µF Vcc 1µF GND Vo 1µF 1Vrms ~ Vcc A 1µF GND 100mA Vo
A
1µF
Measurement Circuit of Fig.4 and Fig.13
Measurement Circuit of Fig.5 and Fig.14
Measurement Circuit of Fig.6 and Fig.15
Vcc 1µF GND
Vo
Vcc 1µF V 1µF GND
Vo
Vcc 1µF 1µF GND
Vo 1µF V
A
Measurement Circuit of Fig.7 and Fig.16
Measurement Circuit of Fig.8 and Fig.17
Measurement Circuit of Fig.9 and Fig.18
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5/12
2010.11 - Rev.A
BD80C0AFPS,BD90C0AFPS
●BD80C0AFPS, BD90C0AFPS Block diagrams
GND
FIN
VREF: Bandgap Reference OCP: Over Current Protection Circuit TSD: Thermal Shut Down Circuit Driver: Power Transistor Driver
Technical Note
VREF
Driver
OCP TSD
1
2
3
Vcc
N.C.
Vo
Fig.19
Pin No.. 1 2 3 FIN
Pin Name Vcc N.C. Vo GND N.C. Pin
Function Power Supply Pin Output Pin GND
●Package dimensions
●Input / Output Equivalent Circuit Diagrams
Vcc Pin Vo Pin
Vcc
20kΩ Vcc IC Circuit
Vo 48.3kΩ(80) 55kΩ(90) 5 kΩ
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2010.11 - Rev.A
BD80C0AFPS,BD90C0AFPS
●Thermal Design
5 Mounted on a Rohm standard board Board size : 70mm×70 mm×1.6 mm Copper foil area :7mm×7mm TO252-3θja=104.2(℃/W) Power Dissipation: Pd (W) 5
Technical Note
③ 4.80
4
Mounted on a Rohm standard board Board size : 70mm×70 mm×1.6 mm Copper foil area :7mm×7mm
①2-layer board (back surface copper foil area :15mm×15mm) ②2-layer board (back surface copper foil area :70mm×70mm) ③4-layer board (back surface copper foil area :70mm×70mm)) ①:θja=67.6℃/W ②:θja=35.7℃/W ③:θja=26.0℃/W
4 Power Dissipation: Pd (W)
② 3.50
3 3
2
2
① 1.85
1.20
1
1
0 0 25 50 75 100 125 150 Ambient Temperature: Ta(℃)
0 0 25 50 75 100 125 150 Ambient Temperature: Ta(℃)
Fig.20
Fig.21(reference data)
When using at temperatures over Ta=25℃, please refer to the heat reducing characteristics shown in Fig.20 and Fig.21. The IC characteristics are closely related to the temperature at which the IC is used, so it is necessary to operate the IC at temperatures less than the maximum junction temperature Tjmax. Fig.20 and Fig.21 shows the acceptable loss and heat reducing characteristics of the TO252S-3 package. Even when the ambient temperature Ta is a normal temperature (25℃), the chip (junction) temperature Tj may be quite high so please operate the IC at temperatures less than the acceptable loss Pd. The calculation method for power consumption Pc(W) is as follows :(Fig.21③) Pc=(Vcc-Vo)×Io+Vcc×Ib Acceptable loss Pd≧Pc Solving this for load current Io in order to operate within the acceptable loss, Io≦ Pd-Vcc×Ib Vcc-Vo (Please refer to Fig.8,Fig.17 for Ib.) It is then possible to find the maximum load current IoMax with respect to the applied voltage Vcc at the time of thermal design. Calculation Example for BD80C0AFPS) When Ta=85℃, Vcc=13V, Vo=8V Io≦ 2.496-13×Ib 5 (Ib: 0.6 mA)
Vcc: Vo: Io: Ib: Ishort:
Input voltage Output voltage Load current Circuit current Short current
Fig.21③ :θja=26.0℃/W → -38.4mW/℃ 25℃=4.80W → 85℃=2.496W
Io≦497.6mA
Please refer to the above information and keep thermal designs within the scope of acceptable loss for all operating temperature ranges. The power consumption Pc of the IC when there is a short circuit (short between Vo and GND) is : Pc=Vcc×(Ib + Ishort) (Please refer to Fig.4,Fig.13 for Ishort.)
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2010.11 - Rev.A
BD80C0AFPS,BD90C0AFPS
Technical Note
●Notes for use 1. Absolute maximum ratings Use of the IC in excess of absolute maximum ratings (such as the input voltage or operating temperature range) may result in damage to the IC. Assumptions should not be made regarding the state of the IC (e.g., short mode or open mode) when such damage is suffered. If operational values are expected to exceed the maximum ratings for the device, consider adding protective circuitry (such as fuses) to eliminate the risk of damaging the IC. 2. Electrical characteristics described in these specifications may vary, depending on temperature, supply voltage external circuits and other conditions. Therefore, be sure to check all relevant factors, including transient characteristics. 3. GND potential The potential of the GND pin must be the minimum potential in the system in all operating conditions. Ensure that no pins are at a voltage below the GND at any time, regardless of transient characteristics. 4. Ground wiring pattern When using both small-signal and large-current GND traces, the two ground traces should be routed separately but connected to a single ground potential within the application in order to avoid variations in the small-signal ground caused by large currents. Also ensure that the GND traces of external components do not cause variations on GND voltage. The power supply and ground lines must be as short and thick as possible to reduce line impedance. 5. Inter-pin shorts and mounting errors Use caution when orienting and positioning the IC for mounting on printed circuit boards. Improper mounting may result in damage to the IC. Shorts between output pins or between output pins and the power supply or GND pins (caused by poor soldering or foreign objects) may result in damage to the IC. 6. Operation in strong electromagnetic fields Using this product in strong electromagnetic fields may cause IC malfunction. Caution should be exercised in applications where strong electromagnetic fields may be present. 7. Testing on application boards When testing the IC on an application board, connecting a capacitor directly to a low-impedance pin may subject the IC to stress. Always discharge capacitors completely after each process or step. The IC’s power supply should always be turned off completely before connecting or removing it from a jig or fixture during the evaluation process. To prevent damage from static discharge, ground the IC during assembly and use similar precautions during transport and storage. 8. Thermal consideration Use a thermal design that allows for a sufficient margin in light of the Pd in actual operating conditions. Consider Pc that does not exceed Pd in actual operating conditions. (Pd≧Pc) Tjmax: Maximum junction temperature=150℃, Ta: Peripheral temperature[℃] , θja: Thermal resistance of package-ambience[℃/W], Pd: Package Power dissipation [W] Pc: Power dissipation [W], Vcc: Input Voltage, Vo: Output Voltage, Io: Load, Ib: Bias Current 9. Vcc pin Insert a capacitor(capacitor≧1µF ~ ) between the Vcc and GND pins. application. Be sure to allow a sufficient margin for input voltage levels. Electric capacitance
IC
The appropriate capacitance value varies by
Ceramic capacitors,Low ESR capacitors
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2010.11 - Rev.A
BD80C0AFPS,BD90C0AFPS
Technical Note
10. Output pins It is necessary to place capacitors between each output pin and GND to prevent oscillation on the output. Usable capacitance values range from 1µF to 1000µF. Ceramic capacitors can be used as long as their ESR value is low enough to prevent oscillation (0.001Ω to 20Ω). Abrupt fluctuations in input voltage and load conditions may affect the output voltage. Output capacitance values should be determined only through sufficient testing of the actual application.
Vcc=9V~25V(BD80C0AFPS) Vcc=10V~25V(BD90C0AFPS) Ta=-40℃~+105℃ Cin=1µF~100µF Cout=1µF~100µF Vcc=9V~25V(BD80C0AFPS) Vcc=10V~25V(BD90C0AFPS) Ta=-40℃~+105℃ Cin=1µF~100µF Cout=1µF~100µF Io=0A~1A
100
Unstable operating region
10
100
Cout_ESR(Ω)
Cin(μF)
1
Stable operating region
Stable operating region
0.1
10
0.01
1
0.001 0 200 400 600 800 1000
1
10 Cout(μF)
100
Io(mA)
Cout_ESR vs Io(reference data)
Cin vs Cout(reference data)
Cout(1µF~ )
Vcc Vcc
ESR (0.001Ω~ ) Vo
Cin (1µF~ ) GND Io(ROUT)
※Operation Notes10 Measurement circuit
11. For a steep change of the Vcc voltage Because MOS for output Transistor is used when an input voltage change is very steep, it may evoke large current. When selecting the value of external circuit constants, please make sure that the operation on the actual application takes these conditions into account. 12. For an infinitesimal fluctuations of output voltage. At the use of the application that infinitesimal fluctuations of output voltage caused by some factors (e.g. disturbance noise, input voltage fluctuations, load fluctuations, etc.), please take enough measures to avoid some influence (e.g. insert the filter, etc.). 13. Over current protection circuit (OCP) The IC incorporates an integrated over-current protection circuit that operates in accordance with the rated output capacity. This circuit serves to protect the IC from damage when the load becomes shorted. It is also designed to limit output current (without latching) in the event of a large and instantaneous current flow from a large capacitor or other component. These protection circuits are effective in preventing damage due to sudden and unexpected accidents. However, the IC should not be used in applications characterized by the continuous or transitive operation of the protection circuits. 14. Thermal shutdown circuit (TSD) The IC incorporates a built-in thermal shutdown circuit, which is designed to turn the IC off completely in the event of thermal overload. It is not designed to protect the IC from damage or guarantee its operation. ICs should not be used after this function has activated, or in applications where the operation of this circuit is assumed.
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2010.11 - Rev.A
BD80C0AFPS,BD90C0AFPS
Technical Note
15. Applications or inspection processes where the potential of the Vcc pin or other pins may be reversed from their normal state may cause damage to the IC's internal circuitry or elements. Use an output pin capacitance of 1000µF or lower in case Vcc is shorted with the GND pin while the external capacitor is charged. Insert a diode in series with Vcc to prevent reverse current flow, or insert bypass diodes between Vcc and each pin. 16. Positive voltage surges on VCC pin A power zener diode should be inserted between VCC and GND for protection against voltage surges of more than 35V on the VCC pin.
Vcc
GND
17. Negative voltage surges on VCC pin A schottky barrier diode should be inserted between VCC and GND for protection against voltages lower than GND on the VCC pin.
Vcc
GND
18. Output protection diode Loads with large inductance components may cause reverse current flow during startup or shutdown. protection diode should be inserted on the output to protect the IC.
In such cases, a
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2010.11 - Rev.A
BD80C0AFPS,BD90C0AFPS
Technical Note
19. Regarding input pins of the IC This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them isolated. PN junctions are formed at the intersection of these P layers with the N layers of other elements, creating parasitic diodes and/or transistors. For example (refer to the figure below): ○When GND > Pin A and GND > Pin B, the PN junction operates as a parasitic diode ○When GND > Pin B, the PN junction operates as a parasitic transistor Parasitic diodes occur inevitably in the structure of the IC, and the operation of these parasitic diodes can result in mutual interference among circuits, operational faults, or physical damage. Accordingly, conditions that cause these diodes to operate, such as applying a voltage lower than the GND voltage to an input pin (and thus to the P substrate) should be avoided.
Resistor (Pin A) (Pin B) C Transistor (NPN) B E B N P+ N Parasitic elements GND Parasitic elements or transistors N N P substrate GND (Pin B) C E P P+ N GND Parasitic elements or transistors (Pin A) Parasitic elements
P+ N P N
P
P+
Example of Simple Monolithic IC Architecture
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2010.11 - Rev.A
BD80C0AFPS,BD90C0AFPS
●Ordering part number
Technical Note
B
D
8
0
C
0
A
F
P
S
-
E
2
ROHM model Name
Output Voltage 80:8V Output 90:9V Output
Current capacity C0A:1A
Package
FPS:TO252S-3
Packaging specification E2: Embossed tape and reel
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2010.11 - Rev.A
Notice
Notes
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R1010A