Datasheet
Power Supply IC Series for TFT-LCD Panels
Gamma voltage generated IC
with built-in DAC
BD81010MUV
General Description
Key Specifications
The feature of gamma voltage generated IC
BD81010MUV provides a single-chip solution with a
high-precision 10-bit DAC setting controlled by I2C serial
communications interface, a buffer amp (14ch), and a
operational amplifier for HVDD (1ch).
Power Supply Voltage Range(VDD):
2.1V to 3.6V
Power Supply Voltage Range(VCC): 8.0V to 18.0V
Operating Temperature Range:
-40°C to +85°C
Package
W(Typ) x D(Typ) x H(Max)
Features
Single-chip Design means Fewer Components
Built in 10bit DAC (14ch)
Built in DAC Output Buffer Amplifier (14ch)
Built in Operation Amplifier (1ch) for HVDD
I2C Interface ( SDA, SCL )
Thermal Shutdown Circuit
Under-voltage Lockout Protection Circuit
Power ON Reset Circuit
Input Tolerant ( SDA, SCL, EN )
VQFN032V5050
5.00mm x 5.00mm x 1.00mm
Applications
It may be used with TFT-LCD panels, such as big screen
and high resolution LCD televisions.
○Product structure：Silicon monolithic integrated circuit
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○This product has no designed protection against radioactive rays
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BD81010MUV
Block Diagram
VCC
DACGND
24
23
REFIN
VDAC
22
21
FB
20
VDD
DACGND
VCC
19
18
17
VCC
VDD
16 GND
GND 25
REFIN
VCC
OUT13 26
×3
×3
×3
OUT10 29
×3
OUT9 30
×3
×3
OUT7 32
×3
×3
REFIN
Serial
I/F
DAC
×3
REFIN
×3
REFIN
11 OUT4
VCC
DAC
×3
REFIN
DAC
12 OUT3
VCC
DAC
DAC
13 OUT2
VCC
DAC
DAC
14 OUT1
VCC
DAC
REFIN
VCC
×3
REFIN
DAC
15 OUT0
VCC
DAC
REFIN
VCC
OUT8 31
DAC
REFIN
VCC
×3
REFIN
REFIN
VCC
VCC
DAC
REFIN
VCC
OUT11 28
DAC
REFIN
VCC
OUT12 27
REFIN
10 OUT5
VCC
DAC
×3
9
OUT6
VDD
UVLO
VREF
(VCC, REFIN, VDD)
TSD
VCC
Power ON
Reset
OP-AMP
1
2
3
4
5
6
7
EN
DGND
VDD
SDA
SCL
INP
INN
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HVDD
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BD81010MUV
Pin Configuration
TOP VIEW
24 23 22 21 20 19 18 17
25
16
26
15
27
14
28
13
29
12
30
11
31
10
32
9
1
2
3
4
5
6
7
8
Pin Description
PIN
No.
Pin name
1
EN
PIN
No.
Pin name
VDAC enable pin
17
VCC
Power supply input
Logic , Protection circuit GND input
GND input for DAC
Function
Function
2
DGND
18
DACGND
3
VDD
Logic power supply input
19
VDD
4
SDA
Serial data input pin
20
FB
5
SCL
Serial clock input pin
21
REFIN
DAC reference voltage input pin
6
INP
Amplifier + input pin
22
VDAC
DAC voltage output
7
INN
Amplifier – input pin
23
DACGND
GND input for DAC
8
HVDD
HVDD amplifier output pin
24
VCC
Power supply input
Buffer amplifier GND input
Logic power supply input
Feedback pin
9
OUT6
Gamma output pin
25
GND
10
OUT5
Gamma output pin
26
OUT13
Gamma output pin
11
OUT4
Gamma output pin
27
OUT12
Gamma output pin
12
OUT3
Gamma output pin
28
OUT11
Gamma output pin
13
OUT2
Gamma output pin
29
OUT10
Gamma output pin
14
OUT1
Gamma output pin
30
OUT9
Gamma output pin
15
OUT0
Gamma output pin
31
OUT8
Gamma output pin
16
GND
Buffer amplifier GND input
32
OUT7
Gamma output pin
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BD81010MUV
Absolute Maximum Ratings (Ta=25°C)
Parameter
Symbol
Rating
Unit
Power Supply Voltage 1
VDD
4.5
V
Power Supply Voltage 2
VCC
19.0
V
REFIN Voltage
VREFIN
7.0
V
DAC Reference Voltage
VDAC
7.0
V
VINP, VINN
15.0
V
VEN
4.5
V
VSDA, VSCL
4.5
V
Tjmax
150
°C
Pd
4.56 (Note 1)
W
Operating Temperature Range
Topr
-40 to +85
°C
Storage Temperature Range
Tstg
-55 to +150
°C
OP. Amplifier Input Pin Voltage
Functional Pin Voltage
2 Lines Serial Terminal Voltage
Junction Temperature
Power Dissipation
(Note 1) To use the IC at temperatures over Ta25°C, derate power rating by 27.4mW/°C.
When mounted on a four-layer glass epoxy board measuring 74.2mm x 74.2mm x 1.6mm.
Caution: Operating the IC over the absolute maximum ratings may damage the IC. The damage can either be a short circuit between pins or an open circuit
between pins and the internal circuitry. Therefore, it is important to consider circuit protection measures, such as adding a fuse, in case the IC is operated over
the absolute maximum ratings.
Recommended Operating Conditions (Ta-40°C to +85°C)
Parameter
Symbol
Min
Max
Unit
Power Supply Voltage 1
VDD
2.1
3.6
V
Power Supply Voltage 2
VCC
8.0
18.0
V
REFIN Voltage
VREFIN
2.1
5.5
V
DAC Reference Voltage
VDAC
2.1
5.5
V
VINP, VINN
(< VCCH - 2.5[V] )
0.0
14.0
V
VEN
-0.1
+3.6
V
VSDA, VSCL
-0.1
+3.6
V
fCLK
-
400
kHz
CVDAC
1.0
-
µF
OP. Amplifier Input Pin Voltage
Function Terminal Voltage
2 Lines Serial Terminal Voltage
2 Lines Serial Frequency
VDAC Output Capacity
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BD81010MUV
Electrical Characteristics (Unless otherwise noted, Ta25°C, VDD=3.3V, VCC=15.0V, VREFIN=5.0V )
MIN
Limit
TYP
MAX
VFB
IFB
IO
0.492
-1.2
10
0.500
0.0
50
0.508
1.2
-
V
µA
mA
VFB=0.60V
IooA
-
-10.0
-6.6
mA
during REG0=3BBh (14.0V ) setting,
OUT0=15V input
IooB
-
-30
-20
mA
IooC
-
-60
-40
mA
IoiA
40
60
-
mA
IoiB
20
30
-
mA
IoiC
6.6
10.0
-
mA
Load Stability (OUT0)
⊿VO-A
-
10
70
mV
Load Stability
(OUT1 to OUT12)
⊿VO-B
-
10
70
mV
Load Stability (OUT13)
⊿VO-C
-
10
70
mV
MAX Output Voltage (OUT0)
MAX Output Voltage
(OUT1 to OUT12)
MAX Output Voltage (OUT13)
MIN Output Voltage (OUT0)
MIN Output Voltage
(OUT1 to OUT12)
MIN Output Voltage (OUT13)
Slew Rate (AMP0)
Slew Rate (AMP1 to OUT12)
Slew Rate (AMP13)
【 10 Bit DAC 】
Resolution
Integral Non-linearity Error
(INL)
Differential Non-linearity Error
(DNL)
VOH-A
VCC-0.20
VCC-0.10
-
V
during REG13=043h (1.0V) setting,
OUT13=0V input
IO=0mA to -30mA
REG0=199h (6.0V) setting
IO=-15mA to 15mA
REG1 to REG12=199h (6.0V) setting
IO=0mA to 30mA
REG13=199h (6.0V) setting
IO=-30mA
VOH-B
VCC-1.00
VCC-0.50
-
V
IO=-15mA
VOH-C
VOL-A
VCC-0.60
-
VCC-0.30
0.30
0.60
V
V
IO=-5mA
IO=5mA
VOL-B
-
0.60
1.20
V
IO=15mA
VOL-C
SR-A
SR-B
SR-C
1
1
1
0.10
4
4
4
0.20
-
V
V/µsec
V/µsec
V/µsec
RES
-
10
-
Bit
LE
-2
-
+2
LSB
DLE
-2
-
+2
LSB
Parameter
【 Regulator (VDAC) 】
FB Voltage
Input Bias Current
Current Capability
【 Gamma Amplifier 】
Sink Current Capability
Nch Side (AMP0)
Sink Current Capability
Nch Side (AMP1 to AMP12)
Sink Current Capability
Nch Side (AMP13)
Source Current Capability
Pch Side (AMP0)
Source Current Capability
Pch Side (AMP1 to AMP12)
Source Current Capability
Pch Side (AMP13)
Symbol
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Unit
Condition
during REG1 to REG12=199h (6.0V) setting,
OUT1to OUT12=7V input
during REG13=043h (1.0V) setting,
OUT13=2V input
during REG0=3BBh (14.0V) setting,
OUT0=13V input
during REG1 to REG12=199h (6.0V) setting,
OUT1to OUT12=5V
IO=30mA
OUT0=No-load
OUT1 to OUT12= No-load
OUT13= No-load
00Ah to 3F5h is the allowable margin of
error against the ideal linear.
00Ah to 3F5h is the allowable margin of error
against the ideal increase of 1LSB.
TSZ02201-0313AAF00360-1-2
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BD81010MUV
Electrical Characteristics – continued (Unless otherwise noted, Ta25°C, VDD=3.3V, VCC=15.0V, VREFIN=5.0V )
MIN
Limit
TYP
MAX
0.8
0.6
10.0
16.5
1.7
1.7
23.1
V
V
µA
VDD=2.5V
VEN=3.3V
0.8
0.6
-
-
1.7
1.7
0.4
V
V
V
VDD=2.5V
ISDA=3mA
-15
-1.2
0.0
+15
+1.2
mV
µA
-
-100
-66
mA
66
100
-
mA
⊿VO-HV
-
10
70
mV
VOH-HV
VOL-HV
SRHV
VCC-0.20
1
VCC-0.10
0.10
4
0.20
-
V
V
V/µsec
VDDUV
1.7
1.9
2.1
V
VDDHY
-
100
-
mV
VCCUV
2.3
2.6
2.9
V
VCCHY
-
400
-
mV
VREFUV
1.7
1.9
2.1
V
VREFHY
-
100
-
mV
VDD Circuit Current
ICCL
0.31
0.51
0.71
mA
VCC Circuit Current
ICCH
4.4
8.6
13.2
mA
Parameter
Symbol
【 Control Signal 1 (EN) 】
Threshold Voltage 1
VENth1
Threshold Voltage 2
VENth2
Input Sinking Current
IEN
【 Control Signal 2 (SDA, SCL) 】
Threshold Voltage 1
Vth1
Threshold Voltage 2
Vth2
MIN Output Voltage
VOCL
【 Operation Amplifier 】
Input Offset Voltage
VOFF-HV
Input Bias Current
IB-HV
Sink Current Capability
IooHV
(Nch side)
Source Current Capability
IoiHV
(Pch side)
Load Stability
MAX Output Voltage
MIN Output Voltage
Slew Rate
【 Whole Device 】
VDD under-voltage Protection
Voltage
VDD under-voltage Protection
Hysteresis Voltage
VCC under-voltage Protection
Voltage
VCC under-voltage Protection
Hysteresis Voltage
REFIN under-voltage
Protection Voltage
REFIN under-voltage
Protection Hysteresis Voltage
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Unit
Condition
during VINP = 7V, INN = HVDD setting,
VHVDD=8V input
during VINP = 7V, INN = HVDD setting,
VHVDD=6V input
VINP = 7V, INN = HVDD setting
IO=-50mA to +50mA
IO=-30mA
IO=30mA
HVDD=No-load
VDD falling voltage
VCC falling voltage
REFIN falling voltage
No-load output,
DAC initial value setting
No-load output,
DAC initial value setting
TSZ02201-0313AAF00360-1-2
19.Feb.2016 Rev.001
BD81010MUV
Operation of each block
(1) Regulator (VDAC)
This is a regulator block for setting a reference voltage of DAC.
VDAC has enable function so that if EN=Low, shut down is performed, or EN=High, settable VDAC voltage by FB voltage
and external resistor. At this time, VDAC voltage < 5.5[V] (MAX operating voltage) should be configured.
VDAC output capacity (C11) is set over 1[µF].
Phase compensation (C12) is able to use as OPEN, but it is recommended to set the PCB pattern.
EN
VCC
VDD
VREF
VDAC
REFIN
C11
R11
C12
FB
R12
Figure 1. Regulator block
VDAC 0.50
R11 R12
[V ]
R12
Example) In case R11=18[kΩ], R12=2 [kΩ], VDAC equals to 5.0[V].
10[kΩ] to 100[kΩ] is a recommended range for the sum of setting value of R11,R12. If the setting is below 10[kΩ],
consumption current may increase, thus resulting in degraded power efficiency. If the setting exceeds 100[kΩ], offset
voltage is likely increase due to the input bias current.
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BD81010MUV
(2) 10 Bit DAC Block
・Serial data control block
The serial interface uses a 2-line serial data format (SCL, SDA).
The serial data control block consists of a register that stores data from the SDA and SCL pins, and a DAC circuit that
receives the output from this register and provides adjusted voltages to other IC blocks.
SDA
Acknowledge
SCL
Shift Register
Register 0
DAC
Register 1
DAC
Register 2
DAC
Register 3
DAC
Register 4
DAC
Register 5
DAC
Register 6
DAC
Register 7
DAC
Register 8
DAC
Register 9
DAC
Register 10
DAC
Register 11
DAC
Register 12
DAC
Register 13
DAC
×3
OUT0
×3
×3
OUT1
OUT2
×3
×3
OUT3
OUT4
×3
×3
OUT5
OUT6
×3
×3
OUT7
OUT8
×3
×3
OUT9
OUT10
×3
×3
OUT11
OUT12
×3
OUT13
Figure 2. Serial Block Diagram
・Register ( Ch0 to Ch13 )
A serial signal (consisting of 10-bit gamma correction voltage values) input using the serial interface or I 2C bus interface
is held for each register address.
Data is initialized by the reset signal generated during a power-on reset.
・DAC
The DAC LOGIC converts the 10-bit digital signal read to the register to a voltage.
・Amp ( Ch0 to Ch13 )
The Amp amplifies the voltage output from the DAC LOGIC by 3 times.
While Under Voltage Lock-Out (UVLO) circuit or Thermal Shut Down (TSD) circuit is operating, output goes into Hi-z.
In case connecting high capacity capacitor with low ESR, damping is needed with a resistor to keep phase margin.
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BD81010MUV
・Output Voltage setting mode
Writes to a register address specified by I2C BUS.
Mode for writing from I2C BUS to register are ( i )Single mode and ( ii )Multi mode.
On single mode, write data to one designated register.
On multi mode, multi data write can be performed continuously from a start address register specified with the second
byte of data.
Single mode or multi mode can be configured by having or not having “stop bit”.
(i)
Single mode timing chart
Write single DAC register. R3-R0 specify DAC address.
start
Device Address
Write Ackn Start DAC address pointer. R6-R4 have no meaning Ackn
DAC(pointer) MSbyte. D15-D10 have no meaning
Ackn
DAC(pointer) LSbyte.
Ackn
Stop
SCL
SDA_in
Device_Out
A6
A5
A4
A3
A2
A1
A0
R/W Ackn
WS
R6
R5
R4
R3
R2
R1
R0
Ackn D15
D14
D13
D12
D11
D10
D9
D8
Ackn
D7
D6
D5
D4
D3
D2
D1
D0
Ackn
A6
A5
A4
A3
A2
A1
A0
R/W Ackn
WS
R6
R5
R4
R3
R2
R1
R0
Ackn D15
D14
D13
D12
D11
D10
D9
D8
Ackn
D7
D6
D5
D4
D3
D2
D1
D0
Ackn
Device Address ECh
The whole DAC Register D9-D0 is
update in this moment.
Figure 3. Output Voltage Setting (Single mode)
(ii)
Multi mode timing chart
Write multiple DAC registers. R3-R0 specify start DAC
address
start
Device Address
Write Ackn Start DAC address pointer. R6-R4 have no meaning Ackn
DAC(pointer) MSbyte. D15-D10 have no meaning
Ackn
DAC(pointer) LSbyte.
Ackn
SCL
・・・
SDA_in
Device_Out
A6
A5
A4
A3
A2
A1
A0
R/W Ackn
WS
R6
R5
R4
R3
R2
R1
R0
Ackn D15
D14
D13
D12
D11
D10
D9
D8
Ackn
D7
D6
D5
D4
D3
D2
D1
D0
Ackn
・・・
A6
A5
A4
A3
A2
A1
A0
R/W Ackn
WS
R6
R5
R4
R3
R2
R1
R0
Ackn D15
D14
D13
D12
D11
D10
D9
D8
Ackn
D7
D6
D5
D4
D3
D2
D1
D0
Ackn
・・・
The whole DAC Register D9-D0 is
update in this moment.
Device Address ECh
DAC(3) MSbyte. D15-D10 have no meaning
Ackn
DAC(3) LSbyte.
Ackn
Stop
・・・
・・・
D15
D14
D13
D12
D11
D10
D9
D8
Ackn
D7
D6
D5
D4
D3
D2
D1
D0
Ackn
・・・
D15
D14
D13
D12
D11
D10
D9
D8
Ackn
D7
D6
D5
D4
D3
D2
D1
D0
Ackn
The whole DAC Register D9-D0 is
update in this moment.
Figure 4. Output Voltage Setting (Multi mode)
・Device address
Device addresses A6 to A0 are specific to the IC and should be set as follows: (A6 to A0) = 1110110.
The lower 4 bits (R3 to R0) of the second byte are used to store the register address.
R6 to R4 should be set to 0 as usual.
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BD81010MUV
・Command interface
Use I2C BUS for command interface with host. Writing or reading by specifying 1 byte select address, along with slave
address. I2C BUS Slave mode format is shown below.
MSB
LSB
Slave Address
S
S
Slave Address
:
:
A
:
Select Address
DATA
P
:
:
:
A
MSB
LSB
Select Address
MSB
A
LSB
DATA
A
P
Start condition
After slave mode(7bit), with read mode (H) or light mode (L), send 8 bit data in all.
(MSB first)）
Acknowledge
Added acknowledge bit per byte in sending and receiving data.
If the data is sent/ received properly, “L” is send/ received.
Sending/ Receiving ”H” means lack of acknowledge.
Use 1 byte select address.
Data byte. Sending/ Receiving data. （MSB first）.
Stop condition
The case where writing 3FCh to DAC1（Single mode）
S
Slave Address
A
Select Address
(Ex.)
ECh
01h
A
Register1 DATA0
03h
A
: Slave from master
Register1 DATA1
FCh
A
P
: Master from slave
The case where writing 3FCh from DAC0 to DAC3 (Multi mode)
S
Slave Address
(Ex.)
A
Select Address
ECh
A
00h
Register0
DATA0
A
03h
Register0
DATA1
A
FCh
Register1
DATA0
Register1 to 3
DATA0,DATA1
A
A
03h
: Slave from master
: Master from slave
・DAC register address diagram
R3
Register Address
R2
R1
R0
Register name
0
0
0
0
Register 0
0
0
0
1
Register 1
0
0
1
0
Register 2
0
0
1
1
Register 3
0
1
0
0
Register 4
0
1
0
1
Register 5
0
1
1
0
Register 6
0
1
1
1
Register 7
1
0
0
0
Register 8
1
0
0
1
Register 9
1
0
1
0
Register 10
1
0
1
1
Register 11
1
1
0
0
Register 12
1
1
0
1
Register 13
DATA0
DATA1
DATA0
DATA1
DATA0
DATA1
DATA0
DATA1
DATA0
DATA1
DATA0
DATA1
DATA0
DATA1
DATA0
DATA1
DATA0
DATA1
DATA0
DATA1
DATA0
DATA1
DATA0
DATA1
DATA0
DATA1
DATA0
DATA1
BIT
7
X
D7
X
D7
X
D7
X
D7
X
D7
X
D7
X
D7
X
D7
X
D7
X
D7
X
D7
X
D7
X
D7
X
D7
DATA0：Upper 8 bits, DATA1：Lower 8 bit,
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TSZ22111・15・001
6
X
D6
X
D6
X
D6
X
D6
X
D6
X
D6
X
D6
X
D6
X
D6
X
D6
X
D6
X
D6
X
D6
X
D6
5
X
D5
X
D5
X
D5
X
D5
X
D5
X
D5
X
D5
X
D5
X
D5
X
D5
X
D5
X
D5
X
D5
X
D5
4
X
D4
X
D4
X
D4
X
D4
X
D4
X
D4
X
D4
X
D4
X
D4
X
D4
X
D4
X
D4
X
D4
X
D4
3
X
D3
X
D3
X
D3
X
D3
X
D3
X
D3
X
D3
X
D3
X
D3
X
D3
X
D3
X
D3
X
D3
X
D3
2
X
D2
X
D2
X
D2
X
D2
X
D2
X
D2
X
D2
X
D2
X
D2
X
D2
X
D2
X
D2
X
D2
X
D2
1
D9
D1
D9
D1
D9
D1
D9
D1
D9
D1
D9
D1
D9
D1
D9
D1
D9
D1
D9
D1
D9
D1
D9
D1
D9
D1
D9
D1
0
D8
D0
D8
D0
D8
D0
D8
D0
D8
D0
D8
D0
D8
D0
D8
D0
D8
D0
D8
D0
D8
D0
D8
D0
D8
D0
D8
D0
Initial
Output
value
pin
03BBh
OUT0
0376h
OUT1
0332h
OUT2
02EEh
OUT3
02AAh
OUT4
0265h
OUT5
0221h
OUT6
01DDh
OUT7
0199h
OUT8
0154h
OUT9
0110h
OUT10
00CCh
OUT11
0088h
OUT12
0043h
OUT13
X：don’t care, D9 to D0：Data bit
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TSZ02201-0313AAF00360-1-2
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P
BD81010MUV
・I2C Timing
tHIGH
tR
tF
SCL
tLOW
tSU;DAT
tHD:STA
tPD
tHD;DAT
SDA
(IN)
tBUF
tDH
SDA
(OUT)
SCL
tSU;STA
tHD;STA
tSU;STO
SDA
tl
S
P
S：START bit
P：STOP bit
Figure 5. Timing
・Timing regulation
Parameter
SCL Frequency
SCL”H” time
SCL”L” time
Rise time
Fall time
Start condition holding time
Start condition setup time
SDA Holding time
SDA Setup time
Acknowledge delay time
Acknowledge holding time
Stop condition setup time
BUS open time
Noise spike width
Symbol
fSCL
tHIGH
tLOW
tR
tF
tHD;STA
tSU;STA
tHD;DAT
tSU;DAT
tPD
tDH
tSU;STO
tBUF
tl
MIN
FAST mode
TYP
MAX
0.6
1.2
0.6
0.6
100
100
0.6
1.2
-
0.1
0.1
400
0.3
0.3
0.9
-
Unit
kHz
µs
µs
µs
µs
µs
µs
ns
ns
µs
µs
µs
µs
µs
・Buffer output setting
The relation between buffer output voltage (OUT0 to OUT13) and DAC setting value is shown below.
Output voltage (OUT 0 to OUT13)
DAC setting value 1
3 REFIN
1024
Buffer output terminals OUT0 to OUT13 output after UVLO release of VCC. While UVLO detection, the output is HiZ.
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(3) Operation amplifier for HVDD
If output current ability over ±20mA is needed for DAC output, shown below.
Only using an amplifier, voltage is able to set by resistor, shown below Figure 7.
・ For the reference side, use the regulator output type of power supply.
・ It is recommended to set the RCOM1,RCOM2 in the range of 10kΩ to 100kΩ.
Setting them to not more than 10kΩ may increase current consumption, thus resulting in degraded power efficiency.
Setting them to not less than 100kΩ may result in higher offset voltage due to the input bias current of 0.1µA(TYP).
・ In case connecting HVDD with low ESR capacitor, damping is needed with a resistor (R32) to keep phase margin.
Use the buffer type if HVDD is not used, and ground the INP pin.
Reference voltage
OUT5
RCOM1
INP
INP
INN
INN
RCOM2
R31
HVDD
HVDD
(For thermal shut down)
R32
C31
C32
Figure 6. Use as output for DAC
Figure 7. Use amplifier only by having resistor divider
(4) Power On Reset
When the digital power supply VDD is activated, each IC generates a reset digital to initialize the serial I/F and each
registers.
(5) UVLO(Under Voltage Lock Out)
Turns output OFF when the voltage of digital power supply VDD, amplifier power supply VCC and DAC reference voltage
REFIN goes below the limit value.
(6) TSD(Thermal Shut Down)
The TSD circuit turns output off when the chip temperature reaches or exceeds approximately 175°C in order to prevent
thermal destruction or thermal runaway. When the chip returns to a specified temperature, the circuit resets.
The TSD circuit is designed only to protect the IC itself. Application thermal design should ensure operation of the IC
below the junction temperature of approximately 150°C.
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BD81010MUV
Sequence image
1. EN=High before VCC power supply turns ON
VCC(15.6V)
VDAC = REFIN
VDD(3.3V)
EN
DAC Control
If EN becomes High simultaneously with
VDD, similar sequence comes out.
(DAC output）OUT0
OUT0～13
to OUT13
VCC(15.6V)
HVDD
(In case using INP as VCC resistor divider）
Figure 8. Sequence image 1
2. EN=High after VCC power supply turns ON
VCC(15.6V)
VDAC = REFIN
VDD(3.3V)
EN
DAC Control
(DAC output）OUT0
OUT0～13
to OUT13
VCC(15.6V)
HVDD
(In case using INP as VCC resistor divider）
Figure 9. Sequence image 2
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BD81010MUV
Operational Notes
1.
Reverse Connection of Power Supply
Connecting the power supply in reverse polarity can damage the IC. Take precautions against reverse polarity when
connecting the power supply, such as mounting an external diode between the power supply and the IC’s power
supply pins.
2.
Power Supply Lines
Design the PCB layout pattern to provide low impedance supply lines. Separate the ground and supply lines of the
digital and analog blocks to prevent noise in the ground and supply lines of the digital block from affecting the analog
block. Furthermore, connect a capacitor to ground at all power supply pins. Consider the effect of temperature and
aging on the capacitance value when using electrolytic capacitors.
3.
Ground Voltage
Ensure that no pins are at a voltage below that of the ground pin at any time, even during transient condition.
4.
Ground Wiring Pattern
When using both small-signal and large-current ground traces, the two ground traces should be routed separately but
connected to a single ground at the reference point of the application board to avoid fluctuations in the small-signal
ground caused by large currents. Also ensure that the ground traces of external components do not cause variations
on the ground voltage. The ground lines must be as short and thick as possible to reduce line impedance.
5.
Thermal Consideration
Should by any chance the maximum junction temperature rating be exceeded the rise in temperature of the chip may
result in deterioration of the properties of the chip. In case of exceeding this absolute maximum rating, increase the
board size and copper area to prevent exceeding the maximum junction temperature rating.
6.
Recommended Operating Conditions
These conditions represent a range within which the expected characteristics of the IC can be approximately
obtained. The electrical characteristics are guaranteed under the conditions of each parameter.
7.
Inrush Current
When power is first supplied to the IC, it is possible that the internal logic may be unstable and inrush current may
flow instantaneously due to the internal powering sequence and delays, especially if the IC has more than one power
supply. Therefore, give special consideration to power coupling capacitance, power wiring, width of ground wiring,
and routing of connections.
8.
Operation Under Strong Electromagnetic Field
Operating the IC in the presence of a strong electromagnetic field may cause the IC to malfunction.
9.
Testing on Application Boards
When testing the IC on an application board, connecting a capacitor directly to a low-impedance output pin may
subject the IC to stress. Always discharge capacitors completely after each process or step. The IC’s power supply
should always be turned off completely before connecting or removing it from the test setup during the inspection
process. To prevent damage from static discharge, ground the IC during assembly and use similar precautions during
transport and storage.
10. Inter-pin Short and Mounting Errors
Ensure that the direction and position are correct when mounting the IC on the PCB. Incorrect mounting may result in
damaging the IC. Avoid nearby pins being shorted to each other especially to ground, power supply and output pin.
Inter-pin shorts could be due to many reasons such as metal particles, water droplets (in very humid environment)
and unintentional solder bridge deposited in between pins during assembly to name a few.
11. Unused Input Pins
Input pins of an IC are often connected to the gate of a MOS transistor. The gate has extremely high impedance and
extremely low capacitance. If left unconnected, the electric field from the outside can easily charge it. The small
charge acquired in this way is enough to produce a significant effect on the conduction through the transistor and
cause unexpected operation of the IC. So unless otherwise specified, unused input pins should be connected to the
power supply or ground line.
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Operational Notes – continued
12. Regarding the Input Pin of the IC
This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them
isolated. P-N junctions are formed at the intersection of the P layers with the N layers of other elements, creating a
parasitic diode or transistor. For example (refer to figure below):
When GND > Pin A and GND > Pin B, the P-N junction operates as a parasitic diode.
When GND > Pin B, the P-N junction operates as a parasitic transistor.
Parasitic diodes inevitably occur in the structure of the IC. The operation of parasitic diodes can result in mutual
interference among circuits, operational faults, or physical damage. Therefore, conditions that cause these diodes to
operate, such as applying a voltage lower than the GND voltage to an input pin (and thus to the P substrate) should
be avoided.
Resistor
Transistor (NPN)
Pin A
Pin B
C
E
Pin A
N
P+
P
N
N
P+
N
Pin B
B
Parasitic
Elements
N
P+
N P
N
P+
B
N
C
E
Parasitic
Elements
P Substrate
P Substrate
GND
GND
Parasitic
Elements
GND
Parasitic
Elements
GND
N Region
close-by
Figure 10. Example of monolithic IC structure
13. Thermal Shutdown Circuit(TSD)
This IC has a built-in thermal shutdown circuit that prevents heat damage to the IC. Normal operation should always
be within the IC’s power dissipation rating. If however the rating is exceeded for a continued period, the junction
temperature (Tj) will rise which will activate the TSD circuit that will turn OFF all output pins. When the Tj falls below
the TSD threshold, the circuits are automatically restored to normal operation.
Note that the TSD circuit operates in a situation that exceeds the absolute maximum ratings and therefore, under no
circumstances, should the TSD circuit be used in a set design or for any purpose other than protecting the IC from
heat damage.
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BD81010MUV
Ordering Information
B
D
8
1
0
Part number
1
0
M
U
V
-
Package
MUV: VQFN032V5050
E2
Packaging and forming specification
E2: Embossed tape and reel
Marking Diagram
VQFN032V5050 (TOP VIEW)
Part Number Marking
BD
LOT Number
8 1 0 1 0
1PIN MARK
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BD81010MUV
Physical Dimension, Tape and Reel Information
Package Name
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BD81010MUV
Revision History
Date
Revision
19.Feb.2016
001
Changes
New Release
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Notice
Precaution on using ROHM Products
1.
Our Products are designed and manufactured for application in ordinary electronic equipments (such as AV equipment,
OA equipment, telecommunication equipment, home electronic appliances, amusement equipment, etc.). If you
(Note 1)
intend to use our Products in devices requiring extremely high reliability (such as medical equipment
, transport
equipment, traffic equipment, aircraft/spacecraft, nuclear power controllers, fuel controllers, car equipment including car
accessories, safety devices, etc.) and whose malfunction or failure may cause loss of human life, bodily injury or
serious damage to property (“Specific Applications”), please consult with the ROHM sales representative in advance.
Unless otherwise agreed in writing by ROHM in advance, ROHM shall not be in any way responsible or liable for any
damages, expenses or losses incurred by you or third parties arising from the use of any ROHM’s Products for Specific
Applications.
(Note1) Medical Equipment Classification of the Specific Applications
JAPAN
USA
EU
CHINA
CLASSⅢ
CLASSⅡb
CLASSⅢ
CLASSⅢ
CLASSⅣ
CLASSⅢ
2.
ROHM designs and manufactures its Products subject to strict quality control system. However, semiconductor
products can fail or malfunction at a certain rate. Please be sure to implement, at your own responsibilities, adequate
safety measures including but not limited to fail-safe design against the physical injury, damage to any property, which
a failure or malfunction of our Products may cause. The following are examples of safety measures:
[a] Installation of protection circuits or other protective devices to improve system safety
[b] Installation of redundant circuits to reduce the impact of single or multiple circuit failure
3.
Our Products are designed and manufactured for use under standard conditions and not under any special or
extraordinary environments or conditions, as exemplified below. Accordingly, ROHM shall not be in any way
responsible or liable for any damages, expenses or losses arising from the use of any ROHM’s Products under any
special or extraordinary environments or conditions. If you intend to use our Products under any special or
extraordinary environments or conditions (as exemplified below), your independent verification and confirmation of
product performance, reliability, etc, prior to use, must be necessary:
[a] Use of our Products in any types of liquid, including water, oils, chemicals, and organic solvents
[b] Use of our Products outdoors or in places where the Products are exposed to direct sunlight or dust
[c] Use of our Products in places where the Products are exposed to sea wind or corrosive gases, including Cl2,
H2S, NH3, SO2, and NO2
[d] Use of our Products in places where the Products are exposed to static electricity or electromagnetic waves
[e] Use of our Products in proximity to heat-producing components, plastic cords, or other flammable items
[f] Sealing or coating our Products with resin or other coating materials
[g] Use of our Products without cleaning residue of flux (even if you use no-clean type fluxes, cleaning residue of
flux is recommended); or Washing our Products by using water or water-soluble cleaning agents for cleaning
residue after soldering
[h] Use of the Products in places subject to dew condensation
4.
The Products are not subject to radiation-proof design.
5.
Please verify and confirm characteristics of the final or mounted products in using the Products.
6.
In particular, if a transient load (a large amount of load applied in a short period of time, such as pulse. is applied,
confirmation of performance characteristics after on-board mounting is strongly recommended. Avoid applying power
exceeding normal rated power; exceeding the power rating under steady-state loading condition may negatively affect
product performance and reliability.
7.
De-rate Power Dissipation depending on ambient temperature. When used in sealed area, confirm that it is the use in
the range that does not exceed the maximum junction temperature.
8.
Confirm that operation temperature is within the specified range described in the product specification.
9.
ROHM shall not be in any way responsible or liable for failure induced under deviant condition from what is defined in
this document.
Precaution for Mounting / Circuit board design
1.
When a highly active halogenous (chlorine, bromine, etc.) flux is used, the residue of flux may negatively affect product
performance and reliability.
2.
In principle, the reflow soldering method must be used on a surface-mount products, the flow soldering method must
be used on a through hole mount products. If the flow soldering method is preferred on a surface-mount products,
please consult with the ROHM representative in advance.
For details, please refer to ROHM Mounting specification
Notice-PGA-E
© 2015 ROHM Co., Ltd. All rights reserved.
Rev.003
Precautions Regarding Application Examples and External Circuits
1.
If change is made to the constant of an external circuit, please allow a sufficient margin considering variations of the
characteristics of the Products and external components, including transient characteristics, as well as static
characteristics.
2.
You agree that application notes, reference designs, and associated data and information contained in this document
are presented only as guidance for Products use. Therefore, in case you use such information, you are solely
responsible for it and you must exercise your own independent verification and judgment in the use of such information
contained in this document. ROHM shall not be in any way responsible or liable for any damages, expenses or losses
incurred by you or third parties arising from the use of such information.
Precaution for Electrostatic
This Product is electrostatic sensitive product, which may be damaged due to electrostatic discharge. Please take proper
caution in your manufacturing process and storage so that voltage exceeding the Products maximum rating will not be
applied to Products. Please take special care under dry condition (e.g. Grounding of human body / equipment / solder iron,
isolation from charged objects, setting of Ionizer, friction prevention and temperature / humidity control).
Precaution for Storage / Transportation
1.
Product performance and soldered connections may deteriorate if the Products are stored in the places where:
[a] the Products are exposed to sea winds or corrosive gases, including Cl2, H2S, NH3, SO2, and NO2
[b] the temperature or humidity exceeds those recommended by ROHM
[c] the Products are exposed to direct sunshine or condensation
[d] the Products are exposed to high Electrostatic
2.
Even under ROHM recommended storage condition, solderability of products out of recommended storage time period
may be degraded. It is strongly recommended to confirm solderability before using Products of which storage time is
exceeding the recommended storage time period.
3.
Store / transport cartons in the correct direction, which is indicated on a carton with a symbol. Otherwise bent leads
may occur due to excessive stress applied when dropping of a carton.
4.
Use Products within the specified time after opening a humidity barrier bag. Baking is required before using Products of
which storage time is exceeding the recommended storage time period.
Precaution for Product Label
A two-dimensional barcode printed on ROHM Products label is for ROHM’s internal use only.
Precaution for Disposition
When disposing Products please dispose them properly using an authorized industry waste company.
Precaution for Foreign Exchange and Foreign Trade act
Since concerned goods might be fallen under listed items of export control prescribed by Foreign exchange and Foreign
trade act, please consult with ROHM in case of export.
Precaution Regarding Intellectual Property Rights
1.
All information and data including but not limited to application example contained in this document is for reference
only. ROHM does not warrant that foregoing information or data will not infringe any intellectual property rights or any
other rights of any third party regarding such information or data.
2.
ROHM shall not have any obligations where the claims, actions or demands arising from the combination of the
Products with other articles such as components, circuits, systems or external equipment (including software).
3.
No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of ROHM or any
third parties with respect to the Products or the information contained in this document. Provided, however, that ROHM
will not assert its intellectual property rights or other rights against you or your customers to the extent necessary to
manufacture or sell products containing the Products, subject to the terms and conditions herein.
Other Precaution
1.
This document may not be reprinted or reproduced, in whole or in part, without prior written consent of ROHM.
2.
The Products may not be disassembled, converted, modified, reproduced or otherwise changed without prior written
consent of ROHM.
3.
In no event shall you use in any way whatsoever the Products and the related technical information contained in the
Products or this document for any military purposes, including but not limited to, the development of mass-destruction
weapons.
4.
The proper names of companies or products described in this document are trademarks or registered trademarks of
ROHM, its affiliated companies or third parties.
Notice-PGA-E
© 2015 ROHM Co., Ltd. All rights reserved.
Rev.003
Datasheet
General Precaution
1. Before you use our Pro ducts, you are requested to care fully read this document and fully understand its contents.
ROHM shall n ot be in an y way responsible or liabl e for fa ilure, malfunction or acci dent arising from the use of a ny
ROHM’s Products against warning, caution or note contained in this document.
2. All information contained in this docume nt is current as of the issuing date and subj ect to change without any prior
notice. Before purchasing or using ROHM’s Products, please confirm the la test information with a ROHM sale s
representative.
3.
The information contained in this doc ument is provi ded on an “as is” basis and ROHM does not warrant that all
information contained in this document is accurate an d/or error-free. ROHM shall not be in an y way responsible or
liable for an y damages, expenses or losses incurred b y you or third parties resulting from inaccur acy or errors of or
concerning such information.
Notice – WE
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