BD8115F-MTE2

Automotive Body Power Management LSI Series LED Driver IC BD8115F-M ●Description The BD8115F is a serial parallel control LED driver with 35V input voltage rating. Responding to the 3-line serial data, it turns the 8ch open drain output on/off. Due to its compact size, it is optimal for small spaces. rrev. 0.34 ev. 0.4 ●Features 1) Open Drain Output 2) 3-line Serial Control + Enable Signal 3) Internal Temperature Protection Circuit (TSD) 4) Cascade Connection Compatible 5) SOP16 6) Internal 8ch Power Transistor Applications These ICs can be used with car and consumer electronic. ●Absolute Maximum Ratings (Ta=25℃) Item P ower Supply Voltage Output Voltage（Pin No : 3～6, 11～14） Input Voltage（Pin No : 2, 7, 8, 10, 15） Power Dissipation Operating Temperature Range Storage Temperature Range Drive Current (DC) Drive Current（Pulse） Junction Temperature Symbol VCC VDmax VIN Pd Topr Tstg IomaxD IomaxP Tjmax Value 7 35 -0.3～VCC 560* -40～+105 -55～+150 50 150** 150 Unit V V V mW ℃ ℃ mA mA ℃ * Pd decreased at 4.48mW/℃ for temperatures above Ta=25℃,mounted on 70×70×1.6mm Glass-epoxy PCB. ** Do not however exceed Pd. Time to impress≦200msec www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 1/12 2009.12 - Rev.0.34 BD8115F-M Technical Note ●Operational Conditions (Ta=-40~105℃) Item P ower Supply Voltage Drive Current Symbol Vcc Io Standard Value Min 4.5 Typ 5 20 Max 5.5 40 Unit V mA * This product is not designed for protection against radioactive rays. ●Electrical Characteristics (Unless specified, Ta=-40~105℃ Vcc=4.5～5.5V) Item Symbol Standard Value Min Typ Max Unit Conditions 【Output D0～D7】 Pin No : 3～6, 11～14） （ ON Resistor Output leakage current 【Logic input】 Pin No : 2, 7, 8, 10, 15） （ Upper limit threshold voltage Bottom limit threshold voltage Hysteresis width Serial clock frequency Input Current Input leakage Current 【WHOLE】 Circuit Current ICC 0.3 5 mA Serial Data Input, VCC=5V,CLK=500KHz, SEROUT=OPEN RST_B=OPEN, SEROUT=OPEN VTH VTL VHYS FCLK IIN IINL Vcc ×0.8 0.15 20 0.3 50 0 Vcc ×0.2 0.45 1.25 100 5 V V V MHz uA uA VIN=5V VIN=0V VCC=5V RON IDL 6 0 12 5 Ω uA ID=20mA VD=34V Static Current 【SER OUT】(Pin No. : 9) Output Voltage high Output voltage Low ISTN - 0 50 uA VOH VOL 4.6 - 4.8 0.2 0.4 V V VCC=5V, ISO=-4mA VCC=5V, ISO=4mA * This product is not designed for protection against radioactive rays. www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 2/12 2009.12 - Rev.0.34 BD8115F-M ●Electrical Characteristic Diagrams (Unless otherwise specified Ta=25℃) Technical Note 450 OUTPUT ON RESISTANCE：RON[Ω] 9 400 310 SUPPLY CURREN T：Icc[μA] 25℃ 5.0V 5.5V 8 7 6 5 4 3 2 1 0 105℃ SUPPLY CURRENT ：Icc[μA] 350 300 105℃ 250 200 150 100 50 0 0 290 270 250 -40℃ 4.5V 25℃ -40℃ 230 210 1 2 3 4 SUPPLY VOLTAGE：Vcc[V] 5 -40 -15 10 35 60 85 4.5 AMBIENT TEMPERATURE ： Ta[℃] 4.7 4.9 5.1 5.3 SUPPLY VOLTAGE：Vcc[V] 5.5 Fig.1 Circuit current （VCC characteristic） 9 OUTPUT ON RESISTANCE ： RON[Ω] 8 7 6 5 4 3 2 1 0 -40 -15 10 35 60 85 Fig.2 Circuit current （Temperature characteristic） 300 Fig.3 Output on resistance （VCC characteristic @ IDD=20mA） 6.0 4.5V 250 OUTPUT VOLTAGE ： [mV] OUTPU T VOLTAGE ： VOH[V] 4.5V 5V 200 5.5 5V 150 -40℃ 5.0 5.5V 5.5V 100 50 0 10 20 30 40 INPUT CURRENT： ID[mA] 50 4.5 25℃ 105℃ 4.0 4.5 4.7 4.9 5.1 5.3 SUPPLY VOLTAGE： Vcc[V] 5.5 AMBIENT TEMPERATURE ： Ta[℃] Fig.4 Output on resistance （Temperature characteristic @ IDD=20mA） 6.0 Fig.5 Output on resistance （IDD characteristic） 0.30 Fig.6 SEROUT high side voltage （VCC characteristic @ ISO=-5mA） 0.30 105℃ 5.5V OUTPUT VOLTAGE ： VOH[V] 5.5 OUTPUT VOLTAGE ： VOL[V] 0.25 5V 5.0 OUTPU T VOLTAGE ： VOL[V] 25℃ 0.25 0.20 0.15 0.10 0.05 0.00 4.5V 0.20 0.15 5.5V 5V -40℃ 0.10 0.05 0.00 4.5 4.0 -40 -15 10 4.5V 35 60 85 4.5 4.7 4.9 5.1 5.3 5.5 -40 AMBIENT TEMPERATURE ： Ta[℃] SUPPLY VOLTAGE ： Vcc[V] -15 10 35 60 85 AMBIENT TEMPERATURE ： Ta[℃] Fig.7 SEROUT high side voltage （Temperature characteristic @ ISO=-5mA） Fig.8 SEROUT low side voltage （VCC characteristic @ ISO=5mA） Fig.9 SEROUT low side voltage （Temperature characteristic @ ISO=4mA） www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 3/12 2009.12 - Rev.0.34 BD8115F-M ●Block Diagram Technical Note TSD VCC 1 D Q CK CLR D Q CK CLR 16 GND SERIN 2 D Q CK CLR D Q CK CLR 15 CLK D Q CK CLR D Q CK CLR D0 3 D Q CK CLR D Q CK CLR 14 D7 D Q CK CLR D Q CK CLR D1 4 D Q CK CLR D Q CK CLR 13 D6 D2 5 D Q CK CLR D Q CK CLR 12 D5 D Q CK CLR D Q CK CLR D3 6 D Q CK CLR 11 D4 RST_B 7 10 LATCH SDWN 8 9 SEROUT Fig.10 ●Pin Setup Diagram BD8115FV（SOP16） ●Terminal Number・Terminal Name Pin Number 1 2 3 16 15 14 13 12 11 10 9 Terminal Name VCC SERIN D0 D1 D2 D3 RST_B SDWN SEROUT LATCH D4 D5 D6 D7 CLK GND Function Power supply voltage input terminal Serial data input terminal Drain output terminal 0 Drain output terminal 1 Drain output terminal 2 Drain output terminal 3 Reset return input terminal (L:FF data 0) Shut down input terminal (H: Output OFF) Serial data output terminal Latch signal input terminal (H: Data latch) Drain output terminal 4 Drain output terminal 5 Drain output terminal 6 Drain output terminal 7 Clock input terminal GND terminal VCC SERIN D0 D1 D2 D3 RST_B SDWN 1 2 3 4 5 6 7 8 GND CLK D7 D6 D5 D4 LATCH SEROUT 4 5 6 7 8 9 10 11 12 13 14 15 16 Fig.11 www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 4/12 2009.12 - Rev.0.34 BD8115F-M ●Block Operation 1）Serial I/F The I/F is a 3-line serial (LATCH, CLK, SERIN) style. 8-bit output ON/OFF can be set-up. This is composed of shift register. + 8-bit register. 2）Driver It is a 8-bit open drain output. Technical Note 3）TSD (Thermal Shut Down) To prevent heat damage and overheating, when the chip temperature goes over approximately 175℃, the output turns off. When the temperature goes back down, normal operation resumes. However, the intended use of the temperature protection circuit is to protect the IC, so please construct thermal design with the junction temperature Tjmax under 150℃. ●Application Circuit VCC 10uF VBAT 10uF ↓IF Rres VF VCC SDWN LATC H RST_B CLK SERIN SEROUT GND D0 D1 D2 D3 D4 D5 D6 D7 Micro computer VCC 10uF VCC SDWN LATC H RST_B CLK SERIN SEROUT GND D0 D1 D2 D3 D4 D5 D6 D7 IF= Fig.12 VBAT - VF Rres + RON www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 5/12 2009.12 - Rev.0.34 BD8115F-M Technical Note ●Serial Communication The serial I/F is composed of a shift register which changes the CLK and SERIN serial signals to parallel signals, and a register to remember those signals with a LATCH signal. The registers are reset by applying a voltage under VCC×0.2 to the RST_B terminal or opening it, and D7~D0 become open. To prevent erroneous LED lighting, please apply voltage under VCC×0.2 to RST_B or make it open during start-up. CLK SERIN Shift Register 8bit 8bit Driver Register LATCH Fig.13 1）Serial Communication Timing The 8-bit serial data input from SERIN is taken into the shift register by the rise edge of the CLK signal, and is recorded in the register by the rise edge of the LATCH signal. The recorded data is valid until the next rise edge of the LATCH signal. 2）Serial Communication Data The serial data input configuration of SERIN terminal is shown below: First → →Last d7 d6 d5 d4 d3 d2 d1 d0 Data Terminal Name D7 D6 D5 D4 D3 D2 D1 D0 Output Status ON OFF ON OFF ON OFF ON OFF ON OFF ON OFF ON OFF ON Data d7 1 0 * * * * * * * * * * * * * d6 * * 1 0 * * * * * * * * * * * * d5 * * * * 1 0 * * * * * * * * * * d4 * * * * * * 1 0 * * * * * * * * d3 * * * * * * * * 1 0 * * * * * * d2 * * * * * * * * * * 1 0 * * * * d1 * * * * * * * * * * * * 1 0 * * d0 * * * * * * * * * * * * * * 1 0 OFF * * represents “Don’t care”. www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 6/12 2009.12 - Rev.0.34 BD8115F-M Technical Note 3）Enable Signal By applying voltage at least VCC×0.8 or more to the SDWN terminal, D0~D7 become open forcibly. At this time, the temperature protection circuit (TSD) stops. D7～D0 become PWM operation by inputting PWM to SDWN. 4）SEROUT A cascade connection can be made (connecting at least 2 or more IC’s in serial). Serial signal input from SERIN is transferred into receiver IC by the fall edge of the CLK signal. Since this functionality gives enough margins for the setup time prior to the rise edge of the CLK signal on the receiver IC (using the exact same CLK signal of sender IC), the application reliability can be improved as cascade connection functionality. LATCH SERIN CLK SEROUT d7 1 d6 2 d5 d4 d3 d2 5 6 d1 7 d0 8 3 4 D7 Fig.14 ●Cascade Connection By using (at least) 2 ICs, each IC’s D7~D0, at (at least) 16ch, can be controlled by the 16-bit SERIN signal. The serial data input to the sender IC can be transferred to the receiver IC by inputting 8CLK to the CLK terminal. Send side IC Receive side IC LATCH SERIN CLK d15 d14 d13 1 2 3 d12 d11 d10 4 5 6 d9 7 d8 8 d7 9 d6 10 d5 d4 d3 d2 14 d1 15 d0 16 11 12 13 Fig.15 www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 7/12 2009.12 - Rev.0.34 BD8115F-M Technical Note ●INPUT SIGNAL’S TIMING CHART TCK CLK 50% TCKH TSEST SEHD T TCKL SERIN 50% TLADZ TLAH TSEW LATCH 50% Fig.16 ●INPUT SIGNAL’S TIMING RULE（Ta=-40～105℃ Vcc=4.5～5.5V） Parameter CLK period CLK high pulse width CLK low pulse width SERIN high and low pulse width SERIN setup time prior to CLK rise SERIN hold time after CLK rise LATCH high pulse time Last CLK rise to LATCH rise Symbol TCK TCKH TCKL TSEW TSEST TSEHD TLAH TLADZ Min 800 380 380 780 150 150 380 200 Unit ns ns ns ns ns ns ns ns www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 8/12 2009.12 - Rev.0.34 BD8115F-M Technical Note ●OUTPUT SIGNAL’S DELAY CHART SDWN 50% TDSNH TDSNL OUTPUT (D7～D0) 50% LATCH 50% TDLAH OUTPUT (D7～D0) 50% CLK 50% TDSOH SEROUT TDSOL 50% Fig.17 ●OUTPUT SIGNAL’S DELAY TIME（Ta=-40～105℃ Vcc=4.5～5.5V） Parameter SDWN Switching Time(L→H) SDWN Switching Time(H→L) LATCH Switching Delay Time SEROUT Propagation Delay Time(L→H) SEROUT Propagation Delay Time (H→L) Symbol TDSNH TDSNL TDLAH TDSOH TDSOL Max 300 300 300 350 350 Unit ns ns ns ns ns www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 9/12 2009.12 - Rev.0.34 BD8115F-M Technical Note ●INPUT/OUTPUT EQUIVALENT CIRCUIT（PIN NAME） 10PIN（LATCH） 14PIN（D7） 13PIN（D6） ， 7PIN（RST_B） 12PIN（D5） 11PIN（D4） ， 8PIN（SDWN） 6PIN（D3） 5PIN（D2） ， 2PIN（SERIN） 4PIN（D1） 3PIN（D0） ， 15PIN（CLK） VCC 9PIN（SEROUT） VCC VCC 100k (TYP) Fig.18 www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 10/12 2009.12 - Rev.0.34 BD8115F-M ●Operation Notes (1) Technical Note Absolute maximum ratings Use of the IC in excess of absolute maximum ratings such as the applied voltage or operating temperature range may result in IC damage. Assumptions should not be made regarding the state of the IC (short mode or open mode) when such damage is suffered. A physical safety measure such as a fuse should be implemented when use of the IC in a special mode where the absolute maximum ratings may be exceeded is anticipated. (2) Reverse connection of a power supply connector If the connector of power is wrong connected, it may result in IC breakage. In order to prevent the breakage from the wrong connection, the diode should be connected between external power and the power terminal of IC as protection solution. (3) GND potential Ensure a minimum GND pin potential in all operating conditions. (4) Setting of heat Use a setting of heat that allows for a sufficient margin in light of the power dissipation (Pd) in actual operating conditions. (5) Pin short and mistake fitting Use caution when orienting and positioning the IC for mounting on printed circuit boards. Improper mounting may result in damage to the IC. Use of the IC in excess of absolute maximum ratings such as the applied voltage or operating temperature range may result in IC damage. (6) Actions in strong magnetic field Use caution when using the IC in the presence of a strong electromagnetic field as doing so may cause the IC to malfunction. (7) Thermal shutdown circuit(TSD) This IC built-in a Thermal shutdown circuit (TSD circuit). If Chip temperature becomes 175 (TYP.), make the output an Open state. Eventually, warmly clearing the circuit is decided by the condition of whether the heat excesses over the assigned limit, resulting the cutoff of the circuit of IC, and not by the purpose of preventing and ensuring the IC. Therefore, the warm switch-off should not be applied in the premise of continuous employing and operation after the circuit is switched on. (8) Testing on application boards When testing the IC on an application board, connecting a capacitor to a pin with low impedance subjects the IC to stress. Always discharge capacitors after each process or step. Ground the IC during assembly steps as an antistatic measure, and use similar caution when transporting or storing the IC. Always turn the IC's power supply off before connecting it to or removing it from a jig or fixture during the inspection process (9) IC terminal input This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them isolated. P/N junctions are formed at the intersection of these P layers with the N layers of other elements to create a variety of parasitic elements. For example, when a resistor and transistor are connected to pins. (See the chart below.) the P/N junction functions as a parasitic diode when GND > (Pin A) for the resistor or GND > (Pin B) for the transistor (NPN). Similarly, when GND > (Pin B) for the transistor (NPN), the parasitic diode described above combines with the N layer of other adjacent elements to operate as a parasitic NPN transistor. The formation of parasitic elements as a result of the relationships of the potentials of different pins is an inevitable result of the IC's architecture. The operation of parasitic elements can cause interference with circuit operation as well as IC malfunction and damage. For these reasons, it is necessary to use caution so that the IC is not used in a way that will trigger the operation of parasitic elements, such as by the application of voltages lower than the GND (PCB) voltage to input pins. Resistor (Pin A) (Pin B) C Transistor (NPN) B (Pin B) B C E GND Parasitic elements N (Pin A) Parasitic elements GND ～ ～ ～ ～ GND P+ N N P N Parasitic elements GND Parasitic elements N P N P+ P+ N P substrate GND P P+ ～ ～ E (10) Ground wiring patterns When using both small signal and large current GND patterns, it is recommended to isolate the two ground patterns, placing a single ground point at the application's reference point so that the pattern wiring resistance and voltage variations caused by large currents do not cause variations in the small signal ground voltage. Be careful not to change the GND wiring patterns of any external components. www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. ～ ～ 11/12 2009.12 - Rev.0.34 BD8115F-M ●Ordering part number Technical Note B D 8 Part No. 1 1 5 F Package F: SOP8 FP: HSOP25 HFP:HRP7 - M T E 2 Part No. Packaging and forming specification E2: Embossed tape and reel (SOP8/HSOP25) TR: Embossed tape and reel (HRP7) None:Tray,Tube SOP16 10 ± 0.2 (MAX 10.35 include BURR) 16 9 Tape Quantity Direction of feed 0.3MIN Embossed carrier tape 2500pcs E2 The direction is the 1pin of product is at the upper left when you hold 6.2 ± 0.3 4.4 ± 0.2 ( reel on the left hand and you pull out the tape on the right hand ) 1 8 0.15 ± 0.1 1.5 ± 0.1 0.11 1.27 0.4 ± 0.1 0.1 1pin (Unit : mm) Direction of feed Reel ∗ Order quantity needs to be multiple of the minimum quantity. www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 12/12 2009.12 - Rev.0.34