BD8153EFV

Power Supply IC Series for TFT-LCD Panels 5V Input Multi-channel System Power Supply IC BD8153EFV No.09035JBT09 ●Description The BD8153EFV is a system power supply IC for TFT panels.A 1-chip IC providing a total of four voltages required for TFT panels, i.e., logic voltage, sauce voltage, gate high-level, and gate low-level voltage, thus constructing a TFT panel power supply with minimal components required. ●Features (BD8153EFV) 1) Operates in an operating voltage range as low as 2.1 V to 6. 0 V. 2) Incorporates a step-up DC/DC converter. 3) Incorporates a 3.3-V regulator. 4) Incorporates positive and negative-side charge pumps. 5) Switching frequency of 1100 kHz 6) DC/DC converter feedback voltage of 1.24 V ± 1% 7) Incorporates a gate shading function 8) Under-voltage lockout protection circuit 9) Thermal shutdown circuit 10) Overcurrent protection circuit 11) HTSSOP-B24 package ●Applications Liquid crystal TV, PC monitor, and TFT-LCD panel ●Absolute maximum ratings (Ta = 25°C) Parameter Power supply voltage Vo1 voltage Vo2 voltage SW voltage Maximum junction temperature Power dissipation Operating temperature range Storage temperature range Symbol VCC Vo1 Vo2 Vsw Tjmax Pd Topr Tstg Limit 7 19 32 19 150 1100* -40 to 125 -55 to 150 Unit V V V V °C mW °C °C * Reduced by 4.7 mW/°C over 25°C, when mounted on a glass epoxy board. (70 mm  70 mm  1.6 mm). ●Recommended Operating Ranges Parameter Power supply voltage Vo1 voltage SW voltage SW Current Vo2 voltage Symbol VCC Vo1 Vsw Isw Vo2 Limit MIN 2.1 8 — — — MAX 6 18 18 1.8 30 Unit V V V A V www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 1/17 2009.07 - Rev.B BD8153EFV Technical Note ●Electrical Characteristics (Unless otherwise specified, VCC = 5 V; Vo1 = 15 V; Vo2 = 25 V; Ta = 25°C) 1 DC/DC Converter Block Limit Parameter Symbol Unit Conditions Min. Typ. Max. [Soft start] Source current Sinking current [Error amp] Input bias current 1 Feedback voltage 1 Voltage gain Sinking current Source current [SW] ON resistance N-channel Leak current N-channel Maximum duty cycle [Overcurrent protection] Saw current limit 2. Regulator controller Parameter [Error amp] VDD voltage Maximum base current Line regulation Load regulation Off threshold voltage On threshold voltage VDD IBMAX RegI RegL VROFF VRON 3.2 4 — — 1.7 1.6 3.3 7 10 10 1.8 1.7 3.4 11 30 50 1.9 1.8 V mA mV mV V V VCC = 4.5 V to 5.5 V Io = 10 mA to 100 mA Symbol Limit Min. Typ. Max. Unit Conditions Insw 2 3 — A * RON_N ILEAKN DMAX 50 — 75 200 — 85 600 10 95 mΩ μA % * Vsw = 18 V IFB1 VFB1 AV IoI Ioo — 1.227 — 25 -100 0.1 1.240 200 50 -50 0.5 1.253 — 100 -25 μA V V/V μA μA Buffer * VFB = 1.5 V VCOMP = 0.5 V VFB = 1.0 V VCOMP = 0.5 V Iso Isi 6 0.1 10 0.2 14 1.0 μA mA Vss = 0.5 V Vss = 0.5 V,VDD = 1.65 V [Under-voltage lockout protection] This product is not designed for protection against radio active rays. * Design guarantee (No total shipment inspection is made.) www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 2/17 2009.07 - Rev.B BD8153EFV Technical Note ●Electrical Characteristics (Unless otherwise specified, VCC = 5 V; Vo1 = 15 V; Vo2 = 25 V; Ta = 25°C) 3.Charge pump Limit Parameter Symbol Unit Conditions Min. Typ. Max. [Error amp] Input bias current 2 Input bias current 3 Feedback voltage 2 Feedback voltage 3 [Delay start block] Source current Sinking current Startup voltage [Switch] ON resistance N-channel ON resistance P-channel [Diode] Voltage of diode [Gate shading block] ON resistance N-channel ON resistance P-channel Leak current N-channel Leak current P-channel High voltage Low voltage Input current 4.Overall Parameter [Reference block] Reference voltage Drive current Load regulation [Oscillator] Oscillating frequency [Oscillator] DET 1 On threshold voltage DET 1 Off threshold voltage DET 2 On threshold voltage DET 2 Off threshold voltage DET 3 On threshold voltage DET 3 Off threshold voltage DET 4 On threshold voltage DET 4 Off threshold voltage [Device] Average circuit current Icc 0.5 2 5 mA No switching This product is not designed for protection against radio active rays. * Design guarantee (No total shipment inspection is made.) IFB2 IFB3 VFB2 VFB3 IDSO IDSI VST RON_NC RON_PC Vf RON_NGS RON_PGS ILEAK_NGS ILEAK_PGS IGH IGL IIG — — 1.183 0.15 3 0.1 0.45 0.5 0.5 600 2 2 — — VDD × 0.7 — 8 0.1 0.1 1.240 0.2 5 0.5 0.60 2 4 710 10 10 — — VDD 0 16.5 0.5 0.5 1.307 0.25 7 1.0 0.75 4 8 800 20 20 10 10 — VDD × 0.3 30 μA μA V V μA mA V Ω Ω mV Ω Ω μA μA V V μA IG = 3.3 V Io = 10 mA * Io = -10 mA * Io = 10 mA Io = 10 mA * Io = -10 mA * VDLS = 0.5V VDLS = 0.5V Symbol Limit Min. 1.215 — — 0.94 1.7 1.6 1.02 0.90 0.25 0.35 1.02 0.90 Typ. 1.240 23 1 1.1 1.8 1.7 1.12 1.00 0.30 0.41 1.12 1.00 Max. 1.265 — 10 1.265 1.9 1.8 1.22 1.10 0.35 0.47 1.22 1.10 Unit Conditions VREF IREF ∆V Fosc VDON1 VDOFF1 VDON2 VDOFF2 VDON3 VDOFF3 VDON4 VDOFF4 V mA mV MHz V V V V V V V V VREF = 0 V IREF = -1 mA www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 3/17 2009.07 - Rev.B BD8153EFV ● Reference Data (Unless otherwise specified, Ta = 25°C) 1 Technical Note 10 SUPPLY CURRENT : IDD[mA] 125℃ 8 6 4 2 1.26 REF VOLTAGE : VREF[V] SUPPLY CURRENT : ICC[mA] 0.8 1.25 0.6 25℃ 0.4 1.24 125℃ 25℃ 1.23 0.2 -40℃ -40℃ 0 0 1.5 3 4.5 6 0 0 1.5 3 4.5 6 1.22 -50 -25 0 25 50 75 100 125 SUPPLY VOLTAGE : VCC [V] SUPPLY VOLTAGE : VDD[V] AMBIENT TEMPERATURE : Ta[℃] Fig. 1 Total Supply Current 1 1.6 REF VOLTAGE : VREF[V] REF VOLTAGE : VREF[V] 1.6 Fig. 2 Total Supply Current 2 12 SS SOURCE CURRENT : ISS[μ A] . 10 8 6 4 2 0 0 5 10 15 20 25 30 Fig. 3 Internal Reference Temperature 1.2 1.2 0.8 0.8 0.4 0.4 0 0 1.5 3 4.5 6 SUPPLY VOLTAGE : VCC[V] 0 REF CURRENT : IREF[mA] 0 1.5 3 4.5 6 SUPPLY VOLTAGE : VDD[V] Fig. 4 Internal Reference Line Regulation 12 DLS SOURCE CURRENT : IDLS[μA] 10 8 6 4 2 0 0 1.5 3 4.5 6 SUPPLY VOLTAGE : VDD[V] SWITCHHING FREQUENCY : f [MHz] 2 Fig. 5 Internal Reference Load Regulation 5 4 3 2 1 0 -25 0 25 50 75 100 125 0 Fig. 6 SS Source Current 1.5 1 0.5 0 -50 - 40 VDD VOLTAGE : VDD[V] 2 4 6 8 10 AMBIENT TEMPERATURE : Ta[℃] BASE CURRENT : IBASE[mA] Fig. 7 DLS Source Current Fig. 8 Switching Frequency Temperature 200 OUTPUT VOLTAGE : Vcp[mV]. 160 GS VOLTAGE : Vgs[V] Fig. 9 REG Current Capacity 200 160 120 80 40 0 0 0.2 0.4 0.6 0.8 1 SW CURRENT : ISW [A] 1 0.8 0.6 N channel 0.4 0.2 0 0 20 40 60 80 100 SW VOLTAGE : VSW [V] 120 N channel 80 P channel 40 0 INPUT CURRENT : Icp[mA] P channel 0 20 40 60 80 100 GS CURRENT : Igs[mA] Fig. 10 SW On Resistance Fig. 11 Charge Pump On Voltage Fig. 12 Gate Shading On Voltage www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 4/17 2009.07 - Rev.B BD8153EFV ●Reference Data (Unless otherwise specified, Ta = 25°C) 15 OUTPUT VOLTAGE : VDD [V] OUTPUT VOLTAGE : VDD[V] 5 4 3 2 1 0 0 1.5 3 4.5 6 0 0.4 0.8 1.2 1.6 2 SUPPLY VOLTAGE : VCC [V] OUTPUT CURRENT : IDD[mA] 12.5 12.4 Vo1 VOLTAGE : VO1[V] 12.3 12.2 12.1 12.0 11.9 11.8 11.7 11.6 11.5 2 3 Technical Note 10 5 0 4 5 6 SUPPLY VOLTAGE : VCC[V] Fig. 13 Vo1 Line Regulation 14 OUTPUT VOLTAGE : VO1[V] 13V EFFICIENCY [ % ] Fig. 14 VDD Load Regulation 100 Fig. 15 Vo1 Line Regulation 100 12V 12 EFFICIENCY [ % ] 13 95 90 90 10.8V 12V 13V 80 11 10.8V 85 70 10 0 100 200 300 400 500 600 700 OUTPUT CURRENT : IO[mA] 80 0 150 300 450 600 OUTPUT CURRENT : IO1[mA] 60 2.5 3 3.5 4 4.5 5 5.5 6 SUPPLY VOLTAGE : VCC[V] Fig. 16 Vo1 Load Regulation Fig. 17 Efficiency vs Output Current Fig. 18 Efficiency vs Power Supply Voltage 24 OUTPUT VOLTAGE : VO2[V] 23.8 23.6 23.4 23.2 23 1600 MAXIMUM CURRENT : IoMAX[mA] OUTPUT VOLTAGE : VO2[V] 23.8 1200 23.7 800 23.6 400 23.5 0 1.5 23.4 3 4.5 6 10 11.5 13 14.5 16 SUPPLY VOLTAGE : VCC[V] INPUT VOLTAGE : Vo1[v] 0 50 100 150 OUTPUT CURRENT : IO2[mA] Fig. 19 Power Supply Voltage vs Max. Output Current Capacity -6 OUTPUT VOLTAGE : VO3[V] OUTPUT VOLTAGE : VO1[V] -6 Fig. 20 Vo2 Line Regulation Fig. 21 Vo2 Load Regulation -6.1 -6.1 IG -6.2 -6.2 VO2GS -6.3 -6.3 - 6.4 10 11 12 13 14 15 INPUT VOLTAGE : VO1[V] - 6.4 0 50 100 150 200 OUTPUT CURRENT : IO[mA] Fig. 22 Negative-side Charge Pump Line Regulation Fig. 23 Negative-side Charge Pump Load Regulation Fig. 24 Gate Shading Output Waveform www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 5/17 2009.07 - Rev.B BD8153EFV ●Pin Assignments Diagram ●Block Diagram VCC 5V 10uF 10uF Technical Note Vo1=14.5V VCC SW Vo1 10uF 160kΩ Step-up Controller PGND DET2 ＋ － 1.1V (18V MAX) SS FB1 15kΩ GND VDD BASE VCC DLS COMP FB1 SS PGND SW IG FB2 REF FB3 GND C3 Vo1 C1H C1L C2L C2H GSOUT Vo2GS Vo2 0.1uF REF 0.1uF COMP 5.1kΩ 1000pF Charge Pump Control 1 Vo1 Vo1 VREF Vo2 C2H 0.1uF C2L C1H 0.1uF C1L TSD UVLO DET4 FB2 ＋ － 1.1V Vo2G R 1uF Vo2 23.5V (30V MAX) 270kΩ 16kΩ DLS 0.1uF Start-up Controller IG DET2 DET4 Gate Shading Controller Vo2G 0.01uF GSOUT Vo3=-5V Vo1 Charge Pump Control 2 VCC 91kΩ 1uF 18kΩ C3 0.1uF REF Regulator C tl DET3 ＋ － 0.3V ＋ － 1.8V DET1 FB3 Vcc 1uF BASE VDD 4.7uF PGND VDD=3.3V GND GND Fig. 25 Pin Arrangements and Block Diagram ●Pin Assignments and Function PIN NO. 1 2 3 4 5 6 7 8 9 10 11 12 Pin name GND Ground pin VDD LDO feedback input pin BASE LDO base drive output pin VCC Power supply input pin DLS FB1 SS SW IG FB2 Capacity connection pin for delay start DC/DC feedback input Soft start capacitor connection pin Switch output Gate shading input Positive-side charge pump feedback input COMP DC/DC difference amplifier output Function PIN NO. 13 14 15 16 17 18 19 20 21 22 23 24 Pin name Vo2 Function Positive-side charge pump output Vo2GS Gate shading source output pin GSOUT Gate shading sink output pin C2H C2L C1L C1H Vo1 C3 GND FB3 REF Flying capacitor connection pin Flying capacitor connection pin Flying capacitor connection pin Flying capacitor connection pin Negative-side charge pump power supply input pin Negative-side charge pump driver output Ground pin Negative-side charge pump feedback input Internal standard output pin PGND Ground pin www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 6/17 2009.07 - Rev.B BD8153EFV Technical Note ●Block Function  Step-up Controller A controller circuit for DC/DC boosting. The switching duty is controlled so that the feedback voltage FB1 is set to 1.24 V (typ.). A soft start operates at the time of starting. Therefore, the switching duty is controlled by the SS pin voltage.  Charge Pump Control 1 A controller circuit for the positive-side charge pump. The switching amplitude is controlled so that the feedback voltage FB2 will be set to 1.24 V (typ.). The start delay time can be set in the DLS terminal at the time of starting. When the DLS voltage reaches 0.6 V (Typ.), switching waves will be output from the C1L and C2L pins.  Charge Pump Control 2 A controller circuit for the negative-side charge pump. The switching amplitude is controlled so that the feedback voltage FB2 will be set to 0.6 V (Typ.).  Gate Shading Controller A controller circuit of gate shading. The Vo2GS and GSOUT are in on/off control according to IG pin input.  Regulator Control A regulator controller circuit for VDD voltage generation. The base pin current is controlled so that VDD voltage will be set to 3.3 V (typ.).  DET 1 to DET 4 A detection circuit of each output voltage. This detected signal is used for the starting sequential circuit.  Start-up Controller A control circuit for the starting sequence. Controls to start in order of VCC VDD Vo1 Vo3 Vo2.  VREF A block that generates internal reference voltage. 1.24V (Typ.) is output.  TSD/UVLO Thermal shutdown/Under-voltage lockout protection/circuit blocks. The thermal shutdown circuit is shut down at an IC internal temperature of 175°C and reset at 160°C. The under-voltage lockout protection circuit shuts down the IC when the VCC is 1.8 V (typ.) or below. ●Starting sequence For malfunction prevention, starting logic control operates so that each output will rise in order of VCC VDD Vo1 Vo3 Vo2. As shown below, detectors DET1 to DET3 detect that the output on the detection side has reached 90% (typ.) of the set voltage, and starts the next block. V CC R eg V DD D ET1 C TL1 S tep up DC/DC DET2 Vo1 N egative Charge Pum p DET3 Vo3 Positive Charge Pum p Vo2 C TL2 C TL3 D ET4 CLT4 Starting sequence model 5V 0 0 3.3V Vcc VDD Vo2 Vo1 0 Vo3 Fig. 26 Starting Timing Chart www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 7/17 2009.07 - Rev.B BD8153EFV Technical Note ●Selecting Application Components (1) Setting the Output L Constant The coil to use for output is decided by the rating current ILR and input current maximum value IINMAX of the coil. IINMAX + ∆IL should not reach the rating value level L ILR IINMAX average current VCC IL Vo IL Co Fig. 27 Coil Current Waveform Fig. 28 Output Application Circuit Diagram Adjust so that IINMAX +∆IL does not reach the rating current value ILR. At this time, ∆IL can be obtained by the following equation. 1 Vo-VCC 1 VCC   ΔIL = L VCC f [A] Here, f is the switching frequency. Set with sufficient margin because the coil value may have the dispersion of 30%. If the coil current exceeds the rating current ILR of the coil, it may damage the IC internal element. BD8153EFV uses the current mode DC/DC converter control and has the optimized design at the coil value. A coil inductance (L) of 4.7 µH to 15 µH is recommended from viewpoints of electric power efficiency, response, and stability. (2) Output Capacity Settings For the capacitor to use for the output, select the capacitor which has the larger value in the ripple voltage VPP allowance value and the drop voltage allowance value at the time of sudden load change. Output ripple voltage is decided by the following equation. 1 VCC ΔIL [V] Here, f is the switching frequency. = ILMAX  RESR +   (ILMAX ) ΔVPP fCo Vo 2 Perform setting so that the voltage is within the allowable ripple voltage range. For the drop voltage during sudden load change; VDR, please perform the rough calculation by the following equation. ΔI VDR =  10 us [V] Co However, 10 µs is the rough calculation value of the DC/DC response speed. Please set the capacitance considering the sufficient margin so that these two values are within the standard value range. (3) Selecting the Input Capacitor Since the peak current flows between the input and output at the DC/DC converter, a capacitor is required to install at the input side. For the reason, the low ESR capacitor is recommended as an input capacitor which has the value more than 10 µF and less than 100 m. If a capacitor out of this range is selected, the excessive ripple voltage is superposed on the input voltage, accordingly it may cause the malfunction of IC. However these conditions may vary according to the load current, input voltage, output voltage, inductance and switching frequency. Be sure to perform the margin check using the actual product. www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 8/17 2009.07 - Rev.B BD8153EFV Technical Note (4) Setting RC, CC of the Phase Compensation Circuit In the current mode control, since the coil current is controlled, a pole (phase lag) made by the CR filter composed of the output capacitor and load resistor will be created in the low frequency range, and a zero (phase lead) by the output capacitor and ESR of capacitor will be created in the high frequency range. In this case, to cancel the pole of the power amplifier, it is easy to compensate by adding the zero point with CC and RC to the output from the error amp as shown in the illustration. Open loop gain characteristics 1 A fp(Min) fp(Max) Gain [dB] lOUTMin lOUTMax fz(ESR) 0 Fp = 2   RO  CO 1 2   ESR  CO [Hz] fz(ESR) = [Hz] 0 Phase [deg] -90 Pole at the power amplification stage When the output current reduces, the load resistance Ro increases and the pole frequency lowers. fp(Min) = fz(Max) = 1 2   ROMax  CO 1 2   ROMin  CO [Hz] at light load [Hz] at heavy load Error amp phase compensation characteristics A Gain [dB] 0 Phase [deg] 0 -90 Zero at the power amplification stage When the output capacitor is set larger, the pole frequency lowers but the zero frequency will not change. (This is because the capacitor ESR becomes 1/2 when the capacitor becomes 2 times.) fp(Amp.) = Fig. 29 Gain vs Phase 1 2   Rc  Cc [Hz] L Vo VCC Cin COMP Rc Cc Vcc,PVcc SW ESR Ro Co GND,PGND Fig. 30 Application Circuit Diagram It is possible to realize the stable feedback loop by canceling the pole fp(Min.), which is created by the output capacitor and load resistor, with CR zero compensation of the error amp as shown below. fz(Amp.) = fp(Min.) 1 2   Rc  Cc = 1 2   Romax  Co [Hz] www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 9/17 2009.07 - Rev.B BD8153EFV Technical Note (5) Regulator Controller Settings The IC incorporates a 3.3-V regulator controller, and a regulator can be formed by using an external PNP transistor. Design the current capability of the regulator with a margin according to the following formula. VCC=5 V VCC IOMAX = 7mA  hfe [A] The hfe is the current gain of the external PNP transistor. 7 mA is the sinking current of the internal transistor. Regulator controller VDD VDD=3.3 V To inside IC Ceramic capacitor with a capacity of 4.7 F or over Fig.31 3.3 V It is not necessary to use the regulator if the input voltage is 3.3 V. In that case, input 3.3 V to both VCC and VDD. Regulator controller VCC Base IC To inside VDD Fig.32 5V When incorporating a regulator into the external transistor, input the output voltage into the regulator. Regulator controller To inside IC VCC 3 pin regulator Base (Open) Voltage other than 3.3 V VDD Fig.33 (6) Setting the Soft Start Time Soft start is required to prevent the coil current at the time of start from increasing and the overshoot of the output voltage at the starting time. The relation between the capacity and soft start time is shown in the following figure. Refer to the figure and set capacity C1.Soft start is required to prevent the coil current at the time of start from increasing and the overshoot of the output voltage at the starting time. Fig. 34 shows the relation between the capacitance and soft start time. Please refer to it to set the capacitance. 10 DELAY TIME[ms] 1 0.1 0.01 0.001 0.01 SS CAPACITANCE[uF] 0.1 Fig. 34 SS Pin Capacitance vs Delay Time As the capacitance, 0.001µF to 0.1µF is recommended. If the capacitance is set lower than 0.001µF, the overshooting may occur on the output voltage. If the capacitance is set larger than 0.1µF, the excessive back current flow may occur in the internal parasitic elements when the power is turned OFF and it may damage IC. When there is the activation relation (sequences) with other power supplies, be sure to use the high accuracy product (such as X5R). Soft start time may vary according to the input voltage, loads, coils and output capacity. Be sure to verify the operation using the actual product. www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 10/17 2009.07 - Rev.B BD8153EFV Technical Note (7) Design of the Feedback Resistor Constant Refer to the following equation to set the feedback resistor. As the setting range, 10 k to 330 k is recommended. If the resistor is set lower than a 10 k, it causes the reduction of power efficiency. If it is set more than 330 k, the offset voltage becomes larger by the input bias current 0.4 µA(Typ.) in the internal error amplifier. Sep-up Vo = R8 + R9 R9 Vo  1.24 [V] R8 7 ＋ － Reference voltage 1.24 V ERR R9 FB1 Fig. 35 (8) Positive-side Charge Pump Settings BU8513EFV incorporates a charge pump controller, thus making it possible to generate stable gate voltage. The output voltage is determined by the following formula. As the setting range, 10 k to 330 k is recommended. If the resistor is set lower than a 10k, it causes the reduction of power efficiency. If it is set more than 330 k, the offset voltage becomes larger by the input bias current 0.4 µA (Typ.) in the internal error amp. Vo2 Reference voltage 1.24 V R8 12 ＋ Vo = R8 + R9 R9  1.24 [V] C8 1000 pF to 4700 pF R9 FB2 － ERR Fig. 36 In order to prevent output voltage overshooting, add capacitor C8 in parallel with R8. The recommended capacitance is 1000 pF to 4700 pF. If a capacitor outside this range is inserted, the output voltage may oscillate. By connecting capacitance to the DLS, a rising delay time can be set for the positive-side charge pump. The delay time is determined by the following formula.  Delay time of charge pump block t DELAY t DELAY = ( CDLS  0.6 )/5 µA [s6] where, CDLS is the external capacitance. (9) Negative-side Charge Pump Settings BU8513EFV incorporates a charge pump controller for negative voltage, thus making it possible to generate stable gate voltage. The output voltage is determined by the following formula. As the setting range, 10 k to 330 k is recommended. If the resistor is set lower than a 10 k, it causes the reduction of power efficiency. If it is set more than 330 k, the offset voltage becomes larger by the input bias current 0.4 µA (Typ.) in the internal error amp. Vo3 C6 Vo3 = R6 R7  1.04 + 0.2 V [V] 1000 pF to 4700 pF R7 R6 23 FB3 0.2 V － ＋ ERR 24 REF 1.24 V Fig.37 The delay time is internally fixed at 200 us. In order to prevent output voltage overshooting, insert capacitor C6 in parallel with R6. The recommended capacitance is 1000 pF to 4700 pF. If a capacitor outside this range is inserted, the output voltage may oscillate. www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 11/17 2009.07 - Rev.B BD8153EFV Technical Note ●Gate Shading Setting Method The IG input signal allows the high-level and low-level control of the positive-side gate voltage. The slope of output can be set by the external RC. The recommended resistance set value is 200  to 5.1 k and the recommended capacitor set value is 0.001 µF to 0.1 µF. The aggravation of efficiency may be caused if settings outside this range are made. Determine ∆V by referring to the following value. The following calculation formula is used for ∆V. ΔV = Vo2GS ( 1 - exp ( tWL CR )) [V] IG tWH tWL H L tLH Vo2GS H ΔV L Fig. 38 LIMIT MIN 1 1 TYP 2 18 10 0.1 MAX - PARAMETER IG “L” Time IG “H” Time Vo2GS “H” to “L Voltage difference Vo2GS “L” to “H” Time TIMING STANDARD VALUE SYMBOL tWL tWH ΔV tLH UNIT µs µs V µs ∆V = 10 V * CONDITION TWL = 2 µs ,R = 500  * From positive-side pump Vo2 Gate IG Shading Control Vo2GS R GSOUT C Gate driver IC Fig. 39 www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 12/17 2009.07 - Rev.B BD8153EFV Technical Note ●Application Examples *Although we are confident that the application circuit diagram reflects the best possible recommendations, be sure to verify circuit characteristics for your particular application. When a circuit is used modifying the externally connected circuit constant, be sure to decide allowing sufficient margins considering the dispersion of values by external parts as well as our IC including not only the static but also the transient characteristic. For the patent, we have not acquired the sufficient confirmation. Please acknowledge the status. (a) Input voltage 5V Vo3 Vo2GS REF Vo2 VDD Vo1 Fig. 40 Vo3 Vo2GS REF Vo2 (b) Input voltage 3.3 V VDD Fig. 41 Vo1 (c) When Inserting PMOS Switch Vo3 Vo2GS REF Vo2 VDD Vo1 Fig. 42 www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 13/17 2009.07 - Rev.B BD8153EFV ●I/O Equivalent Circuits 2.VDD VCC 120kΩ 30kΩ Technical Note 3.BASE VCC 5.DLS,8.SS VDD 6.COMP VDD VDD 7.FB1,12.FB2 VDD 10.SW 11.IG VDD VDD 13.Vo2 14.Vo2GS Vo2 Vo2 200KΩ 15.GSOUT Vo2 16.C2H,19.C1H 17.C2L,18.C1L,21.C3 Vo1 Vo1 23.FB3 VDD 24.REF VDD VDD Fig.43 www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 14/17 2009.07 - Rev.B BD8153EFV Technical Note ●Operation Notes 1) Absolute maximum ratings Use of the IC in excess of absolute maximum ratings such as the applied voltage or operating temperature range may result in IC damage. Assumptions should not be made regarding the state of the IC (short mode or open mode) when such damage is suffered. A physical safety measure such as a fuse should be implemented when use of the IC in a special mode where the absolute maximum ratings may be exceeded is anticipated. 2) GND potential Ensure a minimum GND pin potential in all operating conditions. 3) Setting of heat Use a thermal design that allows for a sufficient margin in light of the power dissipation (Pd) in actual operating conditions. 4) Pin short and mistake fitting Use caution when orienting and positioning the IC for mounting on printed circuit boards. Improper mounting may result in damage to the IC. Shorts between output pins or between output pins and the power supply and GND pins caused by the presence of a foreign object may result in damage to the IC. 5) Actions in strong magnetic field Use caution when using the IC in the presence of a strong magnetic field as doing so may cause the IC to malfunction. 6) Testing on application boards When testing the IC on an application board, connecting a capacitor to a pin with low impedance subjects the IC to stress. Always discharge capacitors after each process or step. Ground the IC during assembly steps as an antistatic measure, and use similar caution when transporting or storing the IC. Always turn the IC's power supply off before connecting it to or removing it from a jig or fixture during the inspection process. 7) Ground wiring patterns When using both small signal and large current GND patterns, it is recommended to isolate the two ground patterns, placing a single ground point at the application's reference point so that the pattern wiring resistance and voltage variations caused by large currents do not cause variations in the small signal ground voltage. Be careful not to change the GND wiring patterns of any external components. 8) This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them isolated. P/N junctions are formed at the intersection of these P layers with the N layers of other elements to create a variety of parasitic elements. For example, when the resistors and transistors are connected to the pins as shown in Fig. 44, a parasitic diode or a transistor operates by inversing the pin voltage and GND voltage. The formation of parasitic elements as a result of the relationships of the potentials of different pins is an inevitable result of the IC's architecture. The operation of parasitic elements can cause interference with circuit operation as well as IC malfunction and damage. For these reasons, it is necessary to use caution so that the IC is not used in a way that will trigger the operation of parasitic elements, such as the application of voltages lower than the GND (P board) voltage to input and output pins. Resistor (Pin A) ～ ～ Transistor (NPN) B (Pin B) B C E GND Parasitic elements N (Pin A) ～ ～ (Pin B) C GND P+ N N P N Parasitic element GND Parasitic elements N P N P+ P＋ N P substrate GND GND P P＋ ～ ～ E Parasitic element Fig.44 Example of a Simple Monolithic IC Architecture 9) Overcurrent protection circuits An over current protection circuit designed according to the output current is incorporated for the prevention of IC destruction that may result in the event of load shorting. This protection circuit is effective in preventing damage due to sudden and unexpected accidents. However, the IC should not be used in applications characterized by the continuous operation or transitioning of the protection circuits. At the time of thermal designing, keep in mind that the current capability has negative characteristics to temperatures. www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. ～ ～ 15/17 2009.07 - Rev.B BD8153EFV Technical Note 10) Thermal shutdown circuit This IC incorporates a built-in thermal shutdown circuit for the protection from thermal destruction. The IC should be used within the specified power dissipation range. However, in the event that the IC continues to be operated in excess of its power dissipation limits, the attendant rise in the chip's temperature Tj will trigger the thermal shutdown circuit to turn off all output power elements. The circuit automatically resets once the chip's temperature Tj drops. Operation of the thermal shutdown circuit presumes that the IC's absolute maximum ratings have been exceeded. Application designs should never make use of the thermal shutdown circuit. 11) Testing on application boards At the time of inspection of the installation boards, when the capacitor is connected to the pin with low impedance, be sure to discharge electricity per process because it may load stresses to the IC. Always turn the IC's power supply off before connecting it to or removing it from a jig or fixture during the inspection process. Ground the IC during assembly steps as an antistatic measure, and use similar caution when transporting or storing the IC. ●Power Dissipation Reduction POWER DISSIPATION :PD[mW］ 1200 1000 800 600 400 200 0 On 70×70×1.6mm Glass-epoxy PCB 1100 25 50 75 100 125 AMBIENT TEMPERATURE :Ta[℃] Fig.45 150 www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 16/17 2009.07 - Rev.B BD8153EFV ●Ordering part number Technical Note B D 8 Part No. 1 5 3 E F V - E 2 Part No. Package EFV:HTSSOP-B24 Packaging and forming specification E2: Embossed tape and reel HTSSOP-B24 7.8±0.1 (MAX 8.15 include BURR) (5.0) 24 13 +6° 4° −4° 0.53±0.15 Tape Quantity 1.0±0.2 Embossed carrier tape (with dry pack) 2000pcs E2 The direction is the 1pin of product is at the upper left when you hold 7.6±0.2 5.6±0.1 Direction of feed (3.4) ( reel on the left hand and you pull out the tape on the right hand ) 1 12 0.325 0.85±0.05 1PIN MARK S +0.05 0.17 -0.03 1.0MAX 0.08±0.05 0.65 +0.05 0.24 -0.04 0.08 S 0.08 M 1pin Direction of feed (Unit : mm) Reel ∗ Order quantity needs to be multiple of the minimum quantity. www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 17/17 2009.07 - Rev.B Notice Notes No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM Co.,Ltd. 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If a Product is intended to be used for any such special purpose, please contact a ROHM sales representative before purchasing. If you intend to export or ship overseas any Product or technology specified herein that may be controlled under the Foreign Exchange and the Foreign Trade Law, you will be required to obtain a license or permit under the Law. Thank you for your accessing to ROHM product informations. More detail product informations and catalogs are available, please contact us. ROHM Customer Support System http://www.rohm.com/contact/ www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. R0039A