Datasheet
4-Channel Back-Boost
White LED Driver
with Integrated FET for up to 32 LEDs
BD81A04EFV-M
●General Description
BD81A04EFV-M is a white LED driver with the capability
of withstanding high input voltage
(40V MAX).This driver has 4ch constant-current drivers
integrated in 1-chip, which each channel can draw up to
120mA max, so that high brightness LED driving can be
realized. Furthermore, a current-mode buck-boost DC/DC
controller is also integrated to achieve stable operation
against unstable car-battery voltage input and also to
remove the constraint of the number of LEDs in series
connection. The brightness can be controlled by PWM
techniques. The set board can be made a conserve area
because MOSFET is built into
●Features
■ Integrated buck-boost current-mode DC/DC controller
■ Four integrated LED current driver channels (120 mA
max. each channel)
■ PWM Light Modulation
■ Built-in protection functions (UVLO, OVP, TSD, OCP,
SCP)
■ Abnormal status detection function (OPEN/ SHORT)
●Key Specifications
■ Power supply voltage
■ LED output current accuracy
■ Oscillation frequency
■ Operating temperature range
■ PWM minimum pulse width
■ LED maximum output current
●Packages
HTSSOP-B28
4.5 to 35 [V]
±3.0 % @50mA
200 to 2200 KHz
-40 to 85 ℃
1usec
120ｍA／ch
6.5 ㎜×6.4 ㎜×1.0 ㎜
●Applications
For display audio, Small and medium-sized type
LCD panel
●Typical Application Circuits
CIN
(GND)
COUT
Vin
VREG
VDISC
(GND)
(DGND)
OVP
(GND)
VCC
CS
(DGND)
EN
BOOT
OUTH
SW
SYNC
(DGND)
RT
RRT
OUTL
(GND)
DGND
BD81A04EFV/MUV
(DGND)
COMP
RPC
LED1
CPC
(GND)
SS
LED2
CSS
LED3
(GND)
PWM
LED4
PGND
ISET
(PGND)
FAIL1
RISET
(GND)
FAIL2
GND
SHDETEN
LEDEN1
LEDEN2
(GND)
○Product structure：Silicon monolithic integrated circuit
○This product is not designed protection against radioactive rays.
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Datasheet
BD81A04EFV-M
●Pin Configuration
●Pin Description
HTSSOP
-B28
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
VQFN028
V5050
19
20
21
22
23
24
25
26
27
28
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
Symbol
VCC
SS
COMP
RT
SYNC
SHDETEN
GND
PWM
FAIL1
FAIL2
LEDEN1
LEDEN2
LED1
LED2
LED3
LED4
OVP
ISET
PGND
OUTL
DGND
VDISC
SW
OUTH
BOOT
VREG
EN
CS
Function
Input power supply
Soft start time-setting capacitance input
Error amplifier output
Oscillation frequency-setting resistance input
External synchronization signal input
LED short detection enable signal
Small-signal GND
PWM light modulation input
Failure signal output
LED open/short detection signal output
LED output enable input 1
LED output enable input 2
LED output 1
LED output 2
LED output 3
LED output 4
Over voltage detection input
LED output current-setting resistance input
LED output GND
Low-side internal MOSFET Drain output
DCDC output GND
VOUT discharge signal
High-side external MOSFET Source pin
High-side external MOSFET Gate output
High-side external MOSFET power supply pin
Internal reference voltage output
Enable input
DC/DC current sence pin
●Block Diagram
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Datasheet
BD81A04EFV-M
● Absolute maximum ratings (Ta=25℃)
Parameter
Power supply voltage
BOOT ,OUTH Voltage
SW,CS,OUTL Voltage
BOOT-SW Voltage
LED output, VDISC voltage
VREG, OVP, FAIL1, FAIL2,
LEDEN1, LEDEN2
ISET, VDAC, PWM, SS, COMP, RT,
SYNC, EN, SHDETEN Voltage
Power Consumption
Operating temperature range
Storage temperature range
LED maximum output current
Junction temperature
Symbol
VCC
VBOOT, VOUTH
VSW, VCS, VOUTL
VBOOT-SW
VLED1,2,3,4, VDISC
VVREG, VOVP, VFAIL1, VFAIL2,
VLEDEN1, VLEDEN2, VISET, VPWM,
VSS, VCOMP, VRT, VSYNC, VEN,
VSHDETEN
Pd
Topr
Tstg
ILED
Tjmax
Rating
40
45
40
7
40
Unit
V
V
V
V
V
-0.3～7 < VCC
V
1
1.45 ※
-40～+85
-55～+150
2 3
120 ※ ※
150
※1
IC mounted on glass epoxy board measuring 70mm×70mm×1.6mm, power dissipated at a rate of 11.6mw/℃ at temperatures above 25℃.
※2
Dispersion figures for LED maximum output current and VF are correlated. Please refer to data on separate sheet.
W
℃
℃
mA
℃
※3 Amount of current per channel.
● Operating conditions (Ta=25℃)
Parameter
Power supply voltage
Oscillating frequency range
External synchronization frequency range
External synchronization pulse duty range
※4 ※5
Symbol
VCC
FOSC
FSYNC
FSDUTY
Limits
4.5～35
200～2200
fosc～2200
40～60
Unit
V
KHz
KHz
%
※4 Connect SYNC to GND or OPEN when not using external frequency synchronization.
※5 Do not switch between internal and external synchronization when an external synchronization signal is input to the device.
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Datasheet
BD81A04EFV-M
●Electrical Characteristics (unless otherwise specified, VCC=12V Ta=25℃)
Limits
Parameter
Symbol
Min
Typ
Max.
Unit
Conditions
EN=Hi, SYNC=Hi, RT=OPEN
PWM=Low,ISET=OPEN,CIN=10 F
Circuit current
ICC
-
-
10
mA
Standby current
IST
-
-
10
A
EN=Low
VREG
4.5
5
5.5
V
IREG=-5mA, CREG=2.2 F
OUTHhigh-side ON resistance
RONHH
1.5
3.5
7.0
ION=-10mA
OUTH low-side ON resistance
RONHL
1.0
2.5
5.0
ION=10mA
OCP voltage
[OUTL Block]
VOLIMIT
VCC-0.66
VCC-0.6
VCC-0.54
RONL
0.44
0.8
1.15
ION=10mA
RON_SW
5.0
10.0
15.0
ION_SW=10mA
VLED
0.9
1.0
1.1
V
20
80
160
A
VLED=2V, Vcomp=1V
-160
-80
-20
A
VLED=0V, Vcomp=1V
[VREG Block (VREG)]
Reference voltage
[OUTH Block
OUTL ON resistance
V
[SW Block]
SW ON resistance
[Error Amplifie Block]
LED control voltage
ICOMP
COMP sink current
SINK
ICOMP
COMP source current
SOURCE
[Oscillator Block]
Oscillating frequency1
FOSC1
285
300
315
KHz
RT=27K
Oscillating frequency2
FOSC2
1800
2000
2200
KHz
RT=3.9K
VOVP
1.9
2.0
2.1
V
VOVP=Sweep up
VOHYS
0.45
0.55
0.65
V
VOVP=Sweep down
TSCP
70
100
130
ms
UVLO voltage
VUVLO
3.2
3.5
3.8
V
UVLO hysteresis width
VUHYS
250
500
750
mV
LEDcurrentrelativedispersionwidth
△ILED1
-3
-
+3
%
LEDcurrentabsolutedispersionwidth
△ILED2
-3
-
+3
%
ILED=50mA,
∆ILED1=(ILED/ILED_AVG-1)×100
ILED=50mA,
∆ILED2=(ILED/50mA-1)×100
VISET
0.9
1.0
1.1
V
RISET=100K
PWM minimum pulse width
Tmin
1
-
-
s
FPWM=150Hz, ILED=100mA
PWM maximum duty
Dmax
-
-
100
%
FPWM=150Hz, ILED=50mA
PWM frequency
FPWM
-
-
20
KHz
Open detection voltage
VOPEN
0.2
0.3
0.4
V
VLED= Sweep down
LED Short detection voltage
VSHORT
4.2
4.5
4.8
V
VLED= Sweep up
LED Short Latch OFF Delay Time
TSHORT
70
100
130
TPWM
70
100
[OVP Block]
OVP voltage
OVP hysteresis width
SCP Latch OFF Delay Time
RT=27K
[UVLO Block ]
VCC : Sweep down
VCC : Sweep up,VREG>3.5V
[LED Output Block]
ISET voltage
PWM Latch OFF Delay Time
Duty=2%, ILED=50mA
ms
RT=27K
130
ms
RT=27K
[Logic Inputs (EN, SYNC, SHDETEN, PWM, LEDEN1, LEDEN2)]
Input HIGH voltage
VINH
2.1
-
5.5
V
Input LOW voltage
VINL
GND
-
0.8
V
IIN
25
50
100
A
VIN=5V(EN,SYNC,PWM,
SHDETEN, LEDEN1, LEDEN2)
VOL
-
0.1
0.2
V
IOL=0.1ｍA
Input current
[FAIL Output (open drain) ]
FAIL LOW voltage
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Datasheet
BD81A04EFV-M
● Reference data (unless otherwise specified, Ta=25℃)
5.5
VCC=SWEEP
EN=4V
PWM=0V
Ta=25℃
6
VCC=12V,35V
Output Voltage ： VREG[V]
Output Current ： ICC [mA]
8
4
2
0
5.0
4.5
VCC=4.5V
4.0
3.5
0
10
20
30
Supply Voltage ：VCC[V]
40
-60
20
60
100
Tempurature ： Ta[℃]
Fig.2 VREG temperature characteristic
Fig.1 Circuit Current
(Switching OFF)
3000
400
VCC=12V
EN=4V
RT=27KΩ
350
Swiching frequency ： fosc[KHz]
Swiching frequency ： fosc[KHz]
-20
300
250
200
-60
-20
20
60
Temperature ： Ta[℃]
100
VCC=12V
EN=4V
RT=3.9KΩ
2500
2000
1500
1000
-60
-20
20
60
100
Temperature ： Ta[℃]
Fig.4 OSC temperature characteristic
(@2000KHz)
Fig.3 OSC temperature characteristic
(@300KHz)
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Datasheet
BD81A04EFV-M
52
Output Current ： ILED[mA]
52
Output Current ： ILED[mA]
51
50
VCC=12V,EN=4V
VLED=SWEEP
Ta=25℃
49
VCC=12V
EN=4V
VLED＝2V
PWM＝VREG
51
50
49
48
48
0
1
2
3
4
Supply Voltage ： VLED[V]
5
-60
100
95
95
90
90
VCC=12V
EN=4V
PWM=VREG
Ta=25℃
LED4 4ch mode
75
70
65
EFFICIENCY [%]
EFFICIENCY [%]
100
80
20
60
Temperature ： Ta[℃]
100
Fig.6 ILED temperature characteristic
Fig.5 VLED vs ILED
85
-20
85
VCC=12V
EN=4V
PWM=VREG
Ta=25℃
LED7 4ch mode
80
75
70
65
60
60
80
130
180
230
Output current ： ILED[mA]
80
Fig.7 Efficiency (Back-boost application)
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130
180
230
Output current ： ILED[mA]
Fig.8 Efficiency (Boost application)
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Datasheet
BD81A04EFV-M
● Description of Blocks
1.voltage reference (VREG)
5V (Typ.) is generated from the VCC input voltage when the enable pin is set HI. This voltage is used to power internal
circuitry, as well as the voltage source for device pins that need to be fixed to a logical HI.
UVLO protection is integrated into the VREG pin. The voltage regulation circuitry operates uninterrupted for VREG
voltages VCC>4.0V(Typ.) and VREG>3.5V（Typ.）, but if output voltage drops to VCC 32 V if ROVP1 = 22 k
and ROVP2 = 330 k .
(3) Buck-boost DC/DC converter oscillation frequency (FOSC)
RRT vs Fosc
Fosc [kHz]
10000
1000
100
1
10
RRT[kΩ]
Fig.12
100
RRT VS FOSC
The regulator’s internal triangular wave oscillation frequency can be set via a resistor connected to the RT pin (pin 4). This
resistor determines the charge/discharge current to the internal capacitor, thereby changing the oscillating frequency.
Refer to the above graph and following expression when setting RT.
8
fosc = 81×10 / RRT[ ] x α [kHz]
8
81×10 is constant value in IC (+-5%) and α is adjustment factor.
(RT :α = 43k : 1.01, 27k : 1.00 , 18k : 0.99, 10 k : 0.98, 4.7k : 0.97, 3.9k : 0.96 )
A resistor in the range of 3 k ～33 k is recommended. Settings that deviate from the frequency range shown below may
cause switching to stop, and proper operation cannot be guaranteed.
(4) External DC/DC converter oscillating frequency synchronization (FSYNC)
Do not switch from external to internal oscillation of the DC/DC converter if an external synchronization signal is present on
the SYNC pin. When the signal on the SYNC terminal is switched from high to low, a delay of about 30 µS (typ.) occurs
before the internal oscillation circuitry starts to operate (only the rising edge of the input clock signal on the SYNC terminal
is recognized). Moreover, if external input frequency is less than the internal oscillation frequency, the internal oscillator
will engage after the above-mentioned 30 µS (typ.) delay; thus, do not input a synchronization signal with a frequency less
than the internal oscillation frequency.
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BD81A04EFV-M
(5)Soft Start Function
The soft-start (SS) limits the current and slows the rise-time of the output voltage during the start-up, and hence leads to
prevention of the overshoot of the output voltage and the inrush current.
4.LED Short Detection
Table2 Detecting condition and operation after detect about each protection
Detecting Condition
Protection
UVLO
Operation after detect
[Detect]
[Release]
VCC3.5V
All blocks shut down
TSD
Tj>175℃
Tj2.0V
VOVPVCC-0.6V
SS discharged
SCP
VLED4.5V
(100ms delay 300kHz)
EN or UVLO
The only detected channel latches off
(after the counter sets)
Fig.13
Protection flag output part block diagram
The operating status of the built-in protection circuitry is propagated to FAIL1 and FAIL2 pins (open-drain outputs). FAIL1
becomes low when UVLO, TSD, OVP, or SCP protection is engaged, whereas FAIL2 becomes low when open or short LED
is detected.
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BD81A04EFV-M
●Operation of the Protection Circuitry
(1)Under-Voltage Lock Out (UVLO)
The UVLO shuts down all the circuits other than REG when VCC2.0V.
→SS pulling out
→FAIL1 becomes Low.
③-2 Shutdown after about 100ms when LED4 IL_MAX
3.
Select the value of L such that 0.05/µs < VOUT / L < 0.3V/ µs
4.
Select coil, schottky diodes, MOSFET and RCS which meet with the ratings
5.
Select the output capacitor which meets with the ripple voltage requirements
6.
Select the input capacitor
7.
Work on with the compensation circuit
8.
Work on with the Over-Voltage Protection (OVP) setting
9.
Work on with the soft-start setting
10.
Feedback the value of L
Verify experimentally
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Datasheet
BD81A04EFV-M
1.
Computation of the Input Peak Current and IL_MAX
VIN
IL
Rcs
CS
M1
D2
Vout
L
M2
Co
D1
①
Fig.15 Output application circuit diagram
Calculation of the maximum output voltage (Vout_max)
To calculate the Vout_max, it is necessary to take into account of the VF variation and the number of LED connection in
series.
∆VF：VF Variation
N：Number of LED connection in series
Vout_max = (VF + ΔVF) × N + 1.1V
②
Calculation of the max output current Iout_max
Iout_max = ILED × 1.03 × M
M: Number of LED connection in parallel
③Calculation of the max input peak current IL_MAX
IL_MAX = IL_AVG + 1/2ΔIL
IL_AVG = (VIN + Vout_max) × Iout_max / (n × VIN)
VIN
ΔIL=
2.
3.
L
1
×
n: efficiency
Fosc: switching frequency
Vout
×
Fosc
VIN+Vout
・The worst case scenario for VIN is when it is at the minimum, and thus the minimum value should be applied in the
equation.
・ The L value of 2.2µH ∼ 47µH is recommended. The current-mode type of DC/DC conversion is adopted for
BD81A04EFV-M, which is optimized with the use of the recommended L value in the design stage. This recommendation is
based upon the efficiency as well as the stability. The L values outside this recommended range may cause irregular
switching waveform and hence deteriorate stable operation.
・n (efficiency) is approximately 80%
The setting of over-current protection
Choose Rcs with the use of the equation
(VIN - Vocp_min (=0.54V) ) / Rcs > IL_MAX
The selection of the L
In order to achieve stable operation of the current-mode DC/DC converter, we recommend selecting the L value in the
range indicated below:
Vout×Rcs
0.05 [V/μS] <
< 0.3 [V/μS]
L
When investigating the margin, it is worth noting that the L value may vary by approximately ±30%.
The smaller
Vout×Rcs
allows stability improvement but slows down the response time.
L
4.
Selection of coil L, diode D1 and D2, MOSFET M1 and M2, and Rcs
Coil L
Current rating
> IL_MAX
Voltage rating
―
Diode D1
Diode D2
> Iocp
> Iocp
> VIN_MAX
> Vout
MOSFET M1
MOSFET M2
> Iocp
> Iocp
> VIN_MAX
> Vout
Heat loss
2
※
※
Rcs
―
―
> Iocp × Rcs
Allow some margin, such as the tolerance of the external components, when selecting.
In order to achieve fast switching, choose the MOSFETs with the smaller gate-capacitance.
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BD81A04EFV-M
5.
Selection of the output capacitor
Select the output capacitor Cout based on the requirement of the ripple voltage Vpp.
Vpp =
×
Cout
6.
7.
1
Vout
Iout
+ ΔIL × RESR
×
Vout+VIN
Fosc
Choose Cout that allows the Vpp to settle within the requirement. Allow some margin also, such as the tolerance of the
external components.
Selection of the input capacitor
A capacitor at the input is also required as the peak current flows between the input and the output in DC/DC conversion.
We recommend an input capacitor greater than 10µF with the ESR smaller than 100mΩ. The input capacitor outside of our
recommendation may cause large ripple voltage at the input and hence lead to malfunction.
Phase Compensation Guidelines
Vout
LED
FB
A
COMP
Rpc
Cpc
Fig.16 COMP part application circuit diagram
In general, the negative feedback loop is stable when the following condition is met
・Overall gain of 1 (0dB) with a phase lag of less than 150º (i.e., a phase margin of 30º or more)
However, as the DC/DC converter constantly samples the switching frequency, the gain-bandwidth (GBW) product of the
entire series should be set to 1/10 the switching frequency of the system. Therefore, the overall stability characteristics of
the application are as follows:
• Overall gain of 1 (0dB) with a phase lag of less than 150º (i.e., a phase margin of 30º or more)
• GBW (frequency at gain 0dB) of 1/10 the switching frequency
Thus, to improve response within the GBW product limits, the switching frequency must be increased.
※
RL is the load impedance. ( RL = VOUT / IOUT )
The key for achieving stability is to place fz near to the GBW.
Phase-lead
fz =
1
2πCpcRpc
[Hz]
Phase-lag
fp1 =
1
2πRLCout
[Hz]
Good stability would be obtained when the fz is set between 1kHz～10kHz.
In buck-boost applications, Right-Hand-Plane (RHP) Zero exists. This Zero has no gain but a pole characteristic in terms of
phase. As this Zero would cause instability when it is in the control loop, so it is necessary to bring this zero before the
GBW.
2
fRHP=
Vout×{VIN/(Vout+VIN)}
[Hz]
2πILOADL
ILOAD: MAXIMUM LOAD CURRENT
It is important to keep in mind that these are very loose guidelines, and adjustments may have to be made to ensure
stability in the actual circuitry. It is also important to note that stability characteristics can change greatly depending on
factors such as substrate layout and load conditions. Therefore, when designing for mass-production, stability should be
thoroughly investigated and confirmed in the actual physical design.
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Datasheet
BD81A04EFV-M
8.
Setting of the over-voltage protection Vo
－
＋
ROVP2
2.0V/1.45V
OVP
－
＋
ROVP1
1.7V/1.6V
Fig.17 OVP part application circuit diagram
* We recommend setting the over-voltage protection Vovp
1.2V to 1.5V greater than Vout which is adjusted by the
number of LEDs in series connection. Less than 1.2V may
cause unexpected detection of the LED open and short during
the PWM brightness control. For the Vovp greater than 1.5V,
the LED short detection may become invalid.
9.
Setting of the soft-start
The soft-start allows minimization of the coil current as well as the overshoot of the output voltage at the start-up.
For the capacitance we recommend in the range of 0.001 to 0.1uF. For the capacitance less than 0.001uF may cause
overshoot of the output voltage. For the capacitance greater than 0.1uF may cause massive reverse current through the
parasitic elements of the IC and damage the whole device. In case it is necessary to use the capacitance greater than
0.1uF, ensure to have a reverse current protection diode at the VCC or a bypass diode placed between the SS-pin and the
VCC.
Soft-start time TSS [TYP.]
TSS = CSSX0.7V / 5uA [s]
CSS: The capacitance at the SS-pin
There is the possibility of SCP error detection hang on CSS setting and Oscillating frequency setting.
Please check the following condition.
Trise = CSS X V1 / Iss
Trise : DCDC start up time, V1 : IC constant voltage(MAX 2.5V), Iss : SS source current(MIN 3.0uA)
Tscp = 32770 X (1/Fosc)
Tscp : SCP Latch OFF Delay Time, Fosc : Oscillating frequency
SCP error detection avoid condition : Trise < Tscp
10.
Verification of the operation by taking measurements
The overall characteristic may change by load current, input voltage, output voltage, inductance, load capacitance,
switching frequency, and the PCB layout. We strongly recommend verifying your design by taking the actual
measurements.
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TSZ22111・15・001
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Datasheet
BD81A04EFV-M
●Recommended operating range
The following data is recommended operating range of BD81A04EFV-M (VCC vs Vout).
The following data is reference data in Rohm evaluation board. So please check the behavior of practice board
and use this IC.
Boost
Fosc=300kHz
ILEDtotal=360ｍA
Boost
Fosc=300kHz
ILEDtotal=200ｍA
Recommended
operating range
Recommended
operating range
Fig.18 Boost operating range (1)
Boost
Fosc=2200kHz
ILEDtotal=360ｍA
Fig.19 Boost operating range (2)
Boost
Fosc=2200kHz
ILEDtotal=200ｍA
Recommended
operating range
Recommended
operating range
Fig.20 Boost operating range (3)
Fig.21 Boost operating range (4)
VCC [V]
35
Buckboost
Fosc=300kHz
ILEDtotal=360ｍA
Recommended
operating range
Buckboost
Fosc=300kHz
ILEDtotal=200ｍA
Recommended
operating range
8
4.5
12
Fig.22 Buck-boost operating range (1)
32 35 VOUT [V]
Fig.23 Buck-boost operating range (2)
VCC [V]
Buckboost
Fosc=2200kHz
ILEDtotal=360ｍA
Recommended
operating range
Buckboost
Fosc=2200kHz
ILEDtotal=200ｍA
35
Recommended
operating range
14
4.5
4.5
Fig.24 Buck-boost operating range (3)
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© 2012 ROHM Co., Ltd. All rights reserved.
TSZ22111・15・001
32 35 VOUT [V]
Fig.25 Buck-boost operating range (4)
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TSZ02201-0G1G0C600010-1-2
16.APR.2012 Rev.002
Datasheet
BD81A04EFV-M
● PCB application circuit diagram
Fig.26 PCB application circuit diagram
•
•
The coupling capacitors CVCC and CREG should be mounted as close as possible to the IC’s pins.
•
Noise should be minimized as much as possible on pins PWM, ISET, RT and COMP.
•
PWM,OUTH,SW,SYNC and LED1-4 carry switching signals, so ensure during layout that surrounding traces are not affected
Large currents may pass through DGND and PGND, so each should have its own low-impedance routing to the system ground.
by crosstalk.
.
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Datasheet
BD81A04EFV-M
● Application Board Daigram
When using it as Boost DCDC converter
CIN
(GND)
COUT
VDISC
VREG
Vin
OVP
(GND)
(DGND)
UVLO
TSD
(GND)
OVP
VCC
VREG
OCP
＋
－
CS
(DGND)
Timer
EN
FAIL1
PWM
Latch
BOOT
Control Logic
OUTH
DRV
SW
CTL
SYNC
SLOPE
－
PWM
＋
OSC
RT
VREG
OUTL
RRT
(GND)
ERR AMP
－
－
－
－
＋
COMP
RPC
DGND
(DGND)
LED1
OCP OVP
CPC
SS
(GND)
LED2
SS
CSS
LED3
(GND)
Current driver
LED4
PWM
PGND
ISET
Open Short Detect
ISET
Open Det
RISET
Timer
Latch
(PGND)
Short Det
(GND)
FAIL2
GND
(GND)
SHDETEN LEDEN1 LEDEN2
Fig.27 Boost application circuit diagram
When using it as Buck DCDC converter
Fig.28 Buck application circuit diagram
Note：When VOUT and the LED terminal are shorted to GND, the overcurrent from VIN cannot be obstructed when
using it as stated above as the Step-up DCDC converter. Therefore, please do measures of the insertion of the fuse
between VCC and RCS etc.
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Datasheet
BD81A04EFV-M
●PCB board external part list
serial No.
component name
component value
product name
Manufacturer
1
CIN1
10 F
GRM31CB31E106KA75B
2
CIN2
－
－
－
3
CPC1
0.1 F
GRM188B31H104KA92
murata
4
CPC2
－
5
RPC1
510
6
CSS
0.1 F
7
RRT
27k
8
RFL1
9
RFL2
murata
－
－
MCR03 Series
Rohm
GRM188B31H104KA92
murata
MCR03 Series
Rohm
100k
MCR03 Series
Rohm
100k
MCR03 Series
Rohm
10
CCS
－
－
11
RCS1
620m
MCR100JZHFLR620
Rohm
12
RCS2
620m
MCR100JZHFLR620
Rohm
13
RCS3
0
－
－
14
CREG
2.2 F
GRM188B31A225KE33
murata
15
CPC3
0.1 F
GRM188B31H104KA92
murata
16
M1
－
RSH070N05
Rohm
17
M2
－
－
－
18
D1
－
RB050L-40
Rohm
19
D2
－
RF201L2S
Rohm
20
L1
33 H
SLF10145T-330M1R6-H
TDK
21
L2
-
－
－
22
COUT1
10 F
GRM31CB31E106KA75B
murata
23
COUT2
10 F
GRM31CB31E106KA75B
murata
24
COUT3
-
－
－
25
ROVP1
30k
MCR03 Series
Rohm
26
ROVP2
360k
MCR03 Series
Rohm
27
RISET
100k
MCR03 Series
Rohm
28
RG1
0
－
－
－
29
RG2
－
－
－
30
LED1
0
－
Rohm
31
LED2
0
－
Rohm
32
JP1
0
－
－
33
JP2
0
－
－
34
JP3
－
－
－
35
JP4
0
－
－
36
JP5
0
－
－
37
JP6
－
－
－
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Datasheet
BD81A04EFV-M
● Power Dissipation Calculation
Pc
= Icc×VCC
＋ Ciss1×VREG×Fsw×VREG
＋ Ciss2×VREG×Fsw×VREG
＋ { VLED×M + △Vf×(M-1) }×ILED
＋ RonFET×IFET×IFET
・・・①Power of circuit
・・・②Boost FET (internal) drive power
・・・③Buck FET (external) drive power
・・・④Power of current driver
・・・⑤Internal FET power
IL_AVG = (VCC+Vout)/VCC×Iout/n
IFET=
IL_AVG×Vout/(VCC+Vout)
Iout =
ILED×1.03×M
Vout =
(Vf +ΔVf)×N ＋ VLED
Pc
Ciss1
Fsw
N
△Vf
：
：
：
：
：
IC power consumption
Boost FET gate capacitance
Switching frequency
LED number
LED Vf difference
・・・⑥Inductance average current
・・・⑦Current that flows to Boost FET (internal)
・・・⑧LED output current
・・・⑨DCDC output voltage
Icc
： Current of the maximum circuit
VCC
Ciss2
： Buck FET gate capacitance
VREG
VLED
： LED control voltage
ILED
M
： Parallel number of LED
Vf
RonFET ： Step-up FET (internal) ON resistance
： Power-supply voltage
： VREG voltage
： LED output current
：LED forward voltage
n ：Efficiency
＜Calculation example＞
When assuming Icc=10 ｍ A, VCC=12V, Ciss1=65pF, Ciss2=2000pF, VREG=5V, Fsw=2200kHz, VLED=1V, ILED=50mA,
N=7steps, M=4 row, Vf=3.5V, ΔVf=0.5V, RonFET=1.15Ω, n=80%
Vout =
(3.5V+0.5V)×7 steps＋1V = 29V
Iout =
50mA×1.03×4 row = 0.206A
IL_AVG= (12+29V)/12V×0.206A/0.8 = 0.88A
IFET=
0.88A×29V/(12V+29V)=0.622A
Pc (4) =
10mA×12V + 65pF×5V×2200kHz×5V + 2000pF×5V×2200kHz×5V +
｛1.0V×4+0.5V×(4-1)｝×50mA + 1.15Ω×0.622A×0.622A = 0.898[W]
● Power Dissipation of packaging
6.0
(1)θja=26.6℃/W(4 layer board, and area of cupper foil is 89%)
5.5
(1) 4.70W
Power dissipation Pd [W]
5.0
(2)θja=37.9℃/W(2 layer board, and area of cupper foil is 89%)
(3)θja=67.6℃/W(2 layer board, and area of cupper foil is 4.6%)
4.5
4.0
(2) 3.30W
3.5
3.0
2.5
(3) 1.85W
2.0
1.5
1.0
0.5
0.0
0
25
50
75
100
125
150
Temp Ta [℃]
Fig.29 HTSSOP-B28 Power dissipation
Note 1: Power dissipation calculated when mounted on 70mm X 70mm X 1.6mm glass epoxy substrate (1-layer platform/copper thickness 18 m)
Note 2: Power dissipation changes with the copper foil density of the board. This value represents only observed values, not guaranteed values.
HTSSOP-B28
Pd=1.85W (0.97W)： Board copper foil area 225m ㎡
Pd=3.30W (1.72W)： Board copper foil area 4900m ㎡
Pd=4.70W (2.44W)： Board copper foil area 4900m ㎡
(Value within parentheses represents power dissipation when Ta=85°C)
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Datasheet
BD81A04EFV-M
● Input/output Equivalent Circuits (terminal name follows pin number)
2.SS
3.COMP
VREG
VCC
4.RT
VREG
VREG
VREG
VREG
1K
12.5
5K
SS
RT
COMP
10K
1K
1K
1K
9.FAIL1,10.FAIL2
5.SYNC,6.SHDETEN,8.PWM,11.LEDEN1,12.LEDEN2
VREG
VREG
VREG
COMP
SHDETEN
PWM
LEDEN1
LEDEN2
1K
FAIL1
FAIL2
10K
100K
13～16. LED1～4
17.OVP
18.ISET
VREG
VREG
LED1
LED2
LED3
LED4
VREG
10K
100K
OVP
1K
10K
1K
10K
ISET
90K
2Ω
20.OUTL
22.VDISC
23.SW
VCC
VDISC
OUTL
SW
24.OUTH
26.VREG
25.BOOT
VCC
BOOT
BOOT
BOOT
VREG
BOOT
VREG
1K
OUTH
SW
SW
SW
SW
27.EN
SW
28.CS
VCC
VCC
VCC
5p
EN
62.5K
1.1K
CS
5K
125K
166
2p
SW
※All values typical.
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Datasheet
BD81A04EFV-M
● Operating Notes
1) Absolute maximum ratings
Use of the IC in excess of absolute maximum ratings (such as the input voltage or operating temperature range) may result in
damage to the IC. Assumptions should not be made regarding the state of the IC (e.g., short mode or open mode) when such
damage is suffered. If operational values are expected to exceed the maximum ratings for the device, consider adding
protective circuitry (such as fuses) to eliminate the risk of damaging the IC.
2) GND potential
Ensure that the GND pin is held at the minimum potential in all operating conditions.
3) Thermal Design
Use a thermal design that allows for a sufficient margin for power dissipation (Pd) under actual operating conditions.
4) Inter-pin shorts and mounting errors
Use caution when orienting and positioning the IC for mounting on printed circuit boards. Improper mounting may result in
damage to the IC. Shorts between output pins or between output pins and the power supply and GND pins caused by poor
soldering or foreign objects may result in damage to the IC.
5) Operation in strong electromagnetic fields
Exercise caution when using the IC in the presence of strong electromagnetic fields as doing so may cause the IC to
malfunction.
6) Testing on application boards
When testing the IC on an application board, connecting a capacitor directly to a low-impedance pin may subject the IC to
stress. Always discharge capacitors completely after each process or step. The IC’s power supply should always be turned off
completely before connecting or removing it from a jig or fixture during the evaluation process. To prevent damage from
static discharge, ground the IC during assembly and use similar precautions during transport and storage.
7) Ground wiring patterns
When using both small-signal and large-current GND traces, the two ground traces should be routed separately but
connected to a single ground potential within the application in order to avoid variations in the small-signal ground caused by
large currents. Also ensure that the GND traces of external components do not cause variations on GND voltage.
8) IC input pins and parasitic elements
This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them isolated.
PN junctions are formed at the intersection of these P layers with the N layers of other elements, creating parasitic diodes
and/or transistors. For example (refer to the figure below):
Transistor (NPN)
Resistance
Pin A
Pin B
C
E
Pin A
N
N
P
P
+
Parasitic Element
N
P
+
GND
P
+
N
P
Substrate
Pin B
B
B
B
N
R
Parasitic Element
Parasitic Elements
P
P
+
GND
N
P
substr
GND
C
E
GND
Parasitic Elements
Other Adjacent Elements
Fig.30 Example of IC Structure
•
When GND > Pin A and GND > Pin B, the PN junction operates as a parasitic diode
•
When GND > Pin B, the PN junction operates as a parasitic transistor
Parasitic diodes occur inevitably in the structure of the IC, and the operation of these parasitic diodes can result in mutual
interference among circuits, operational faults, or physical damage. Accordingly, conditions that cause these diodes to
operate, such as applying a voltage lower than the GND voltage to an input pin (and thus to the P substrate) should be
avoided.
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Datasheet
BD81A04EFV-M
9) Over-current protection circuits
An over-current protection circuit (designed according to the output current) is integrated into the IC to prevent damage in the
event of load shorting. This protection circuit is effective in preventing damage due to sudden and unexpected overloads on
the output. However, the IC should not be used in applications where operation of the OCP function is anticipated or assumed
10) Thermal shutdown circuit (TSD)
This IC also incorporates a built-in TSD circuit for the protection from thermal destruction. The IC should be used within the
specified power dissipation range. However, in the event that the IC continues to be operated in excess of its power
dissipation limits, the rise in the chip's junction temperature Tj will trigger the TSD circuit, shutting off all output power
elements. The circuit automatically resets itself once the junction temperature Tj drops down to normal operating
temperatures. The TSD protection will only engage when the IC's absolute maximum ratings have been exceeded;
therefore, application designs should never attempt to purposely make use of the TSD function.
The Japanese version of this document is the formal specification.
A customer may use this translation version only for a reference to help reading the formal version.
If there are any differences in translation version of this document, formal version takes priority.
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Datasheet
BD81A04EFV-M
●Ordering Information
B
D
8
1
A
0
4
E
F
V
-
Package
EFV: HTSSOP-B28
ME2
Packaging
M: high reliability
E2: Embossed carrier tape
(HTSSOP-B28)
●Physical Dimension Tape and Reel Information
HTSSOP-B28
9.7±0.1
(MAX 10.05 include BURR)
(5.5)
1
Tape
Embossed carrier tape (with dry pack)
Quantity
2500pcs
E2
Direction
of feed
The direction is the 1pin of product is at the upper left when you hold
( reel on the left hand and you pull out the tape on the right hand
)
14
+0.05
0.17 -0.03
1PIN MARK
1.0MAX
0.625
1.0±0.2
(2.9)
0.5±0.15
15
4.4±0.1
6.4±0.2
28
+6°
4° −4°
0.08±0.05
0.85±0.05
S
0.08 S
0.65
+0.05
0.24 -0.04
0.08
1pin
M
Reel
(Unit : mm)
Direction of feed
∗ Order quantity needs to be multiple of the minimum quantity.
●Marking Diagram
HTSSOP-B28 (TOP VIEW)
Part Number Marking
BD81A04EFV
LOT Number
1PIN MARK
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