Datasheet
System Motor Driver Series for CD・DVD・BD Player
9ch System Motor Driver
For Car AV
BD8256EFV-M
General Description
Key Specifications
Ron(Spindle):
Ron(Loading):
Power Supply Voltage Range:
BD8256EFV-M is a 9ch motor driver developed for
driving coil actuator (3ch), sled motor (2ch), a loading
motor, and a three-phase motor for spindle. This chip
has a built-in 2ch LVDS (Low Voltage Differential
Signaling) output for spherical aberration. This can drive
the motor and coil of blu-ray drive.
It has a built-in Serial Peripheral Interface (SPI) with a
max clock frequency of 35MHz, for interfacing with the
Micro-controller.
Package
1.0Ω(Typ)
1.5Ω(Typ)
4.5V to 10.5V
W(Typ) × D(Typ) × H(Max)
18.50mm × 9.50mm × 1.00mm
HTSSOP-B54
Features
Built-in Serial Peripheral Interface(SPI)
High efficiency at 180° PWM for spindle driver
Built-in 2-channel stepping motor driver for sled
Built-in actuator over current protection circuit
Built-in loading driver short-circuit protection
AEC-Q100 Qualified
Applications
Car navigation
Car AV
HTSSOP-B54
Typical Application Circuit
VCC
VCC
PREVCC
HALL
HALL
HALL
PREVCC
FCTLRNF
TKRNF
FCTLCDET
TKCDET
SLRNF1
SLRNF2
BHLD
SPRNF
SDI
SDO
SCLK
SLV
MUTEB
HU+
HUHV+
HVHW+
HW-
HALL_VC
PREGND
PREVCC
SPGND
VCC
BD8256EFV-M
SLGND
SHV
ACTGND
ERROUT
PRTLIM
PRTT
PRTFT
PRTOUT
FCTLO1+
FCTLO1-
FCTLO2+
TKO+
FCTLO2-
TKO-
LDO+
LDO-
SLO1-
SLO1+
SLO2+
SLO2-
U_OUT
V_OUT
W_OUT
FG
SPCNF
VREG
SAO1+
SAO1SAO2+
SAO2-
M
M
SHV
SHV
SHV
Figure 1. Typical Application Circuit
○Product structure：Silicon monolithic integrated circuit
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TSZ02201-0G1G0BK00030-1-2
4.Apr.2016 Rev.004
BD8256EFV-M
PREVCC
53
TKRNF
HV+
3
52
FCTLRNF
HV-
4
51
FCTLCDET
HW+
5
50
TKCDET
HW-
6
49
SAO1+
HALL_VC
7
48
SAO1-
SPCNF
8
47
SAO2+
BHLD
9
46
SAO2-
FCTLRNF
TKRNF
FCTLCDET
TKCDET
Regulator
VREG
PRTLIM
PRTFT
PRTT
PRTOUT
Over Current
Protect
ERROUT
SDO
SHV
Level
Shift
54
2
DAC
SDI
FCTLO1+
FCTLO1-
SCLK
Level
Shift
1
HU-
VCC
HU+
PREVCC
Block Diagram
SPI
Pin Configuration (TOP VIEW)
DAC
SLV
FCTLO2+
FCTLO2-
Level
Shift
MUTEB
DAC
SPRNF
10
45
FCTLO1+
FG
11
44
FCTLO1-
W_OUT
12
43
FCTLO2+
V_OUT
13
42
FCTLO2-
U_OUT
14
41
TKO+
SPGND
15
40
TKO-
SLGND
16
39
ACTGND
SLO1+
17
38
LDO+
SLO1-
18
37
LDO-
SLRNF1
SLRNF1
19
36
PRTOUT
SLRNF2
SLO2+
20
35
MUTEB
SLO2-
21
34
PRTLIM
SLRNF2
22
33
VCC
ERROUT
23
32
PRTFT
TKO+
TKO-
LDO-
SAO1+
SAO1SAO2+
SAO2-
PREGND
SCLK
26
29
SHV
SLV
27
28
VREG
HU+
HUHV+
HVHW+
HW-
Matrix
V_OUT
FF
FF
W_OUT
Hall Amp /
Reverse Protect
FG
HALL_VC
Figure 2. Pin configuration
Duty
Control
U_OUT
OSC
ACTGND
30
SLO2-
SPCNF
Current
Detector
SPRNF
SLGND
25
SLO1-
DAC
PRTT
SDI
SLO2+
BHLD
SPGND
31
SLO1+
OSC
LIMIT
PREGND
24
PRE
LOGIC
LIMIT
Current
Detector
Current
Detector
PRE
LOGIC
DAC
DAC
SDO
Level
Shift
LDO+
DAC
Figure 3. Block diagram
Pin Description
Pin
No.
1
HU+
Hall amp. U positive input
Pin
No.
28
2
HU-
Hall amp. U negative input
29
SHV
3
HV+
Hall amp. V positive input
30
PREGND
4
HV-
Hall amp. V negative input
31
PRTT
5
HW+
Hall amp. W positive input
32
PRTFT
HW-
Hall amp. W negative input
33
VCC
34
PRTLIM
Limit setting for actuator protect
Mute input
6
7
Pin Name
Function
HALL_VC Hall bias
8
SPCNF
9
BHLD
10
SPRNF
11
FG
12
13
Pin Name
VREG
Function
Inside power supply for SPI logic
Power supply for SDO output
Pre block ground
Protect time setting for tracking
Protect time setting for focus and tilt
Power supply for pre driver and loading
Spindle driver loop filter
35
MUTEB
Spindle current bottom hold
36
PRTOUT
Spindle power supply and current sense
37
LDO-
Loading driver negative output
FG output
38
LDO+
Loading driver positive output
W_OUT
Spindle driver W output
39
ACTGND
V_OUT
Spindle driver V output
40
TKO-
Tracking driver negative output
14
U_OUT
Spindle driver U output
41
TKO+
Tracking driver positive output
15
SPGND
Spindle power ground
42
FCTLO2-
Focus tilt driver 2 negative output
16
SLGND
Sled power ground
43
FCTLO2+
Focus tilt driver 2 positive output
17
SLO1+
Sled driver 1 positive output
44
FCTLO1-
Focus tilt driver 1 negative output
18
SLO1-
Sled driver 1 negative output
45
FCTLO1+
Focus tilt driver 1 positive output
19
SLRNF1
Sled 1 power supply and current sense
46
SAO2-
Sphere aberration 2 negative output
20
SLO2+
Sled driver 2 positive output
47
SAO2+
Sphere aberration 2 positive output
21
SLO2-
Sled driver 2 negative output
48
SAO1-
Sphere aberration 1 negative output
22
SLRNF2
Sled 2 power supply and current sense
49
SAO1+
Sphere aberration 1 positive output
23
ERROUT
Serial data error output
50
24
SDO
Serial data output
51
FCTLCDET Current detect for focus tilt drive
25
SDI
Serial data input
52
FCTLRNF
Focus tilt power supply and current sense
26
SCLK
Serial clock input
53
TKRNF
Tracking power supply and current sense
27
SLV
Serial slave input
54
PREVCC
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TKCDET
Protect output
Actuator and loading power ground
Current detect for tracking drive
Pre driver power supply
TSZ02201-0G1G0BK00030-1-2
4.Apr.2016 Rev.004
BD8256EFV-M
Absolute Maximum Ratings (Ta = 25°C)
Parameter
Pre Power supply voltage
Power MOS power supply voltage
PWM control / BTL power supply voltage
Serial Output power supply
Input pin voltage 1
Input pin voltage 2
Symbol
Rating
Unit
VVCC
15
V
VSPRNF,VSLRNF1,VSLRNF2
15
V
VPREVCC,VTKRNF,VFCTLRNF
7
V
VSHV
7
V
15
V
7
V
15
V
VIN1
(1)
VIN2
(2)
VOUT1
(3)
Output pin voltage 2
VOUT2
(4)
Power Consumption
Pd
Output pin voltage 1
Operating temperature range
Storage temperature range
Junction temperature
(1)
(2)
(3)
(4)
(5)
7
2.0
V
(5)
W
Topr
-40 to +90
°C
Tstg
-55 to +150
°C
Tjmax
150
°C
BHLD, SPCNF
HU+, HU-, HV+, HV-, HW+, HW-, HALL_VC, PRTFT, PRTT, SLV, SCLK, SDI, TKCDET, FCTLCDET, MUTEB
FG, U_OUT, V_OUT, W_OUT, SLO1+, SLO1-, SLO2+, SLO2-, ERROUT, PRTLIM, PRTOUT, LDO+, LDOSDO, VREG, FCTLO1+, FCTLO1-, FCTLO2+, FCTLO2-, TKO+, TKO-, SAO1+, SAO1-, SAO2+, SAO2Ta=25°C, PCB (70mm×70mm×1.6mm, glass epoxy standard board) mounting.
Derated by 16mW/°C when operating above 25°C
Caution: Operating the IC over the absolute maximum ratings may damage the IC. In addition, it is impossible to predict all destructive situations such as
short-circuit modes, open circuit modes, etc. Therefore, it is important to consider circuit protection measures, like adding a fuse, in case the IC is operated in a
special mode exceeding the absolute maximum ratings.
Recommended Operating Ratings (Ta = -40°C to +90°C)
Parameter
Symbol
Pre /Loading driver power supply voltage
Spindle driver power supply voltage
(6)
(7)
(6)
Typ
Max.
Unit
VVCC
4.5
8
10.5
V
-
VVCC
-
V
VSLRNF1, VSLRNF2
-
VVCC
-
V
VPREVCC
4.5
5
5.5
V
VFCTLRNF, VTKRNF
4.5
5
VPREVCC
V
VSHV
3.0
3.3
3.6
V
(6)
Actuator driver power supply voltage
Serial output power supply
(6)(7)
Min.
VSPRNF
(6)(7)
Sled motor driver power supply voltage
PWM control power supply voltage
(6)
Limits
(6)
Consider power consumption when deciding power supply voltage.
Set the voltage same as VVCC.
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BD8256EFV-M
Electrical Characteristics (Unless otherwise specified, Ta=25°C, V VCC =V SPRNF =V SLRNF1 =V SLRNF2 =8V,
V PREVCC =V TKRNF =V FCTLRNF =5V, V SHV =3.3V, RSPRNF=0.33Ω, RSLRNF=0.56Ω)
Limits
Parameter
Symbol
Min.
Typ
Max.
Circuit Current
PREVCC Quiescent Current
IQ1
18
30
VCC Quiescent Current
IQ2
7
14
PREVCC Standby Current
IST1
3
6
VCC Standby Current
IST2
1
2
Spindle Driver
Hall Bias Voltage
VHB
0.45
0.9
1.35
Input Bias Current
IHIB
0.5
3
Input Level
VHIM
50
Common Mode Input Range
VHICM
1.5
3.8
Input Dead Zone (One Side)
VDZSP
0
10
40
Input-Output Gain
gmSP
0.98
1.24
1.50
Output ON Resistance (Total Sum)
RONSP
1
1.8
Output limit Current
ILIMSP
0.85
1.06
1.27
PWM Frequency
fOSC
100
FG Output Low Level Voltage
VFGL
0.1
0.3
Sled Motor Driver
Input Dead Zone (One Side)
VDZSL
5
15
30
Input-Output Gain
gmSL
0.84
1.10
1.36
Output ON Resistance (Total sum)
RONSL
2.2
3.3
Output Limit Current
ILIMSL
0.79
0.93
1.07
PWM Frequency
fOSC
100
Actuator Driver
Output Offset Voltage
VOFACT
-50
0
50
Output ON Resistance
RONACT
1.5
2.0
Voltage Gain 1
GVACT1
10.5
11.7
12.9
Voltage Gain 2
GVACT2
16.4
17.7
18.9
Loading Driver
Output Offset Voltage
VOFLD
-100
0
100
Output ON Resistance
RONLD
1.5
2.5
Voltage Gain 1
GVLD1
15.2
17.2
19.2
Voltage Gain 2
GVLD2
16.7
18.7
20.7
Actuator Protection Circuit
PRTT/PRTF Default Voltage
VPRTREF
1.00
1.06
1.12
PRTT/PRTF Protect Detection Voltage
VPRTDET
2.77
2.95
3.13
PRTLIM Voltage
VPRTLIM
500
530
560
Detection Input Offset Voltage
VOFDET
-5
0
5
Protect Sign Output
PRTOUT Low Level Output Voltage
VOL1
0.1
0.3
ERROUT Low Level Output Voltage
VOL2
0.1
0.3
Logic Inputs (SDI,SCLK,SLV,MUTEB)
Low Level Input Voltage
VINL
0.5
High Level Voltage
VINH
2.2
High Level Current
IINH
33
66
(SDI,SCLK,MUTEB)
Low Level Current (SLV)
IINL
-60
-30
Function
VCC Drop Mute Voltage
VMVCC
3.4
3.8
4.2
LVDS Output
Difference Movement Output Voltage
VOD
250
950
Offset Voltage
VOC
0.95
1.25
1.55
TSD
(1)
TTSD
150
175
200
TSD Junction Temperature
(1)
THYS
25
TSD Hysteresis Temperature
Unit
Conditions
mA
mA
mA
mA
MUTEB=High
SPI=72h FE, 70h FE
V
μA
mVpp
V
mV
A/V
Ω
A
kHz
V
MUTEB=Low
IHB=10mA
RSPRNF=0.33Ω, RL=2Ω
IL=500mA
RSPRNF=0.33Ω
RL=2Ω
33KΩ pull-up(3.3V)
mV
A/V
Ω
A
kHz
RSLRNF1,2=0.56Ω, RL=8Ω
IL=500mA
RSLRNF1,2=0.56Ω
RL=8Ω
mV
Ω
dB
dB
Low Gain mode, RL=8Ω
IL=500mA
Low Gain mode, RL=8Ω
High Gain mode, RL=8Ω
mV
Ω
dB
dB
Low Gain mode, RL=8Ω
IL=500mA
Low Gain mode, RL=8Ω
High Gain mode, RL=8Ω
V
V
mV
mV
V
V
33kΩ pull-up(3.3V)
33kΩ pull-up(3.3V)
V
V
μA
SDI,SCLK,MUTEB=3.3V
μA
SLV=0V
V
mV
V
RL=100Ω
RL=100Ω
°C
°C
(1) These items are specified by design,not tested during production
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TSZ02201-0G1G0BK00030-1-2
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BD8256EFV-M
Electrical Characteristics (Unless otherwise specified, Ta=-40°C~90°C, V VCC =V SPRNF =V SLRNF1 =V SL RNF2 =8V,
V PREVCC =V TKRNF =V FCTLRNF =5V, V SHV =3.3V, RSPRNF=0.33Ω, RSLRNF=0.56Ω)
Limits
Parameter
Symbol
Min.
Typ
Max.
Circuit Current
PREVCC Quiescent Current
IQ1
18
36
VCC Quiescent Current
IQ2
7
14
PREVCC Standby Current
IST1
3
6
VCC Standby Current
IST2
1
2
Spindle Driver
Hall Bias Voltage
VHB
0.45
0.9
1.35
Input Bias Current
IHIB
0.5
3
Input Level
VHIM
50
Common Mode Input Range
VHICM
1.5
3.8
Input Dead Zone (One Side)
VDZSP
0
10
45
Input-Output Gain
gmSP
0.85
1.24
1.63
Output ON Resistance (Total Sum)
RONSP
1
1.8
Output limit Current
ILIMSP
0.85
1.06
1.27
PWM Frequency
fOSC
100
FG Output Low Level Voltage
VFGL
0.1
0.3
Sled Motor Driver
Input Dead Zone (One Side)
VDZSL
3
15
35
Input-Output Gain
gmSL
0.84
1.10
1.36
Output ON Resistance (Total sum)
RONSL
2.2
3.3
Output Limit Current
ILIMSL
0.79
0.93
1.07
PWM Frequency
fOSC
100
Actuator Driver
Output Offset Voltage
VOFACT
-50
0
50
Output ON Resistance
RONACT
1.5
2.0
Voltage Gain 1
GVACT1
9.4
11.7
13.5
Voltage Gain 2
GVACT2
15.4
17.7
19.5
Loading Driver
Output Offset Voltage
VOFLD
-110
0
110
Output ON Resistance
RONLD
1.5
2.5
Voltage Gain 1
GVLD1
14.1
17.2
19.5
Voltage Gain 2
GVLD2
15.6
18.7
21.0
Actuator Protection Circuit
PRTT/PRTF Default Voltage
VPRTREF
0.98
1.06
1.14
PRTT/PRTF Protect Detection Voltage
VPRTDET
2.65
2.95
3.25
PRTLIM Voltage
VPRTLIM
490
530
570
Detection Input Offset Voltage
VOFDET
-7
0
7
Protect Sign Output
PRTOUT Low Level Output Voltage
VOL1
0.1
0.3
ERROUT Low Level Output Voltage
VOL2
0.1
0.3
Logic Inputs (SDI,SCLK,SLV,MUTEB)
Low Level Input Voltage
VINL
0.5
High Level Voltage
VINH
2.2
High Level Current
IINH
33
75
(SDI,SCLK,MUTEB)
Low Level Current (SLV)
IINL
-75
-30
Function
VCC Drop Mute Voltage
VMVCC
3.4
3.8
4.2
LVDS Output
Difference Movement Output Voltage
VOD
250
950
Offset Voltage
VOC
0.95
1.25
1.55
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Unit
Conditions
mA
mA
mA
mA
MUTEB=High
SPI=72h FE, 70h FE
V
μA
mVpp
V
mV
A/V
Ω
A
kHz
V
MUTEB=Low
IHB=10mA
RSPRNF=0.33Ω, RL=2Ω
IL=500mA
RSPRNF=0.33Ω
RL=2Ω
33KΩ pull-up(3.3V)
mV
A/V
Ω
A
kHz
RSLRNF1,2=0.56Ω, RL=8Ω
IL=500mA
RSLRNF1,2=0.56Ω
RL=8Ω
mV
Ω
dB
dB
Low Gain mode, RL=8Ω
IL=500mA
Low Gain mode, RL=8Ω
High Gain mode, RL=8Ω
mV
Ω
dB
dB
Low Gain mode, RL=8Ω
IL=500mA
Low Gain mode, RL=8Ω
High Gain mode, RL=8Ω
V
V
mV
mV
V
V
33kΩ pull-up(3.3V)
33kΩ pull-up(3.3V)
V
V
μA
SDI,SCLK,MUTEB=3.3V
μA
SLV=0V
V
mV
V
RL=100Ω
RL=100Ω
TSZ02201-0G1G0BK00030-1-2
4.Apr.2016 Rev.004
BD8256EFV-M
14
20
13
19
Gain : GVACT2 (dB)
Gain : GVACT1 (dB)
Typical Performance Curves
12
11
PREVCC=5V
GAIN_SELFCTL=0
DIFF_FCTL=1
10
18
17
PREVCC=5V
GAIN_SELFCTL=1
DIFF_FCTL=1
16
9
15
-50
-25
0
25
50
Temparature (ºC)
75
100
-50
14
20
13
19
12
11
PREVCC=5V
GAIN_SELFCTL=0
DIFF_FCTL=1
10
0
25
50
Temparature (ºC)
75
100
FCTL1 Voltage gain 2 (High gain mode)
Gain : GVACT2 (dB)
Gain : GVACT1 (dB)
FCTL1 Voltage gain 1 (Low gain mode)
-25
18
17
PREVCC=5V
GAIN_SELFCTL=1
DIFF_FCTL=1
16
9
15
-50
-25
0
25
50
Temparature (ºC)
75
100
FCTL2 Voltage gain 1 (Low gain mode)
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-50
-25
0
25
50
Temparature (ºC)
75
100
FCTL2 Voltage gain 2 (High gain mode)
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BD8256EFV-M
14
20
13
19
Gain : GVACT2 (dB)
Gain : GVACT1 (dB)
Typical Performance Curves - continued
12
11
PREVCC=5V
GAIN_SELTK=0
10
18
17
PREVCC=5V
GAIN_SELTK=1
16
9
15
-50
-25
0
25
50
Temparature (ºC)
75
100
-50
TK Voltage gain 1 (Low gain mode)
-25
0
25
50
Temparature (ºC)
75
100
75
100
TK Voltage gain 2 (High gain mode)
22
20
21
19
Gain : GVLD2 (dB)
Gain : GVLD1 (dB)
20
18
17
16
VCC=8V
GAIN_SELLD=0
19
18
VCC=8V
GAIN_SELLD=1
17
15
16
14
15
-50
-25
0
25
50
Temparature (ºC)
75
100
LD Voltage gain 1 (Low gain mode)
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-50
-25
0
25
50
Temparature (ºC)
LD Voltage gain 2 (High gain mode)
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BD8256EFV-M
Description of Blocks
■ Serial Peripheral Interface (SPI)
16 bit serial interfaces (SLV, SCLK, SDI, SDO) are provided to perform setting of operations and output levels. SPI
communication is performed while SLV terminal is in Low. SDI data are sent to internal shift register at the rising edge of
SCLK terminal. Shift register data are loaded into 12 bit internal shift register at the rising edge of SLV terminal according to
the address map. Readout operation is performed when readout bit is set to 1. Then state is read out at the falling edge of
SCLK terminal and output to SDO terminal.
◆ Input-Output Timing
Figure 4 shows write/read timing of the serial ports.
Minimum timing of each item is as shown in the table below. In order to prevent increase in delay of SPI input/output timing,
wiring between SLV/SCLK/SDI/SDO and the microcomputer should be as short as possible to minimize the wiring
capacitance.
Symbol
A
B
C
D
E
F
G
H
I
J
K
Item
SDI setup time *
SDI hold time *
Setup SLV to SCLK rising edge *
SCLK high pulse width *
SCLK low pulse width *
Setup SCLK rising edge to SLV *
SLV pulse width *
SDO delay time *
SDO hold time *
SDO OFF time *
SCLK frequency
Min
9
9
9
10
10
9
15
2
-
Typ
-
Max
10
20
35
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
* Guaranteed Design Items
SLV
C
D
F
E
G
SCLK
A
SDI
B
C3
C2
D0
H
D7
SDO
J
H
DN
DN-1
D0
I
Figure 4. SPI Input Timing
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◆ DAC Register
1. Input / Output Sequence
Enter the register address in the SDI input on the first 4 bits and data for a specific DAC voltage in the next 12 bits.
When specified as REG=02h (address for focus), REG 77h data is output to the SDO.
When specified as REG≠02h (address for non-focus), SDO becomes Hi-Z.
SLV
SCLK
SDI
SDO
C3
C2
C1
C0
DB
DA
D9
D8
Hi-Z
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
D2
D1
D0
Figure 5. 12bit Write / 8bit Read Sequence (when specified as REG=02h)
SLV
SCLK
SDI
SDO
C3
C2
C1
C0
DB
DA
D9
D8
D7
D6
D5
D4
D3
Hi-Z
Figure 6. 12bit Write Sequence (when specified as REG≠02h, C3, C2≠1, 1)
2. Address Map (hereinafter register address is referred to as REG)
DAC Register Address Map
REG
NAME
R/W
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
N/A
DFCTL1
DFCTL2
DTK
DSL1
DSL2
DSA1
DSA2
DSP
DLD
N/A
N/A
W
W
W
W
W
W
W
W
W
-
11
11
11
11
11
11
11
11
11
-
10
10
10
10
10
10
10
-
9
9
9
9
9
9
9
-
8
8
8
8
8
8
8
-
7
7
7
7
7
7
7
-
6
6
6
6
6
6
6
-
5
5
5
5
5
5
5
-
4
4
4
4
4
4
4
-
3
3
3
3
3
3
3
-
2
2
2
2
2
2
2
-
1
1
1
1*
1*
1
1
-
0
0
0
0*
0*
0
0
-
Reset
**
B
B
B
B
B
B
B
B
B
-
Default : 0
* : fixed at 0
** : refer to P.15 about reset
- : not affected even when data is written
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◆ Control register
1. Input / Output Sequence
When writing data to the control register, enter the register address in the first 7 bits of the SDI input, then set the 1bit R/W
to 0 and enter the data of each setting in the last 8 bits. SDO is Hi-Z when R/W=0.
When reading data from the control register, enter the register address in the first 7 bits of the SDI input, then set the 1 bit
R/W to 1. The last 8 bits are ignored. When R/W=1, 8-bit data of specified address is output to the SDO.
SLV
SCLK
SDI
A6
A5
A4
A3
A2
A1
A0
R/W
D7
D6
D5
D4
D3
D2
D1
D0
D2
D1
D0
Hi-Z
SDO
Figure 7. Control Register 8 bit Write Sequence (A6, A5=1,1, R/W= 0)
SLV
SCLK
SDI
A6
A5
A4
A3
A2
A1
A0
R/W
Hi-Z
SDO
D7
D6
D5
D4
D3
Figure 8. Control Register 8 bit Read Sequence (A6, A5=1,1, R/W= 1)
2. Address Map
Control Register Address Map
REG
NAME
R/W
D7
D6
D5
D4
D3
D2
D1
D0
70h
OUTPUT
_EN1
R/W
FCTL1
_OUTEN
FCTL2
_OUTEN
TK
_OUTEN
SL
_OUTEN
SA
_OUTEN
SP
_OUTEN
LD
_OUTEN
N/A
71h
-
-
-
-
-
-
-
-
-
-
72h
POWER
_SAVE1
R/W
FCTL1
_PSB
FCTL2
_PSB
TK
_PSB
SL
_PSB
SA
_PSB
SP
_PSB
LD
_PSB
N/A
73h
-
-
-
-
-
-
-
-
-
-
74h
DRIVER
_SET
R/W
N/A
W
RST
_DAC
DIFF
_FCTL
RST
_OCP
LD
_BRAKE
RST
_SHORT
N/A
RESET
GAIN
_SELTK
RST
_PKTSTOP
PKTSTOP
_TIME0
SHORT
_LD
GAIN
_SELLD
75h
SP
_BRAKE
RST
_CTLREG
N/A
N/A
76h
77h
PKT
_TIME
STATUS
_FLAG1
R/W
N/A
N/A
R
ALL
_ERR
OCP
_FCTL
GAIN
_SELFCTL
RST
_PKTERR
PKTSTOP
_TIME1
OCP
_TK
N/A
N/A
N/A
N/A
TSD
PKT
_ERR
PKT
_STOP
UVLO
_VCC
78h
TEST0
R/W
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
79h
TEST1
R/W
Reserved
Reserved
Reserved
Reserved
Reserved
N/A
N/A
N/A
7Ah
TEST2
R/W
N/A
N/A
Reserved
N/A
Reserved
Reserved
Reserved
N/A
7Bh
RST
_CHECK
R/W
RST
_CHECKA
RST
_CHECKB
N/A
N/A
N/A
N/A
N/A
N/A
7Ch
-
-
-
-
-
-
-
-
-
-
7Dh
-
-
-
-
-
-
-
-
-
-
7Eh
-
-
-
-
-
-
-
-
-
-
7Fh
-
-
-
-
-
-
-
-
-
-
Write access to "Reserved" bits should be made by "0" input.
Read access to "N/A" bits will return "0".
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3. Details of Control Registers
Functions of each register are as shown below.
・ REG 70h OUTPUT_EN1 (Read / Write)
Each driver output settings (Hi-Z/Active) can be changed in REG 70h.
Bit
Name
Default
Function
Set "0"
Set "1"
Reset
7
FCTL1_OUTEN
0
FCTL1 Output Enable
Disable
Enable
A
6
FCTL2_OUTEN
0
FCTL2 Output Enable
Disable
Enable
A
5
TK_OUTEN
0
TK Output Enable
Disable
Enable
A
4
SL_OUTEN
0
SL1,SL2 Output Enable
Disable
Enable
A
3
SA_OUTEN
0
SA1,SA2 Output Enable
Disable
Enable
A
2
SP_OUTEN
0
SP Output Enable
Disable
Enable
A
1
LD_OUTEN
0
LD Output Enable
Disable
Enable
A
0
N/A
0
-
-
-
-
・ REG 71h
-
Bit
Name
Default
Function
Set "0"
Set "1"
Reset
7
-
-
-
-
-
-
6
-
-
-
-
-
-
5
-
-
-
-
-
-
4
-
-
-
-
-
-
3
-
-
-
-
-
-
2
-
-
-
-
-
-
1
-
-
-
-
-
-
0
-
-
-
-
-
-
・ REG 72h POWER_SAVE1 (Read / Write)
Power save mode settings for each block can be set in REG 72h.
Power save mode makes the output Hi-Z and turns OFF the internal circuit to reduce the current consumption.
Bit
Name
Default
Function
Set "0"
Set "1"
Reset
7
FCTL1_PSB
0
FCTL1 Block Power Save
Enable
Disable
A
6
FCTL2_PSB
0
FCTL2 Block Power Save
Enable
Disable
A
5
TK_PSB
0
TK Block Power Save
Enable
Disable
A
4
SL_PSB
0
SL1,SL2 Block Power Save
Enable
Disable
A
3
SA_PSB
0
SA1,SA2 Block Power Save
Enable
Disable
A
2
SP_PSB
0
SP Block Power Save
Enable
Disable
A
1
LD_PSB
0
LD Block Power Save
Enable
Disable
A
0
N/A
0
-
-
-
-
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・ REG 73h
-
Bit
Name
Default
Function
Set "0"
Set "1"
Reset
7
-
-
-
-
-
-
6
-
-
-
-
-
-
5
-
-
-
-
-
-
4
-
-
-
-
-
-
3
-
-
-
-
-
-
2
-
-
-
-
-
-
1
-
-
-
-
-
-
0
-
-
-
-
-
-
・ REG 74h DRIVER_SET (Read / Write)
Operation mode settings of the driver can be changed in REG 74h.
Bit
Name
Default
Function
Set "0"
Set "1"
Reset
7
N/A
0
-
-
-
-
6
SP_BRAKE
0
SP Brake Mode
Short Brake
Reverse Brake
A
5
GAIN_SELFCTL
0
Gain Select FCTL
Low Gain
High Gain
A
4
GAIN_SELTK
0
Gain Select TK
Low Gain
High Gain
A
3
DIFF_FCTL
0
Differential FCTL Control Mode
Differential Control
Independent Control
A
A
2
LD_BRAKE
0
LD Brake Mode
LD Output Active
LD Output
Short Brake
1
GAIN_SELLD
0
Gain Select LD
Low Gain
High Gain
A
0
N/A
0
-
-
-
-
Short brake/reverse brake can be selected as spindle brake mode.
Low/high gain mode of the focus/tilt driver's gain can be selected.
Low/high gain mode of the tracking driver's gain can be selected.
Differential/independent drive of the focus and tilt driver can be selected. See page 18 for more information.
Short brake mode (both positive & negative output low) can be activated when loading output is "Active".
Low/high gain mode of the loading driver's gain can be switched.
・ REG 75h RESET (Write)
Resister settings and latched error flag can be reset in REG 75h.
Bit
7
6
Name
RST_DAC
RST_CTLREG
Default
Function
Set "0"
Set "1"
Reset
0
DAC Reset
Normal
Reset
E
0
Control Register Reset
Normal
Reset
E
5
RST_PKTERR
0
Packet Bit Counts Error Reset
Normal
Reset
E
4
RST_PKTSTOP
0
No Packet Input Error Reset
Normal
Reset
E
3
RST_OCP
0
Actuator Overcurrent Protection Latch Off Reset
Normal
Reset
E
Normal
Reset
E
2
RST_SHORT
0
LD Supply/Ground-Fault Protection Latch Off Reset
1
N/A
0
-
-
-
-
0
N/A
0
-
-
-
-
Reset all DAC register value to 0.
Reset all control register value to default.
Reset packet bit counts error flag register value to 0.
Reset no packet input error flag register value to 0.
Reset actuator overcurrent protection flag register value to 0.
Reset loading supply/ground-fault protection flag register value to 0.
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・ REG 76h PKT_TIME (Read / Write)
In REG 76h, you can specify or disable wait time until error operation in case of no SPI input.
Bit
Name
Default
Function
Set "0"
Set "1"
Reset
7
N/A
0
-
-
-
-
6
N/A
0
-
-
-
5
PKTSTOP_TIME1
0
4
PKTSTOP_TIME0
0
SPI Packet Watchdog Timer
Operation Time Selection
3
N/A
0
-
-
-
-
2
N/A
0
-
-
-
-
1
N/A
0
-
-
-
-
0
N/A
0
-
-
-
-
(00)=Disabled, (01)=1ms,
(10)=100μs, (11)=30μs
A
A
・ REG 77h STATUS_FLAG (Read)
REG 77h outputs each protection state flag
Bit
Name
Default
Function
Set "0"
Set "1"
Reset
7
ALL_ERR
0
All Error Flags
Normal
Abnormal
*
6
OCP_FCTL
0
Normal
Abnormal
C
5
OCP_TK
0
Normal
Abnormal
C
4
SHORT_LD
0
Normal
Abnormal
C
3
TSD
0
TSD Detection Flag (All Output Hi-Z)
Normal
Abnormal
F
Normal
Abnormal
C
FCTL Overcurrent Detection Flag
(FCTL1, 2, TK Output Hi-Z)
TK Overcurrent Detection Flag
(FCTL1, 2, TK Output Hi-Z)
LD Supply/Ground-Fault Protection
Detection Flag (LD Output Hi-Z)
2
PKT_ERR
0
Number of Packet Bits Error Flag
(Flag Only)
1
PKT_STOP
0
Packet Watchdog Timer (All Output Hi-Z)
Normal
Abnormal
C
0
UVLO_VCC
0
VCC Low Voltage Fault Flag (All Output Hi-Z)
Normal
Abnormal
D
*How to reset: ALL_ERR outputs all the error flags (OCP_FCTL, OCP_TK, SHORT_LD, TSD, PKT_ERR,
PKT_STOP, UVLO_VCC). Therefore, reset conditions are depending on each flags.
・ REG 78h
TEST0 (Read / Write)
Bit
Name
Default
Function
Set "0"
Set "1"
Reset
7
Reserved
0
-
-
-
D
6
Reserved
0
-
-
-
D
5
Reserved
0
-
-
-
D
4
Reserved
0
-
-
-
D
3
Reserved
0
-
-
-
D
2
Reserved
0
-
-
-
D
1
Reserved
0
-
-
-
D
0
Reserved
0
-
-
-
D
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・ REG 79h
TEST1 (Read / Write)
Bit
Name
Default
Function
Set "0"
Set "1"
Reset
7
Reserved
0
-
-
-
F
6
Reserved
0
-
-
-
F
5
Reserved
0
-
-
-
F
4
Reserved
0
-
-
-
F
3
Reserved
0
-
-
-
F
2
N/A
0
-
-
-
-
1
N/A
0
-
-
-
-
0
N/A
0
-
-
-
-
・ REG 7Ah
TEST2 (Read / Write)
Bit
Name
Default
Function
Set "0"
Set "1"
Reset
7
N/A
0
-
-
-
-
6
N/A
0
-
-
-
-
5
Reserved
0
-
-
-
F
4
N/A
0
-
-
-
-
3
Reserved
0
-
-
-
F
2
Reserved
0
-
-
-
F
1
Reserved
0
-
-
-
F
0
N/A
0
-
-
-
-
・ REG 7Bh RST_CHECK (Read / Write)
REG 7Bh is the flag confirming reset completion of registers listed in page 15.
Bit
Name
Default
Function
Set "0"
Set "1"
Reset
7
RST_CHECKA
0
Reset A Completion Check Flag
0
1
A
6
RST_CHECKB
0
Reset B Completion Check Flag
0
1
B
5
N/A
0
-
-
-
-
4
N/A
0
-
-
-
-
3
N/A
0
-
-
-
-
2
N/A
0
-
-
-
-
1
N/A
0
-
-
-
-
0
N/A
0
-
-
-
-
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◆ Register Reset Operations
Type "A" ： MODE Setting Bit (REG 70h, 72h, 74h, 76h, 7Bh[7])
Reset Conditions：
VCC < 3.8V
or PREVCC < 3.8V
or VREG < 2.0V
or MUTEB < 0.5V
or RST_CTLREG(75h[6]) = 1
Type "B" ： DAC Setting Bit (REG 01h~09h, 7Bh[6])
Reset Conditions：
VCC < 3.8V
or PREVCC < 3.8V
or VREG < 2.0V
or MUTEB < 0.5V
or RST_DAC(75h[7]) = 1
Type "C" ：Operational State (Latched) Output Bit (REG 77h[1,2,4,5,6])
Reset Conditions：
VCC < 3.8V
or PREVCC < 3.8V
or VREG < 2.0V
or MUTEB < 0.5V
or RST_CTLREG (75h[6]) = 1
or RST_PKTERR (75h[5]) = 1 (for PKT_ERR(77h[2]))
or RST_PKTSTOP (75h[4]) = 1 (for PKT_STOP(77h[1]))
or RST_OCP (75h[3]) = 1 (for OCPFCTL(77h[6]) and OCPTK(77h[5]))
or RST_SHORT (75h[2]) = 1 (for SHORT_LD(77h[4]))
Type "D" ：Operational State (Continuously Updated) Output Bit 1 (REG 77h[0])
Reset Conditions：
PREVCC < 2.0V
or VREG < 1.2V
or MUTEB < 0.5V
Type "E" ：Reset Setting Bit (REG 75h)
Reset Conditions：
Self-reset (If set to 1, automatically returns to "0" following reset operation)
Type "F" ：Operational State (Continuously Updated) Output Bit 2 (REG 77h[3])
Reset Conditions：
VCC < 3.8V
or PREVCC < 3.8V
or VREG < 2.0V
or MUTEB < 0.5V
Reset Operations
Control REG
DAC REG
Reset condition
01h ~ 09h 70h
VCC < 3.8V
PREVCC < 2.0V
Hard
PREVCC < 3.8V
MUTEB < 0.5V
RST_SHORT 75h[2] = 1
RST_OCP
75h[3] = 1
RST_PKTSTOP 75h[4] = 1
Soft
RST_PKTERR 75h[5] = 1
RST_CTLREG 75h[6] = 1
RST_DAC
75h[7] = 1
Self reset
○
○
○
○
○
○
○
○
○
72h
74h
○
○
○
○
○
○
○
○
○
75h
76h
○
○
○
○
○
○
○
D7
○
○
○
○
*1
*1
*1
*1
*1
*1
D6
○
○
○
○
D5
○
○
○
○
○
○
77h
D4 D3
○ ○
○ ○
○ ○
○ ○
○
D2
○
○
○
○
D1
○
○
○
○
D0
○
○
7Bh
D7 D6
○ ○
○ ○
○ ○
○ ○
○
○
○
○
○
*1 Reset conditions of REG 77h[7] are dependent upon REG 77h[6]-77h[0].
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■ SPI Input / Output Terminal Processing
Provided with input terminals SLV, SCLK and SDI, and output terminal SDO, as serial interfaces. Input terminals SLV, SCLK
and SDI have built-in 100kΩ (Typ) pull-up/pull-down resistor. Output terminal SDO is able to output the voltage set at SHV
as high level voltage in 3-state CMOS output.
100kΩ(Typ)
VREG
SHV
SLV
100kΩ
(Typ)
SCLK
SDO
100kΩ
(Typ)
SDI
Figure 9. SPI Input / Output Terminal Processing
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■ DAC and Gain Setting
◆ Actuator (FCTL1, FCTL2, TK)
Suppose that voltage difference between positive/negative outputs is VOUT, VOUT can be expressed as follows.
VOUT = GVACT ×VDAC
Here, GVACT value will be different as below depending upon gain mode settings.
Low Gain Mode (REG 74h[5] GAIN_SELFCTL, REG74h[4] GAIN_SELTK = 0 (Default))
GVACT1 = 3.85 times (11.7dB)
High Gain Mode (GAIN_SELFCTL, GAIN_SELTK = 1)
GVACT2 = 7.67 times (17.7dB)
VDAC, the DAC output voltage, can be obtained from DAC register settings through the following equation.
MSB=0:
1
2
3
11
VDAC = 1.0×(bit[10]×0.5 +bit[9]×0.5 +bit[8]×0.5 +…+bit[0]×0.5 )
MSB=1::
1
2
3
11
11
VDAC = (-1.0)×(^bit[10]×0.5 +^bit[9]×0.5 +^bit[8]×0.5 +…+^bit[0]×0.5 +0.5 )
DAC format (DFCTL1, DFCTL2, DTK)
REG
01h(DFCTL1),
02h(DFCTL2),
03h(DTK)
MSB
Digital input (BIN) LSB
Hex
Dec
VDAC [V]
VOUT [V]*
1000_0000_0000
800h
-2048
-0.9995
-3.848
1000_0000_0001
801h
-2047
-0.9995
-3.848
1000_0000_0010
802h
-2046
-0.9990
-3.846
1111_1111_1111
FFFh
-1
-0.0005
-0.002
0000_0000_0000
000h
0
0
0.000
0000_0000_0001
001h
+1
+0.0005
+0.002
0111_1111_1110
7FEh
+2046
+0.9990
+3.846
0111_1111_1111
7FFh
+2047
+0.9995
+3.848
* In low gain mode setting. Output voltage saturation is not taken into account in the table.
VOUT [V]
VDAC [V]
+3.848
+0.9995
800h
0
7FFh
-3.848
DAC code
-0.9995
Figure 10. DAC Setting vs. VDAC/VOUT (in low gain mode)
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◆ FCTL 1, FCTL 2 Differential Drive Mode
If you set REG 74h[3] DIFF_FCTL to 0, FCTL1 and FCTL2 turn into differential drive mode. In this mode, 12 bit data to be
input into DAC of FCTL1 and FCTL2 will be the values obtained by the following equations. DAC FCTL1, 2 shows 12-bit data to
be input into respective DACs. Note that the DAC output voltage V DAC, gain GVACT and output voltage VOUT are to be in
accordance with page 17.
DACFCTL1 = DFCTL2 + DFCTL1
DACFCTL2 = DFCTL2 – DFCTL1
Operation images during the differential drive mode are as shown below.
FCTL1, 2 Differential Operation Images when DIFF_FCTL=0
VOUT
DFCTL1 > 0x000
If DFCTL2=100h and
DFCTL2=100h,
DFCTL1=080h
DFCTL1=080hの場合
DFCTL2+DFCTL1 : 180h
DFCTL2-DFCTL1 : 080h
A
B
FCTL1
0
DFCTL2 Code
DFCTL1 = 0x000
VOUT
800h
7FFh
FCTL2
A : +FCTL1
B : -FCTL1
0
DFCTL2 Code
7FFh
DFCTL1 < 0x000
VOUT
800h
FCTL1
FCTL2
If DFCTL2=100h and
DFCTL2=100h,
DFCTL1=F80h
DFCTL1=F80hの場合
DFCTL2+DFCTL1 : 080h
DFCTL2-DFCTL1 : 180h
B
A
FCTL2
0
DFCTL2 Code
800h
7FFh
FCTL1
A : +FCTL1
B : -FCTL1
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◆Loading (LD)
Suppose that voltage difference between positive/negative outputs is V OUT, VOUT can be expressed as follows.
VOUT = GVLD ×VDAC
Here, GVLD value will be different as below depending upon gain mode settings.
Low Gain Mode (REG 74h[1] GAIN_SELLD = 0 (Default))
GVLD1 = 7.24 times (17.2dB)
High Gain Mode (GAIN_SELLD =1)
GVLD2 = 8.51 times (18.7dB)
VDAC, the DAC output voltage, can be obtained from DAC register settings through the following equation.
MSB=0:
1
2
3
11
VDAC = 1.0×(bit[10]×0.5 +bit[9]×0.5 +bit[8]×0.5 +…+bit[0]×0.5 )
MSB=1 :
1
2
3
11
11
VDAC = (-1.0)×(^bit[10]×0.5 +^bit[9]×0.5 +^bit[8]×0.5 +…+^bit[0]×0.5 +0.5 )
DAC format (DLD)
REG
09h(DLD)
MSB
Digital input (BIN) LSB
Hex
Dec
VDAC [V]
VOUT [V]*
1000_0000_0000
800h
-2048
-0.9995
-7.236
1000_0000_0001
801h
-2047
-0.9995
-7.236
1000_0000_0010
802h
-2046
-0.9990
-7.233
1111_1111_1111
FFFh
-1
-0.0005
-0.004
0000_0000_0000
000h
0
0
0.000
0000_0000_0001
001h
+1
+0.0005
+0.004
0111_1111_1110
7FEh
+2046
+0.9990
+7.233
0111_1111_1111
7FFh
+2047
+0.9995
+7.236
* In low gain mode setting. Output voltage saturation is not taken into account in the table.
VOUT [V]
VDAC [V]
+7.236
+0.9995
800h
0
7FFh
-7.236
DAC code
-0.9995
Figure 11. DAC Setting vs. VDAC/VOUT (in low gain mode)
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◆ Sled (SL1, SL2)
Suppose that IO PEAK represents peak output current, IO PEAK can be expressed in the following ways.
IO PEAK = 0
IO PEAK = gmSL × | VDAC |
IO PEAK = ILIMSL
( | VDAC | < VDZSL )
( gmSL × | VDAC | < ILIMSL )
( gmSL × | VDAC | > ILIMSL )
Where VDZSL is input deadzone (single-sided) of 15mV (Typ). The gmSL is output/input gain and ILIMSL is output limit current,
and they can be obtained respectively as follows.
gmSL = 0.616 / RSLRNF [A/V]
ILIMSL = 0.52 / RSLRNF [A]
VDAC, the DAC output voltage, can be obtained from DAC register settings through the following equation.
MSB=0
1
2
3
9
VDAC = 1.0×(bit[10]×0.5 +bit[9]×0.5 +bit[8]×0.5 +…+bit[2]×0.5 )
MSB=1
1
2
3
9
9
VDAC = (-1.0) × (^bit[10]×0.5 +^bit[9]×0.5 +^bit[8]×0.5 +…+^bit[2]×0.5 +0.5 )
DAC format (DSL1, DSL2)
REG
MSB
Digital input (BIN)
LSB
Hex
Dec
VDAC [V]
IO PEAK [A]*
1000_0000_0000
800h
-2048
-0.9980
-1.098
1000_0000_0100
804h
-2044
-0.9980
-1.098
1111_1110_0000
FE0h
-32
-0.0156
-0.017
1111_1110_0100
FE4h
-28
-0.0137
0
1111_1111_1100
FFCh
-4
0.0020
0
04h(DSL1),
0000_0000_0000
000h
0
0
0
05h(DSL2)
0000_0000_0100
004h
+4
+0.0020
0
0000_0001_1100
01Ch
+28
+0.0137
0
0000_0010_0000
020h
+32
+0.0156
+0.017
0111_1111_1000
7F8h
+2040
+0.9961
+1.096
0111_1111_1100
7FCh
+2044
+0.9980
+1.098
*Output voltage saturation and limit current setting are not taken into account in the table. Condition:RSLRNF=0.56Ω
IO PEAK [A]
VDAC [V]
+1.098
+0.998
+0.93
=ILIMSL(Limit Current)
1.10 A/V
=gmSL(Input-output Gain)
800h
FE4h
0 01Ch
7FCh
DAC code
+/- 15mV
=VDZSL(Input Deadzone)
-0.93
-1.098
-0.998
Figure 12. IO PEAK Characteristics (When set as RSLRNF=0.56 Ω).
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◆ Spindle (SP)
Suppose that IO PEAK represents peak output current, IO PEAK can be expressed in the following ways.
IO PEAK = 0
IO PEAK = gmSP × | VDAC |
IO PEAK = ILIMSP
( | VDAC | < VDZSP )
( gmSP × | VDAC | < ILIMSP )
( gmSP × | VDAC | > ILIMSP )
Where VDZSP is input deadzone (single-sided) of 10mV (Typ). The gmSP is output/input gain and ILIMSP is output limit current,
and they can be obtained respectively as follows.
gmSP = 0.409 / RSPRNF [A/V]
ILIMSP = 0.35 / RSPRNF [A]
VDAC, the DAC output voltage, can be obtained from DAC register settings through the following equation.
MSB=0 :
1
2
3
11
VDAC = 1.0×(bit[10]×0.5 +bit[9]×0.5 +bit[8]×0.5 +…+bit[0]×0.5 )
MSB=1 :
1
2
3
11
11
VDAC = (-1.0)×(^bit[10]×0.5 +^bit[9]×0.5 +^bit[8]×0.5 +…+^bit[0]×0.5 +0.5 )
DAC format (DSP)
REG
MSB
Digital input (BIN) LSB
Hex
Dec
VDAC [V]
IO PEAK [A]※
1000_0000_0000
800h
-2048
-0.9995
-1.239
1000_0000_0001
801h
-2047
-0.9995
-1.239
1111_1110_1011
FEBh
-21
-0.0103
-0.013
1111_1110_1100
FECh
-20
-0.0098
0
1111_1111_1111
FFFh
-1
-0.0005
0
08h(DSP)
0000_0000_0000
000h
0
0
0
0000_0000_0001
001h
+1
+0.0005
0
0000_0001_0100
014h
+20
+0.0098
0
0000_0001_0101
015h
+21
+0.0103
+0.013
0111_1111_1110
7FEh
+2046
+0.9990
+1.238
0111_1111_1111
7FFh
+2047
+0.9995
+1.239
*Output voltage saturation and limit current setting are not taken into account in the table. Condition:RSPRNF=0.33Ω
IO PEAK [A]
VDAC [V]
+1.239
+1.06
=ILIMSP(Limit Current)
+0.9995
1.24 A/V
=gmSP(Input-output Gain)
800h
FECh
0 014h
7FFh
DAC code
+/- 10mV
=VDZSP(Input Deadzone)
-1.06
-1.239
-0.9995
Figure 13. IO PEAK Characteristics (When set as RSPRNF=0.33 Ω).
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■ Description of Driver Operations
◆ LVDS for Spherical Aberration Driver (SA1, SA2)
LVDS for Spherical Aberration Driver delivers output corresponding to data stored in DSA1 and DSA2, in accordance with
the table below.
SAO1+ and SAO1- correspond to DSA1, while SAO2+ and SAO2- to DSA2, and they can be controlled independently.
Recommended operation frequency of each output is 10 kHz or less.
DAC format (DSA1, DSA2)
REG
MSB
06h(DSA1),
07h(DSA2)
DSA1
Digital input (BIN) LSB
0 - - -_- - - -_- - - 1 - - -_- - - -_- - - -
0
Hex
000h
800h
Dec
0
-2048
1
SAO+
L
H
SAOH
L
0
1
SAO1-
SAO1+
VOD = |V(SAO1+)-V(SAO1-)|
VOC= (V(SAO1+)+V(SAO1-))/2
0V(GND)
DSA2
0
1
0
SAO2-
SAO2+
VOD = |V(SAO2+)-V(SAO2-)|
VOC= (V(SAO2+)+V(SAO2-))/2
0V(GND)
Figure 14. Timing Chart of LVDS for Spherical Aberration Driver
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◆ Sled Motor Driver
VCC
AMP
COMP
SLRNF1,2
DAC
LIMIT
PWM
Clock
OSC
M
SLO1+,
SLO2+
SLO1-,
SLO2-
PRE
LOGIC
Figure 15. Sled motor driver block
State 1
State 2
VCC
VCC
IO
SLRNF1
ON
SLRNF1
reset
OFF
SLO1+
ON
ON
M
M
SLO1+
SLO1-
OFF
ON
SLO1-
OFF
set
OFF
Figure 16. Current Paths in Set [State 1] and Reset [State 2]
PWM
Clock
Current value
proportional to
driver input, or
limit current
value
Motor Current
set
State 1
reset
State 2
set
State 1
reset
State 2
set
State 1
reset
State 2
Figure 17. Sled Motor Driver Operation Timing Chart
Set [State1] : Output turned ON at the rise of PWM clock --> Load current supplied from VCC.
Reset [State2] : Output turned OFF when load current increases to reach current value proportional to input or limit
current value --> Load current regenerated by L component of the motor through the path shown in State
2 diagram.
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◆ Spindle Driver
12000
12000
10000
10000
Speed of Rotation [rpm]
Speed of Rotation [rpm]
1. Spindle Driver Input-Output Characteristics
Figure 18 shows input-output characteristics of the average current detection control and the peak current detection control.
This IC controls output by detecting peak current. Linearity of the input/output characteristics is improved compared with the
one in the average current detection method.
8000
6000
4000
2000
0
8000
6000
4000
2000
0
0
0.1
0.2
0.3
0.4
Input voltage [V]
0.5
0.6
0
(a) Peak Current Control Method (BD8256EFV-M)
0.1
0.2
0.3
Input voltage [V]
0.4
0.5
0.6
(b) Average Current Control Method
Figure 18. Spindle Driver Input-Output Characteristics
Difference in input/output characteristics due to control method can be explained as below.
Motor coil comprises not only pure inductance but also impedance component. Suppose that V O represents peak value of
output pulse, IO, current which flows into the motor when output pulse is turned on, can be expressed in the following ways.
VO,IO
R
IO
VO
VO IO ( t ) R L
IO
VO
L
dIO ( t )
dt
R
IO
t
VO
(1 e L )
R
t
Figure 19. Current Waveform Including Impedance Component
You can see from the above equation that motor current Io follows a curve of natural logarithm. If you try to express this as
motor current characteristics as opposed to input voltage controlled by the respective methods, you will get Figure 20.
Spindle motor speed is proportional to motor current. In case of PWM driver, motor current is roughly equivalent to peak
current because it includes regenerative current. In the peak current control, therefore, motor current (rotation speed)
becomes proportional to input voltage.
In contrast, in the average current control, average value of supply current (integral of supply current) becomes proportional
to input voltage. So motor current (rotation speed) as opposed to input voltage roughly follows a curve of natural logarithm
(Figure 20. (b)). And therefore, you get higher gain in low speed range.
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Vo,Io
Vo
Vo,Io
Vo
Io
Io
Constant
increase in
(integral of)
current area
Constant
increase in
peak current
t
t
(a) Peak Current Control
(b) Average Current Control
Figure 20. Input Voltage vs. Motor Current
2. Current Limit Operation.
Figure 21 shows the operation timing chart.
In this IC, flip-flop is activated based on a clock signal generated by the built-in triangular wave generator to generate PWM
pulse. The spindle driver starts operation at the rising edge of internal clock. Short brake mode is activated if peak current
defined by limit current or gain is detected, and no output pulse is delivered until next clock input. Both during limit current
detection and usual peak current detection, it operates at PWM oscillating frequency generated by the same internal clock.
VCC
Voltage, Current
SPRNF
Dotted line：BHLD(No Capa case)
BHLD
charge
charge
charge
SPCNF
Peak current detection by Limit current or gain.
IO PEAK (Peak Load Current)
IO (Load Current)
Internal Clock
(100kHz)
Internal Clock Rise
Output State
Active
Short
brake
Active
Short
brake
Active
Short
brake
Active
Time
Figure 21. Spindle Driver Operation Timing Chart
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3. Role of Capacitors of BHLD and SPCNF Terminals
Figure 22 shows a block diagram of the spindle driver.
In this IC, peak current control method is realized by monitoring Io, the load current flowing in the spindle motor, at SPRNF
terminal, and holding the peak current in C BHLD, the capacitor connected to BHLD terminal. Charging time of BHLD terminal
is a time constant defined by capacity of CBHLD and 200 kΩ (Typ) internal resistance.
CSPCNF, the capacitor of SPCNF terminal, influences fc, the cut-off frequency, of the spindle driver control loop. f c can be
expressed in the following formula. Where ROERR is internal error amplifier output impedance of approximately 700 kΩ (Typ).
fc
1
2πCSPCNFROERR
VCC
VCC
CBHLD (Outside)
BHLD(Pin9)
VCC
BD8256EFV
VCC
Spindle motor current
200kΩ
SPRNF
amp.
Output current wave
Error Amp
amp.
D/A
U_OUT
Wave
range
CSPCNF(Outside) control
SPCNF(Pin8)
comp.
Limit current
Normal voltage
H+
Limit detection signal
amp.
comp.
Hole signal
PWM
Duty control、
Limit detection
short brake
control
V_OUT
W_OUT
HTriangle wave
(inside wave)
Figure 22. Spindle Driver Block Diagram
4. Spindle Hall Signal Setting
In this IC, as shown in Figure 22, low noise (silence) is realized by controlling output current into a sine wave. Hall signal
amplified according to REG 08h DSP is used to control the output current. So, if amplitude of the hall signal is too small,
amplitude of the output current will also be too small, and rotation speed will become too low. Therefore, make sure that
input level of the hall signal be 50 mV (input level at hall amplifier: V HIM) or greater as shown in Figure 23. Also make sure
that waveform of the hall signal be as close as possible to sine wave.
HU+
HU+
50mV
50mV
50mV
HU50mV
HU-
Figure 23. Minimum Amplitude of Hall Input (Example of HU+ and HU- Input).
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5. Hall input (Pin 1 to Pin 6) / Hall bias (Pin 7) (Spindle)
Hall elements can be connected either in series or in parallel as shown in Figure 24.
Hall input voltage should be set within the range of 1.5 V to 3.8 V (In-phase input voltage range of hall amplifier: VHICM).
If the Hall input range is not meeting the specification due to variation in characteristics of Hall elements, there is a setting
to connect resistor parallel to a resistor.
Additionally, they can also be connected to GND instead of hall bias (Pin 7). In this case, GND should be set as PREGND
(Pin 30) and the hall bias (Pin 7) to open.
For connection details, please refer to the page with Application Example.
HVCC
HVCC
HU
HU
HV
HW
HV
HW
Pin7
Pin7
Figure 24. Example of Hall Elements Connection
6. FG Pulse
3FG is output to FG terminal. Pull-up resistor of FG is recommended to be 3.3 kΩ or less. If the resistance setting is higher
than that, High logic of FG output can be reversed to become "Low" as soon as spindle output becomes Hi-Z.
Since FG pulse is generated from hall output signal, it can become unstable if the hall signal catches noise. Radiation noise
on circuit patterns or flexible cables should be avoided as much as possible. Against any remaining noise, it is
recommended to insert a capacitor (around 0.01 µF) between positive and negative sides of the hall signal.
7. Reverse brake
When reverse brake is done coming from high speed, take note of the counter-electromotive force. Also, consider the
speed of motor rotation to ensure sufficient output current when using the reverse brake.
8.Capacitor between SPVM-SPGND
There is change in voltage and current because of the steep drive PWM. The capacitor between SPVM-SPGND is placed
in order to suppress the fluctuations due to the SPVM voltage. However, the effect is reduced if this capacitor is placed far
from the IC due to the effect of line impedances. Therefore, this capacitor should be placed near the IC.
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9. Spindle Dricer Input-Output Timing Chart
HU+
HUHVHV+
HW+
HWSource
U_OUT
Sink
Source
V_OUT
Sink
Source
W_OUT
Sink
High
FG
Low
State
A
B
C
D
E
F
(a) Forward Mode
(b) Short Brake Mode
(DSP>000h)
(DSP
