Datasheet
4.5V to 18V, 5A 1ch
Synchronous Buck Converter
BD86120EFJ
●Description
The BD86120EFJ is synchronous buck converters. The
device integrates power MOSFETS that provide a each
maximums current output current continuous load current
over a wide operating input voltage of 4.5V to 18V.
Current mode operation provides fast transient response
and easy phase compensation.
The output power MOSFETs using P-type MOSEFT (HI
side) and N-type MOSEFT (LOW side), then this device
don’t need boot capacitor.
The BD86120EFJ is HTSOP-J8 standard packages.
●Features
Input voltage range:
4.5V to 18.0V
Reference voltage
0.8V ± 1%
Average output Current:
5A(Max.)
Switching frequency:
550kHz(Typ.)
Pch FET ON resistance:
50mΩ(Typ.)
Nch FET ON resistance:
35mΩ(Typ.)
Standby current:
1μA (Typ.)
Operating temperature range:
-40℃ to +85℃
Cycle by cycle over current protection(OCP)
Thermal shutdown (TSD)
Under voltage lock out(UVLO)
Short circuit protection(SCP)
Over voltage protection(OVP)
Fixed soft start 5msec
●Applications
■ LCD TVs
■ Set top boxes
■ DVD/Blu-ray players/recorders
■ Broadband Network and Communication Interface
■ Amusement, other
W(Typ.) x D(Typ.) x H(Max.)
4.90mm x 6.00mm x 1.00mm
●Package
HTSOP-J8
(TOP VIEW)
PGND
1
8
SW
VIN
2
7
SW
EN
3
6
COMP
AGND
4
5
FB
Figure 2. Pin configuration
●Typical Application
BD86120EFJ
VIN
C1
L
SW
PGND
C2
R2
FB
EN
R3
COMP
AGND
R1
C3
Figure 1. Application Circuit
○Product structure：Silicon monolithic integrated circuit
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Datasheet
BD86120EFJ
●Block Diagram
EN
VREG
OSC
OVP
SCP
OCP
UVLO
IBIAS
VIN
TSD
S
LOGIC
ERR
FB
SW
SLOPE
PWM
R
COMP
PGND
SoftStart
AGND
Figure 3. Block diagram
●Pin Description
No.
Symbol
Description
1
PGND
2
VIN
Input voltage supply pin.
3
EN
Enable input control. Active high.
4
AGND
5
FB
6
COMP
7
SW
Switch node connection between high-side Pch FET and Low-side Nch FET.
8
SW
Switch node connection between high-side Pch FET and Low-side Nch FET.
Thermal
Pad
Back side
Power Ground pin. Power ground return for switching circuit.
Analog Ground pin. Electrically needs to be connected to PGND.
Converter feedback input. Connect to output voltage with feedback resistor divider.
Error amplifier output, and input to the output switch current comparator.
External loop compensation pin.
Thermal pad of the package. Must be soldered to achieve appropriate dissipation. Must be connected
to AGND.
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Datasheet
BD86120EFJ
●Absolute maximum ratings (Ta=25℃)
Parameter
Symbol
Ratings
Unit
Input supply voltage
VIN
20
V
SW terminal voltage
VSW
20
V
SW terminal voltage
（10ns transient）
VSW (AC)
22
V
EN terminal voltage
VEN
20
V
Power dissipation
Pd
3760*
mW
Operating temperature
Topr
-40～+85
℃
Storage temperature
Tstg
-55～+150
℃
Tjmax
150
℃
VLVPINS
7
V
Maximum Junction temperature
FB, COMP terminal voltage
*
Condition
70mm×70mm, thickness 1.6mm,
and 4 layer glass epoxy substrates
Operating at higher than Ta=25℃, 30.08mW shall be reduced per 1℃
●Operating ratings
Parameter
Symbol
Ratings
Min.
Typ.
Max.
Unit
Input supply voltage
VIN
4.5
-
18.0
V
Output current
IOUT
-
-
5.0
A
VRANGE
VIN×0.068*
-
VIN×0.8
V
Output voltage range
*
VIN×0.068 ≧ 0.8 [V]
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Datasheet
BD86120EFJ
●Electrical characteristics
(Unless otherwise noted Ta=25℃, VIN=12V, VEN = 3V)
Parameter
Symbol
Limits
Min.
Typ.
Max.
UNIT
Condition
VIN supply current (operating)
IQ_active
-
1.5
2.5
mA
VFB= 0.75V, VEN= 5V
VIN supply current (standby)
IQ_stby
-
1.0
10.0
μA
VEN = 0V
Reference voltage (VREF)
VFB
0.792
0.800
0.808
V
FB-COMP Short
(Voltage follower)
FB input bias current
IFB
-
0
2
μA
Oscillation frequency
fOSC
500
550
600
kHz
High side FET ON resistance
RONH
-
50
-
mΩ
VIN= 12V , ISW = -1A
Low side FET ON resistance
RONL
-
35
-
mΩ
VIN= 12V , ISW = -1A
SW leak current
ILSW
-
0
5
μA
VIN= 18V , VSW = 18V
Switch Current Limit
ILIMIT
5.5
-
-
A
Min_duty
-
-
6.8
%
VUVLO
3.8
4.1
4.4
V
VUVLOHYS
-
0.3
-
V
EN terminal H threshold voltage
VENH
2.0
-
-
V
EN terminal L threshold voltage
VENL
-
-
0.8
V
Soft Start Time
TSS
3.0
5.0
7.0
msec
Min duty
UVLO voltage
UVLO hysteresis
●
●
VIN Sweep up
VFB :FB terminal voltage, VEN :EN terminal voltage,
Current capability should not exceed Pd.
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Datasheet
BD86120EFJ
●Typical Performance Curves (Reference data)
110
100
Vout = 5.0V
90
100
80
90
80
Vout = 3.3V
60
Tc[℃]
Efficiency [%]
70
50
40
Vout = 1.2V
VIN=12V
L=4.7µH
Cout=44µF
10
60
50
30
20
70
40
30
0
20
0.01
0.1
1
10
0
1
2
ILOAD[A]
Figure 4. Efficiency
SW
4
Figure 5. TC-ILOAD
(VIN=12V, Vout=3.3V, L=4.7µH, Cout=44µF)
[20mV/div]
Vout(AC)
[5V/div]
SW
[20mV/div]
[5V/div]
T - Time - 1usec/div
T - Time - 1usec/div
Figure 6. Vout Ripple
Figure 7. Vout Ripple
(VIN=12V, Vout=3.3V, L=4.7µH, Cout=44µF, Iout=0A)
(VIN=12V, Vout=3.3V, L=4.7µH, Cout=44µF, Iout=5A)
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5
ILOAD[A]
(VIN=12V, L=3.3/4.7/4.7µH(Vout=1.2/3.3/5.0V), Cout=44µF)
Vout(AC)
3
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Datasheet
BD86120EFJ
3.40
3.40
3.38
3.38
3.36
3.36
3.34
3.34
3.32
3.32
Vout [V]
Vout [V]
●Typical Performance Curves (Reference data) (continued)
3.30
3.28
3.30
3.28
3.26
3.26
3.24
3.24
3.22
3.22
3.20
3.20
0
1
2
3
4
4
5
6
8
ILOAD [A]
10
12
14
16
18
80
100
VIN [V]
Figure 8. Load regulation
Figure 9. Line regulation
(VIN=12V, Vout=3.3V, L=4.7µH, Cout=44µF)
(Vout=3.3V, L=4.7µH, Cout=44µF, Iout=0A)
3.40
610
3.38
3.36
3.34
570
Vout [V]
Frequency [kHz]
590
550
530
3.32
3.30
3.28
3.26
3.24
510
3.22
490
3.20
4
6
8
10
12
14
16
18
-40
VIN [V]
-20
0
20
40
60
Ta [℃]
Figure 10. Frequency
Figure 11. Vout-Temperature
(Vout=3.3V, L=4.7µH, Cout=44µF, Iout=0A)
(Vin=12V, Vout=3.3V, L=4.7µH, Cout=44µF, Iout=0A)
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Datasheet
BD86120EFJ
●Typical Performance Curves (Reference data) (continued)
EN [5V/div]
EN [5V/div]
Vout
[2V/div]
Vout
[2V/div]
SW
[10V/div]
SW
[10V/div]
T - Time – 200msec/div
T - Time – 1msec/div
Figure 12. Start up wave form
Figure 13. Off wave form
(Vin=12V, Vout=3.3V, L=4.7µH, Cout=44µF, Iout=0A)
(Vin=12V, Vout=3.3V, L=4.7µH, Cout=44µF, Iout=0A)
Δ=+64mV
Δ=-88mV
Vout(AC) [50mV/div]
Vout
[5V/div]
SW
[20V/div]
IL [5A/div]
Iout
[2A/div]
T - Time - 200usec/div
T - Time - 100usec/div
Figure 14. Transient response
Figure 15. OCP function
(Vin=12V, Vout=3.3V, L=4.7µH, Cout=44µF, Iout=2A)
(Vin=12V, Vout=3.3V, L=4.7µH, Cout=44µF, Vout is short to GND)
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Datasheet
BD86120EFJ
●Functional descriptions
1 Enable control
The device can be controlled ON/OFF by EN terminal voltage.
An internal circuit starts when VEN reaches 2.0V.
When standing up of VIN is too steep (1msec or less), a defective start might be caused according to the state of Pascon
between GND substrate pattern and power supply-when the terminal EN is short-circuited to the terminal VIN and it is
used.
VEN
EN terminal
VENH
VENL
0
VO
Output setting voltage
0
TSS
Figure 16. ON/OFF transition wave form in EN controlling
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Datasheet
BD86120EFJ
2 Protection function
Protection circuit is effective for destruction prevention due to accident so that avoid using under continuous
protection operation.
2-1 Short Circuit protection function (SCP)
The FB terminal voltage is compared with internal reference voltage VREF.
If FB terminal voltage falls below VSCP (= VREF - 240mV) and the state continues, output changes to low voltage and the
state is fixed.
During soft start, the FB terminal voltage is compared with internal soft start slope
Table 1 output short circuit protection function
EN terminal
Short Circuit
Protection function
FB terminal
＜VSCP
>VENH
VENH
＜VOVP
> RUP||RDW
V OUT
A
(a)
Gain [dB]
R UP
C RUP
FB
R DW
－
GBW(b)
COMP
0
＋
R CMP
0.8V
PHASE
－90
C CMP
F
FCRS
0
－90°
PHASE MARGIN
－180°
－180
F
Figure 26.
Figure 25.
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Datasheet
BD86120EFJ
●I/O equivalence circuit(s)
5.FB
7,8.SW
ＶＩＮ
ＶＩＮ
ＦＢ
20ｋΩ
10ｋΩ
ＳＷ
10ｋΩ
ＡＧＮＤ
ＰＧＮＤ
3.EN
6.COMP
ＶＲＥＧ
ＶＩＮ
ＶＩＮ
2ｋΩ
ＥＮ
0.5ｋΩ
250ｋΩ
2ｋΩ
ＣＯＭＰ
0.5ｋΩ
725ｋΩ
ＡＧＮＤ
ＡＧＮＤ
Figure 27.
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Datasheet
BD86120EFJ
●Notes for use
1) Absolute maximum ratings
Use of the IC in excess of absolute maximum ratings such as the applied voltage or operating temperature range may
result in IC damage. Assumptions should not be made regarding the state of the IC (short mode or open mode) when
such damage is suffered. A physical safety measure such as a fuse should be implemented when use of the IC in a
special mode where the absolute maximum ratings may be exceeded is anticipated.
2) GND potential
Ensure a minimum GND pin potential in all operating conditions.
3) Setting of heat
Use a thermal design that allows for a sufficient margin in light of the power dissipation (Pd) in actual operating
conditions.
4) Pin short and mistake fitting
Use caution when orienting and positioning the IC for mounting on printed circuit boards. Improper mounting may result
in damage to the IC. Shorts between output pins or between output pins and the power supply and GND pins caused by
the presence of a foreign object may result in damage to the IC.
5) Actions in strong magnetic field
Use caution when using the IC in the presence of a strong magnetic field as doing so may cause the IC to malfunction.
6) Testing on application boards
When testing the IC on an application board, connecting a capacitor to a pin with low impedance subjects the IC to stress.
Always discharge capacitors after each process or step. Ground the IC during assembly steps as an antistatic measure,
and use similar caution when transporting or storing the IC. Always turn the IC's power supply off before connecting it to
or removing it from a jig or fixture during the inspection process.
7) Ground wiring patterns
When using both small signal and large current GND patterns, it is recommended to isolate the two ground patterns,
placing a single ground point at the application's reference point so that the pattern wiring resistance and voltage
variations caused by large currents do not cause variations in the small signal ground voltage. Be careful not to change
the GND wiring patterns of any external components.
8) Regarding input pin of the IC
This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them isolated.
P/N junctions are formed at the intersection of these P layers with the N layers of other elements to create a variety of
parasitic elements.
For example, when the resistors and transistors are connected to the pins as shown in Figure 26. , a parasitic diode or a
transistor operates by inverting the pin voltage and GND voltage.
The formation of parasitic elements as a result of the relationships of the potentials of different pins is an inevitable result
of the IC's architecture. The operation of parasitic elements can cause interference with circuit operation as well as IC
malfunction and damage. For these reasons, it is necessary to use caution so that the IC is not used in a way that will
trigger the operation of parasitic elements such as by the application of voltages lower than the GND (P substrate)
voltage to input and output pins.
Resistor
Transistor (NPN)
B
～
～
B
E
～
～
C
(Pin B)
(Pin B)
～
～
(Pin A)
GND
N
N
P
P
P+
N
N
N
N
(Pin A)
P substrate
Parasitic elements
GND
Parasitic
elements
P+
～
～
P+
Parasitic elements
E
GND
N
P
P+
C
Parasitic
elements
GND
GND
Figure 28.
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Datasheet
BD86120EFJ
9) Overcurrent protection circuits
An overcurrent protection circuit designed according to the output current is incorporated for the prevention of IC damage
that may result in the event of load shorting. This protection circuit is effective in preventing damage due to sudden and
unexpected accidents. However, the IC should not be used in applications characterized by the continuous operation or
transitioning of the protection circuits. At the time of thermal designing, keep in mind that the current capacity has
negative characteristics to temperatures.
10) Thermal shutdown circuit (TSD)
This IC incorporates a built-in TSD circuit for the protection from thermal destruction. The IC should be used within the
specified power dissipation range. However, in the event that the IC continues to be operated in excess of its power
dissipation limits, the attendant rise in the chip's junction temperature Tj will trigger the TSD circuit to turn off all output
power elements. Operation of the TSD circuit presumes that the
IC's absolute maximum ratings have been exceeded. Application designs should never make use of the TSD circuit.
11) EN control speed
Chattering happens if standing lowering speed is slow when standing of EN pin is lowered.
The reverse current in which the input side and the pressure operation are done from the output side is generated when
chattering operates with the output voltage remained, and there is a case to destruction.
Please set to stand within 100µs when you control ON/OFF by the EN signal.
Status of this document
The Japanese version of this document is formal specification. A customer may use this translation version only for a
reference to help reading the formal version.
If there are any differences in translation version of this document formal version takes priority
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Datasheet
BD86120EFJ
●Power Dissipation
HTSOP-J8 Package
On 70 70 1.6 mm glass epoxy PCB
(1) 1-layer board (Backside copper foil area 0 mm 0 mm)
(2) 2-layer board (Backside copper foil area 15 mm 15 mm)
(3) 2-layer board (Backside copper foil area 70 mm 70 mm)
(4) 4-layer board (Backside copper foil area 70 mm 70 mm)
●Ordering Information
B
D
8
6
1
2
0
Part Number
E
F
J
-
Package
EFJ: HTSOP-J8
E2
Packaging and forming specification
E2: Embossed tape and reel
●Physical Dimension Tape and Reel Information
HTSOP-J8
+6°
4°
−4°
(2.4)
3.9±0.1
6.0±0.2
8 7 6 5
1
1.05±0.2
(3.2)
0.65±0.15
4.9±0.1
(MAX 5.25 include BURR)
Tape
Embossed carrier tape
Quantity
2500pcs
Direction
of feed
E2
The direction is the 1pin of product is at the upper left when you hold
( reel on the left hand and you pull out the tape on the right hand
)
2 3 4
1PIN MARK
+0.05
0.17 -0.03
1.0MAX
0.545
S
0.08±0.08
0.85±0.05
1.27
+0.05
0.42 -0.04
0.08
M
0.08 S
1pin
(Unit : mm)
Reel
Direction of feed
∗ Order quantity needs to be multiple of the minimum quantity.
●Marking Diagram(s)(TOP VIEW)
HTSOP-J8(TOP VIEW)
Part Number Marking
D 8 6 1 2 0
LOT Number
1PIN MARK
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Datasheet
BD86120EFJ
●History
Date
Revision
07.Sep.2012
001
Changes
New Release
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